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Force those to true and 0 when passing off to _internal. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/tcg/mte_helper.h | 18 +++--------------- target/arm/gdbstub64.c | 10 +++++----- target/arm/tcg/mte_helper.c | 29 ++++++++++++++++++----------- 3 files changed, 26 insertions(+), 31 deletions(-) diff --git a/target/arm/tcg/mte_helper.h b/target/arm/tcg/mte_helper.h index 1f471fb69b..b23a5de193 100644 --- a/target/arm/tcg/mte_helper.h +++ b/target/arm/tcg/mte_helper.h @@ -19,8 +19,6 @@ * @ptr_access: the access to use for the virtual address * @ptr_size: the number of bytes in the normal memory access * @tag_access: the access to use for the tag memory - * @probe: true to merely probe, never taking an exception - * @ra: the return address for exception handling * * Our tag memory is formatted as a sequence of little-endian nibbles. * That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two @@ -31,22 +29,12 @@ * a pointer to the corresponding tag byte. * * If there is no tag storage corresponding to @ptr, return NULL. - * - * If the page is inaccessible for @ptr_access, or has a watchpoint, there= are - * three options: - * (1) probe =3D true, ra =3D 0 : pure probe -- we return NULL if the page= is not - * accessible, and do not take watchpoint traps. The calling code must - * handle those cases in the right priority compared to MTE traps. - * (2) probe =3D false, ra =3D 0 : probe, no fault expected -- the caller = guarantees - * that the page is going to be accessible. We will take watchpoint tr= aps. - * (3) probe =3D false, ra !=3D 0 : non-probe -- we will take both memory = access - * traps and watchpoint traps. - * (probe =3D true, ra !=3D 0 is invalid and will assert.) + * If the page is inaccessible for @ptr_access, return NULL. + * Do not take watcnpoint traps. */ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, uint64_t ptr, MMUAccessType ptr_access, - int ptr_size, MMUAccessType tag_access, - bool probe, uintptr_t ra); + int ptr_size, MMUAccessType tag_access); =20 /** * load_tag1 - Load 1 tag (nibble) from byte diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 0c3e5b30bd..08900f6843 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -725,8 +725,8 @@ static void handle_q_memtag(GArray *params, void *user_= ctx) /* Find out the current translation regime for probe. */ mmu_index =3D cpu_mmu_index(env_cpu(env), false); /* Note that tags are packed here (2 tags packed in one byte). */ - tags =3D allocation_tag_mem_probe(env, mmu_index, addr, MMU_DATA_LOAD,= 1, - MMU_DATA_LOAD, true, 0); + tags =3D allocation_tag_mem_probe(env, mmu_index, addr, MMU_DATA_LOAD, + 1, MMU_DATA_LOAD); if (!tags) { /* Address is not in a tagged region. */ gdb_put_packet("E04"); @@ -753,8 +753,8 @@ static void handle_q_isaddresstagged(GArray *params, vo= id *user_ctx) =20 /* Find out the current translation regime for probe. */ mmu_index =3D cpu_mmu_index(env_cpu(env), false); - tags =3D allocation_tag_mem_probe(env, mmu_index, addr, MMU_DATA_LOAD,= 1, - MMU_DATA_LOAD, true, 0); + tags =3D allocation_tag_mem_probe(env, mmu_index, addr, MMU_DATA_LOAD, + 1, MMU_DATA_LOAD); reply =3D tags ? "01" : "00"; =20 gdb_put_packet(reply); @@ -800,7 +800,7 @@ static void handle_Q_memtag(GArray *params, void *user_= ctx) /* Find out the current translation regime for probe. */ mmu_index =3D cpu_mmu_index(env_cpu(env), false); tags =3D allocation_tag_mem_probe(env, mmu_index, start_addr, MMU_DATA= _STORE, - 1, MMU_DATA_STORE, true, 0); + 1, MMU_DATA_STORE); if (!tags) { /* Address is not in a tagged region. */ gdb_put_packet("E04"); diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index ad4ad5b4cc..a1d8618ddb 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -79,10 +79,11 @@ static void mte_perm_check_fail(CPUARMState *env, uint6= 4_t dirty_ptr, } #endif =20 -uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, - uint64_t ptr, MMUAccessType ptr_access, - int ptr_size, MMUAccessType tag_access, - bool probe, uintptr_t ra) +static uint8_t * +allocation_tag_mem_internal(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access, + bool probe, uintptr_t ra) { #ifdef CONFIG_USER_ONLY const size_t page_data_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE = + 1); @@ -91,8 +92,6 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int p= tr_mmu_idx, uint8_t *tags; uintptr_t index; =20 - assert(!(probe && ra)); - if (!(flags & (ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE_ORG : PAG= E_READ))) { if (probe) { return NULL; @@ -249,8 +248,16 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, i= nt ptr_mmu_idx, int ptr_size, MMUAccessType tag_access, uintptr_t ra) { - return allocation_tag_mem_probe(env, ptr_mmu_idx, ptr, ptr_access, - ptr_size, tag_access, false, ra); + return allocation_tag_mem_internal(env, ptr_mmu_idx, ptr, ptr_access, + ptr_size, tag_access, false, ra); +} + +uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access) +{ + return allocation_tag_mem_internal(env, ptr_mmu_idx, ptr, ptr_access, + ptr_size, tag_access, true, 0); } =20 uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) @@ -1144,7 +1151,7 @@ uint64_t mte_mops_probe(CPUARMState *env, uint64_t pt= r, uint64_t size, /* True probe; this will never fault */ mem =3D allocation_tag_mem_probe(env, mmu_idx, ptr, w ? MMU_DATA_STORE : MMU_DATA_LOAD, - size, MMU_DATA_LOAD, true, 0); + size, MMU_DATA_LOAD); if (!mem) { return size; } @@ -1202,7 +1209,7 @@ uint64_t mte_mops_probe_rev(CPUARMState *env, uint64_= t ptr, uint64_t size, */ mem =3D allocation_tag_mem_probe(env, mmu_idx, ptr, w ? MMU_DATA_STORE : MMU_DATA_LOAD, - 1, MMU_DATA_LOAD, true, 0); + 1, MMU_DATA_LOAD); if (!mem) { return size; } @@ -1254,7 +1261,7 @@ void mte_mops_set_tags(CPUARMState *env, uint64_t ptr= , uint64_t size, mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); /* True probe: this will never fault */ mem =3D allocation_tag_mem_probe(env, mmu_idx, ptr, MMU_DATA_STORE, si= ze, - MMU_DATA_STORE, true, 0); + MMU_DATA_STORE); if (!mem) { return; } --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826431; cv=none; d=zohomail.com; s=zohoarc; b=CEmKQndp9XnWtA4naUvzV81o++ZL656XE8cCkuGkaskjXwcR4lWLUg8g/bEDVaw1E3iTCg09WSNp651FeZPUMWFE6vcDCDbEV0wLZW92fYsyGTNd/XPSExJDQ+xwWt0+0Q5Nnvhzq3apAst+RMNRvN1THllk107dQKo0Y3BSHMQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786826431; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=p1tuew/8yZ3WUepEtCLWv5OHi9k/pwAQkc4Skx4oIwo=; b=jUkt0w338coqjNRDbnqOE9mDeZv9Fl1+L+E5PpxERKpUEo0TIanVnyDjcPemWdcctfp1BaJgRKcPXJ/GMWGvlmwRUGA/ZhB/0FMjiIzJLqV81jkCbBUyMk0PDHt3cLSM8SpNmM2JTZurqR7DXx/sQ2n6Wi1yX0zSNXUpkrGnR7w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786826431872636.107464404023; Sat, 15 Aug 2026 13:40:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wvL8T-00084k-L3; Sat, 15 Aug 2026 16:37:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvL8S-000839-1l for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:44 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wvL8P-0008AH-1I for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:43 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-38125cebfdaso3293658a91.1 for ; Sat, 15 Aug 2026 13:37:40 -0700 (PDT) Received: from stoup.. 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Sat, 15 Aug 2026 13:37:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 02/18] target/arm: Simplify invalid page test in allocation_tag_mem_internal Date: Sat, 15 Aug 2026 13:37:14 -0700 Message-ID: <20260815203730.1468365-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260815203730.1468365-1-richard.henderson@linaro.org> References: <20260815203730.1468365-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786826433265158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index a1d8618ddb..e3952fcabf 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -132,10 +132,10 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr= _mmu_idx, */ flags =3D probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx, ra =3D=3D 0, &host, &full, ra); - if (probe && (flags & TLB_INVALID_MASK)) { + if (unlikely(flags & TLB_INVALID_MASK)) { + assert(probe); return NULL; } - assert(!(flags & TLB_INVALID_MASK)); =20 switch (full->extra.arm.pte_attrs) { case 0xf0: /* Tagged */ --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826389; cv=none; d=zohomail.com; s=zohoarc; b=mSMX4NRLKLDMRRheKW5atLFRcEIWVMQRmfNrovamRQxsnDXUlRZ8/+0xg1I3eWDLQuC5XGuFQnvNx76cfk2Ko29pz+F/IXUPwJcBKUgAICCx7E8CpRDryoeGSlm1yxE1FqQ1Oe6awNvbsD2ZOIYNf8c/oAWlKvpQxxlu8rhPwO4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786826389; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Make sure probe of NoTagAccess looks like any other page permission failure. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 104 +++++++++++++++++++++--------------- 1 file changed, 62 insertions(+), 42 deletions(-) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index e3952fcabf..dd4c10ef4f 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -27,6 +27,7 @@ #ifdef CONFIG_USER_ONLY #include "user/cpu_loop.h" #include "user/page-protection.h" +#include "user/guest-host.h" #else #include "system/physmem.h" #endif @@ -79,46 +80,55 @@ static void mte_perm_check_fail(CPUARMState *env, uint6= 4_t dirty_ptr, } #endif =20 -static uint8_t * +typedef struct AllocationTagMem { + uint8_t *tag_mem; + void *ptr_mem; + int flags; + MemTxAttrs attrs; +} AllocationTagMem; + +static AllocationTagMem allocation_tag_mem_internal(CPUARMState *env, int ptr_mmu_idx, - uint64_t ptr, MMUAccessType ptr_access, + vaddr ptr, MMUAccessType ptr_access, int ptr_size, MMUAccessType tag_access, bool probe, uintptr_t ra) { -#ifdef CONFIG_USER_ONLY - const size_t page_data_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE = + 1); - uint64_t clean_ptr =3D useronly_clean_ptr(ptr); - int flags =3D page_get_flags(clean_ptr); - uint8_t *tags; - uintptr_t index; + AllocationTagMem ret =3D { + .flags =3D TLB_INVALID_MASK, + .attrs =3D MEMTXATTRS_UNSPECIFIED, + }; =20 - if (!(flags & (ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE_ORG : PAG= E_READ))) { +#ifdef CONFIG_USER_ONLY + vaddr clean_ptr =3D useronly_clean_ptr(ptr); + int flags =3D page_get_flags(clean_ptr); + int req_flags =3D ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE_ORG : = PAGE_READ; + + if (unlikely(!(flags & req_flags))) { if (probe) { - return NULL; + goto fini; } cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access, !(flags & PAGE_VALID), ra); } =20 /* Require both MAP_ANON and PROT_MTE for the page. */ - if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) { - return NULL; + if ((flags & PAGE_ANON) && (flags & PAGE_MTE)) { + size_t page_data_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + = 1); + uint8_t *tags =3D page_get_target_data(clean_ptr, page_data_size); + uintptr_t index =3D extract64(ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - = 1); + ret.tag_mem =3D tags + index; } =20 - tags =3D page_get_target_data(clean_ptr, page_data_size); - - index =3D extract32(ptr, LOG2_TAG_GRANULE + 1, - TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); - return tags + index; + ret.ptr_mem =3D g2h_untagged_vaddr(clean_ptr); + ret.flags =3D 0; #else CPUTLBEntryFull *full; - MemTxAttrs attrs; - int in_page, flags; + int in_page; hwaddr ptr_paddr, tag_paddr, xlat; MemoryRegion *mr; ARMASIdx tag_asi; AddressSpace *tag_as; - void *host; =20 /* * Probe the first byte of the virtual address. This raises an @@ -130,12 +140,13 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr= _mmu_idx, * for the pure probe, or assert that we received a valid page for the * no-fault-expected probe. */ - flags =3D probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx, - ra =3D=3D 0, &host, &full, ra); - if (unlikely(flags & TLB_INVALID_MASK)) { + ret.flags =3D probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx, + ra =3D=3D 0, &ret.ptr_mem, &full, ra); + if (unlikely(ret.flags & TLB_INVALID_MASK)) { assert(probe); - return NULL; + goto fini; } + ret.attrs =3D full->attrs; =20 switch (full->extra.arm.pte_attrs) { case 0xf0: /* Tagged */ @@ -144,7 +155,9 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr_m= mu_idx, case 0xe0: /* NoTagAccess */ if (cpu_isar_feature(aa64_mteperm, env_archcpu(env))) { if (probe) { - return NULL; + ret.ptr_mem =3D NULL; + ret.flags =3D TLB_INVALID_MASK; + goto fini; } assert(ra); mte_perm_check_fail(env, ptr, ra, tag_access =3D=3D MMU_DATA_S= TORE); @@ -152,27 +165,25 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr= _mmu_idx, /* fall through */ =20 default: /* Not Tagged */ - return NULL; + goto fini; } =20 /* * If not backed by host ram, there is no tag storage: access unchecke= d. * This is probably a guest os bug though, so log it. */ - if (unlikely(flags & TLB_MMIO)) { + if (unlikely(ret.flags & TLB_MMIO)) { qemu_log_mask(LOG_GUEST_ERROR, "Page @ 0x%" PRIx64 " indicates Tagged Normal memory= " "but is not backed by host ram\n", ptr); - return NULL; + goto fini; } =20 /* - * Remember these values across the second lookup below, + * Remember this across the second lookup below, * which may invalidate this pointer via tlb resize. */ ptr_paddr =3D full->phys_addr | (ptr & ~TARGET_PAGE_MASK); - attrs =3D full->attrs; - full =3D NULL; =20 /* * The Normal memory access can extend to the next page. E.g. a single @@ -182,26 +193,30 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr= _mmu_idx, */ in_page =3D -(ptr | TARGET_PAGE_MASK); if (unlikely(ptr_size > in_page)) { - flags |=3D probe_access_full(env, ptr + in_page, 0, ptr_access, - ptr_mmu_idx, ra =3D=3D 0, &host, &full,= ra); - assert(!(flags & TLB_INVALID_MASK)); + void *discard_mem; + int flags2 =3D probe_access_full(env, ptr + in_page, 0, ptr_access, + ptr_mmu_idx, ra =3D=3D 0, + &discard_mem, &full, ra); + + assert(!(flags2 & TLB_INVALID_MASK)); + ret.flags |=3D flags2; } =20 /* Any debug exception has priority over a tag check exception. */ - if (!probe && unlikely(flags & TLB_WATCHPOINT)) { + if (!probe && unlikely(ret.flags & TLB_WATCHPOINT)) { int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; assert(ra !=3D 0); - cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra); + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, ret.attrs, wp, r= a); } =20 /* Convert to the physical address in tag space. */ tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); =20 /* Look up the address in tag space. */ - tag_asi =3D attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_asi =3D ret.attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, - tag_access =3D=3D MMU_DATA_STORE, attrs); + tag_access =3D=3D MMU_DATA_STORE, ret.att= rs); =20 /* * Note that @mr will never be NULL. If there is nothing in the addre= ss @@ -214,7 +229,7 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr_m= mu_idx, "Tag Memory @ 0x%" HWADDR_PRIx " not found for " "Normal Memory @ 0x%" HWADDR_PRIx "\n", tag_paddr, ptr_paddr); - return NULL; + goto fini; } =20 /* @@ -226,8 +241,11 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr_= mmu_idx, physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION); } =20 - return memory_region_get_ram_ptr(mr) + xlat; + ret.tag_mem =3D memory_region_get_ram_ptr(mr) + xlat; #endif + + fini: + return ret; } =20 static G_NORETURN void canonical_tag_write_fail(CPUARMState *env, @@ -249,7 +267,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, uintptr_t ra) { return allocation_tag_mem_internal(env, ptr_mmu_idx, ptr, ptr_access, - ptr_size, tag_access, false, ra); + ptr_size, tag_access, false, ra) + .tag_mem; } =20 uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, @@ -257,7 +276,8 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int= ptr_mmu_idx, int ptr_size, MMUAccessType tag_access) { return allocation_tag_mem_internal(env, ptr_mmu_idx, ptr, ptr_access, - ptr_size, tag_access, true, 0); + ptr_size, tag_access, true, 0) + .tag_mem; } =20 uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826364; cv=none; d=zohomail.com; s=zohoarc; b=fZloGIgh9ebCIGifwxbBdbC3HDobE/+du+uYHRs/Mh50ulMJEqwkWDAUBtV41BxAsLY5NH+HB80K1FZ0g50tAdGHMwVS4naJRtCQatgLDcpRp9pVE6Xa8pslofRDGCmjUQqclICTJCZc8vT1Yq+UEP+qq2ZC907e5w9ZsT6Elqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786826364; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eV7TgD7exsKP95UC/n8h4naw41ahKSdAn16sZErXcgc=; b=iwSR6y4UwLqnQ9jEbHzThDEoI19L7nIcZ8vgcVnzFTQ6VO6Rp+9F9WiE5QFwbf+6VxROl99LgVSLBICN8g2053o05DJZhmKurZO7uWYmsN796opbFHC7lwPNkCjm8eR3MElm0omNm69kLHbFtJc6ZkMF0Vqc+zZLOyXimZ7TZ0w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786826363993678.3195102511969; Sat, 15 Aug 2026 13:39:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wvL8g-0008CJ-6X; Sat, 15 Aug 2026 16:37:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvL8c-00088B-UM for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:55 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wvL8R-0008DG-A0 for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:46 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-38dc69c74b8so2298915a91.0 for ; Sat, 15 Aug 2026 13:37:42 -0700 (PDT) Received: from stoup.. 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Make this explicit via an enumeration. Signed-off-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 130 ++++++++++++++++++++++-------------- 1 file changed, 80 insertions(+), 50 deletions(-) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index dd4c10ef4f..31bf58c937 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -87,28 +87,48 @@ typedef struct AllocationTagMem { MemTxAttrs attrs; } AllocationTagMem; =20 +typedef enum { + /* Trap on missing pages, invalid tag access, or watchpoints. */ + ATM_NORMAL, + /* Gracefully return no tag memory for invalid pages. */ + ATM_PROBE_PAGES, + /* + * Basic page access has already been checked, + * so a missing tlb entry is some sort of bug. + * Assert the tlb entry is present, but gracefully fail if tag + * access is not permitted to the page. + */ + ATM_ASSERT_PAGES, +} AllocationTagMemKind; + static AllocationTagMem allocation_tag_mem_internal(CPUARMState *env, int ptr_mmu_idx, vaddr ptr, MMUAccessType ptr_access, int ptr_size, MMUAccessType tag_access, - bool probe, uintptr_t ra) + uintptr_t ra, AllocationTagMemKind atm_kind) { AllocationTagMem ret =3D { .flags =3D TLB_INVALID_MASK, .attrs =3D MEMTXATTRS_UNSPECIFIED, }; =20 + assert((atm_kind >=3D ATM_PROBE_PAGES) =3D=3D (ra =3D=3D 0)); + #ifdef CONFIG_USER_ONLY vaddr clean_ptr =3D useronly_clean_ptr(ptr); int flags =3D page_get_flags(clean_ptr); int req_flags =3D ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE_ORG : = PAGE_READ; =20 if (unlikely(!(flags & req_flags))) { - if (probe) { + switch (atm_kind) { + case ATM_PROBE_PAGES: goto fini; + case ATM_NORMAL: + cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access, + !(flags & PAGE_VALID), ra); + default: + g_assert_not_reached(); } - cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access, - !(flags & PAGE_VALID), ra); } =20 /* Require both MAP_ANON and PROT_MTE for the page. */ @@ -124,7 +144,6 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr_m= mu_idx, ret.flags =3D 0; #else CPUTLBEntryFull *full; - int in_page; hwaddr ptr_paddr, tag_paddr, xlat; MemoryRegion *mr; ARMASIdx tag_asi; @@ -134,16 +153,12 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr= _mmu_idx, * Probe the first byte of the virtual address. This raises an * exception for inaccessible pages, and resolves the virtual address * into the softmmu tlb. - * - * When RA =3D=3D 0, this is either a pure probe or a no-fault-expecte= d probe. - * Indicate to probe_access_flags no-fault, then either return NULL - * for the pure probe, or assert that we received a valid page for the - * no-fault-expected probe. */ ret.flags =3D probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx, - ra =3D=3D 0, &ret.ptr_mem, &full, ra); + atm_kind >=3D ATM_PROBE_PAGES, + &ret.ptr_mem, &full, ra); if (unlikely(ret.flags & TLB_INVALID_MASK)) { - assert(probe); + assert(atm_kind =3D=3D ATM_PROBE_PAGES); goto fini; } ret.attrs =3D full->attrs; @@ -154,12 +169,11 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr= _mmu_idx, =20 case 0xe0: /* NoTagAccess */ if (cpu_isar_feature(aa64_mteperm, env_archcpu(env))) { - if (probe) { + if (atm_kind >=3D ATM_PROBE_PAGES) { ret.ptr_mem =3D NULL; ret.flags =3D TLB_INVALID_MASK; goto fini; } - assert(ra); mte_perm_check_fail(env, ptr, ra, tag_access =3D=3D MMU_DATA_S= TORE); } /* fall through */ @@ -191,22 +205,21 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr= _mmu_idx, * tag on the first page. * Any page access exception has priority over tag check exception. */ - in_page =3D -(ptr | TARGET_PAGE_MASK); - if (unlikely(ptr_size > in_page)) { - void *discard_mem; - int flags2 =3D probe_access_full(env, ptr + in_page, 0, ptr_access, - ptr_mmu_idx, ra =3D=3D 0, - &discard_mem, &full, ra); + if (atm_kind =3D=3D ATM_NORMAL) { + int in_page =3D -(ptr | TARGET_PAGE_MASK); + if (unlikely(ptr_size > in_page)) { + void *discard_mem; + ret.flags |=3D probe_access_full(env, ptr + in_page, 0, ptr_ac= cess, + ptr_mmu_idx, false, + &discard_mem, &full, ra); + } =20 - assert(!(flags2 & TLB_INVALID_MASK)); - ret.flags |=3D flags2; - } - - /* Any debug exception has priority over a tag check exception. */ - if (!probe && unlikely(ret.flags & TLB_WATCHPOINT)) { - int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; - assert(ra !=3D 0); - cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, ret.attrs, wp, r= a); + /* Any debug exception has priority over a tag check exception. */ + if (unlikely(ret.flags & TLB_WATCHPOINT)) { + int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_= MEM_WRITE; + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, + ret.attrs, wp, ra); + } } =20 /* Convert to the physical address in tag space. */ @@ -267,8 +280,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, uintptr_t ra) { return allocation_tag_mem_internal(env, ptr_mmu_idx, ptr, ptr_access, - ptr_size, tag_access, false, ra) - .tag_mem; + ptr_size, tag_access, + ra, ATM_NORMAL).tag_mem; } =20 uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, @@ -276,8 +289,8 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int= ptr_mmu_idx, int ptr_size, MMUAccessType tag_access) { return allocation_tag_mem_internal(env, ptr_mmu_idx, ptr, ptr_access, - ptr_size, tag_access, true, 0) - .tag_mem; + ptr_size, tag_access, + 0, ATM_PROBE_PAGES).tag_mem; } =20 uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) @@ -881,6 +894,7 @@ static int checkNrev(uint8_t *mem, int odd, int cmp, in= t count) * @desc: MTEDESC descriptor * @ptr: virtual address of the base of the access * @fault: return virtual address of the first check failure + * @kind: per allocation_tag_mem_internal * * Internal routine for both mte_probe and mte_check. * Return zero on failure, filling in *fault. @@ -888,13 +902,14 @@ static int checkNrev(uint8_t *mem, int odd, int cmp, = int count) * Return positive on success with tbi enabled. */ static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr, - uintptr_t ra, uint64_t *fault) + uintptr_t ra, uint64_t *fault, + AllocationTagMemKind atm_kind) { int mmu_idx, ptr_tag, bit55; uint64_t ptr_last, prev_page, next_page; uint64_t tag_first, tag_last; uint32_t sizem1, tag_count, n, c; - uint8_t *mem1, *mem2; + AllocationTagMem r1, r2; MMUAccessType type; =20 bit55 =3D extract64(ptr, 55, 1); @@ -932,9 +947,14 @@ static int mte_probe_int(CPUARMState *env, uint32_t de= sc, uint64_t ptr, =20 if (likely(tag_last - prev_page < TARGET_PAGE_SIZE)) { /* Memory access stays on one page. */ - mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, sizem1 + 1, - MMU_DATA_LOAD, ra); - if (!mem1) { + r1 =3D allocation_tag_mem_internal(env, mmu_idx, ptr, type, sizem1= + 1, + MMU_DATA_LOAD, ra, atm_kind); + if (unlikely(r1.flags & TLB_INVALID_MASK)) { + /* Tag access disabled on an otherwise accessible page. */ + assert(atm_kind =3D=3D ATM_ASSERT_PAGES); + return 0; + } + if (r1.tag_mem =3D=3D NULL) { /* * If mtx is enabled, then the access is MemTag_CanonicallyTag= ged, * otherwise it is Untagged. See AArch64.S1DecodeMemAttrs and @@ -946,15 +966,22 @@ static int mte_probe_int(CPUARMState *env, uint32_t d= esc, uint64_t ptr, return 1; } /* Perform all of the comparisons. */ - n =3D checkN(mem1, ptr & TAG_GRANULE, ptr_tag, tag_count); + n =3D checkN(r1.tag_mem, ptr & TAG_GRANULE, ptr_tag, tag_count); } else { /* Memory access crosses to next page. */ - mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, next_page - p= tr, - MMU_DATA_LOAD, ra); + r1 =3D allocation_tag_mem_internal(env, mmu_idx, ptr, type, + next_page - ptr, MMU_DATA_LOAD, + ra, atm_kind); =20 - mem2 =3D allocation_tag_mem(env, mmu_idx, next_page, type, - ptr_last - next_page + 1, - MMU_DATA_LOAD, ra); + if (r1.flags & TLB_INVALID_MASK) { + /* Tag access disabled on an otherwise accessible page. */ + assert(atm_kind =3D=3D ATM_ASSERT_PAGES); + return 0; + } + + r2 =3D allocation_tag_mem_internal(env, mmu_idx, next_page, type, + ptr_last - next_page + 1, + MMU_DATA_LOAD, ra, atm_kind); =20 /* * Perform all of the comparisons. @@ -963,15 +990,18 @@ static int mte_probe_int(CPUARMState *env, uint32_t d= esc, uint64_t ptr, * happen with or without mtx (canonical tagging) enabled. */ n =3D c =3D (next_page - tag_first) / TAG_GRANULE; - if (mem1) { - n =3D checkN(mem1, ptr & TAG_GRANULE, ptr_tag, c); + if (r1.tag_mem) { + n =3D checkN(r1.tag_mem, ptr & TAG_GRANULE, ptr_tag, c); } else if (mtx_check(desc, bit55) && !tag_is_canonical(ptr_tag, bit55)) { return 0; } if (n =3D=3D c) { - if (mem2) { - n +=3D checkN(mem2, 0, ptr_tag, tag_count - c); + if (r2.flags & TLB_INVALID_MASK) { + /* Tag access disabled on an otherwise accessible page. */ + assert(atm_kind =3D=3D ATM_ASSERT_PAGES); + } else if (r2.tag_mem) { + n +=3D checkN(r2.tag_mem, 0, ptr_tag, tag_count - c); } else if (!mtx_check(desc, bit55) || tag_is_canonical(ptr_tag, bit55)) { return 1; @@ -997,7 +1027,7 @@ static int mte_probe_int(CPUARMState *env, uint32_t de= sc, uint64_t ptr, uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_= t ra) { uint64_t fault; - int ret =3D mte_probe_int(env, desc, ptr, ra, &fault); + int ret =3D mte_probe_int(env, desc, ptr, ra, &fault, ATM_NORMAL); =20 if (unlikely(ret =3D=3D 0)) { mte_check_fail(env, desc, fault, ra); @@ -1039,7 +1069,7 @@ uint64_t HELPER(mte_check)(CPUARMState *env, uint32_t= desc, uint64_t ptr) bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr) { uint64_t fault; - int ret =3D mte_probe_int(env, desc, ptr, 0, &fault); + int ret =3D mte_probe_int(env, desc, ptr, 0, &fault, ATM_ASSERT_PAGES); =20 return ret !=3D 0; } --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826408; cv=none; d=zohomail.com; s=zohoarc; b=gFCnHkf96ZbyN9AbbNmmMizLoeiFop3cm5Pv62KsMxOncKqF1kGHp4K6vV/2NFPxcAfnnFNcUaQmtdZsbsEU3V7b6gdd2lYYWPaL4cDPcNGVZn/D/fACUXIhE4YLj2/hxcovjyXIcp4vaV6EgdEDWcK0nuW6YIsSkgkwyidj4iQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786826408; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9QUKUc1DTLQNdki6YTXLbAayjzSGK/v6LBFa+ortZzU=; b=iaaQLDkYlU9CqcRwFLciv6OJVWWV8sqYV2Bt/fn1rpq9KNbBATsfWg59uFo39VjvOt5pNWVJyJ4yX6WDUzXOnQiuYR4plFC50UIQ0usnf5Z3y2QSZ9c9AyC+yqNCTzOxc664POD5Yypb+kZRLBv8xSJ03CV73I2m0hTm6kdI/tI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786826408707421.9812681327455; Sat, 15 Aug 2026 13:40:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wvL8e-00089t-KJ; Sat, 15 Aug 2026 16:37:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvL8c-000885-TA for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:55 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wvL8S-0008Ep-5x for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:47 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-38e7109321dso1472286a91.3 for ; Sat, 15 Aug 2026 13:37:43 -0700 (PDT) Received: from stoup.. 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We were failing to trap for the second page entirely in the user-only case, and when tag access is disabled on the first page for the system case. Signed-off-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 55 ++++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 22 deletions(-) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 31bf58c937..399bca30c9 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -130,6 +130,13 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr_= mmu_idx, g_assert_not_reached(); } } + if (atm_kind =3D=3D ATM_NORMAL) { + int in_page =3D -(ptr | TARGET_PAGE_MASK); + if (unlikely(ptr_size > in_page)) { + probe_access(env, ptr + in_page, ptr_size - in_page, + ptr_access, MMU_USER_IDX, ra); + } + } =20 /* Require both MAP_ANON and PROT_MTE for the page. */ if ((flags & PAGE_ANON) && (flags & PAGE_MTE)) { @@ -148,6 +155,7 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr_m= mu_idx, MemoryRegion *mr; ARMASIdx tag_asi; AddressSpace *tag_as; + uint8_t pte_attrs; =20 /* * Probe the first byte of the virtual address. This raises an @@ -161,9 +169,32 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr_= mmu_idx, assert(atm_kind =3D=3D ATM_PROBE_PAGES); goto fini; } + + /* + * Remember these across the second lookup below, + * which may invalidate this pointer via tlb resize. + */ + ptr_paddr =3D full->phys_addr | (ptr & ~TARGET_PAGE_MASK); + pte_attrs =3D full->extra.arm.pte_attrs; ret.attrs =3D full->attrs; =20 - switch (full->extra.arm.pte_attrs) { + /* + * The Normal memory access can extend to the next page. E.g. a single + * 8-byte access to the last byte of a page will check only the last + * tag on the first page. + * Any page access exception has priority over tag check exception. + */ + if (atm_kind =3D=3D ATM_NORMAL) { + int in_page =3D -(ptr | TARGET_PAGE_MASK); + if (unlikely(ptr_size > in_page)) { + void *discard_mem; + ret.flags |=3D probe_access_full(env, ptr + in_page, 0, ptr_ac= cess, + ptr_mmu_idx, false, + &discard_mem, &full, ra); + } + } + + switch (pte_attrs) { case 0xf0: /* Tagged */ break; =20 @@ -193,28 +224,8 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr_= mmu_idx, goto fini; } =20 - /* - * Remember this across the second lookup below, - * which may invalidate this pointer via tlb resize. - */ - ptr_paddr =3D full->phys_addr | (ptr & ~TARGET_PAGE_MASK); - - /* - * The Normal memory access can extend to the next page. E.g. a single - * 8-byte access to the last byte of a page will check only the last - * tag on the first page. - * Any page access exception has priority over tag check exception. - */ + /* Any debug exception has priority over a tag check exception. */ if (atm_kind =3D=3D ATM_NORMAL) { - int in_page =3D -(ptr | TARGET_PAGE_MASK); - if (unlikely(ptr_size > in_page)) { - void *discard_mem; - ret.flags |=3D probe_access_full(env, ptr + in_page, 0, ptr_ac= cess, - ptr_mmu_idx, false, - &discard_mem, &full, ra); - } - - /* Any debug exception has priority over a tag check exception. */ if (unlikely(ret.flags & TLB_WATCHPOINT)) { int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_= MEM_WRITE; cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826442; cv=none; d=zohomail.com; s=zohoarc; b=TGPBGQl7fd0z1qISHhIS+qHN9yCXNslAOh6aFBULB37MKKkABIyoYHFON+du3TxuFKpyevMvAstGvFM4dPMN9YX1MMpRYMOmrAQet/+WVxeSfNxBPHin49pcwhWqQhJQjyrXESE6VNYKw81/tc96eX5eE9dFQQWrVdqrStgNZzQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786826442; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Xpi+58NLvsNGE5roXXmz2yeQ2sLTmSOVbtvh5q+nBos=; b=OTYi531l0DR5WmnCPgK38Ffwr0nWW1q389/kJZKadOKe+ibvPyRyglNdBaEiwDAuPiFNytS9OIxqfmFZ6bxOQzQZ7IKsxhHEQRSvoHBHFrfEfBqCHdEkDeUK3KYi4iewbKiEQEnTm9QW+giEWJ8SPa/XjZYQcA+6tfR75/3aG8E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786826442231555.2586409178567; Sat, 15 Aug 2026 13:40:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wvL8e-00089z-NT; Sat, 15 Aug 2026 16:37:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvL8c-000889-UH for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:55 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wvL8T-0008Fl-4r for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:47 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-3900e39d935so2062006a91.0 for ; Sat, 15 Aug 2026 13:37:44 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/user-exec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index a35aca7889..3724e5d98e 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -749,7 +749,7 @@ int page_unprotect(CPUState *cpu, tb_page_addr_t addres= s, uintptr_t pc) } =20 static int probe_access_internal(CPUArchState *env, vaddr addr, - int fault_size, MMUAccessType access_type, + MMUAccessType access_type, bool nonfault, uintptr_t ra) { int acc_flag; @@ -797,7 +797,7 @@ int probe_access_flags(CPUArchState *env, vaddr addr, i= nt size, int flags; =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); - flags =3D probe_access_internal(env, addr, size, access_type, nonfault= , ra); + flags =3D probe_access_internal(env, addr, access_type, nonfault, ra); *phost =3D (flags & TLB_INVALID_MASK) ? NULL : g2h_vaddr(env_cpu(env),= addr); return flags; } @@ -808,7 +808,7 @@ void *probe_access(CPUArchState *env, vaddr addr, int s= ize, int flags; =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); - flags =3D probe_access_internal(env, addr, size, access_type, false, r= a); + flags =3D probe_access_internal(env, addr, access_type, false, ra); g_assert((flags & ~TLB_FORCE_SLOW) =3D=3D 0); =20 return size ? g2h_vaddr(env_cpu(env), addr) : NULL; @@ -825,7 +825,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *e= nv, vaddr addr, { int flags; =20 - flags =3D probe_access_internal(env, addr, 1, MMU_INST_FETCH, false, 0= ); + flags =3D probe_access_internal(env, addr, MMU_INST_FETCH, false, 0); g_assert(flags =3D=3D 0); =20 *hostp =3D g2h_untagged_vaddr(addr); --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826353; cv=none; d=zohomail.com; s=zohoarc; b=AH6r+yALnwDHf9NQzL+hLnQFy5qeTsqos/9Wh5Da2gxzjBYCI2owNw9RIgYuiMK7pPEp22AOrLFHn20MA7z3+1dsknVKl6H9bMQThQXM+5QVkhzUcmqRD+gsM4euF1KLreyLBkZm+i84IaYYgQh95f7J/ksSiBzI5/KdkGiOCdk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786826353; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bmDly23NRAJZVHzXBA8ZcB1bIBMliGfEqbn9ZrSxSas=; b=l8Brid7GN3KFKFqIEarXK+luZA50tW2OJe4N3eYh6l1OWOIR3QYojEi3zVaNSoH+zXTBLY3QSJZC0dUGydgd9bkix64XxJjRyljs9O6mNoxCtJSR3NXxO/9cJeUmOoPXcxxxSrCZwP/XPnSv5ZAsamGHRMK3FPuE9u3ZJTR5Wm4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786826353404805.0893984077151; Sat, 15 Aug 2026 13:39:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wvL8j-0008Gs-22; Sat, 15 Aug 2026 16:38:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvL8f-0008BH-Mv for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:57 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wvL8c-0008Ho-FF for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:57 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-38dc69c74b8so2298943a91.0 for ; Sat, 15 Aug 2026 13:37:46 -0700 (PDT) Received: from stoup.. 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Sat, 15 Aug 2026 13:37:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 07/18] accel/tcg: Replace size with first/last in probe_access_full Date: Sat, 15 Aug 2026 13:37:19 -0700 Message-ID: <20260815203730.1468365-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260815203730.1468365-1-richard.henderson@linaro.org> References: <20260815203730.1468365-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786826355092158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/accel/tcg/probe.h | 2 +- accel/tcg/cputlb.c | 17 +++++++++++------ target/arm/tcg/helper-a64.c | 5 ++++- target/arm/tcg/mte_helper.c | 21 ++++++++++++--------- target/arm/tcg/sve_helper.c | 5 ++++- target/mips/tcg/ldst_helper.c | 4 ++-- 6 files changed, 34 insertions(+), 20 deletions(-) diff --git a/include/accel/tcg/probe.h b/include/accel/tcg/probe.h index 0b788901ba..e3068a79de 100644 --- a/include/accel/tcg/probe.h +++ b/include/accel/tcg/probe.h @@ -86,7 +86,7 @@ int probe_access_flags(CPUArchState *env, vaddr addr, int= size, * This function will return TLB_MMIO in order to force the access * to be handled out-of-line if plugins wish to instrument the access. */ -int probe_access_full(CPUArchState *env, vaddr addr, int size, +int probe_access_full(CPUArchState *env, vaddr addr, vaddr first, vaddr la= st, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, CPUTLBEntryFull **pfull, uintptr_t retaddr); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 7f7c208ba1..6299cc73a4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1412,19 +1412,24 @@ static int probe_access_internal(CPUState *cpu, vad= dr addr, return flags; } =20 -int probe_access_full(CPUArchState *env, vaddr addr, int size, +int probe_access_full(CPUArchState *env, vaddr addr, vaddr first, vaddr la= st, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, CPUTLBEntryFull **pfull, uintptr_t retaddr) { - int flags =3D probe_access_internal(env_cpu(env), addr, size, access_t= ype, - mmu_idx, nonfault, phost, pfull, ret= addr, - true); + int flags; + + assert(first <=3D addr); + assert(addr <=3D last); + assert(((first ^ last) & TARGET_PAGE_MASK) =3D=3D 0); + + flags =3D probe_access_internal(env_cpu(env), addr, last - addr + 1, + access_type, mmu_idx, nonfault, + phost, pfull, retaddr, true); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { - int dirtysize =3D size =3D=3D 0 ? 1 : size; - notdirty_write(env_cpu(env), addr, dirtysize, *pfull, retaddr); + notdirty_write(env_cpu(env), first, last - first + 1, *pfull, reta= ddr); flags &=3D ~TLB_NOTDIRTY; } =20 diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 05ab9ab6d3..2e0e7cd756 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -1745,7 +1745,10 @@ static bool is_guarded_page(CPUARMState *env, vaddr = addr, uintptr_t ra) CPUTLBEntryFull *full; void *host; int mmu_idx =3D cpu_mmu_index(env_cpu(env), true); - int flags =3D probe_access_full(env, addr, 0, MMU_INST_FETCH, mmu_idx, + int flags =3D probe_access_full(env, addr, + addr & TARGET_PAGE_MASK, + addr | ~TARGET_PAGE_MASK, + MMU_INST_FETCH, mmu_idx, false, &host, &full, ra); =20 assert(!(flags & TLB_INVALID_MASK)); diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 399bca30c9..f36286d596 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -151,6 +151,7 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr_m= mu_idx, ret.flags =3D 0; #else CPUTLBEntryFull *full; + vaddr ptr_last, ptr_page_last; hwaddr ptr_paddr, tag_paddr, xlat; MemoryRegion *mr; ARMASIdx tag_asi; @@ -162,7 +163,11 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr_= mmu_idx, * exception for inaccessible pages, and resolves the virtual address * into the softmmu tlb. */ - ret.flags =3D probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx, + ptr_last =3D ptr + ptr_size - 1; + ptr_page_last =3D ptr | ~TARGET_PAGE_MASK; + + ret.flags =3D probe_access_full(env, ptr, ptr, MIN(ptr_last, ptr_page_= last), + ptr_access, ptr_mmu_idx, atm_kind >=3D ATM_PROBE_PAGES, &ret.ptr_mem, &full, ra); if (unlikely(ret.flags & TLB_INVALID_MASK)) { @@ -184,14 +189,12 @@ allocation_tag_mem_internal(CPUARMState *env, int ptr= _mmu_idx, * tag on the first page. * Any page access exception has priority over tag check exception. */ - if (atm_kind =3D=3D ATM_NORMAL) { - int in_page =3D -(ptr | TARGET_PAGE_MASK); - if (unlikely(ptr_size > in_page)) { - void *discard_mem; - ret.flags |=3D probe_access_full(env, ptr + in_page, 0, ptr_ac= cess, - ptr_mmu_idx, false, - &discard_mem, &full, ra); - } + if (atm_kind =3D=3D ATM_NORMAL && unlikely(ptr_page_last < ptr_last)) { + void *discard_mem; + ret.flags |=3D probe_access_full(env, ptr_page_last + 1, + ptr_page_last + 1, ptr_last, + ptr_access, ptr_mmu_idx, false, + &discard_mem, &full, ra); } =20 switch (pte_attrs) { diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index ac96b18784..4e77a824dd 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -6040,7 +6040,10 @@ bool sve_probe_page(SVEHostPage *info, bool nofault,= CPUARMState *env, &info->host, retaddr); #else CPUTLBEntryFull *full; - flags =3D probe_access_full(env, addr, 0, access_type, mmu_idx, nofaul= t, + flags =3D probe_access_full(env, addr, + addr & TARGET_PAGE_MASK, + addr | ~TARGET_PAGE_MASK, + access_type, mmu_idx, nofault, &info->host, &full, retaddr); #endif info->flags =3D flags; diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index 1b25466b49..065570a8f1 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -44,8 +44,8 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulon= g arg, \ int flags; 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Sat, 15 Aug 2026 13:37:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 08/18] accel/tcg: Replace size with first/last in probe_access_flags Date: Sat, 15 Aug 2026 13:37:20 -0700 Message-ID: <20260815203730.1468365-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260815203730.1468365-1-richard.henderson@linaro.org> References: <20260815203730.1468365-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_FILL_THIS_FORM_SHORT=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786826391245158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/accel/tcg/probe.h | 24 +++++++++++++++++------- accel/tcg/cputlb.c | 15 ++++++++------- accel/tcg/user-exec.c | 7 +++++-- semihosting/uaccess.c | 10 ++++------ target/arm/tcg/sve_helper.c | 5 ++++- target/riscv/tcg/op_helper.c | 4 ++-- target/riscv/tcg/vector_helper.c | 21 ++++++++++++--------- target/s390x/tcg/mem_helper.c | 4 ++-- 8 files changed, 54 insertions(+), 36 deletions(-) diff --git a/include/accel/tcg/probe.h b/include/accel/tcg/probe.h index e3068a79de..06faf1269d 100644 --- a/include/accel/tcg/probe.h +++ b/include/accel/tcg/probe.h @@ -49,23 +49,33 @@ static inline void *probe_read(CPUArchState *env, vaddr= addr, int size, /** * probe_access_flags: * @env: CPUArchState - * @addr: guest virtual address to look up - * @size: size of the access + * @addr: virtual address + * @first: beginning of virtual address range + * @last: end of virtual address range * @access_type: read, write or execute permission * @mmu_idx: MMU index to use for lookup * @nonfault: suppress the fault * @phost: return value for host address * @retaddr: return address for unwinding * - * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for - * the page, and storing the host address for RAM in @phost. + * Probe an access for [@first, @last], where @addr is somewhere + * in that range. Normally @addr =3D=3D @first, but some targets have + * accesses which are forcibly aligned after an initial fault for an + * inaccessible page (e.g. Arm DC_ZVA, where [@first, @last] will be + * the bounds of the cacheline containing @addr). + * + * If the access does not satisfy @access_type: + * - if @nonfault is false, raise an exception at @addr + * - otherwise return TLB_INVALID_MASK. + * + * Otherwise, return the TLB_FLAGS_MASK for the page, and set @phost: + * - host address for @addr, if direct host accesses are allowed, + * - otherwise NULL. * - * If @nonfault is set, do not raise an exception but return TLB_INVALID_M= ASK. * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned f= lags. * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. - * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. */ -int probe_access_flags(CPUArchState *env, vaddr addr, int size, +int probe_access_flags(CPUArchState *env, vaddr addr, vaddr first, vaddr l= ast, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr); =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6299cc73a4..a192c50e90 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1460,23 +1460,24 @@ int probe_access_full_mmu(CPUArchState *env, vaddr = addr, int size, return flags; } =20 -int probe_access_flags(CPUArchState *env, vaddr addr, int size, +int probe_access_flags(CPUArchState *env, vaddr addr, vaddr first, vaddr l= ast, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) { CPUTLBEntryFull *full; int flags; =20 - g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); + assert(first <=3D addr); + assert(addr <=3D last); + assert(((first ^ last) & TARGET_PAGE_MASK) =3D=3D 0); =20 - flags =3D probe_access_internal(env_cpu(env), addr, size, access_type, - mmu_idx, nonfault, phost, &full, retaddr, - true); + flags =3D probe_access_internal(env_cpu(env), addr, last - addr + 1, + access_type, mmu_idx, nonfault, + phost, &full, retaddr, true); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { - int dirtysize =3D size =3D=3D 0 ? 1 : size; - notdirty_write(env_cpu(env), addr, dirtysize, full, retaddr); + notdirty_write(env_cpu(env), first, last - first + 1, full, retadd= r); flags &=3D ~TLB_NOTDIRTY; } =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3724e5d98e..44e9f7fa1a 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -790,13 +790,16 @@ static int probe_access_internal(CPUArchState *env, v= addr addr, cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra); } =20 -int probe_access_flags(CPUArchState *env, vaddr addr, int size, +int probe_access_flags(CPUArchState *env, vaddr addr, vaddr first, vaddr l= ast, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { int flags; =20 - g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); + assert(first <=3D addr); + assert(addr <=3D first); + assert(((first ^ last) & TARGET_PAGE_MASK) =3D=3D 0); + flags =3D probe_access_internal(env, addr, access_type, nonfault, ra); *phost =3D (flags & TLB_INVALID_MASK) ? NULL : g2h_vaddr(env_cpu(env),= addr); return flags; diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index ff944d8c2f..1efe8464d7 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -33,15 +33,13 @@ ssize_t uaccess_strlen_user(CPUArchState *env, vaddr ad= dr) size_t len =3D 0; =20 while (1) { - size_t left_in_page; + vaddr last_in_page =3D addr | ~TARGET_PAGE_MASK; + size_t left_in_page =3D last_in_page - addr + 1; int flags; void *h; =20 - /* Find the number of bytes remaining in the page. */ - left_in_page =3D TARGET_PAGE_SIZE - (addr & ~TARGET_PAGE_MASK); - - flags =3D probe_access_flags(env, addr, 0, MMU_DATA_LOAD, - mmu_idx, true, &h, 0); + flags =3D probe_access_flags(env, addr, addr, last_in_page, + MMU_DATA_LOAD, mmu_idx, true, &h, 0); if (flags & TLB_INVALID_MASK) { return -1; } diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 4e77a824dd..b824933694 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -6036,7 +6036,10 @@ bool sve_probe_page(SVEHostPage *info, bool nofault,= CPUARMState *env, addr =3D useronly_clean_ptr(addr); =20 #ifdef CONFIG_USER_ONLY - flags =3D probe_access_flags(env, addr, 0, access_type, mmu_idx, nofau= lt, + flags =3D probe_access_flags(env, addr, + addr & TARGET_PAGE_MASK, + addr | ~TARGET_PAGE_MASK, + access_type, mmu_idx, nofault, &info->host, retaddr); #else CPUTLBEntryFull *full; diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index a7bd42d2c6..b18bf683f4 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -250,8 +250,8 @@ static void check_zicbom_access(CPURISCVState *env, * addresses, whether a cache-block management instruction is * permitted to access the cache block is UNSPECIFIED." */ - ret =3D probe_access_flags(env, address, cbomlen, MMU_DATA_LOAD, - mmu_idx, true, &phost, ra); + ret =3D probe_access_flags(env, address, address, address + cbomlen - = 1, + MMU_DATA_LOAD, mmu_idx, true, &phost, ra); if (ret !=3D TLB_INVALID_MASK) { /* Success: readable */ return; diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_hel= per.c index b7b3805a6d..87f2196bc7 100644 --- a/target/riscv/tcg/vector_helper.c +++ b/target/riscv/tcg/vector_helper.c @@ -704,7 +704,7 @@ vext_ldff(void *vd, target_ulong base, CPURISCVState *e= nv, uint32_t esz =3D 1 << log2_esz; uint32_t msize =3D nf * esz; uint32_t vma =3D vext_vma(desc); - target_ulong addr, last, last_in_page, page_split, elems; + target_ulong addr, last, last_in_page, page_split, elems, adj, adj_las= t; MemOpIdx oi =3D vext_oi(desc, log2_esz); int mmu_index =3D get_mmuidx(oi); bool first_active; @@ -759,10 +759,10 @@ vext_ldff(void *vd, target_ulong base, CPURISCVState = *env, * Test whether the first page is accessible. * If the first element is active, it must succeed. */ - flags =3D probe_access_flags(env, adjust_addr(env, addr), - MIN(last, last_in_page) - addr + 1, - MMU_DATA_LOAD, mmu_index, !first_active, - &host, ra); + adj =3D adjust_addr(env, addr); + adj_last =3D MIN(last, last_in_page) - (addr - adj); + flags =3D probe_access_flags(env, adj, adj, adj_last, MMU_DATA_LOAD, + mmu_index, !first_active, &host, ra); =20 /* Get number of complete elements in the first page. */ elems =3D MIN(page_split / msize, vl - i); @@ -853,8 +853,10 @@ vext_ldff(void *vd, target_ulong base, CPURISCVState *= env, * We have not yet advanced addr to the next page. */ target_ulong next_page =3D addr + page_split; - flags |=3D probe_access_flags(env, adjust_addr(env, next_page), - last - next_page + 1, MMU_DATA_LOAD, + + adj =3D adjust_addr(env, next_page); + adj_last =3D last - (next_page - adj); + flags |=3D probe_access_flags(env, adj, adj, adj_last, MMU_DATA_LO= AD, mmu_index, true, &host, ra); =20 /* Stop if invalid (unmapped) or mmio (transaction may fail). */ @@ -873,8 +875,9 @@ vext_ldff(void *vd, target_ulong base, CPURISCVState *e= nv, host +=3D addr - next_page; } } else { - flags =3D probe_access_flags(env, adjust_addr(env, addr), - last - addr + 1, MMU_DATA_LOAD, + adj =3D adjust_addr(env, addr); + adj_last =3D last - (addr - adj); + flags =3D probe_access_flags(env, adj, adj, adj_last, MMU_DATA_LOA= D, mmu_index, true, &host, ra); =20 /* Stop if invalid (unmapped) or mmio (transaction may fail). */ diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 414e6838c8..d490434806 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -155,8 +155,8 @@ static inline int s390_probe_access(CPUArchState *env, = vaddr addr, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { - int flags =3D probe_access_flags(env, addr, size, access_type, mmu_idx, - nonfault, phost, ra); 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The one instance so far is riscv check_zicbom_access. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/accel/tcg/probe.h | 3 ++- accel/tcg/cputlb.c | 4 +++- accel/tcg/user-exec.c | 5 ++++- target/riscv/tcg/op_helper.c | 3 +-- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/include/accel/tcg/probe.h b/include/accel/tcg/probe.h index 06faf1269d..477320c88d 100644 --- a/include/accel/tcg/probe.h +++ b/include/accel/tcg/probe.h @@ -68,7 +68,8 @@ static inline void *probe_read(CPUArchState *env, vaddr a= ddr, int size, * - if @nonfault is false, raise an exception at @addr * - otherwise return TLB_INVALID_MASK. * - * Otherwise, return the TLB_FLAGS_MASK for the page, and set @phost: + * Otherwise, return the TLB_FLAGS_MASK for the page, + * and, if @phost is not NULL, set @phost: * - host address for @addr, if direct host accesses are allowed, * - otherwise NULL. * diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a192c50e90..c2ea31a397 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1465,6 +1465,7 @@ int probe_access_flags(CPUArchState *env, vaddr addr,= vaddr first, vaddr last, bool nonfault, void **phost, uintptr_t retaddr) { CPUTLBEntryFull *full; + void *discard_host; int flags; =20 assert(first <=3D addr); @@ -1473,7 +1474,8 @@ int probe_access_flags(CPUArchState *env, vaddr addr,= vaddr first, vaddr last, =20 flags =3D probe_access_internal(env_cpu(env), addr, last - addr + 1, access_type, mmu_idx, nonfault, - phost, &full, retaddr, true); + phost ? phost : &discard_host, + &full, retaddr, true); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 44e9f7fa1a..3578282a3d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -801,7 +801,10 @@ int probe_access_flags(CPUArchState *env, vaddr addr, = vaddr first, vaddr last, assert(((first ^ last) & TARGET_PAGE_MASK) =3D=3D 0); =20 flags =3D probe_access_internal(env, addr, access_type, nonfault, ra); - *phost =3D (flags & TLB_INVALID_MASK) ? NULL : g2h_vaddr(env_cpu(env),= addr); + if (phost) { + *phost =3D (flags & TLB_INVALID_MASK ? NULL + : g2h_vaddr(env_cpu(env), addr)); + } return flags; } =20 diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index b18bf683f4..9c0cfd35fc 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -232,7 +232,6 @@ static void check_zicbom_access(CPURISCVState *env, RISCVCPU *cpu =3D env_archcpu(env); int mmu_idx =3D riscv_env_mmu_index(env, false); uint16_t cbomlen =3D cpu->cfg.cbom_blocksize; - void *phost; int ret; =20 /* Mask off low-bits to align-down to the cache-block. */ @@ -251,7 +250,7 @@ static void check_zicbom_access(CPURISCVState *env, * permitted to access the cache block is UNSPECIFIED." */ ret =3D probe_access_flags(env, address, address, address + cbomlen - = 1, - MMU_DATA_LOAD, mmu_idx, true, &phost, ra); + MMU_DATA_LOAD, mmu_idx, true, NULL, ra); if (ret !=3D TLB_INVALID_MASK) { /* Success: readable */ return; --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826398; cv=none; d=zohomail.com; s=zohoarc; b=BPRT4i2mq4AunfIfLbksfOgOrxEOwjyWL5IF30Nx8WVhOaUpv98Nu6DCuWHH+sZG+vuf+scgEUT5pQm7+9RhNwpqVje92ZyNh6ekEU8SOGG5FVcJKhpOfQaYrYATUP9hIhD5sx5/UN3xc9MnIGhJfBNQHqIZlX0jpuCozSS2r4s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786826398; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=m/W0Rg3ZT8aB8ztQ7+mQ84An4E9x9bWgouBn0XbAmNY=; b=V9VuV3jUaW2ARrV7Zi5plSmI2FEVlwEdKyT/LMxWC9IK1L3C/6zYq/FLrhhZaDKykLCLuHI9ZYVhDSoya56f/SnMVPMzLbqXKjH2pciwJp8f3U9f21NcGMHagvhvXrZrOitUuVMhRZ84BJDqGw/hbFwY22T5k0vlcvlvxNALYlo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786826398585199.81581872724826; Sat, 15 Aug 2026 13:39:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wvL8m-0008Jl-BN; Sat, 15 Aug 2026 16:38:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvL8i-0008FH-6q for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:38:00 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wvL8c-0008Im-HD for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:59 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-2cc7e86e7aeso23237575ad.2 for ; Sat, 15 Aug 2026 13:37:48 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c2ea31a397..b8c23b2948 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1358,8 +1358,8 @@ static void notdirty_write(CPUState *cpu, vaddr mem_v= addr, unsigned size, } } =20 -static int probe_access_internal(CPUState *cpu, vaddr addr, - int fault_size, MMUAccessType access_type, +static int probe_access_internal(CPUState *cpu, vaddr addr, vaddr first, + vaddr last, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, CPUTLBEntryFull **pfull, uintptr_t retaddr, bool check_mem_cbs) @@ -1375,7 +1375,7 @@ static int probe_access_internal(CPUState *cpu, vaddr= addr, if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, page_addr)) { if (!tlb_fill_align(cpu, addr, access_type, mmu_idx, - 0, fault_size, nonfault, retaddr)) { + 0, last - addr + 1, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; *pfull =3D NULL; @@ -1423,7 +1423,7 @@ int probe_access_full(CPUArchState *env, vaddr addr, = vaddr first, vaddr last, assert(addr <=3D last); assert(((first ^ last) & TARGET_PAGE_MASK) =3D=3D 0); =20 - flags =3D probe_access_internal(env_cpu(env), addr, last - addr + 1, + flags =3D probe_access_internal(env_cpu(env), addr, first, last, access_type, mmu_idx, nonfault, phost, pfull, retaddr, true); =20 @@ -1440,6 +1440,7 @@ int probe_access_full_mmu(CPUArchState *env, vaddr ad= dr, int size, MMUAccessType access_type, int mmu_idx, void **phost, CPUTLBEntryFull **pfull) { + vaddr last =3D size ? addr + size - 1 : addr; void *discard_phost; CPUTLBEntryFull *discard_tlb; =20 @@ -1447,13 +1448,13 @@ int probe_access_full_mmu(CPUArchState *env, vaddr = addr, int size, phost =3D phost ? phost : &discard_phost; pfull =3D pfull ? pfull : &discard_tlb; =20 - int flags =3D probe_access_internal(env_cpu(env), addr, size, access_t= ype, - mmu_idx, true, phost, pfull, 0, fals= e); + int flags =3D probe_access_internal(env_cpu(env), addr, addr, last, + access_type, mmu_idx, true, phost, + pfull, 0, false); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { - int dirtysize =3D size =3D=3D 0 ? 1 : size; - notdirty_write(env_cpu(env), addr, dirtysize, *pfull, 0); + notdirty_write(env_cpu(env), addr, last - addr + 1, *pfull, 0); flags &=3D ~TLB_NOTDIRTY; } =20 @@ -1472,7 +1473,7 @@ int probe_access_flags(CPUArchState *env, vaddr addr,= vaddr first, vaddr last, assert(addr <=3D last); assert(((first ^ last) & TARGET_PAGE_MASK) =3D=3D 0); =20 - flags =3D probe_access_internal(env_cpu(env), addr, last - addr + 1, + flags =3D probe_access_internal(env_cpu(env), addr, first, last, access_type, mmu_idx, nonfault, phost ? phost : &discard_host, &full, retaddr, true); @@ -1489,15 +1490,16 @@ int probe_access_flags(CPUArchState *env, vaddr add= r, vaddr first, vaddr last, void *probe_access(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr) { + vaddr last =3D size ? addr + size - 1 : addr; CPUTLBEntryFull *full; void *host; int flags; =20 - g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); + assert(((addr ^ last) & TARGET_PAGE_MASK) =3D=3D 0); =20 - flags =3D probe_access_internal(env_cpu(env), addr, size, access_type, - mmu_idx, false, &host, &full, retaddr, - true); + flags =3D probe_access_internal(env_cpu(env), addr, addr, last, + access_type, mmu_idx, false, + &host, &full, retaddr, true); =20 /* Per the interface, size =3D=3D 0 merely faults the access. */ if (size =3D=3D 0) { @@ -1529,7 +1531,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, void *host; int flags; =20 - flags =3D probe_access_internal(env_cpu(env), addr, 0, access_type, + flags =3D probe_access_internal(env_cpu(env), addr, addr, addr, access= _type, mmu_idx, true, &host, &full, 0, false); =20 /* No combination of flags are expected by the caller. */ @@ -1552,9 +1554,10 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState= *env, vaddr addr, CPUTLBEntryFull *full; void *p; =20 - (void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH, - cpu_mmu_index(env_cpu(env), true), false, - hostp, &full, 0, false); + (void)probe_access_internal(env_cpu(env), addr, addr, addr, + MMU_INST_FETCH, + cpu_mmu_index(env_cpu(env), true), + false, hostp, &full, 0, false); =20 p =3D *hostp; if (p =3D=3D NULL) { --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826402; cv=none; d=zohomail.com; s=zohoarc; b=C8ueWvacZLQpUx9TIoLZhlZEamQCIiOqnHx1jotCT7BGuwb931txgf9S/Mwumiv2L3+SmS/UPvLpMNi2I3vOfbJfGOGuVx67WmTZWvlY1zGbi77SE9BLijlUo1r4X8d1jQ6TGW1QWvyEdfbpwIIYSnkC9C/9LCkKESJf7PT5Y5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786826402; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Zk4qMQYX28j97m/g2YYmzDXr2lMBSgsykgiPV83NOik=; b=QNCht+C9Ms7jM1/CnYhYuXjyNewhLK7t3fwBLGKmNQoympYRYgsYY9bWoNx6cC7NHcxTxb5wD1F0aDD+RXkRLbyj95UT5NE8NM4hBEln6cF62U80b2TnGpR7rgOw/Bdgtnx7xqC18yIUeM61Geaa9h0CYOpJXWtG7AXISM7kj5A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786826402791670.6556381389365; Sat, 15 Aug 2026 13:40:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wvL8i-0008Er-1V; Sat, 15 Aug 2026 16:38:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvL8f-0008BB-KF for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:57 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wvL8c-0008JD-FQ for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:57 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-2d02b4c3601so24310815ad.3 for ; Sat, 15 Aug 2026 13:37:49 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b8c23b2948..95db2c22e2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1236,11 +1236,12 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr= addr) * (e.g. CPUTLBEntry pointers) must be discarded and looked up again * (e.g. via tlb_entry()). */ -static bool tlb_fill_align(CPUState *cpu, vaddr addr, MMUAccessType type, - int mmu_idx, MemOp memop, int size, +static bool tlb_fill_align(CPUState *cpu, vaddr addr, vaddr first, vaddr l= ast, + MMUAccessType type, int mmu_idx, MemOp memop, bool probe, uintptr_t ra) { const TCGCPUOps *ops =3D cpu->cc->tcg_ops; + int size =3D last - addr + 1; CPUTLBEntryFull full; =20 if (ops->tlb_fill_align) { @@ -1374,8 +1375,8 @@ static int probe_access_internal(CPUState *cpu, vaddr= addr, vaddr first, =20 if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, page_addr)) { - if (!tlb_fill_align(cpu, addr, access_type, mmu_idx, - 0, last - addr + 1, nonfault, retaddr)) { + if (!tlb_fill_align(cpu, addr, first, last, access_type, + mmu_idx, MO_UNALN, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; *pfull =3D NULL; @@ -1664,8 +1665,8 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageD= ata *data, MemOp memop, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { - tlb_fill_align(cpu, addr, access_type, mmu_idx, - memop, data->size, false, ra); + tlb_fill_align(cpu, addr, addr, addr + data->size - 1, + access_type, mmu_idx, memop, false, ra); maybe_resized =3D true; index =3D tlb_index(cpu, mmu_idx, addr); entry =3D tlb_entry(cpu, mmu_idx, addr); @@ -1833,8 +1834,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr a= ddr, MemOpIdx oi, if (!tlb_hit(tlb_addr, addr)) { if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE, addr & TARGET_PAGE_MASK)) { - tlb_fill_align(cpu, addr, MMU_DATA_STORE, mmu_idx, - mop, size, false, retaddr); + tlb_fill_align(cpu, addr, addr, addr + size - 1, + MMU_DATA_STORE, mmu_idx, mop, false, retaddr); did_tlb_fill =3D true; index =3D tlb_index(cpu, mmu_idx, addr); tlbe =3D tlb_entry(cpu, mmu_idx, addr); @@ -1849,8 +1850,8 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr a= ddr, MemOpIdx oi, * but addr_read will only be -1 if PAGE_READ was unset. */ if (unlikely(tlbe->addr_read =3D=3D -1)) { - tlb_fill_align(cpu, addr, MMU_DATA_LOAD, mmu_idx, - 0, size, false, retaddr); + tlb_fill_align(cpu, addr, addr, addr + size - 1, + MMU_DATA_LOAD, mmu_idx, 0, false, retaddr); /* * Since we don't support reads and writes to different * addresses, and we do have the proper page loaded for --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826341; cv=none; d=zohomail.com; s=zohoarc; b=n6iqA+ma6sXOHm4Na2cFQhqEYJhA2lYqjvsLg3unpFzoJDX0qn5snpE7uFa/f4RosRD7arO6S41hm95/q/XDKlE9Tpce8gImcS0AqfoEutHgF7tFP0YSu/bgVRFi1aDgMnNrvRn9saa5ROoZvlGGNJc+VW4hzLabcZT6oshITqg= ARC-Message-Signature: i=1; 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Additionally, where was an edge case of size =3D=3D 0 which was ambiguous, and is now eliminated. Only change the functional interface. Where required by the callee, rebuild "size =3D last - addr + 1" locally. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/accel/tcg/cpu-ops.h | 16 ++++++++++++---- target/alpha/cpu.h | 2 +- target/arm/internals.h | 5 +++-- target/avr/cpu.h | 2 +- target/hppa/cpu.h | 5 +++-- target/i386/tcg/helper-tcg.h | 2 +- target/loongarch/tcg/tcg_loongarch.h | 2 +- target/m68k/cpu.h | 2 +- target/microblaze/cpu.h | 2 +- target/mips/tcg/tcg-internal.h | 2 +- target/or1k/cpu.h | 2 +- target/ppc/internal.h | 2 +- target/riscv/cpu.h | 2 +- target/s390x/s390x-internal.h | 2 +- target/sh4/cpu.h | 2 +- target/sparc/cpu.h | 2 +- target/tricore/cpu.h | 2 +- target/xtensa/cpu.h | 2 +- accel/tcg/cputlb.c | 7 +++---- target/alpha/helper.c | 2 +- target/arm/tcg/tlb_helper.c | 5 +++-- target/avr/helper.c | 2 +- target/hexagon/cpu.c | 8 +++++--- target/hppa/mem_helper.c | 6 ++++-- target/i386/tcg/system/excp_helper.c | 2 +- target/loongarch/tcg/tlb_helper.c | 3 ++- target/m68k/helper.c | 3 ++- target/microblaze/helper.c | 2 +- target/mips/tcg/system/tlb_helper.c | 2 +- target/or1k/mmu.c | 2 +- target/ppc/mmu_helper.c | 2 +- target/riscv/tcg/cpu_helper.c | 3 ++- target/rx/cpu.c | 2 +- target/s390x/tcg/excp_helper.c | 2 +- target/sh4/helper.c | 2 +- target/sparc/mmu_helper.c | 4 ++-- target/tricore/helper.c | 2 +- target/xtensa/helper.c | 2 +- 38 files changed, 68 insertions(+), 51 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 3ff6e6810e..4f162ae5b0 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -196,13 +196,20 @@ struct TCGCPUOps { * @cpu: cpu context * @out: output page properties * @addr: virtual address + * @first: beginning of virtual address range + * @last: end of virtual address range * @access_type: read, write or execute * @mmu_idx: mmu context * @memop: memory operation for the access - * @size: memory access size, or 0 for whole page * @probe: test only, no fault * @ra: host return address for exception unwind * + * The access in progress is [@first, @last], where @addr is somewhere + * in that range. Normally @addr =3D=3D @first, but some targets have + * accesses which are forcibly aligned after an initial fault for an + * inaccessible page (e.g. Arm DC_ZVA, where [@first, @last] will be + * the bounds of the cacheline containing @addr). + * * If the access is valid, fill in @out and return true. * Otherwise if probe is true, return false. * Otherwise raise an exception and do not return. @@ -213,9 +220,10 @@ struct TCGCPUOps { * Zero may be passed for @memop to skip any alignment check * for non-memory-access operations such as probing. */ - bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, + bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, + vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, - MemOp memop, int size, bool probe, uintptr_t ra= ); + MemOp memop, bool probe, uintptr_t ra); /** * @tlb_fill: Handle a softmmu tlb miss * @@ -223,7 +231,7 @@ struct TCGCPUOps { * if the access is invalid and probe is true, return false; * otherwise raise an exception and do not return. */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + bool (*tlb_fill)(CPUState *cpu, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); /** diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 378bd96d94..1ee3a6855e 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -450,7 +450,7 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr addre= ss, void alpha_cpu_record_sigbus(CPUState *cs, vaddr address, MMUAccessType access_type, uintptr_t retaddr); #else -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); G_NORETURN void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, diff --git a/target/arm/internals.h b/target/arm/internals.h index 4026f67579..6457fa06ee 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1011,9 +1011,10 @@ void arm_cpu_record_sigsegv(CPUState *cpu, vaddr add= r, void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, MMUAccessType access_type, uintptr_t ra); #else -bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, +bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, - MemOp memop, int size, bool probe, uintptr_t r= a); + MemOp memop, bool probe, uintptr_t ra); #endif =20 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index a818db753b..e40367b832 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -233,7 +233,7 @@ static inline void cpu_set_sreg(CPUAVRState *env, uint8= _t sreg) env->sregI =3D (sreg >> 7) & 0x01; } =20 -bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool avr_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f453444d7f..bbf44ea220 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -391,9 +391,10 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); void hppa_ptlbe(CPUHPPAState *env); hwaddr hppa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr); void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled= ); -bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr add= r, +bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, - MemOp memop, int size, bool probe, uintptr_t = ra); + MemOp memop, bool probe, uintptr_t ra); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index f4b2ff740d..ba0a4da322 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -78,7 +78,7 @@ void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, void x86_cpu_record_sigbus(CPUState *cs, vaddr addr, MMUAccessType access_type, uintptr_t ra); #else -bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); G_NORETURN void x86_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tc= g_loongarch.h index 7fb627f2d6..1d43dbc751 100644 --- a/target/loongarch/tcg/tcg_loongarch.h +++ b/target/loongarch/tcg/tcg_loongarch.h @@ -12,7 +12,7 @@ extern const TCGCPUOps loongarch_tcg_ops; void loongarch_csr_translate_init(void); =20 -bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr l= ast, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7cf3791108..08bdf27c7e 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -585,7 +585,7 @@ enum { #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 1 =20 -bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool m68k_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); #ifndef CONFIG_USER_ONLY diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b9602f72b9..08d2a8f843 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -413,7 +413,7 @@ void mb_translate_code(CPUState *cs, TranslationBlock *= tb, QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); =20 #if !defined(CONFIG_USER_ONLY) -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool mb_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 950e6afc3f..de179d0d5f 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -63,7 +63,7 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr = physaddr, MemTxResult response, uintptr_t retadd= r); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool mips_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 diff --git a/target/or1k/cpu.h b/target/or1k/cpu.h index fc4387ce7a..8a6293c030 100644 --- a/target/or1k/cpu.h +++ b/target/or1k/cpu.h @@ -298,7 +298,7 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *inf= o); #ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); =20 -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr la= st, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 diff --git a/target/ppc/internal.h b/target/ppc/internal.h index a3bb12afd9..3a80719a16 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -292,7 +292,7 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); #else -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); G_NORETURN void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e980b5964d..ed712761d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -659,7 +659,7 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env,= bool virt); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); -bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 35d1e34ef4..559a8d9201 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -271,7 +271,7 @@ void s390_cpu_record_sigsegv(CPUState *cs, vaddr addres= s, void s390_cpu_record_sigbus(CPUState *cs, vaddr address, MMUAccessType access_type, uintptr_t retaddr); #else -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool s390_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); G_NORETURN void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 3302702376..be377d4178 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -252,7 +252,7 @@ void sh4_translate_code(CPUState *cs, TranslationBlock = *tb, =20 #if !defined(CONFIG_USER_ONLY) hwaddr superh_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); -bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool superh_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); void superh_cpu_do_interrupt(CPUState *cpu); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5f583ed9de..13ec3f4a3a 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -596,7 +596,7 @@ G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *,= int, uintptr_t); /* cpu_init.c */ void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); /* mmu_helper.c */ -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmule= v); diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 12e497d2a7..880c5e0067 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -260,7 +260,7 @@ void tricore_translate_code(CPUState *cs, TranslationBl= ock *tb, #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU =20 /* helpers.c */ -bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool tricore_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr las= t, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 442e98bd1b..46660a7dad 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -581,7 +581,7 @@ struct XtensaCPUClass { }; =20 #ifndef CONFIG_USER_ONLY -bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 95db2c22e2..d559ce1ef6 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1241,12 +1241,11 @@ static bool tlb_fill_align(CPUState *cpu, vaddr add= r, vaddr first, vaddr last, bool probe, uintptr_t ra) { const TCGCPUOps *ops =3D cpu->cc->tcg_ops; - int size =3D last - addr + 1; CPUTLBEntryFull full; =20 if (ops->tlb_fill_align) { - if (ops->tlb_fill_align(cpu, &full, addr, type, mmu_idx, - memop, size, probe, ra)) { + if (ops->tlb_fill_align(cpu, &full, addr, first, last, type, mmu_i= dx, + memop, probe, ra)) { tlb_set_page_full(cpu, mmu_idx, addr, &full); return true; } @@ -1255,7 +1254,7 @@ static bool tlb_fill_align(CPUState *cpu, vaddr addr,= vaddr first, vaddr last, if (addr & ((1u << memop_alignment_bits(memop)) - 1)) { ops->do_unaligned_access(cpu, addr, type, mmu_idx, ra); } - if (ops->tlb_fill(cpu, addr, size, type, mmu_idx, probe, ra)) { + if (ops->tlb_fill(cpu, addr, first, last, type, mmu_idx, probe, ra= )) { return true; } } diff --git a/target/alpha/helper.c b/target/alpha/helper.c index c3614ecafd..d24b206388 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -307,7 +307,7 @@ hwaddr alpha_cpu_get_phys_addr_debug(CPUState *cs, vadd= r addr) return (fail >=3D 0 ? -1 : phys); } =20 -bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 4c3f16dc2a..826daf6772 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -353,9 +353,10 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } =20 -bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr= ess, +bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr address, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, - MemOp memop, int size, bool probe, uintptr_t r= a) + MemOp memop, bool probe, uintptr_t ra) { ARMCPU *cpu =3D ARM_CPU(cs); GetPhysAddrResult res =3D {}; diff --git a/target/avr/helper.c b/target/avr/helper.c index f452c9d904..b5cbdc7b2c 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -113,7 +113,7 @@ hwaddr avr_cpu_get_phys_addr_debug(CPUState *cs, vaddr = addr) return addr; /* I assume 1:1 address correspondence */ } =20 -bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 0ddd898e6e..bfcd9b6159 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -666,11 +666,13 @@ static const char *access_type_names[] =3D { "MMU_DAT= A_LOAD ", "MMU_DATA_STORE", static const char *mmu_idx_names[] =3D { "MMU_USER_IDX", "MMU_GUEST_IDX", "MMU_KERNEL_IDX" }; =20 -static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, bool = probe, - uintptr_t retaddr) +static bool hexagon_tlb_fill(CPUState *cs, vaddr address, + vaddr first, vaddr last, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { CPUHexagonState *env =3D cpu_env(cs); + int size =3D last - address + 1; int slot =3D 0; hwaddr phys; int prot =3D 0; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 01e6149c81..0427fd0917 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -435,11 +435,13 @@ void hppa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, } } =20 -bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr add= r, +bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, vaddr first, vaddr last, MMUAccessType type, int mmu_idx, - MemOp memop, int size, bool probe, uintptr_t = ra) + MemOp memop, bool probe, uintptr_t ra) { CPUHPPAState *env =3D cpu_env(cs); + int size =3D last - addr + 1; int prot, excp, a_prot; hwaddr phys; =20 diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index d7ea77c855..fd21287a8b 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -610,7 +610,7 @@ static bool get_physical_address(CPUX86State *env, vadd= r addr, return true; } =20 -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, +bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index a4b90beca6..08c992d774 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -630,7 +630,8 @@ static void ptw_update_tlb(CPULoongArchState *env, MMUC= ontext *context) update_tlb_index(env, context, index); } =20 -bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, + vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 5f91d206f5..c15fb1bc05 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -954,11 +954,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint= 8_t vector) } } =20 -bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, vaddr first, vaddr las= t, MMUAccessType qemu_access_type, int mmu_idx, bool probe, uintptr_t retaddr) { CPUM68KState *env =3D cpu_env(cs); + int size =3D last - address + 1; hwaddr physical; int prot; int access_type; diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 05a90f5ecb..65c73951ca 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -85,7 +85,7 @@ static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, } } =20 -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index 4398c6f80b..a54a98dd08 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -906,7 +906,7 @@ refill: } #endif =20 -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, vaddr first, vaddr las= t, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/or1k/mmu.c b/target/or1k/mmu.c index 3fc56e1b77..a3c0fd7089 100644 --- a/target/or1k/mmu.c +++ b/target/or1k/mmu.c @@ -104,7 +104,7 @@ static void raise_mmu_exception(OpenRISCCPU *cpu, vaddr= address, cpu->env.lock_addr =3D -1; } =20 -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr la= st, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index ac60705402..0edaeab045 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1358,7 +1358,7 @@ void helper_check_tlb_flush_global(CPUPPCState *env) } =20 =20 -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int size, +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, vaddr first, vaddr last, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 07d9222652..11f2654da1 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -1649,12 +1649,13 @@ static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MM= UAccessType access_type) riscv_pmu_incr_ctr(cpu, pmu_event_type); } =20 -bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, vaddr first, vaddr la= st, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + int size =3D last - address + 1; vaddr im_address; hwaddr pa =3D 0; int prot, prot2, prot_pmp; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 20b188c24c..5d955c3763 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -185,7 +185,7 @@ static void rx_cpu_disas_set_info(const CPUState *cpu, = disassemble_info *info) info->print_insn =3D print_insn_rx; } =20 -static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, +static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, vaddr first, vaddr l= ast, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index d952bb20cf..d9f68e1afc 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -145,7 +145,7 @@ static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) } } =20 -bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, vaddr first, vaddr las= t, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/sh4/helper.c b/target/sh4/helper.c index b6b057f104..1fe1fe0275 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -798,7 +798,7 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) return false; } =20 -bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, vaddr first, vaddr l= ast, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 07ba25dfce..cab476006a 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -211,7 +211,7 @@ static int get_physical_address(CPUSPARCState *env, CPU= TLBEntryFull *full, } =20 /* Perform address translation */ -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, vaddr first, vaddr la= st, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { @@ -776,7 +776,7 @@ static int get_physical_address(CPUSPARCState *env, CPU= TLBEntryFull *full, } =20 /* Perform address translation */ -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, vaddr first, vaddr la= st, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 273713a147..5a6fb6c6c9 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -67,7 +67,7 @@ static void raise_mmu_exception(CPUTriCoreState *env, vad= dr address, { } =20 -bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, +bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, vaddr first, vaddr = last, MMUAccessType rw, int mmu_idx, bool probe, uintptr_t retaddr) { diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 5a0e865514..a99956614b 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -264,7 +264,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, addr); 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Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/tcg/pmp.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/riscv/tcg/pmp.c b/target/riscv/tcg/pmp.c index 41b55519a8..5bccc60527 100644 --- a/target/riscv/tcg/pmp.c +++ b/target/riscv/tcg/pmp.c @@ -415,6 +415,10 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr add= r, * from low to high */ for (i =3D 0; i < pmp_regions; i++) { + if (pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg) =3D=3D PMP_AMAT= CH_OFF) { + continue; + } + s =3D pmp_is_in_range(env, i, addr); e =3D pmp_is_in_range(env, i, addr + pmp_size - 1); =20 @@ -427,10 +431,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr add= r, } =20 /* fully inside */ - const uint8_t a_field =3D - pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); - - if (((s + e) =3D=3D 2) && (PMP_AMATCH_OFF !=3D a_field)) { + if (s + e =3D=3D 2) { /* * If the PMP entry is not off and the address is in range, * do the priv check --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826315; cv=none; d=zohomail.com; s=zohoarc; b=J0vbgOpB57pa6D9PDCy2H6gofRjk6NbU2A4bHtRXWiz2SWXXvZ/grG0uECo+nVOXk6lh2gxJtdEwY9FWcCOkJyfe3Qd4vopkSz7d1UxGgY7iz4p0rb3Pdd+OXVmAFpz0DcYCuVfNtLg2eHWAwnFF9slxz8aJtf51khE2Uz0R2BY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786826315; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OtKLwewARJo/bPnddqGwtlSMmGFQ3XmZ9aODd7omBE4=; b=bZAEL0PVwqA+QEk1ZVFr4kp9LhkM/DAxHAGOevjXlPjaAHW5X9qgDlbKBJBXFTfFfDdDTeXmisIxGn0TCtVEZlwyA00QtTgFbGEKw0xuFFXxs/CJ6Z4VFXnpgI0aFDSs/j4W7xHQFzEKXDAdQNnOVbXFSTkneaGm3pq5h7a7YwA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178682631578720.323220833528012; Sat, 15 Aug 2026 13:38:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wvL8h-0008EW-PE; Sat, 15 Aug 2026 16:37:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvL8g-0008D1-Oz for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:58 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wvL8c-0008Kv-Gu for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:58 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-38e07ebd263so1499320a91.1 for ; Sat, 15 Aug 2026 13:37:51 -0700 (PDT) Received: from stoup.. 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Sat, 15 Aug 2026 13:37:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 14/18] target/riscv: Return bool from pmp_is_in_range Date: Sat, 15 Aug 2026 13:37:26 -0700 Message-ID: <20260815203730.1468365-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260815203730.1468365-1-richard.henderson@linaro.org> References: <20260815203730.1468365-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786826317555158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/tcg/pmp.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/target/riscv/tcg/pmp.c b/target/riscv/tcg/pmp.c index 5bccc60527..5ea0e5b6c3 100644 --- a/target/riscv/tcg/pmp.c +++ b/target/riscv/tcg/pmp.c @@ -299,18 +299,10 @@ void pmp_update_rule_nums(CPURISCVState *env) } } =20 -static int pmp_is_in_range(CPURISCVState *env, int pmp_index, hwaddr addr) +static bool pmp_is_in_range(CPURISCVState *env, int pmp_index, hwaddr addr) { - int result =3D 0; - - if ((addr >=3D env->pmp_state.addr[pmp_index].sa) && - (addr <=3D env->pmp_state.addr[pmp_index].ea)) { - result =3D 1; - } else { - result =3D 0; - } - - return result; + return (addr >=3D env->pmp_state.addr[pmp_index].sa && + addr <=3D env->pmp_state.addr[pmp_index].ea); } =20 /* @@ -385,10 +377,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr add= r, pmp_priv_t *allowed_privs, privilege_mode_t mode) { - int i =3D 0; int pmp_size =3D 0; - hwaddr s =3D 0; - hwaddr e =3D 0; uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 /* Short cut if no rules */ @@ -414,7 +403,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, * 1.10 draft priv spec states there is an implicit order * from low to high */ - for (i =3D 0; i < pmp_regions; i++) { + for (int i =3D 0; i < pmp_regions; i++) { + bool s, e; + if (pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg) =3D=3D PMP_AMAT= CH_OFF) { continue; } --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826454; cv=none; d=zohomail.com; s=zohoarc; b=IoVB8ageL1F3VD8rLmG1U+I8L7u/0JA4Ic1sheY/ciJUphvPgObST3/Qfy8JxIeLj3HgVOV97y9Rc50jIOaUb0YwPIjlQ/I+LtYIVWWobWbkuhnWe2NanIVeKCvdpYCj+4bCBqb3hWpqiUXrOfNOsXNmtH4gzTrzkXK0fEJFd3U= ARC-Message-Signature: i=1; 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Use normal boolean operators instead. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/tcg/pmp.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/tcg/pmp.c b/target/riscv/tcg/pmp.c index 5ea0e5b6c3..fc035c95cf 100644 --- a/target/riscv/tcg/pmp.c +++ b/target/riscv/tcg/pmp.c @@ -413,16 +413,8 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr add= r, s =3D pmp_is_in_range(env, i, addr); e =3D pmp_is_in_range(env, i, addr + pmp_size - 1); =20 - /* partially inside */ - if ((s + e) =3D=3D 1) { - qemu_log_mask(LOG_GUEST_ERROR, - "pmp violation - access is partially inside\n"); - *allowed_privs =3D 0; - return false; - } - /* fully inside */ - if (s + e =3D=3D 2) { + if (s && e) { /* * If the PMP entry is not off and the address is in range, * do the priv check @@ -517,6 +509,14 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr add= r, */ return (privs & *allowed_privs) =3D=3D privs; } + + /* partially inside */ + if (s || e) { + qemu_log_mask(LOG_GUEST_ERROR, + "pmp violation - access is partially inside\n"); + *allowed_privs =3D 0; + return false; + } } =20 /* No rule matched */ --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786826461; cv=none; d=zohomail.com; s=zohoarc; b=BHtxZC1S3sHF8mgtsjHYwQlqz33hmBMcDZPjEBavVC3T6zFyCpvxcGitXLLl3iSla/QxwRkyY+ppreUi+TCEXqEmGtr6/YN4d0gEzyQMGJp1vhEne3s4ODKVdwxTRIxRe3bXcWY43t2tgZhYnYOAKk8Qa5PKWbz8Tt/3P4sNtos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786826461; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=a/hlEFf1FqljA5oL9KqdkF9I8pya5mr0tI2C45YHawA=; b=Gf1T06t2yZW7Dw3MG8gBSWUS2TXMOgtij47zpgqCSw1H75LK3TAk6J+k45A0rXnXXxTKKHmXzT2rNkS2sJ2C/A7S9W11VZ4LNRM0KMJSOkju+eNJ5R+Unvz/5cSxYVsaAQqX66VRy74ypVZPR7GG3JInnFjnIGnxs/RQpHg0Br8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786826461075354.13826796399803; Sat, 15 Aug 2026 13:41:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wvL8m-0008Jh-2S; Sat, 15 Aug 2026 16:38:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wvL8i-0008Eu-1N for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:38:00 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wvL8c-0008Ot-Hv for qemu-devel@nongnu.org; Sat, 15 Aug 2026 16:37:59 -0400 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-38dc4553f62so2898643a91.0 for ; Sat, 15 Aug 2026 13:37:53 -0700 (PDT) Received: from stoup.. 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Sat, 15 Aug 2026 13:37:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 16/18] target/riscv: Recognize watchpoints with first/last Date: Sat, 15 Aug 2026 13:37:28 -0700 Message-ID: <20260815203730.1468365-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260815203730.1468365-1-richard.henderson@linaro.org> References: <20260815203730.1468365-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786826461338158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/tcg/cpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 11f2654da1..3318e82ea7 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -1784,8 +1784,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = vaddr first, vaddr last, * Otherwise we'll throw a debug exception and execution * will continue elsewhere. */ - cpu_check_watchpoint(cs, address, size, MEMTXATTRS_UNSPECIFIED, - wp_access, retaddr); + cpu_check_watchpoint(cs, first, last - first + 1, + MEMTXATTRS_UNSPECIFIED, wp_access, retaddr); =20 raise_mmu_exception(env, address, access_type, pmp_pma_violation, first_stage_error, two_stage_lookup, --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sat, 15 Aug 2026 13:37:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 17/18] target/riscv: Pass first/last to get_physical_address_pmp Date: Sat, 15 Aug 2026 13:37:29 -0700 Message-ID: <20260815203730.1468365-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260815203730.1468365-1-richard.henderson@linaro.org> References: <20260815203730.1468365-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786826318948158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/tcg/cpu_helper.c | 48 +++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 22 deletions(-) diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 3318e82ea7..fb1250a4b8 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -899,12 +899,13 @@ void riscv_cpu_set_mode(CPURISCVState *env, privilege= _mode_t newpriv, * * @env: CPURISCVState * @prot: The returned protection attributes - * @addr: The physical address to be checked permission + * @first, @last: The physical address range to be permission checked * @access_type: The type of MMU access * @mode: Indicates current privilege level. */ -static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr = addr, - int size, MMUAccessType access_type, +static int get_physical_address_pmp(CPURISCVState *env, int *prot, + hwaddr first, hwaddr last, + MMUAccessType access_type, privilege_mode_t mode) { pmp_priv_t pmp_priv; @@ -915,8 +916,8 @@ static int get_physical_address_pmp(CPURISCVState *env,= int *prot, hwaddr addr, return TRANSLATE_SUCCESS; } =20 - pmp_has_privs =3D pmp_hart_has_privs(env, addr, size, 1 << access_type, - &pmp_priv, mode); + pmp_has_privs =3D pmp_hart_has_privs(env, first, last - first + 1, + 1 << access_type, &pmp_priv, mode); if (!pmp_has_privs) { *prot =3D 0; return TRANSLATE_PMP_FAIL; @@ -1142,6 +1143,8 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, base =3D base_root; for (i =3D 0; i < levels; i++, ptshift -=3D ptidxbits) { target_ulong idx; + int pmp_prot, pmp_ret; + if (i =3D=3D 0) { idx =3D (addr >> (PGSHIFT + ptshift)) & ((1 << (ptidxbits + widened)) - 1); @@ -1174,10 +1177,9 @@ static int get_physical_address(CPURISCVState *env, = hwaddr *physical, pte_addr =3D base + idx * ptesize; } =20 - int pmp_prot; - int pmp_ret =3D get_physical_address_pmp(env, &pmp_prot, pte_addr, - sxlen_bytes, - MMU_DATA_LOAD, PRV_S); + pmp_ret =3D get_physical_address_pmp(env, &pmp_prot, pte_addr, + pte_addr + sxlen_bytes - 1, + MMU_DATA_LOAD, PRV_S); if (pmp_ret !=3D TRANSLATE_SUCCESS) { return TRANSLATE_PMP_FAIL; } @@ -1425,7 +1427,8 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, } =20 pmp_ret =3D get_physical_address_pmp(env, &pmp_prot, pte_addr, - sxlen_bytes, MMU_DATA_STORE, PR= V_S); + pte_addr + sxlen_bytes - 1, + MMU_DATA_STORE, PRV_S); if (pmp_ret !=3D TRANSLATE_SUCCESS) { return TRANSLATE_PMP_FAIL; } @@ -1655,8 +1658,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = vaddr first, vaddr last, { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - int size =3D last - address + 1; - vaddr im_address; hwaddr pa =3D 0; int prot, prot2, prot_pmp; bool pmp_pma_violation =3D false; @@ -1676,7 +1677,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = vaddr first, vaddr last, pmu_tlb_fill_incr_ctr(cpu, access_type); if (two_stage_lookup) { /* Two stage lookup */ - ret =3D get_physical_address(env, &pa, &prot, address, + ret =3D get_physical_address(env, &pa, &prot, first, &env->guest_phys_fault_addr, access_typ= e, mmu_idx, true, true, false, probe); /* @@ -1692,11 +1693,11 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address= , vaddr first, vaddr last, qemu_log_mask(CPU_LOG_MMU, "%s 1st-stage address=3D%" VADDR_PRIx " ret %d physi= cal " HWADDR_FMT_plx " prot %d\n", - __func__, address, ret, pa, prot); + __func__, first, ret, pa, prot); =20 if (ret =3D=3D TRANSLATE_SUCCESS) { /* Second stage lookup */ - im_address =3D pa; + vaddr im_address =3D pa; =20 ret =3D get_physical_address(env, &pa, &prot2, im_address, NUL= L, access_type, MMUIdx_U, false, true, @@ -1711,8 +1712,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = vaddr first, vaddr last, prot &=3D prot2; =20 if (ret =3D=3D TRANSLATE_SUCCESS) { - ret =3D get_physical_address_pmp(env, &prot_pmp, pa, - size, access_type, mode); + ret =3D get_physical_address_pmp(env, &prot_pmp, + pa, pa + (last - first), + access_type, mode); tlb_size =3D pmp_get_tlb_size(env, pa); =20 qemu_log_mask(CPU_LOG_MMU, @@ -1736,18 +1738,19 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address= , vaddr first, vaddr last, } } else { /* Single stage lookup */ - ret =3D get_physical_address(env, &pa, &prot, address, NULL, + ret =3D get_physical_address(env, &pa, &prot, first, NULL, access_type, mmu_idx, true, false, fals= e, probe); =20 qemu_log_mask(CPU_LOG_MMU, "%s address=3D%" VADDR_PRIx " ret %d physical " HWADDR_FMT_plx " prot %d\n", - __func__, address, ret, pa, prot); + __func__, first, ret, pa, prot); =20 if (ret =3D=3D TRANSLATE_SUCCESS) { - ret =3D get_physical_address_pmp(env, &prot_pmp, pa, - size, access_type, mode); + ret =3D get_physical_address_pmp(env, &prot_pmp, + pa, pa + (last - first), + access_type, mode); tlb_size =3D pmp_get_tlb_size(env, pa); =20 qemu_log_mask(CPU_LOG_MMU, @@ -1764,7 +1767,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = vaddr first, vaddr last, } =20 if (ret =3D=3D TRANSLATE_SUCCESS) { - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), + tlb_set_page(cs, address & ~(tlb_size - 1), + (pa + (address - first)) & ~(tlb_size - 1), prot, mmu_idx, tlb_size); return true; } else if (probe) { --=20 2.43.0 From nobody Fri Aug 28 00:14:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/tcg/pmp.h | 5 ++--- target/riscv/tcg/cpu_helper.c | 2 +- target/riscv/tcg/pmp.c | 24 ++++-------------------- 3 files changed, 7 insertions(+), 24 deletions(-) diff --git a/target/riscv/tcg/pmp.h b/target/riscv/tcg/pmp.h index 4c95c2767a..eacb5b5349 100644 --- a/target/riscv/tcg/pmp.h +++ b/target/riscv/tcg/pmp.h @@ -70,9 +70,8 @@ typedef struct { =20 typedef struct CPUArchState CPURISCVState; =20 -bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, - int size, pmp_priv_t privs, - pmp_priv_t *allowed_privs, +bool pmp_hart_has_privs(CPURISCVState *env, hwaddr first, hwaddr last, + pmp_priv_t privs, pmp_priv_t *allowed_privs, privilege_mode_t mode); uint64_t pmp_get_tlb_size(CPURISCVState *env, hwaddr addr); void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index fb1250a4b8..7ef5ab5277 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -916,7 +916,7 @@ static int get_physical_address_pmp(CPURISCVState *env,= int *prot, return TRANSLATE_SUCCESS; } =20 - pmp_has_privs =3D pmp_hart_has_privs(env, first, last - first + 1, + pmp_has_privs =3D pmp_hart_has_privs(env, first, last, 1 << access_type, &pmp_priv, mode); if (!pmp_has_privs) { *prot =3D 0; diff --git a/target/riscv/tcg/pmp.c b/target/riscv/tcg/pmp.c index fc035c95cf..d3cbb2cb2e 100644 --- a/target/riscv/tcg/pmp.c +++ b/target/riscv/tcg/pmp.c @@ -372,12 +372,10 @@ static bool pmp_hart_has_privs_default(CPURISCVState = *env, pmp_priv_t privs, * pmpcfg but is not acted upon during access checks. Cache attributes * have no functional impact in QEMU emulation. */ -bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, - int size, pmp_priv_t privs, - pmp_priv_t *allowed_privs, +bool pmp_hart_has_privs(CPURISCVState *env, hwaddr first, hwaddr last, + pmp_priv_t privs, pmp_priv_t *allowed_privs, privilege_mode_t mode) { - int pmp_size =3D 0; uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 /* Short cut if no rules */ @@ -385,20 +383,6 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr add= r, return pmp_hart_has_privs_default(env, privs, allowed_privs, mode); } =20 - if (size =3D=3D 0) { - if (riscv_cpu_cfg(env)->mmu) { - /* - * If size is unknown (0), assume that all bytes - * from addr to the end of the page will be accessed. - */ - pmp_size =3D -(addr | TARGET_PAGE_MASK); - } else { - pmp_size =3D 2 << riscv_cpu_mxl(env); - } - } else { - pmp_size =3D size; - } - /* * 1.10 draft priv spec states there is an implicit order * from low to high @@ -410,8 +394,8 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, continue; } =20 - s =3D pmp_is_in_range(env, i, addr); - e =3D pmp_is_in_range(env, i, addr + pmp_size - 1); + s =3D pmp_is_in_range(env, i, first); + e =3D pmp_is_in_range(env, i, last); =20 /* fully inside */ if (s && e) { --=20 2.43.0