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Separate tcg from qtest initialization. Remove an assert on aarch64_enabled that is directly protected by a preceding if. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu-max.c | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 88b7c04633..0a310d1b15 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -203,29 +203,32 @@ static void cpu_max_initfn(Object *obj) return; } =20 - if (tcg_enabled() || qtest_enabled()) { - aarch64_aa32_a57_init(obj, !aarch64_enabled); - } - - if (!aarch64_enabled) { - aa32_max_features(cpu); -#ifdef CONFIG_USER_ONLY - /* - * Break with true ARMv8 and add back old-style VFP short-vector - * support. Only do this for user-mode, where -cpu max is the defa= ult, - * so that older v6 and v7 programs are more likely to work without - * adjustment. - */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); -#endif - } else if (tcg_enabled()) { - assert(aarch64_enabled); + if (tcg_enabled()) { /* * '-cpu max' for TCG: we currently do this as * "A57 with extra things" */ - aarch64_max_tcg_initfn(obj); + aarch64_aa32_a57_init(obj, !aarch64_enabled); + if (!aarch64_enabled) { + aa32_max_features(cpu); +#ifdef CONFIG_USER_ONLY + /* + * Break with true ARMv8 and add back old-style VFP short-vect= or + * support. Only do this for user-mode, where -cpu max is the = default, + * so that older v6 and v7 programs are more likely to work wi= thout + * adjustment. + */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC= , 1); +#endif + } else { + aarch64_max_tcg_initfn(obj); + } + return; } + + /* Ultimate fallback: -cpu max as cortex-a57. */ + assert(qtest_enabled()); + aarch64_aa32_a57_init(obj, !aarch64_enabled); } =20 static const ARMCPUInfo arm_max_cpu =3D { --=20 2.43.0 From nobody Wed Aug 26 07:29:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786567555; cv=none; d=zohomail.com; s=zohoarc; b=lHzN4txm5rrXfwOoGzRe4oLPsoMDd2OV3yUe/x3wmyJNoR9IaLHp5BWY+JIs7trNinX3hFnnaK+b2uiavvMEuNcaZK5y7s4coCODqfRSpr4uRL063tbrI+/P6pzRJnc0pLVprhukG0ZMk/mo7tHHwrgYwloaebZQhGOwlJefePU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786567555; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jwiqruiRehEXzTLHxQkNSDoYPqOOLh/gwgSxK/nLS4U=; b=kvkgqt0QjlxdtVvKPSDWT4IfVbMI4Q9l9GlyE3hQJyv6i5DiThowQILdzgZez4v0zkYp2hpIZI7j7/21oACsvO3v2AD5BcHBaOfrC3rS/1zRtQPDzb72irusB0gYAZcD2Y8CQGAgTAW2j0GPhXxSPLpaWp3VJ3JM123j3FOL+RU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786567555435726.7917930075754; Wed, 12 Aug 2026 13:45:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wuFol-0003a0-SZ; Wed, 12 Aug 2026 16:44:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wuFog-0003Wt-RP for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:44:51 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wuFof-0002Fv-6Q for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:44:50 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-8486672f03cso40768b3a.0 for ; Wed, 12 Aug 2026 13:44:48 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/cpu-max.c | 7 +++---- target/arm/cpu64.c | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4026f67579..9c9196475b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1813,7 +1813,7 @@ void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); -void aarch64_aa32_a57_init(Object *obj, bool aa32_only); +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only); void aarch64_host_initfn(Object *obj); =20 /* Return true if the gdbstub is presenting an AArch64 CPU */ diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 0a310d1b15..bd858f010c 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -16,9 +16,8 @@ #include "target/arm/internals.h" #include "target/arm/cpregs.h" =20 -void aarch64_aa32_a57_init(Object *obj, bool aa32_only) +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only) { - ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; const bool aarch64_enabled =3D !aa32_only; =20 @@ -208,7 +207,7 @@ static void cpu_max_initfn(Object *obj) * '-cpu max' for TCG: we currently do this as * "A57 with extra things" */ - aarch64_aa32_a57_init(obj, !aarch64_enabled); + aarch64_aa32_a57_init(cpu, !aarch64_enabled); if (!aarch64_enabled) { aa32_max_features(cpu); #ifdef CONFIG_USER_ONLY @@ -228,7 +227,7 @@ static void cpu_max_initfn(Object *obj) =20 /* Ultimate fallback: -cpu max as cortex-a57. */ assert(qtest_enabled()); - aarch64_aa32_a57_init(obj, !aarch64_enabled); + aarch64_aa32_a57_init(cpu, !aarch64_enabled); } =20 static const ARMCPUInfo arm_max_cpu =3D { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2816735577..e3ee0253a0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -688,7 +688,7 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **err= p) =20 static void aarch64_a57_initfn(Object *obj) { - aarch64_aa32_a57_init(obj, false); + aarch64_aa32_a57_init(ARM_CPU(obj), false); } =20 static void aarch64_a53_initfn(Object *obj) --=20 2.43.0 From nobody Wed Aug 26 07:29:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786567542; cv=none; d=zohomail.com; s=zohoarc; b=Gaa7qCbhIxBSRjyVXkOf/DUNCJi6JwN74m+7rVFuUlmWCv3bSFoLcS/IcqHtWbItlctdsIAmcr/qJjmusK54h9mRdSBz/7hdF8r5nPyhr2ylVrPUVE2+7BnRxnZMCfFJ0Ooa3iF17NvD2qydh27Z8wI27AjtbWjxqMSSV/AUWks= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786567542; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dBfwrVCq3v6OU1T4kao3X47pro2yBEmddrlxSU6VEk0=; b=Q0MyKV7i1Mh02d3bOhIG/42A7dbOD3dclBvDhVvfpD+npzHmjQgTKvf27/BTDblohQpOSDkleBtIc8nC4RMyoyYOLUj+Q490RGDD15QhDGCWSf+Q74EzvNkYusETjlZ3I2AqbNJnojK5tpqDhdLLDA1z0IElyVcA1C4SlFWO/4Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786567542035365.46651806183763; Wed, 12 Aug 2026 13:45:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wuFol-0003Zy-S9; Wed, 12 Aug 2026 16:44:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wuFoa-0003U0-EA for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:44:44 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wuFoY-0002EV-S0 for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:44:44 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-84e507b079dso1064435b3a.0 for ; Wed, 12 Aug 2026 13:44:42 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/cpu-max.c | 7 +++---- target/arm/cpu64.c | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 9c9196475b..5e7f41a50d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1813,7 +1813,7 @@ void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); -void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only); +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa64_enabled); void aarch64_host_initfn(Object *obj); =20 /* Return true if the gdbstub is presenting an AArch64 CPU */ diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index bd858f010c..edb5b9e6c3 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -16,10 +16,9 @@ #include "target/arm/internals.h" #include "target/arm/cpregs.h" =20 -void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only) +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aarch64_enabled) { ARMISARegisters *isar =3D &cpu->isar; - const bool aarch64_enabled =3D !aa32_only; =20 cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -207,7 +206,7 @@ static void cpu_max_initfn(Object *obj) * '-cpu max' for TCG: we currently do this as * "A57 with extra things" */ - aarch64_aa32_a57_init(cpu, !aarch64_enabled); + aarch64_aa32_a57_init(cpu, aarch64_enabled); if (!aarch64_enabled) { aa32_max_features(cpu); #ifdef CONFIG_USER_ONLY @@ -227,7 +226,7 @@ static void cpu_max_initfn(Object *obj) =20 /* Ultimate fallback: -cpu max as cortex-a57. */ assert(qtest_enabled()); - aarch64_aa32_a57_init(cpu, !aarch64_enabled); + aarch64_aa32_a57_init(cpu, aarch64_enabled); } =20 static const ARMCPUInfo arm_max_cpu =3D { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e3ee0253a0..faaf3ab879 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -688,7 +688,7 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **err= p) =20 static void aarch64_a57_initfn(Object *obj) { - aarch64_aa32_a57_init(ARM_CPU(obj), false); + aarch64_aa32_a57_init(ARM_CPU(obj), true); } =20 static void aarch64_a53_initfn(Object *obj) --=20 2.43.0 From nobody Wed Aug 26 07:29:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786567605; cv=none; d=zohomail.com; s=zohoarc; b=Dr7iHOeOzfd8Gyu+Bw4BKRRC8TPR3D3qa2bwRtR+HISLVjkYuDT6ZNmeoO63IHMvEwm5XBiukBj2pb2Q6F2LNnYvYThklTJvABKSllZXDD2Sphxgw+zg8nTdsZejLazOQTIhW5lGBvGPrHUKG4rYduxy8ylp2Mlj6D0pAnHz5lQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786567605; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=p/0NSBkDolnRnDgnN31JqXgc+8uH1xvhnMEkNLiV4BQ=; b=DFCzSh01424C3n6ypkoBpshee4zvMmj1FonZfz6l+z/WoE3RtCFR9AT0kmmPYs/6Dpb+WPY78ZpB+S0a0eOjSAhBJRa/yF5fnX8cbQiJDvq+UB4FN4YXijpyRxon0W9qaPaoas/JjIAYW6PE0ddf65fXsZUHii04V+OQU7k/Y4Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786567605025326.64453381752367; Wed, 12 Aug 2026 13:46:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wuFon-0003bb-SN; Wed, 12 Aug 2026 16:44:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wuFob-0003US-GP for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:44:46 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wuFoa-0002Ev-4L for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:44:45 -0400 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-cbeeaac53a9so871381a12.1 for ; Wed, 12 Aug 2026 13:44:43 -0700 (PDT) Received: from stoup.. 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Wed, 12 Aug 2026 13:44:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 04/10] target/arm: Sink aarch64_aa32_a57_init into aarch64_max_tcg_initfn Date: Wed, 12 Aug 2026 13:44:29 -0700 Message-ID: <20260812204435.295067-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260812204435.295067-1-richard.henderson@linaro.org> References: <20260812204435.295067-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786567606462158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/cpu-max.c | 2 +- target/arm/tcg/cpu64.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index edb5b9e6c3..93f24114a5 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -206,8 +206,8 @@ static void cpu_max_initfn(Object *obj) * '-cpu max' for TCG: we currently do this as * "A57 with extra things" */ - aarch64_aa32_a57_init(cpu, aarch64_enabled); if (!aarch64_enabled) { + aarch64_aa32_a57_init(cpu, false); aa32_max_features(cpu); #ifdef CONFIG_USER_ONLY /* diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 24f34947ec..5649b853a7 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1167,6 +1167,8 @@ void aarch64_max_tcg_initfn(Object *obj) uint64_t t; uint32_t u; =20 + aarch64_aa32_a57_init(cpu, true); + SET_IDREG(isar, CLIDR, 0x8200123); /* 64KB L1 dcache */ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); --=20 2.43.0 From nobody Wed Aug 26 07:29:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786567549; cv=none; d=zohomail.com; s=zohoarc; b=KW9NKu/DY77J+LY5v8eWUJGJBKsbd2aneNNpqqp666LGc7T+q4E0yOlSCdLcpZs/SCnjShRbG98fXRtrnrk096a6WHFoV+Jt5DGmxkL+oCzU5fJtf+iY32OFgX71ThIc9ol5d+Lw+AzJLSPZ6bQDr667v2oiU1AnTq4f2ZIvHNE= ARC-Message-Signature: i=1; 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Wed, 12 Aug 2026 13:44:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 05/10] target/arm: Split out aarch32_max_tcg_init Date: Wed, 12 Aug 2026 13:44:30 -0700 Message-ID: <20260812204435.295067-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260812204435.295067-1-richard.henderson@linaro.org> References: <20260812204435.295067-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786567552148158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 1 + target/arm/cpu-max.c | 16 +--------------- target/arm/tcg/cpu32.c | 15 +++++++++++++++ 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5e7f41a50d..f6b4e173a5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1838,6 +1838,7 @@ uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool s= ecure, bool el_is_in_host(CPUARMState *env, int el); =20 void aa32_max_features(ARMCPU *cpu); +void aarch32_max_tcg_init(ARMCPU *cpu); int exception_target_el(CPUARMState *env); bool arm_singlestep_active(CPUARMState *env); bool arm_generate_debug_exceptions(CPUARMState *env); diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 93f24114a5..7df7d015a9 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -202,22 +202,8 @@ static void cpu_max_initfn(Object *obj) } =20 if (tcg_enabled()) { - /* - * '-cpu max' for TCG: we currently do this as - * "A57 with extra things" - */ if (!aarch64_enabled) { - aarch64_aa32_a57_init(cpu, false); - aa32_max_features(cpu); -#ifdef CONFIG_USER_ONLY - /* - * Break with true ARMv8 and add back old-style VFP short-vect= or - * support. Only do this for user-mode, where -cpu max is the = default, - * so that older v6 and v7 programs are more likely to work wi= thout - * adjustment. - */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC= , 1); -#endif + aarch32_max_tcg_init(cpu); } else { aarch64_max_tcg_initfn(obj); } diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 8220d785f5..e1ff074b47 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -748,3 +748,18 @@ static void arm_tcg_cpu_register_types(void) type_init(arm_tcg_cpu_register_types) =20 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ + +void aarch32_max_tcg_init(ARMCPU *cpu) +{ + aarch64_aa32_a57_init(cpu, false); + aa32_max_features(cpu); +#ifdef CONFIG_USER_ONLY + /* + * Break with true ARMv8 and add back old-style VFP short-vector + * support. Only do this for user-mode, where -cpu max is the default, + * so that older v6 and v7 programs are more likely to work without + * adjustment. + */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); +#endif +} --=20 2.43.0 From nobody Wed Aug 26 07:29:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786567556; cv=none; d=zohomail.com; s=zohoarc; b=FP/IuIsESi2p2oGaQSe1sT2VQjWsIFG70i+fQimTfNXuIjt+m/dxVYekOqxA5EjLFl01cu9oxtv8MTPaxpD3gkpnOPBd7QGy5MGqdkx52pCj6AFAOpHb7LQjO0y+GpK0VLL1Je1IQKsH6vkE9OoYXLRGSZ5Jv5TG1G5ie5DKwgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786567556; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fDDfgxcUeDenp1TCRREpiqyxENBHO3/H9gHynAXLyRg=; b=nfvnzplTgSBTZqzo0TJtRNKpfuJ5Divod7VjBLdJXUbCUAw8Fa+VM75tl6fsCFeMoJqZVVn7OFgnNEz16ucp+DUxyck8C54ztJNMWNkw+z605WGmdBeKBM2G8wbRH1Vj6zd9jy7LDga1jSENUKJrtCNBC9v4ewpf0ONiWflYlLc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786567556452279.1855198931886; Wed, 12 Aug 2026 13:45:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wuFop-0003cm-Hf; Wed, 12 Aug 2026 16:45:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wuFon-0003aV-Gk for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:44:57 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wuFol-0002Ge-H7 for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:44:57 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-8487b7b3fc8so1642384b3a.3 for ; Wed, 12 Aug 2026 13:44:55 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu-max.c | 96 ------------------------------------------ target/arm/tcg/cpu32.c | 96 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 96 deletions(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 7df7d015a9..8d968336a8 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -85,102 +85,6 @@ void aarch64_aa32_a57_init(ARMCPU *cpu, bool aarch64_en= abled) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 -/* Share AArch32 -cpu max features with AArch64. */ -void aa32_max_features(ARMCPU *cpu) -{ - uint32_t t; - ARMISARegisters *isar =3D &cpu->isar; - - /* Add additional features supported by QEMU */ - t =3D GET_IDREG(isar, ID_ISAR5); - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ - SET_IDREG(isar, ID_ISAR5, t); - - t =3D GET_IDREG(isar, ID_ISAR6); - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ - SET_IDREG(isar, ID_ISAR6, t); - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ - - t =3D GET_IDREG(isar, ID_MMFR4); - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ - t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */ - SET_IDREG(isar, ID_MMFR4, t); - - FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ - - t =3D GET_IDREG(isar, ID_PFR0); - t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ - SET_IDREG(isar, ID_PFR0, t); - - t =3D GET_IDREG(isar, ID_PFR2); - t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ - SET_IDREG(isar, ID_PFR2, t); - - t =3D GET_IDREG(isar, ID_DFR0); - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ - SET_IDREG(isar, ID_DFR0, t); - - /* Debug ID registers. */ - - /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ - t =3D 0x00008000; - t =3D FIELD_DP32(t, DBGDIDR, SE_IMP, 1); - t =3D FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); - t =3D FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); - t =3D FIELD_DP32(t, DBGDIDR, BRPS, 5); - t =3D FIELD_DP32(t, DBGDIDR, WRPS, 3); - cpu->isar.dbgdidr =3D t; - - t =3D 0; - t =3D FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); - t =3D FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); - t =3D FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); - t =3D FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); - t =3D FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); - t =3D FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); - t =3D FIELD_DP32(t, DBGDEVID, AUXREGS, 0); - t =3D FIELD_DP32(t, DBGDEVID, CIDMASK, 0); - cpu->isar.dbgdevid =3D t; - - /* Bits[31:4] are RES0. */ - t =3D 0; - t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); - cpu->isar.dbgdevid1 =3D t; - - FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ -} - /* * -cpu max: a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index e1ff074b47..d5dd236152 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -749,6 +749,102 @@ type_init(arm_tcg_cpu_register_types) =20 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ =20 +/* Share AArch32 -cpu max features with AArch64. */ +void aa32_max_features(ARMCPU *cpu) +{ + uint32_t t; + ARMISARegisters *isar =3D &cpu->isar; + + /* Add additional features supported by QEMU */ + t =3D GET_IDREG(isar, ID_ISAR5); + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ + SET_IDREG(isar, ID_ISAR5, t); + + t =3D GET_IDREG(isar, ID_ISAR6); + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ + SET_IDREG(isar, ID_ISAR6, t); + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ + + t =3D GET_IDREG(isar, ID_MMFR4); + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ + t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT2 */ + SET_IDREG(isar, ID_MMFR4, t); + + FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ + + t =3D GET_IDREG(isar, ID_PFR0); + t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ + SET_IDREG(isar, ID_PFR0, t); + + t =3D GET_IDREG(isar, ID_PFR2); + t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ + SET_IDREG(isar, ID_PFR2, t); + + t =3D GET_IDREG(isar, ID_DFR0); + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ + SET_IDREG(isar, ID_DFR0, t); + + /* Debug ID registers. */ + + /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ + t =3D 0x00008000; + t =3D FIELD_DP32(t, DBGDIDR, SE_IMP, 1); + t =3D FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); + t =3D FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); + t =3D FIELD_DP32(t, DBGDIDR, BRPS, 5); + t =3D FIELD_DP32(t, DBGDIDR, WRPS, 3); + cpu->isar.dbgdidr =3D t; + + t =3D 0; + t =3D FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); + t =3D FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); + t =3D FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); + t =3D FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); + t =3D FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); + t =3D FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); + t =3D FIELD_DP32(t, DBGDEVID, AUXREGS, 0); + t =3D FIELD_DP32(t, DBGDEVID, CIDMASK, 0); + cpu->isar.dbgdevid =3D t; + + /* Bits[31:4] are RES0. */ + t =3D 0; + t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); + cpu->isar.dbgdevid1 =3D t; + + FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ +} + void aarch32_max_tcg_init(ARMCPU *cpu) { aarch64_aa32_a57_init(cpu, false); --=20 2.43.0 From nobody Wed Aug 26 07:29:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786567575; cv=none; d=zohomail.com; s=zohoarc; b=Mog9GVVvLcSo/jtEkUJwdrWznO4HlmK7DttdjvN3KADB6sa+u6ZsuV2wKOAudxHWJR0LeXZ42wX4DVerRendU/8vQfCgl1S4zPnyLWfpjtkcNMm57MidGCtYAeTLqC5woHsgupAsgJsTgtEsKJS0V63yREgttY9oh3Kr9Q9murE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786567575; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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So far, the cpu types both exactly match "max". Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- hw/arm/sbsa-ref.c | 2 ++ hw/arm/virt.c | 2 ++ target/arm/tcg/cpu64.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 484b90053e..56d08f605c 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -913,6 +913,8 @@ static void sbsa_ref_class_init(ObjectClass *oc, const = void *data) ARM_CPU_TYPE_NAME("neoverse-v1"), ARM_CPU_TYPE_NAME("neoverse-n2"), ARM_CPU_TYPE_NAME("max"), + ARM_CPU_TYPE_NAME("max-v8"), + ARM_CPU_TYPE_NAME("max-v9"), NULL, }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 219597cabd..34cab9017c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -4143,6 +4143,8 @@ static GPtrArray *virt_get_valid_cpu_types(const Mach= ineState *ms) g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v8"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v9"))); } if (target_aarch64()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5649b853a7..967cde787e 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1463,6 +1463,8 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, + { .name =3D "max-v8", .initfn =3D aarch64_max_tcg_initfn }, + { .name =3D "max-v9", .initfn =3D aarch64_max_tcg_initfn }, }; =20 static void aarch64_cpu_register_types(void) --=20 2.43.0 From nobody Wed Aug 26 07:29:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786567554; cv=none; d=zohomail.com; s=zohoarc; b=LhA6lWLWLeUh/vWzs9ekap2Ud4QThb3gC3c5PrpMDe3eDDEZFowVbrIikWkuGOzJq8eVWe6NRKlyW3BbBjF8hacd8qZ3qwnV7nFf6kVl1bDU/cHu2rQma9FSFM0e1USoQEhDsVCrRwtTQukii6Mh3pvcLOkHIj3iRGCJOZJS2/g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786567554; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=92Z59h4EjWpGyEMEUV984CWvR3PXtWrfjl/HvHT0LOw=; b=mjLUAu+mAEt4+l9m4K32yM2nZu1OwagWrHIKhZN9BV/EPqLk4brsi6SLgMqUWE9dxXfTPMqF5Cz9HeCm5C6O4pjutEmMiXHsfIa2JjO1TSC3hL8jUuJ7x3eUJv5wWi72M9Sk1r5QFcG8KOv7JfFkLozyU5AIiEOYHLO8PB99CaU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786567554357588.0131047823423; Wed, 12 Aug 2026 13:45:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wuFov-0003fu-J2; Wed, 12 Aug 2026 16:45:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wuFop-0003ck-3j for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:44:59 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wuFon-0002H4-FU for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:44:58 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-ca00f126b7eso59462a12.2 for ; Wed, 12 Aug 2026 13:44:57 -0700 (PDT) Received: from stoup.. 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These tests must use Armv8. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tests/qtest/arm-cpu-features.c | 4 ++-- tests/functional/aarch64/test_virt_aarch64_off.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index cb4d01fd46..7348fb8d28 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -493,8 +493,8 @@ static void test_query_cpu_model_expansion(const void *= data) sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); =20 - /* TCG allows us to turn off AArch64 on the 'max' CPU type */ - assert_set_feature(qts, "max", "aarch64", false); + /* TCG allows us to turn off AArch64 on the 'max-v8' CPU type */ + assert_set_feature(qts, "max-v8", "aarch64", false); } =20 qtest_quit(qts); diff --git a/tests/functional/aarch64/test_virt_aarch64_off.py b/tests/func= tional/aarch64/test_virt_aarch64_off.py index 13d8b73b0d..73c9a4109c 100755 --- a/tests/functional/aarch64/test_virt_aarch64_off.py +++ b/tests/functional/aarch64/test_virt_aarch64_off.py @@ -18,9 +18,9 @@ class ArmVirtMachine(LinuxKernelTest): def test_arm_virt(self): self.set_machine('virt') # KVM aarch64=3Doff requires a host CPU that supports it, so - # restrict the test to TCG only + # restrict the test to TCG ARMv8. self.require_accelerator('tcg') - self.vm.add_args('-cpu', 'max,aarch64=3Doff') + self.vm.add_args('-cpu', 'max-v8,aarch64=3Doff') =20 kernel_path =3D self.ASSET_KERNEL.fetch() =20 --=20 2.43.0 From nobody Wed Aug 26 07:29:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786567562; cv=none; d=zohomail.com; s=zohoarc; b=DWVM2cs8Eh+gudpZRja31qee+Bq2mz2wn0/fytJjkMv6xJBRvgIh1K5AUmxbCxyB2ARYC5W5WddNXWaNNzzNJLLi3xuoIPKIl+pTUUqpbgGG+I+rjuEhP0ksWcGKDvOgluZqEbyqcXnFLchYB4az45nnmliIM3RzCWYn/RJ7EMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786567562; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Yd/iCXWoWb3RYUvJFUJ/rXNNIXksPHd1mcvaomKYbfY=; b=AHCk2HT3dYjWqIL348nh/FI9OCmaczCnA9aNfDCygolA9Rwnb8Zx7w0+wv3r1iLze0VjqXuZDl72nxuGQu/JyomA93lcegs5zczn2XgGKstRSWXE56sQO+7lm2Yu0ERzZTcy267+240NWHYf/GBfihK7XxrEZrEEjTwgSuL6qS0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786567562801298.4657341705506; Wed, 12 Aug 2026 13:46:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wuFpD-00048r-0V; Wed, 12 Aug 2026 16:45:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wuFot-0003el-PG for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:45:05 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wuFoo-0002HT-Sn for qemu-devel@nongnu.org; Wed, 12 Aug 2026 16:45:01 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-84e84a6c4bfso349341b3a.1 for ; Wed, 12 Aug 2026 13:44:58 -0700 (PDT) Received: from stoup.. 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Modulo some sorting of properties at the end, comment changes only. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/cpu64.c | 303 +++++++++++++++++++++-------------------- 1 file changed, 159 insertions(+), 144 deletions(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 967cde787e..a5cad987d9 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1226,199 +1226,202 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, CTR_EL0, DIC, 1); cpu->ctr =3D t; =20 + /* + * Below, note the revision from which the feature is OPTIONAL. + */ t =3D GET_IDREG(isar, ID_AA64ISAR0); - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* FEAT_LSE, FEAT_LSE1= 28 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* v8.0: FEAT_PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* v8.0: FEAT_SHA1 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* v8.1: FEAT_SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* v8.0: FEAT_CRC32 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* v9.3: FEAT_LSE128 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* v8.0: FEAT_RDM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* v8.1: FEAT_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* v8.1: FEAT_SM3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* v8.1: FEAT_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* v8.1: FEAT_DotProd = */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* v8.1: FEAT_FHM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.1: FEAT_FlagM2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* v8.3: FEAT_TLBIRANG= E */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* v8.4: FEAT_RNG */ SET_IDREG(isar, ID_AA64ISAR0, t); =20 t =3D GET_IDREG(isar, ID_AA64ISAR1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* v8.1: FEAT_DPB2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); /* v8.= 2 */ t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF= 16 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* v8.2: FEAT_JSCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* v8.2: FEAT_FCMA */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* v8.2: FEAT_LRCPC2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* v8.4: FEAT_FRINTTS = */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* v8.0: FEAT_SB */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* v8.0: FEAT_SPECRES = */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* v8.2: FEAT_EBF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* v8.0: FEAT_DGH */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* v8.1: FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* v8.6: FEAT_XS */ SET_IDREG(isar, ID_AA64ISAR1, t); =20 t =3D GET_IDREG(isar, ID_AA64ISAR2); - t =3D FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* FEAT_RPRES */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* FEAT_CSSC, FEAT_CMP= BR */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* FEAT_LUT */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* FEAT_ATS1A */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* v8.6: FEAT_RPRES */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* v8.7: FEAT_MOPS */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* v8.7: FEAT_HBC */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* v8.6: FEAT_WFxT */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* v8.8: FEAT_ATS1A */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 t =3D GET_IDREG(isar, ID_AA64ISAR3); - t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* FEAT_FAMINMAX */ - t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* FEAT_FPRCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* v9.2: FEAT_FAMINMAX= */ + t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* v9.5: FEAT_FPRCVT */ SET_IDREG(isar, ID_AA64ISAR3, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR0); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ - t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* v8.2: FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* v8.2: FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* v8.3: FEAT_DoubleFa= ult */ + t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); /* v8.2: FEAT_SVE */ + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* v8.3: FEAT_SEL2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* v8.3: FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* v8.0: FEAT_CSV2_3 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* v8.0: FEAT_CSV3 */ SET_IDREG(isar, ID_AA64PFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR1); - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* v8.4: FEAT_BTI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* v8.0: FEAT_SSBS2 */ /* * Begin with full support for MTE. This will be downgraded to MTE=3D0 * during realize if the board provides no tag memory, much like * we do for EL2 with the virtualization=3Don property. */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ - t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* FEAT_SME2 */ - t =3D FIELD_DP64(t, ID_AA64PFR1, RNDR_TRAP, 1); /* FEAT_RNG_TRAP */ - t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ - t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ - t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* FEAT_GCS */ - /* FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* v8.5: FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* v8.3: FEAT_DoubleFa= ult */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, RNDR_TRAP, 1); /* v8.4: FEAT_RNG_TRAP= */ + t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* v8.0: FEAT_CSV2_3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* v8.7: FEAT_NMI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* v9.3: FEAT_GCS */ + /* v8.7: FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTEX, 1); SET_IDREG(isar, ID_AA64PFR1, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR2); - t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* FEAT_FPMR */ - t =3D FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* FEAT_MTE_TAGGED_FAR= */ - t =3D FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* FEAT_MTE_STORE= _ONLY */ - t =3D FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* FEAT_MTE_PERM */ + t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */ + t =3D FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* v8.7: FEAT_MTE_TAGG= ED_FAR */ + t =3D FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* v8.7: FEAT_MTE_S= TORE_ONLY */ + t =3D FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* v8.7: FEAT_MTE_PERM= */ SET_IDREG(isar, ID_AA64PFR2, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR0); - t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supporte= d */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* v8.1: FEAT_LPA: 52 = bits */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* v8.0: FEAT_TGran16= K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* v8.0: FEAT_S2TGran= 4K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* v8.0: FEAT_S2TGran= 64K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* v8.0: FEAT_S2TGran= 4K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* v8.5: FEAT_FGT */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* v8.5: FEAT_ECV */ SET_IDREG(isar, ID_AA64MMFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* FEAT_AFP */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* FEAT_CMOW */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* v8.0: FEAT_HAFDBS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* v8.0: FEAT_VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* v8.0: FEAT_VHE */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* v8.1: FEAT_HPDS2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* v8.0: FEAT_LOR */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* v8.1: FEAT_PAN3 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* v8.1: FEAT_XNX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* v8.0: FEAT_ETS2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* v8.6: FEAT_HCX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* v8.6: FEAT_AFP */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* v8.7: FEAT_TIDCP1 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* v8.7: FEAT_CMOW */ SET_IDREG(isar, ID_AA64MMFR1, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR2); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* FEAT_NV2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* v8.1: FEAT_TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* v8.1: FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* v8.1: FEAT_IESB */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* v8.1: FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* v8.3: FEAT_NV2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* v8.3: FEAT_TTST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* v8.2: FEAT_LSE2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* v8.3: FEAT_IDST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* v8.3: FEAT_S2FWB */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* v8.3: FEAT_TTL */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* v8.3: FEAT_BBML2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* v8.2: FEAT_EVT2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* v8.4: FEAT_E0PD */ SET_IDREG(isar, ID_AA64MMFR2, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR3); - t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* FEAT_S1PIE */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* FEAT_S2PIE */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* v8.0: FEAT_TCR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* v8.0: FEAT_SCTLR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* v8.2: FEAT_FPACC_= SPEC */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* v8.8: FEAT_S1PIE */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* v8.8: FEAT_S2PIE */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* v8.8: FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR4); - t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* FEAT_ASID2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ SET_IDREG(isar, ID_AA64MMFR4, t); =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* FEAT_BF16, FEAT_EBF= 16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* FEAT_SVE_B16B16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* v9.2: FEAT_SVE2p1 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* v8.2: FEAT_EBF16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 = */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* v8.1: FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* v8.2: FEAT_F32MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* v8.2: FEAT_F64MM */ SET_IDREG(isar, ID_AA64ZFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64DFR0); - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ - t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* v8.7: FEAT_Debugv8p= 8 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* v8.4: FEAT_PMUv3p5 = */ + t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* v8.5: FEAT_HPMN0 */ SET_IDREG(isar, ID_AA64DFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64SMFR0); - t =3D FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* FEAT_SME_MOP4 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* FEAT_SME_TMOP */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* FEAT_SSVE_FEXPA */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* FEAT_SSVE_AES */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* FEAT_SSVE_FP8DOT2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* FEAT_SSVE_FP8DOT4 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* FEAT_SSVE_FP8FMA */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, BI32I32, 1); /* FEAT_SME2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F32, 1); /* FEAT_SME_F8F32 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F16, 1); /* FEAT_SME_F8F16 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F16, 1); /* FEAT_SME_F16F16 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, B16B16, 1); /* FEAT_SME_B16B16 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* FEAT_SME2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 2); /* FEAT_SME2p1 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, LUTv2, 1); /* FEAT_SME_LUTv2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* v9.4: FEAT_SME_MOP4= */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* v9.4: FEAT_SME_TMOP= */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* v9.4: FEAT_SSVE_FEX= PA */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* v9.5: FEAT_SSVE_AES= */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* v9.2: FEAT_SSVE_FP8= DOT2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* v9.2: FEAT_SSVE_FP8= DOT4 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* v9.2: FEAT_SSVE_FP8= FMA */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, BI32I32, 1); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F32, 1); /* v9.2: FEAT_SME_F8F3= 2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F16, 1); /* v9.2: FEAT_SME_F8F1= 6 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F16, 1); /* v9.2: FEAT_SME_F16F= 16 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16B16, 1); /* v9.2: FEAT_SME_B16B= 16 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* v9.2: FEAT_SME_F64F= 64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* v9.2: FEAT_SME_I16I= 64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 2); /* v9.2: FEAT_SME2p1 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, LUTv2, 1); /* v9.2: FEAT_SME_LUTv= 2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* v9.2: FEAT_SME_FA64= */ SET_IDREG(isar, ID_AA64SMFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64FPFR0); - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* FEAT_FP8 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* FEAT_FP8 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM4, 1); /* FEAT_F8F16MM */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM8, 1); /* FEAT_F8F32MM */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP2, 1); /* FEAT_FP8DOT2 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP4, 1); /* FEAT_FP8DOT4 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8FMA, 1); /* FEAT_FP8FMA */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* FEAT_FP8 */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* v9.2: FEAT_FP8 */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* v9.2: FEAT_FP8 */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM4, 1); /* v9.2: FEAT_F8F16MM = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM8, 1); /* v9.2: FEAT_F8F32MM = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP2, 1); /* v9.2: FEAT_FP8DOT2 = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP4, 1); /* v9.2: FEAT_FP8DOT4 = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8FMA, 1); /* v9.2: FEAT_FP8FMA */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* v9.2: FEAT_FP8 */ SET_IDREG(isar, ID_AA64FPFR0, t); =20 /* Replicate the same data to the 32-bit id registers. */ @@ -1432,19 +1435,31 @@ void aarch64_max_tcg_initfn(Object *obj) cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ set_dczid_bs(cpu, 7); /* 512 bytes */ #endif + + /* v8.4: FEAT_MTE2 */ cpu->gm_blocksize =3D 6; /* 256 bytes */ =20 + /* v8.2: FEAT_SVE */ cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); - cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; - - aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); - aarch64_add_sme_properties(obj); object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, cpu_max_set_sve_max_vq, NULL, NULL); + + /* v9.2: FEAT_SME */ + cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; + aarch64_add_sme_properties(obj); + + /* v8.2: FEAT_PAuth2 */ + aarch64_add_pauth_properties(obj); + + /* v9.1: FEAT_RME */ object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rm= e); + + /* v9.4: FEAT_RME_GPC2 */ object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, cpu_max_set_l0gptsz, NULL, NULL); + + /* v8.6: FEAT_LPA2 */ qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); } =20 --=20 2.43.0 From nobody Wed Aug 26 07:29:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Do not include the prohibited v8 features in "max-v9". In tcg mode, define "max" as "max-v9". Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/cpu-max.c | 2 +- target/arm/tcg/cpu64.c | 162 ++++++++++++++++++++++------------ target/arm/tcg/stubs32.c | 2 +- docs/system/arm/emulation.rst | 11 ++- 5 files changed, 120 insertions(+), 59 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f6b4e173a5..95b201dac3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1809,7 +1809,7 @@ void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **er= rp); void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); -void aarch64_max_tcg_initfn(Object *obj); +void aarch64_max_v9_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 8d968336a8..415142acfc 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -109,7 +109,7 @@ static void cpu_max_initfn(Object *obj) if (!aarch64_enabled) { aarch32_max_tcg_init(cpu); } else { - aarch64_max_tcg_initfn(obj); + aarch64_max_v9_tcg_initfn(obj); } return; } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index a5cad987d9..d54d9b8399 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1156,11 +1156,10 @@ static void aarch64_neoverse_n2_initfn(Object *obj) } =20 /* - * -cpu max: a CPU with as many features enabled as our emulation supports. - * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; - * this only needs to handle 64 bits. + * -cpu max-v8: an ARMv8 CPU with as many features enabled as + * our emulation supports. */ -void aarch64_max_tcg_initfn(Object *obj) +static void aarch64_max_v8_tcg_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; @@ -1234,7 +1233,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* v8.0: FEAT_SHA1 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* v8.1: FEAT_SHA512 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* v8.0: FEAT_CRC32 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* v9.3: FEAT_LSE128 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* v8.0: FEAT_LSE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* v8.0: FEAT_RDM */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* v8.1: FEAT_SHA3 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* v8.1: FEAT_SM3 */ @@ -1267,16 +1266,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* v8.7: FEAT_MOPS */ t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* v8.7: FEAT_HBC */ t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* v8.6: FEAT_WFxT */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 1); /* v8.7: FEAT_CSSC */ t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* v8.8: FEAT_ATS1A */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 - t =3D GET_IDREG(isar, ID_AA64ISAR3); - t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* v9.2: FEAT_FAMINMAX= */ - t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* v9.5: FEAT_FPRCVT */ - SET_IDREG(isar, ID_AA64ISAR3, t); - t =3D GET_IDREG(isar, ID_AA64PFR0); t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* v8.2: FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* v8.2: FEAT_FP16 */ @@ -1298,17 +1291,14 @@ void aarch64_max_tcg_initfn(Object *obj) */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* v8.5: FEAT_MTE3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* v8.3: FEAT_DoubleFa= ult */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* v9.2: FEAT_SME2 */ t =3D FIELD_DP64(t, ID_AA64PFR1, RNDR_TRAP, 1); /* v8.4: FEAT_RNG_TRAP= */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* v8.0: FEAT_CSV2_3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* v8.7: FEAT_NMI */ - t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* v9.3: FEAT_GCS */ /* v8.7: FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTEX, 1); SET_IDREG(isar, ID_AA64PFR1, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR2); - t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */ t =3D FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* v8.7: FEAT_MTE_TAGG= ED_FAR */ t =3D FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* v8.7: FEAT_MTE_S= TORE_ONLY */ t =3D FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* v8.7: FEAT_MTE_PERM= */ @@ -1358,25 +1348,14 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D GET_IDREG(isar, ID_AA64MMFR3); t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* v8.0: FEAT_TCR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* v8.0: FEAT_SCTLR2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* v8.2: FEAT_FPACC_= SPEC */ t =3D FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* v8.8: FEAT_S1PIE */ t =3D FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* v8.8: FEAT_S2PIE */ t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* v8.8: FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 - t =3D GET_IDREG(isar, ID_AA64MMFR4); - t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ - SET_IDREG(isar, ID_AA64MMFR4, t); - t =3D GET_IDREG(isar, ID_AA64ZFR0); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* v9.2: FEAT_SVE2p1 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* v8.2: FEAT_EBF16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 = */ t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* v8.1: FEAT_I8MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* v8.2: FEAT_F32MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* v8.2: FEAT_F64MM */ @@ -1388,6 +1367,106 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* v8.5: FEAT_HPMN0 */ SET_IDREG(isar, ID_AA64DFR0, t); =20 + /* Replicate the same data to the 32-bit id registers. */ + aa32_max_features(cpu); + +#ifdef CONFIG_USER_ONLY + /* + * For usermode -cpu max we can use a larger and more efficient DCZ + * blocksize since we don't have to follow what the hardware does. + */ + cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ + set_dczid_bs(cpu, 7); /* 512 bytes */ +#endif + + /* v8.2: FEAT_SVE */ + cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); + aarch64_add_sve_properties(OBJECT(cpu)); + object_property_add(OBJECT(cpu), "sve-max-vq", "uint32", + cpu_max_get_sve_max_vq, cpu_max_set_sve_max_vq, + NULL, NULL); + + /* v8.2: FEAT_PAuth2 */ + aarch64_add_pauth_properties(OBJECT(cpu)); + + /* v8.4: FEAT_MTE2 */ + cpu->gm_blocksize =3D 6; /* 256 bytes */ + + /* v8.6: FEAT_LPA2 */ + qdev_property_add_static(DEVICE(cpu), &arm_cpu_lpa2_property); +} + +/* + * -cpu max-v9: an ARMv9 CPU with as many features enabled as + * our emulation supports. + */ +void aarch64_max_v9_tcg_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; + uint64_t t; + + /* Armv9.0 is based on a minimum of Armv8.5. */ + aarch64_max_v8_tcg_initfn(obj); + + /* + * Armv9.0 does not support AArch32 except at EL0, + * therefore indicate EL1 through EL3 are AArch64-only. + */ + t =3D GET_IDREG(isar, ID_AA64PFR0); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL1, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL2, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL3, 1); + SET_IDREG(isar, ID_AA64PFR0, t); + + /* v9.0 prohibits FEAT_DoubleLock. */ + FIELD_DP64_IDREG(isar, ID_AA64DFR0, DOUBLELOCK, -1); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, RAS, 1); + isar->dbgdevid =3D FIELD_DP32(isar->dbgdevid, DBGDEVID, DOUBLELOCK, 0); + + /* + * Below, note the revision from which the feature is OPTIONAL. + */ + t =3D GET_IDREG(isar, ID_AA64ISAR0); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* v9.3: FEAT_LSE128 */ + SET_IDREG(isar, ID_AA64ISAR0, t); + + t =3D GET_IDREG(isar, ID_AA64ISAR2); + t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ + SET_IDREG(isar, ID_AA64ISAR2, t); + + t =3D GET_IDREG(isar, ID_AA64ISAR3); + t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* v9.2: FEAT_FAMINMAX= */ + t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* v9.5: FEAT_FPRCVT */ + SET_IDREG(isar, ID_AA64ISAR3, t); + + t =3D GET_IDREG(isar, ID_AA64PFR1); + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* v9.3: FEAT_GCS */ + SET_IDREG(isar, ID_AA64PFR1, t); + + t =3D GET_IDREG(isar, ID_AA64PFR2); + t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */ + SET_IDREG(isar, ID_AA64PFR2, t); + + t =3D GET_IDREG(isar, ID_AA64MMFR3); + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ + SET_IDREG(isar, ID_AA64MMFR3, t); + + t =3D GET_IDREG(isar, ID_AA64MMFR4); + t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ + SET_IDREG(isar, ID_AA64MMFR4, t); + + t =3D GET_IDREG(isar, ID_AA64ZFR0); + t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* v9.2: FEAT_SVE2p1 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 = */ + SET_IDREG(isar, ID_AA64ZFR0, t); + t =3D GET_IDREG(isar, ID_AA64SMFR0); t =3D FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* v9.4: FEAT_SME_MOP4= */ t =3D FIELD_DP64(t, ID_AA64SMFR0, STMOP, 1); /* v9.4: FEAT_SME_TMOP= */ @@ -1424,43 +1503,16 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* v9.2: FEAT_FP8 */ SET_IDREG(isar, ID_AA64FPFR0, t); =20 - /* Replicate the same data to the 32-bit id registers. */ - aa32_max_features(cpu); - -#ifdef CONFIG_USER_ONLY - /* - * For usermode -cpu max we can use a larger and more efficient DCZ - * blocksize since we don't have to follow what the hardware does. - */ - cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ - set_dczid_bs(cpu, 7); /* 512 bytes */ -#endif - - /* v8.4: FEAT_MTE2 */ - cpu->gm_blocksize =3D 6; /* 256 bytes */ - - /* v8.2: FEAT_SVE */ - cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); - aarch64_add_sve_properties(obj); - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, - cpu_max_set_sve_max_vq, NULL, NULL); - /* v9.2: FEAT_SME */ cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; aarch64_add_sme_properties(obj); =20 - /* v8.2: FEAT_PAuth2 */ - aarch64_add_pauth_properties(obj); - /* v9.1: FEAT_RME */ object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rm= e); =20 /* v9.4: FEAT_RME_GPC2 */ object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, cpu_max_set_l0gptsz, NULL, NULL); - - /* v8.6: FEAT_LPA2 */ - qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); } =20 static const ARMCPUInfo aarch64_cpus[] =3D { @@ -1478,8 +1530,8 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, - { .name =3D "max-v8", .initfn =3D aarch64_max_tcg_initfn }, - { .name =3D "max-v9", .initfn =3D aarch64_max_tcg_initfn }, + { .name =3D "max-v8", .initfn =3D aarch64_max_v8_tcg_initf= n }, + { .name =3D "max-v9", .initfn =3D aarch64_max_v9_tcg_initf= n }, }; =20 static void aarch64_cpu_register_types(void) diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c index 78f819ef6f..939cea7189 100644 --- a/target/arm/tcg/stubs32.c +++ b/target/arm/tcg/stubs32.c @@ -28,7 +28,7 @@ void aarch64_host_initfn(Object *obj) g_assert_not_reached(); } =20 -void aarch64_max_tcg_initfn(Object *obj) +void aarch64_max_v9_tcg_initfn(Object *obj) { g_assert_not_reached(); } diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index cc42db9e0b..0a1a5bec93 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -230,7 +230,16 @@ to the `Arm Architecture Reference Manual for A-profil= e architecture When a specific named CPU is being emulated, only those features which are present in hardware for that CPU are emulated. (If a feature is not in the list above then it is not supported, even if the real -hardware should have it.) The ``max`` CPU enables all features. +hardware should have it.) + +The ``max-v8`` CPU enables all of the listed Armv8-A architecture +extensions but none of the Armv9-A architecture extensions. + +The ``max-v9`` CPU enables all of the listed extensions except for +those that are prohibited by the Armv9-A architecture: FEAT_AA32EL1, +FEAT_AA32EL2, FEAT_AA32EL3, and FEAT_DoubleLock. + +The ``max`` CPU is an alias for ``max-v9`` under TCG emulation. =20 R-profile CPU architecture support =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.43.0