From nobody Wed Aug 26 06:37:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1786388428; cv=none; d=zohomail.com; s=zohoarc; b=bPmDwhvT5RjS0h/SxpVouPRbIqv7AgMu6l3vhWtXJobOwSsFC/h+tgBGv6cpKs0U1UYfgOUSN/AGiR903xx3P1lHR/E8pGMw+lCiBN7SdAn8XBRmk6tekFsFpTO5qcpu1iL6Yv6QEdcPhlQPDx6xDc7gsK+N+4ueTftl41Ph71o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786388428; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UrFuDFzpdhvLqMbSp8uSpjVRXqP7RXty94LVtAtZMR8=; b=Y8hgL0XB5WEuFLvmxLtHwqfLZy/xIz6A2uaP7JzM7Z8aZEwmLx4UoJ7gN7jdERnpeOpERYWB06nXRGXw0d7An0P8QMxj03GfWc16b+E7TVmVfoqSE+gkzn1r+Bb+exarxzypDUczuEpVkrr4TF7/RN1lS5OPjOunAxf6XJnqMfM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786388428706448.8754947602863; Mon, 10 Aug 2026 12:00:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wtVD1-0001c7-7U; Mon, 10 Aug 2026 14:58:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCv-0001Z4-OF; Mon, 10 Aug 2026 14:58:45 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCt-0003Ua-N8; Mon, 10 Aug 2026 14:58:45 -0400 Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67AGVocX2111767; Mon, 10 Aug 2026 18:57:55 GMT Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4fwvq99m4b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:54 +0000 (GMT) Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id 67AIun5l020368; Mon, 10 Aug 2026 18:57:53 GMT Received: from smtprelay04.wdc07v.mail.ibm.com ([172.16.1.71]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4fxf5vx5gn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:53 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay04.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67AIvqYv64225576 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Aug 2026 18:57:52 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 16CF75805C; Mon, 10 Aug 2026 18:57:52 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3034658051; Mon, 10 Aug 2026 18:57:51 +0000 (GMT) Received: from IBM-MFS.ibm.com (unknown [9.61.24.176]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 10 Aug 2026 18:57:51 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=UrFuDFzpdhvLqMbSp 8uSpjVRXqP7RXty94LVtAtZMR8=; b=L5BFQt0qKjV1f8dNwgL+37rWYXmDVaFfu 4FS+N80PfyUCEwRX0bgMyBGHZWxmSIcxj4CHiuqTVjUTbrzwdb/tK7zwpR96UAml wsun+2tMBjyyCIaqy+/BJu+j9FuFuqzKvuvnTPv6AEaR4Eaxe+HZVJZDyhNSKbPu zjY+A34mz7qh/qRp5pkiI8WqevhO1pJGGQenP//IrkZ6A1dTWb4sWsVFpHamqX40 iN30HBz0ypeJUpXsSEO+Spuy8i8Fj24wZfcSu6RtlbuVbpuRiyD6zZiwZ03XJswA e0mxOjo5cqui8Pg0Wdr2H3kM50QW2WH74fO5GZ5Rq5SFfOLW077vw== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 1/8] fsi/cfam: Add common CFAM base class Date: Mon, 10 Aug 2026 13:57:39 -0500 Message-ID: <20260810185748.1253-2-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260810185748.1253-1-mikail.sadic@ibm.com> References: <20260810185748.1253-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: 2VYSnMgLRYntnwQ5tkr6wTo4qKwLT2lt X-Authority-Analysis: v=2.4 cv=PbDPQChd c=1 sm=1 tr=0 ts=6a7a1f33 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=0vKXlNE1Mb1R75NS9r0A:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfX/UkgkQeUCdLc 3fT64bpZxfhqbIU3JSgX4FkdMNOOM4pXIviYZiEacny69kful/fbIpqH3Xf/frJGagxGnPD2Cya NaXEf65foALS8P89t5IMqqB1R33qh5Ff/XZPmrfNGdk9vAp5+f0U5Vg5tCbalL5yug+XaGPTcLo 37p/vx5yrkaexAmq7fEod4Bq1S4KH3xkhFNXVSOVecVnVaS2cRvdLYXNN9qQL9fQHrMGFOMn0CV wqkwrIaPxIgWrvQDPOz8X7iTdRFeW7sJqljVDzB5wk7VPvrRaAR8Hjd9T1dIaVaDDwt3SXoaZe8 /hoiJbZ9GJSujWoqk15hOu3AMQtyZVwzwiB5aRjKDgWyINCHbeKxTtt8Mxhq1rnHqPiFENoRaO2 a0M9fqPILiqsMewTRJZfNajt67+Xgs2iCXUySO30/vGlMb+RTVAn2fIJI0GJsrCpJ1vmTijEv5r Zy0d/n+GDYvytyXO17A== X-Proofpoint-ORIG-GUID: JrvSfiMgnZNkXk-Xgb6SZvoR9xa9fVpg X-Proofpoint-Spam-Info: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfX3EJFjF5lsysh sq+XlAr81IsUILlVUtRyjQSQRG1mdSooV3049w0dKhGlrlIk6qcDWLp7S8CR07SIAHOFRdfq+BM tCA69VDDSPEnxK41r1Fy+u+MdJjMtB4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-10_04,2026-08-10_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 impostorscore=0 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608100158 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1786388429555158500 Content-Type: text/plain; charset="utf-8" Prepare a common CFAM parent class for CFAM-S implementation. Add an abstract TYPE_FSI_CFAM_COMMON with an FSICFAMCommonClass holding what varies between types: the config table, the offsets of the FSI responder and the local bus within the register slot, and a realize_engines() hook for the engines on the local bus. Its realize is driven by those fields, so one realize serves every type. TYPE_FSI_CFAM keeps its name and becomes the first derived type, supplying the P9 config table, its slot offsets and the scratchpad engine. The config table becomes data, still written with the same CFAM_CONFIG_REG() expressions, which move to the header so a derived type can describe its own table the same way. Name the new instance struct without a State suffix and rename FSICFAMState to FSICFAM to match. No functional change: same memory map, same config words, same type and child names. aspeed_fsi-test verified. Signed-off-by: Mikail Sadic Reviewed-by: Glenn Miles --- include/hw/fsi/cfam.h | 58 ++++++++++++++++- include/hw/fsi/fsi-master.h | 2 +- hw/fsi/cfam.c | 125 +++++++++++++++++++++--------------- hw/fsi/fsi-master.c | 2 +- 4 files changed, 130 insertions(+), 57 deletions(-) diff --git a/include/hw/fsi/cfam.h b/include/hw/fsi/cfam.h index cceb4bd6f1..bdf579b4fe 100644 --- a/include/hw/fsi/cfam.h +++ b/include/hw/fsi/cfam.h @@ -7,18 +7,44 @@ #ifndef FSI_CFAM_H #define FSI_CFAM_H =20 +#include "qemu/units.h" #include "system/memory.h" =20 #include "hw/fsi/fsi.h" #include "hw/fsi/lbus.h" =20 +/* + * All CFAM flavors present a register slot holding a config table, an FSI + * responder and a local bus carrying the engines the config table describ= es. + * That is the common model; each flavor supplies its own table, slot layo= ut + * and engines. + */ +#define TYPE_FSI_CFAM_COMMON "cfam-common" +OBJECT_DECLARE_TYPE(FSICFAMCommon, FSICFAMCommonClass, FSI_CFAM_COMMON) + #define TYPE_FSI_CFAM "cfam" -#define FSI_CFAM(obj) OBJECT_CHECK(FSICFAMState, (obj), TYPE_FSI_CFAM) +OBJECT_DECLARE_SIMPLE_TYPE(FSICFAM, FSI_CFAM) =20 /* P9-ism */ #define CFAM_CONFIG_NR_REGS 0x28 =20 -typedef struct FSICFAMState { +#define FSI_CFAM_SLOT_SIZE (2 * MiB) +#define FSI_CFAM_CONFIG_SIZE 0x400 + +#define ENGINE_CONFIG_NEXT BIT(31) +#define ENGINE_CONFIG_TYPE_PEEK (0x02 << 4) +#define ENGINE_CONFIG_TYPE_FSI (0x03 << 4) +#define ENGINE_CONFIG_TYPE_SCRATCHPAD (0x06 << 4) + +/* Valid, slots, version, type, crc */ +#define CFAM_CONFIG_REG(__VER, __TYPE, __CRC) \ + (ENGINE_CONFIG_NEXT | \ + 0x00010000 | \ + (__VER) | \ + (__TYPE) | \ + (__CRC)) + +struct FSICFAMCommon { /* < private > */ FSISlaveState parent; =20 @@ -28,7 +54,33 @@ typedef struct FSICFAMState { MemoryRegion mr; =20 FSILBus lbus; +}; + +struct FSICFAMCommonClass { + /* < private > */ + DeviceClass parent_class; + + /* < public > */ + /* Config table served by the common ops, one word per 4-byte offset */ + const uint32_t *config; + unsigned config_nr; + + /* Layout of the register slot */ + hwaddr responder_offset; + hwaddr lbus_offset; + + /* Realize and map this flavor's local bus engines */ + bool (*realize_engines)(FSICFAMCommon *cfam, Error **errp); +}; + +struct FSICFAM { + /* < private > */ + FSICFAMCommon parent; + FSIScratchPad scratchpad; -} FSICFAMState; +}; + +bool fsi_cfam_add_engine(FSICFAMCommon *cfam, DeviceState *engine, + hwaddr offset, Error **errp); =20 #endif /* FSI_CFAM_H */ diff --git a/include/hw/fsi/fsi-master.h b/include/hw/fsi/fsi-master.h index 60ddaa994f..87c11ec3dc 100644 --- a/include/hw/fsi/fsi-master.h +++ b/include/hw/fsi/fsi-master.h @@ -25,7 +25,7 @@ typedef struct FSIMasterState { FSIBus bus; =20 uint32_t regs[FSI_MASTER_NR_REGS]; - FSICFAMState cfam; + FSICFAM cfam; } FSIMasterState; =20 =20 diff --git a/hw/fsi/cfam.c b/hw/fsi/cfam.c index 54c0b05769..5d4d0622d0 100644 --- a/hw/fsi/cfam.c +++ b/hw/fsi/cfam.c @@ -16,19 +16,6 @@ =20 #include "hw/core/qdev-properties.h" =20 -#define ENGINE_CONFIG_NEXT BIT(31) -#define ENGINE_CONFIG_TYPE_PEEK (0x02 << 4) -#define ENGINE_CONFIG_TYPE_FSI (0x03 << 4) -#define ENGINE_CONFIG_TYPE_SCRATCHPAD (0x06 << 4) - -/* Valid, slots, version, type, crc */ -#define CFAM_CONFIG_REG(__VER, __TYPE, __CRC) \ - (ENGINE_CONFIG_NEXT | \ - 0x00010000 | \ - (__VER) | \ - (__TYPE) | \ - (__CRC)) - #define TO_REG(x) ((x) >> 2) =20 #define CFAM_CONFIG_CHIP_ID TO_REG(0x00) @@ -36,34 +23,33 @@ #define CFAM_CONFIG_CHIP_ID_P9 0xc0022d15 #define CFAM_CONFIG_CHIP_ID_BREAK 0xc0de0000 =20 +/* + * Config table of the P9 CFAM: the chip ID followed by one entry per engi= ne, + * entry n describing the engine at address n * 4. We need to add future + * engines from address 0x10 onwards. + */ +static const uint32_t cfam_p9_config[] =3D { + CFAM_CONFIG_CHIP_ID_P9, + CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_PEEK, 0xc), + CFAM_CONFIG_REG(0x5000, ENGINE_CONFIG_TYPE_FSI, 0xa), + CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_SCRATCHPAD, 0x7), +}; + static uint64_t fsi_cfam_config_read(void *opaque, hwaddr addr, unsigned s= ize) { + FSICFAMCommonClass *cc =3D FSI_CFAM_COMMON_GET_CLASS(opaque); + unsigned int reg =3D TO_REG(addr); + trace_fsi_cfam_config_read(addr, size); =20 - switch (addr) { - case 0x00: - return CFAM_CONFIG_CHIP_ID_P9; - case 0x04: - return CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_PEEK, 0xc); - case 0x08: - return CFAM_CONFIG_REG(0x5000, ENGINE_CONFIG_TYPE_FSI, 0xa); - case 0xc: - return CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_SCRATCHPAD, 0x7); - default: - /* - * The config table contains different engines from 0xc onwards. - * The scratch pad is already added at address 0xc. We need to add - * future engines from address 0x10 onwards. Returning 0 as engine - * is not implemented. - */ - return 0; - } + /* Engines past the end of the table are not implemented */ + return reg < cc->config_nr ? cc->config[reg] : 0; } =20 static void fsi_cfam_config_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { - FSICFAMState *cfam =3D FSI_CFAM(opaque); + FSICFAMCommon *cfam =3D FSI_CFAM_COMMON(opaque); =20 trace_fsi_cfam_config_write(addr, size, data); =20 @@ -109,59 +95,94 @@ static const struct MemoryRegionOps fsi_cfam_unimpleme= nted_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void fsi_cfam_instance_init(Object *obj) +bool fsi_cfam_add_engine(FSICFAMCommon *cfam, DeviceState *engine, + hwaddr offset, Error **errp) { - FSICFAMState *s =3D FSI_CFAM(obj); + if (!qdev_realize(engine, BUS(&cfam->lbus), errp)) { + return false; + } =20 - object_initialize_child(obj, "scratchpad", &s->scratchpad, - TYPE_FSI_SCRATCHPAD); + memory_region_add_subregion(&cfam->lbus.mr, offset, + &FSI_LBUS_DEVICE(engine)->iomem); + return true; } =20 -static void fsi_cfam_realize(DeviceState *dev, Error **errp) +static void fsi_cfam_common_realize(DeviceState *dev, Error **errp) { - FSICFAMState *cfam =3D FSI_CFAM(dev); + FSICFAMCommon *cfam =3D FSI_CFAM_COMMON(dev); + FSICFAMCommonClass *cc =3D FSI_CFAM_COMMON_GET_CLASS(dev); FSISlaveState *slave =3D FSI_SLAVE(dev); + const char *type =3D object_get_typename(OBJECT(dev)); + g_autofree char *config_name =3D g_strdup_printf("%s.config", type); =20 /* Each slave has a 2MiB address space */ memory_region_init_io(&cfam->mr, OBJECT(cfam), &fsi_cfam_unimplemented= _ops, - cfam, TYPE_FSI_CFAM, 2 * MiB); + cfam, type, FSI_CFAM_SLOT_SIZE); =20 qbus_init(&cfam->lbus, sizeof(cfam->lbus), TYPE_FSI_LBUS, DEVICE(cfam), NULL); =20 memory_region_init_io(&cfam->config_iomem, OBJECT(cfam), &cfam_config_= ops, - cfam, TYPE_FSI_CFAM ".config", 0x400); + cfam, config_name, FSI_CFAM_CONFIG_SIZE); =20 memory_region_add_subregion(&cfam->mr, 0, &cfam->config_iomem); - memory_region_add_subregion(&cfam->mr, 0x800, &slave->iomem); - memory_region_add_subregion(&cfam->mr, 0xc00, &cfam->lbus.mr); + memory_region_add_subregion(&cfam->mr, cc->responder_offset, &slave->i= omem); + memory_region_add_subregion(&cfam->mr, cc->lbus_offset, &cfam->lbus.mr= ); =20 - /* Add scratchpad engine */ - if (!qdev_realize(DEVICE(&cfam->scratchpad), BUS(&cfam->lbus), errp)) { + if (!cc->realize_engines(cfam, errp)) { return; } - - FSILBusDevice *fsi_dev =3D FSI_LBUS_DEVICE(&cfam->scratchpad); - memory_region_add_subregion(&cfam->lbus.mr, 0, &fsi_dev->iomem); } =20 -static void fsi_cfam_class_init(ObjectClass *klass, const void *data) +static void fsi_cfam_common_class_init(ObjectClass *klass, const void *dat= a) { DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->bus_type =3D TYPE_FSI_BUS; - dc->realize =3D fsi_cfam_realize; + dc->realize =3D fsi_cfam_common_realize; +} + +static bool fsi_cfam_realize_engines(FSICFAMCommon *cfam, Error **errp) +{ + FSICFAM *s =3D FSI_CFAM(cfam); + + /* Add scratchpad engine */ + object_initialize_child(OBJECT(s), "scratchpad", &s->scratchpad, + TYPE_FSI_SCRATCHPAD); + + return fsi_cfam_add_engine(cfam, DEVICE(&s->scratchpad), 0, errp); } =20 +static void fsi_cfam_class_init(ObjectClass *klass, const void *data) +{ + FSICFAMCommonClass *cc =3D FSI_CFAM_COMMON_CLASS(klass); + + cc->config =3D cfam_p9_config; + cc->config_nr =3D ARRAY_SIZE(cfam_p9_config); + cc->responder_offset =3D 0x800; + cc->lbus_offset =3D 0xc00; + cc->realize_engines =3D fsi_cfam_realize_engines; +} + +static const TypeInfo fsi_cfam_common_info =3D { + .name =3D TYPE_FSI_CFAM_COMMON, + .parent =3D TYPE_FSI_SLAVE, + .instance_size =3D sizeof(FSICFAMCommon), + .class_size =3D sizeof(FSICFAMCommonClass), + .class_init =3D fsi_cfam_common_class_init, + .abstract =3D true, +}; + static const TypeInfo fsi_cfam_info =3D { .name =3D TYPE_FSI_CFAM, - .parent =3D TYPE_FSI_SLAVE, - .instance_init =3D fsi_cfam_instance_init, - .instance_size =3D sizeof(FSICFAMState), + .parent =3D TYPE_FSI_CFAM_COMMON, + .instance_size =3D sizeof(FSICFAM), .class_init =3D fsi_cfam_class_init, }; =20 static void fsi_cfam_register_types(void) { + type_register_static(&fsi_cfam_common_info); type_register_static(&fsi_cfam_info); } =20 diff --git a/hw/fsi/fsi-master.c b/hw/fsi/fsi-master.c index 083a5507ab..d82df1c094 100644 --- a/hw/fsi/fsi-master.c +++ b/hw/fsi/fsi-master.c @@ -130,7 +130,7 @@ static void fsi_master_realize(DeviceState *dev, Error = **errp) } =20 /* address ? */ - memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.mr); + memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.parent.mr); } =20 static void fsi_master_reset(DeviceState *dev) --=20 2.53.0 From nobody Wed Aug 26 06:37:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1786388428; cv=none; d=zohomail.com; s=zohoarc; b=F5K8inRLlXAzOh/TwgP4QkJWVyfQDSZ0S2J8QjEzIg9bBNUWRD8D3ZideASlir7h3FCs44jqcXcM1lJAcglB/gMA6ZwKX/nQHF8bPwwmLQ3XubUZ5HIvJ9dgngYkI1EXB4Gsllgby2o8bM1t+InYfSVXWFvfXHo/KsStBhGc0yA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786388428; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sYF/s/U4LgaUiXPbNj1yXqxFesF3T/zSzYSIj81WkTA=; b=UQuau92axJnvdMH4lq1higcFrIlR19pLxH3Wf/hK8BZTgTtfzUP4kS15ZeqlVci1TQelteNCl1/kyI2r4AdBPfj1Y/nmH6POgXkXE6RsWE+TDO4eKbJKyPd09veQIvkVrc624Eqz6hMyvhkAn5KJ7WP3gYwtUEFkqGG+7a4TPZ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786388428968438.8631351021535; Mon, 10 Aug 2026 12:00:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wtVCg-0001Xs-SN; Mon, 10 Aug 2026 14:58:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCe-0001WX-U4; Mon, 10 Aug 2026 14:58:28 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCc-0003Sk-9K; Mon, 10 Aug 2026 14:58:28 -0400 Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67AGVfuC2154231; Mon, 10 Aug 2026 18:57:56 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4fwvm9hngn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:55 +0000 (GMT) Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id 67AIuL6c019212; Mon, 10 Aug 2026 18:57:54 GMT Received: from smtprelay04.wdc07v.mail.ibm.com ([172.16.1.71]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4fxg9gx00n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:54 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay04.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67AIvrdR22217466 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Aug 2026 18:57:53 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DD3F35805E; Mon, 10 Aug 2026 18:57:52 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2F35258051; Mon, 10 Aug 2026 18:57:52 +0000 (GMT) Received: from IBM-MFS.ibm.com (unknown [9.61.24.176]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 10 Aug 2026 18:57:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=sYF/s/U4LgaUiXPbN j1yXqxFesF3T/zSzYSIj81WkTA=; b=fznVtr8dFXP9nO4+DK4RgoxJeh8ROOhk6 RKEoA7uVRLapnZth8dQNd9aM85WwjrImNEhP+LmOoKrCMI/myhV89lNwV04JJeBi wMpQUlGS+gCbPi/g6Jd2CjbJaVfV5JH4ZsE4XNl8dytSBZz15w5+za2usREt7yuJ 93HvzZwgdDEumBNZhdsr1+Ug6WlLAuIqffu8OBW3vJmXuGpUu0IKAI4BMT2FCfIG uKslkROqtPTArbX6BQVZJFOfq63kOYBdvBAiqUP1TcLclyBsIwsTrxTyR+WfSuk8 CmmVNaOyewNec6Yk6dLJvL5EkWxiYViA1TKt4kPbpOcj5hxbDAvMQ== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 2/8] fsi/cfam: Add CFAM-S model Date: Mon, 10 Aug 2026 13:57:40 -0500 Message-ID: <20260810185748.1253-3-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260810185748.1253-1-mikail.sadic@ibm.com> References: <20260810185748.1253-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfX3ItgxrhfK1n7 czdZI9Wz0IGO09RG0YbKHM1eUb/LHBE6D3gRymlv+1OzqUPYD2GSjAdlNjo6NCuvGtYMAfvKoLJ lsPO+tD+SGxpm30Jj2nzpXeVLLTUyIC8bLi57NA5k0bcVDrtesIkwTHngHog+0y0ZDj7SiIZEft TWg7/stDXoaX4DvIVGKbkNLw5taISGGyMtf7ASRu/F9F9la7Raza037lMl7vKiTXDhsjI3i1Iar MK/3zr8fIv05GQNd+Zrxypv89hldhELNUran8AIqsahhVabCvGDbJciau7vHtAAjOc9DIvWl7LV KNVIxxAqyhH/ZT+GE4KsZGecymSqGc3Beqt9OMCcB2bIRehOHCJAO4TWJDAyLzFuvtMrQpOnJtj Ju+fEXjIkHTpMxCfxQH+wx8Figb3bm4prFRZk8YxvCGVVBzJqVnev5DM85KxhRhWOmM/7yqLRRt 4h8E3Q5wm22L2+zFPjQ== X-Proofpoint-ORIG-GUID: aP_OFh-TPG5Rhov69IisQKd0TiM6u1zA X-Proofpoint-Spam-Info: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfXzHlQax9PVAKQ V/JdKST890/ILnd/sER8PKqwWD29w5dz93fbf5dNk0ye5s8CPV+gjB/ZaF0iyOP4f24ICjW7TGT 94EHeg0EJRj1/b46uBA4+YMmbxvN1g4= X-Authority-Analysis: v=2.4 cv=IfK3n2qa c=1 sm=1 tr=0 ts=6a7a1f34 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=NEAV23lmAAAA:8 a=VnNF1IyMAAAA:8 a=GLtLAL1jAtWljCBMQDYA:9 X-Proofpoint-GUID: zGXiNsGtnctVRx7JBsbEtKLsIKVbBcQR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-10_04,2026-08-10_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608100158 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1786388429573158500 Content-Type: text/plain; charset="utf-8" Add TYPE_FSI_CFAM_S, derivative of CFAM, as a second type on the common CFAM base class. The base class builds the register slot, the config table region, the FSI responder and the local bus, so the CFAM-S supplies only its config table (chip ID with major 9, an FSI responder and a v1 mailbox), its slot offsets and the mailbox engine. Its realize chains the base one and adds the one thing that is new: the slot is aliased across the four slave-ID views, so enumeration and normal access reach the same registers. The v1 mailbox is a local bus engine added in lbus.c next to the scratchpad which the CFAM-S just instantiates. Sharing the base config table implementation means the CFAM-S also honors the SID_BREAK sequence and word-only config access. FSIMasterState gains a cfam_s field. fsi_master_init() creates both the cfam and cfam-s children, realize hooks them into the OPB-to-FSI aperture. Signed-off-by: Mikail Sadic --- docs/specs/fsi.rst | 15 ++++++ include/hw/fsi/cfam-s.h | 40 ++++++++++++++++ include/hw/fsi/cfam.h | 10 ++++ include/hw/fsi/fsi-master.h | 2 + include/hw/fsi/lbus.h | 11 +++++ hw/fsi/cfam-s.c | 91 +++++++++++++++++++++++++++++++++++++ hw/fsi/fsi-master.c | 7 +++ hw/fsi/lbus.c | 69 ++++++++++++++++++++++++++++ hw/fsi/meson.build | 2 +- hw/fsi/trace-events | 2 + 10 files changed, 248 insertions(+), 1 deletion(-) create mode 100644 include/hw/fsi/cfam-s.h create mode 100644 hw/fsi/cfam-s.c diff --git a/docs/specs/fsi.rst b/docs/specs/fsi.rst index f7d86d3e37..fb7a3669ef 100644 --- a/docs/specs/fsi.rst +++ b/docs/specs/fsi.rst @@ -120,3 +120,18 @@ from the BMC. (see the `pdbg source repository`_ for m= ore details) =20 .. _pdbg source repository: https://github.com/open-power/pdbg + +CFAM-S model +------------ + +The CFAM-S is a derivative of the CFAM. Both are modelled on a common CFAM +model that builds the register slot, the configuration table, the FSI +responder and the local bus; each supplies its own configuration table, sl= ot +layout and engines. The CFAM-S supports a limited set of engines: an FSI +responder and a version 1 mailbox. + +The configuration table advertises the responder and the mailbox engines. +The responder is backed by the FSI slave control registers; the mailbox +provides a small block of scratch registers. The register block is exposed +through each slave-ID view so that enumeration and normal access reach the +same registers. diff --git a/include/hw/fsi/cfam-s.h b/include/hw/fsi/cfam-s.h new file mode 100644 index 0000000000..041607d5ce --- /dev/null +++ b/include/hw/fsi/cfam-s.h @@ -0,0 +1,40 @@ +/* + * IBM Common FRU Access Macro - S variant (CFAM-S) + * + * Copyright (C) 2026 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef FSI_CFAM_S_H +#define FSI_CFAM_S_H + +#include "system/memory.h" +#include "hw/fsi/cfam.h" +#include "hw/fsi/fsi.h" +#include "hw/fsi/lbus.h" + +#define TYPE_FSI_CFAM_S "cfam-s" +OBJECT_DECLARE_TYPE(FSICFAMS, FSICFAMSClass, FSI_CFAM_S) + +/* The register slot is visible in each of the four slave-ID views */ +#define CFAM_S_WINDOW_SIZE (4 * FSI_CFAM_SLOT_SIZE) + +struct FSICFAMS { + /* < private > */ + FSICFAMCommon parent; + + /* parent.mr aliased across the slave-ID views */ + MemoryRegion window; + MemoryRegion slot_alias[3]; + + FSIMbox mbox; +}; + +struct FSICFAMSClass { + /* < private > */ + FSICFAMCommonClass parent_class; + + DeviceRealize parent_realize; +}; + +#endif /* FSI_CFAM_S_H */ diff --git a/include/hw/fsi/cfam.h b/include/hw/fsi/cfam.h index bdf579b4fe..a9cd7b7f63 100644 --- a/include/hw/fsi/cfam.h +++ b/include/hw/fsi/cfam.h @@ -35,6 +35,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FSICFAM, FSI_CFAM) #define ENGINE_CONFIG_TYPE_PEEK (0x02 << 4) #define ENGINE_CONFIG_TYPE_FSI (0x03 << 4) #define ENGINE_CONFIG_TYPE_SCRATCHPAD (0x06 << 4) +#define ENGINE_CONFIG_TYPE_MBOX_V1 (0x14 << 4) =20 /* Valid, slots, version, type, crc */ #define CFAM_CONFIG_REG(__VER, __TYPE, __CRC) \ @@ -44,6 +45,15 @@ OBJECT_DECLARE_SIMPLE_TYPE(FSICFAM, FSI_CFAM) (__TYPE) | \ (__CRC)) =20 +/* As above, for the last entry in a table: NEXT is clear */ +#define CFAM_CONFIG_LAST(__VER, __TYPE, __CRC) \ + (0x00010000 | \ + (__VER) | \ + (__TYPE) | \ + (__CRC)) + +#define CFAM_CONFIG_CHIP_ID_MAJOR(__MAJOR) (((__MAJOR) & 0xf) << 8) + struct FSICFAMCommon { /* < private > */ FSISlaveState parent; diff --git a/include/hw/fsi/fsi-master.h b/include/hw/fsi/fsi-master.h index 87c11ec3dc..dc51c96840 100644 --- a/include/hw/fsi/fsi-master.h +++ b/include/hw/fsi/fsi-master.h @@ -11,6 +11,7 @@ #include "hw/core/qdev.h" #include "hw/fsi/fsi.h" #include "hw/fsi/cfam.h" +#include "hw/fsi/cfam-s.h" =20 #define TYPE_FSI_MASTER "fsi.master" OBJECT_DECLARE_SIMPLE_TYPE(FSIMasterState, FSI_MASTER) @@ -26,6 +27,7 @@ typedef struct FSIMasterState { =20 uint32_t regs[FSI_MASTER_NR_REGS]; FSICFAM cfam; + FSICFAMS cfam_s; } FSIMasterState; =20 =20 diff --git a/include/hw/fsi/lbus.h b/include/hw/fsi/lbus.h index 1b894509fe..582d7169d6 100644 --- a/include/hw/fsi/lbus.h +++ b/include/hw/fsi/lbus.h @@ -40,4 +40,15 @@ typedef struct FSIScratchPad { uint32_t regs[FSI_SCRATCHPAD_NR_REGS]; } FSIScratchPad; =20 +#define TYPE_FSI_MBOX "fsi.mbox" +OBJECT_DECLARE_SIMPLE_TYPE(FSIMbox, FSI_MBOX) + +#define FSI_MBOX_SCRATCH_NUM 5 + +struct FSIMbox { + FSILBusDevice parent; + + uint32_t scratch[FSI_MBOX_SCRATCH_NUM]; +}; + #endif /* FSI_LBUS_H */ diff --git a/hw/fsi/cfam-s.c b/hw/fsi/cfam-s.c new file mode 100644 index 0000000000..7a6047944f --- /dev/null +++ b/hw/fsi/cfam-s.c @@ -0,0 +1,91 @@ +/* + * IBM Common FRU Access Macro - S variant (CFAM-S) + * + * A CFAM flavor built on the common CFAM model (see cfam.c). It supports = an + * FSI responder and a v1 mailbox, and exposes its register slot in each + * slave-ID view of the link. + * + * Copyright (C) 2026 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/units.h" +#include "hw/fsi/cfam-s.h" +#include "hw/fsi/fsi.h" + +/* Slot layout: 0x000 config table, 0x400 responder, 0x800 mailbox */ +#define CFAM_S_RESPONDER_BASE 0x400 +#define CFAM_S_MBOX_BASE 0x800 + +/* Config table: chip ID with major 9 (the CFAM-S), then the engines */ +static const uint32_t cfam_s_config[] =3D { + ENGINE_CONFIG_NEXT | CFAM_CONFIG_CHIP_ID_MAJOR(9) | 0xd, + CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_FSI, 0xb), + CFAM_CONFIG_LAST(0x1000, ENGINE_CONFIG_TYPE_MBOX_V1, 0x3), +}; + +static bool fsi_cfam_s_realize_engines(FSICFAMCommon *cfam, Error **errp) +{ + FSICFAMS *cfam_s =3D FSI_CFAM_S(cfam); + + object_initialize_child(OBJECT(cfam_s), "mbox", &cfam_s->mbox, + TYPE_FSI_MBOX); + return fsi_cfam_add_engine(cfam, DEVICE(&cfam_s->mbox), 0, errp); +} + +static void fsi_cfam_s_realize(DeviceState *dev, Error **errp) +{ + ERRP_GUARD(); + FSICFAMS *cfam_s =3D FSI_CFAM_S(dev); + FSICFAMCommon *cfam =3D FSI_CFAM_COMMON(dev); + FSICFAMSClass *sc =3D FSI_CFAM_S_GET_CLASS(dev); + + sc->parent_realize(dev, errp); + if (*errp) { + return; + } + + memory_region_init(&cfam_s->window, OBJECT(cfam_s), + TYPE_FSI_CFAM_S ".window", CFAM_S_WINDOW_SIZE); + memory_region_add_subregion(&cfam_s->window, 0, &cfam->mr); + + /* Alias the slot into the other three slave-ID views */ + for (int i =3D 0; i < ARRAY_SIZE(cfam_s->slot_alias); i++) { + memory_region_init_alias(&cfam_s->slot_alias[i], OBJECT(cfam_s), + TYPE_FSI_CFAM_S ".slot-alias", &cfam->mr,= 0, + FSI_CFAM_SLOT_SIZE); + memory_region_add_subregion(&cfam_s->window, + (i + 1) * FSI_CFAM_SLOT_SIZE, + &cfam_s->slot_alias[i]); + } +} + +static void fsi_cfam_s_class_init(ObjectClass *klass, const void *data) +{ + FSICFAMSClass *sc =3D FSI_CFAM_S_CLASS(klass); + FSICFAMCommonClass *cc =3D FSI_CFAM_COMMON_CLASS(klass); + + device_class_set_parent_realize(DEVICE_CLASS(klass), fsi_cfam_s_realiz= e, + &sc->parent_realize); + + cc->config =3D cfam_s_config; + cc->config_nr =3D ARRAY_SIZE(cfam_s_config); + cc->responder_offset =3D CFAM_S_RESPONDER_BASE; + cc->lbus_offset =3D CFAM_S_MBOX_BASE; + cc->realize_engines =3D fsi_cfam_s_realize_engines; +} + +static const TypeInfo cfam_s_types[] =3D { + { + .name =3D TYPE_FSI_CFAM_S, + .parent =3D TYPE_FSI_CFAM_COMMON, + .instance_size =3D sizeof(FSICFAMS), + .class_size =3D sizeof(FSICFAMSClass), + .class_init =3D fsi_cfam_s_class_init, + }, +}; + +DEFINE_TYPES(cfam_s_types) diff --git a/hw/fsi/fsi-master.c b/hw/fsi/fsi-master.c index d82df1c094..82991b1005 100644 --- a/hw/fsi/fsi-master.c +++ b/hw/fsi/fsi-master.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/log.h" +#include "qemu/units.h" #include "trace.h" =20 #include "hw/fsi/fsi-master.h" @@ -113,6 +114,7 @@ static void fsi_master_init(Object *o) FSIMasterState *s =3D FSI_MASTER(o); =20 object_initialize_child(o, "cfam", &s->cfam, TYPE_FSI_CFAM); + object_initialize_child(o, "cfam-s", &s->cfam_s, TYPE_FSI_CFAM_S); =20 qbus_init(&s->bus, sizeof(s->bus), TYPE_FSI_BUS, DEVICE(s), NULL); =20 @@ -131,6 +133,11 @@ static void fsi_master_realize(DeviceState *dev, Error= **errp) =20 /* address ? */ memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.parent.mr); + + if (!qdev_realize(DEVICE(&s->cfam_s), BUS(&s->bus), errp)) { + return; + } + memory_region_add_subregion(&s->opb2fsi, 2 * MiB, &s->cfam_s.window); } =20 static void fsi_master_reset(DeviceState *dev) diff --git a/hw/fsi/lbus.c b/hw/fsi/lbus.c index cae29e0658..902f8d8a5e 100644 --- a/hw/fsi/lbus.c +++ b/hw/fsi/lbus.c @@ -107,11 +107,80 @@ static const TypeInfo fsi_scratchpad_info =3D { .class_init =3D fsi_scratchpad_class_init, }; =20 +/* The mailbox exposes its scratch registers at this offset */ +#define FSI_MBOX_SCRATCH_OFF 0xe0 +#define FSI_MBOX_SCRATCH_END (FSI_MBOX_SCRATCH_OFF + FSI_MBOX_SCRATCH_NUM = * 4) + +static uint64_t fsi_mbox_read(void *opaque, hwaddr addr, unsigned size) +{ + FSIMbox *mbox =3D FSI_MBOX(opaque); + + trace_fsi_mbox_read(addr, size); + + if (addr < FSI_MBOX_SCRATCH_OFF || addr >=3D FSI_MBOX_SCRATCH_END) { + return 0; + } + + return mbox->scratch[TO_REG(addr - FSI_MBOX_SCRATCH_OFF)]; +} + +static void fsi_mbox_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) +{ + FSIMbox *mbox =3D FSI_MBOX(opaque); + + trace_fsi_mbox_write(addr, size, data); + + if (addr < FSI_MBOX_SCRATCH_OFF || addr >=3D FSI_MBOX_SCRATCH_END) { + return; + } + + mbox->scratch[TO_REG(addr - FSI_MBOX_SCRATCH_OFF)] =3D data; +} + +static const struct MemoryRegionOps fsi_mbox_ops =3D { + .read =3D fsi_mbox_read, + .write =3D fsi_mbox_write, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void fsi_mbox_realize(DeviceState *dev, Error **errp) +{ + FSILBusDevice *ldev =3D FSI_LBUS_DEVICE(dev); + + memory_region_init_io(&ldev->iomem, OBJECT(ldev), &fsi_mbox_ops, + ldev, TYPE_FSI_MBOX, 0x400); +} + +static void fsi_mbox_reset(DeviceState *dev) +{ + FSIMbox *mbox =3D FSI_MBOX(dev); + + memset(mbox->scratch, 0, sizeof(mbox->scratch)); +} + +static void fsi_mbox_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->bus_type =3D TYPE_FSI_LBUS; + dc->realize =3D fsi_mbox_realize; + device_class_set_legacy_reset(dc, fsi_mbox_reset); +} + +static const TypeInfo fsi_mbox_info =3D { + .name =3D TYPE_FSI_MBOX, + .parent =3D TYPE_FSI_LBUS_DEVICE, + .instance_size =3D sizeof(FSIMbox), + .class_init =3D fsi_mbox_class_init, +}; + static void fsi_lbus_register_types(void) { type_register_static(&fsi_lbus_info); type_register_static(&fsi_lbus_device_type_info); type_register_static(&fsi_scratchpad_info); + type_register_static(&fsi_mbox_info); } =20 type_init(fsi_lbus_register_types); diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build index a18a076552..585d549405 100644 --- a/hw/fsi/meson.build +++ b/hw/fsi/meson.build @@ -1,2 +1,2 @@ -system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c'= ,'fsi-master.c')) +system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c'= ,'cfam-s.c','fsi-master.c')) system_ss.add(when: 'CONFIG_FSI_APB2OPB_ASPEED', if_true: files('aspeed_ap= b2opb.c')) diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events index 9e286d08d3..42edce6437 100644 --- a/hw/fsi/trace-events +++ b/hw/fsi/trace-events @@ -1,5 +1,7 @@ fsi_scratchpad_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=3D%= d" fsi_scratchpad_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" P= RIx64 " size=3D%d value=3D0x%"PRIx64 +fsi_mbox_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=3D%d" +fsi_mbox_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 = " size=3D%d value=3D0x%"PRIx64 fsi_slave_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=3D%d" fsi_slave_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64= " size=3D%d value=3D0x%"PRIx64 fsi_cfam_config_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=3D= %d" --=20 2.53.0 From nobody Wed Aug 26 06:37:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1786388359; cv=none; d=zohomail.com; s=zohoarc; b=BYM1DFHXP96rA3Mh8pRUxuC847x4FuRd0GQ72rVexMZbqj9uRzn9Jr/kvlQzdFM2zcdlxJYh11v/26LkCtnxb9aNuvCiJFj+Ehj2s6tLM+ZgQSyFot+PW0jHmbaIOoUYJYhkY+4luu5NMx8r9D7TpbK2HTW+J+T+zgVm1yHfbU4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786388359; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TR/zMuZQNfrB4LNiZcJDwIVjsxAmSUCCo0C3kWPvJlw=; b=h5og/VhbSXfU69MR/HGd8qdV/feaMjNBW96gxqpmpO2+r4vMS+wlVV4gyoVDqglklTK7lq4Br9ogATzFAkNUB+++LUm1vm/zN8lbcVNYtEVPFN1J4hquy+5SfcR+/owL/1QLGSvlhW1KQeVPF6yO/9D8xw/UQCI2sorOjaNPaZk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17863883595201007.6692998702152; Mon, 10 Aug 2026 11:59:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wtVCf-0001XM-PI; Mon, 10 Aug 2026 14:58:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCd-0001WJ-P8; Mon, 10 Aug 2026 14:58:27 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCc-0003Sg-53; Mon, 10 Aug 2026 14:58:27 -0400 Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67AGVa292154199; Mon, 10 Aug 2026 18:57:57 GMT Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4fwvm9hngq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:56 +0000 (GMT) Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id 67AIujVN020349; Mon, 10 Aug 2026 18:57:55 GMT Received: from smtprelay05.wdc07v.mail.ibm.com ([172.16.1.72]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4fxf5vx5gr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:55 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay05.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67AIvrHn29557362 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Aug 2026 18:57:53 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8B57F5805E; Mon, 10 Aug 2026 18:57:53 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EA01E58062; Mon, 10 Aug 2026 18:57:52 +0000 (GMT) Received: from IBM-MFS.ibm.com (unknown [9.61.24.176]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 10 Aug 2026 18:57:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=TR/zMuZQNfrB4LNiZ cJDwIVjsxAmSUCCo0C3kWPvJlw=; b=c8FHS8M9NVLvGbwIGQKFRuaRQrNQGR2vk 7GIs30hgxRekn+HZ0IhYomt6rf5oJKMgNvq1bP7oNTNmOLxd5McsjSk1AsY6KgzO 9jtYeiB9sFvjTrlAV/NKKH+8cKH2aPIyslEM3LTf+kNgoI5seHNrDyABFhPB0ijd exraQTKz3XQRnCdFUSSX9LdpgukoS+utkNO6CNr/LBu0Gu8nLOYAlHu8BCeOaZKW EZFDJcKhiv9nrIZIT17rPpkN35EQVltPTocu09L/1xoOB/emnVqo9eQUFV0ItZOn vJ3ZvrQQbfl3L5ksN8tV9n7u1G+UT5ohTpRrlPSEW9hMMAd5slFHw== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 3/8] arm/aspeed: Wire AST2700 FSI controllers to APB-to-OPB bridges Date: Mon, 10 Aug 2026 13:57:41 -0500 Message-ID: <20260810185748.1253-4-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260810185748.1253-1-mikail.sadic@ibm.com> References: <20260810185748.1253-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfX0bBo8KwRv0Fu ygMS3flcMOqAH+/oGC5CK+sfdzHbi2QKE2YVLH/I6hzEJ5TztVrcj7jdVegG5RyvpH9QY+2TmKf W60OCsuZDotr/tGgvJt+smDlUxf3fnPI5QN6CDGT1GytHg3IdrTmpRcWVFHAu8IinqkjyZ3RxL1 rB4rcgBtdUXRmbtZOIicBTj3ngTSn96V8YXFrMQhqjTTYWR59ka4uGd8F6/qGpV25ez9JwvT9mh Fe8TmhL5KGyyO6L+1Fg3/3v0a/j97a8RCMCXuSe+mYgmekSbUrrQcF+TQmnMoNQpxCwSGyJ1pDh NWtXKXhvZcv0KFB667E62lPBuBGNxUr9ZLWpfqwt9HaSRwUQ1boOenFvrfGWp+AebI7By9y0nc0 beu9SAOyEbe8wkXdMRmr/a+gClL+KhvsP6I1ljAYhaTX1+2ZkBsKCWTN51NhklWXwuOdie2llTT GWYPQUXL0IjjkRMVfdg== X-Proofpoint-ORIG-GUID: -ZFAS8FulKbi5Zp4jxJIAgm9tqgQzbWr X-Proofpoint-Spam-Info: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfXxEVEy/zWB7hF HltKEqUiZWl4tCDvqc0shoad/ywTtgor4nCxNcWo/Oo7Q/9cQU6JGfTd2N/v+kvLjb+wFmZGARb 3T9Ay26Sws34q32VGFC7/S8ic3ZM8tk= X-Authority-Analysis: v=2.4 cv=IfK3n2qa c=1 sm=1 tr=0 ts=6a7a1f34 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=phIN1QjiwUTDb9KW1ZcA:9 X-Proofpoint-GUID: 37KPgVB5pCdp9Mywkn7VkZhW67Rl3px8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-10_04,2026-08-10_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608100158 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1786388361002158500 Content-Type: text/plain; charset="utf-8" The AST2700 SoC exposes two FSI controllers behind APB-to-OPB bridges. Add the ASPEED_DEV_FSI1/FSI2 memory-map entries, instantiate both fsi[] APB-to-OPB bridges and map them during SoC realize, so the CFAM/CFAM-S devices on the FSI local buses become reachable from the SoC. Signed-off-by: Mikail Sadic Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index dddd7d2106..b908d7d4ff 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -17,6 +17,7 @@ #include "qemu/module.h" #include "qemu/error-report.h" #include "hw/i2c/aspeed_i2c.h" +#include "hw/fsi/aspeed_apb2opb.h" #include "net/net.h" #include "system/qtest.h" #include "system/system.h" @@ -98,6 +99,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, [ASPEED_DEV_PCIE_MMIO2] =3D 0xA0000000, + [ASPEED_DEV_FSI1] =3D 0x21800000, + [ASPEED_DEV_FSI2] =3D 0x23800000, [ASPEED_DEV_SPI_BOOT] =3D 0x100000000, [ASPEED_DEV_SDRAM] =3D 0x400000000, }; @@ -559,6 +562,11 @@ static void aspeed_soc_ast2700_init(Object *obj) sc->silicon_rev); } =20 + for (i =3D 0; i < ARRAY_SIZE(s->fsi); i++) { + object_initialize_child(obj, "fsi[*]", &s->fsi[i], + TYPE_ASPEED_APB2OPB); + } + object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem", &s->iomem, @@ -1132,6 +1140,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) } } =20 + /* FSI / OPB */ + for (i =3D 0; i < ARRAY_SIZE(s->fsi); i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fsi[i]), 0, + sc->memmap[ASPEED_DEV_FSI1 + i]); + } + + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], --=20 2.53.0 From nobody Wed Aug 26 06:37:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1786388359; cv=none; d=zohomail.com; s=zohoarc; b=QlgxZsX7lBGSFS7WC94lUtlvTZGNlRSPhG82FgFttBjx9KCIXO6SC2gMJpjIkF26ifPcu3xJ3LyCt5jI0Mh6bFnEJ7vmrsBR2Lqa62ofBpQNp7uvI5Ejk7CCgLKoykERSvqdKqqoraYzQo8BhxHKYyzrGNZ5On0X6p0GGQ+Cszs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786388359; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Q7oIuPCYo4p+RjfJB3jCPNS97if4AWQut/dKB+3wAW8=; b=NDUSXGaYOYvxnJBv4IewhPWR/wFTFcd+uZHcRmgiGmbn49VzmlTzgPuBwD4l9Ik6X4ivIr4YK8dIzSFW+9J1XF2MiacDscjjVQXyqWc8TQCFIQa8oamCpjFQ4LL+pBS5mekLPbDlIrYWVQDK8vmdm4Binbjhwax0YXHwT9bSwIw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786388359542153.14771859636107; Mon, 10 Aug 2026 11:59:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wtVCc-0001Vu-BH; Mon, 10 Aug 2026 14:58:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCa-0001UR-GI; Mon, 10 Aug 2026 14:58:24 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCY-0003Rz-Um; Mon, 10 Aug 2026 14:58:24 -0400 Received: from pps.filterd (m0360072.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67AGVbnO2191597; Mon, 10 Aug 2026 18:57:57 GMT Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4fwvnw15js-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:57 +0000 (GMT) Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id 67AIuMkv016188; Mon, 10 Aug 2026 18:57:56 GMT Received: from smtprelay06.wdc07v.mail.ibm.com ([172.16.1.73]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 4fxhfxwu01-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:56 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay06.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67AIvs1021627534 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Aug 2026 18:57:54 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 309E758065; Mon, 10 Aug 2026 18:57:54 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 983305805C; Mon, 10 Aug 2026 18:57:53 +0000 (GMT) Received: from IBM-MFS.ibm.com (unknown [9.61.24.176]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 10 Aug 2026 18:57:53 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=Q7oIuPCYo4p+RjfJB 3jCPNS97if4AWQut/dKB+3wAW8=; b=qyJNvX7InRqp+3cVn5VERfzBHdmG+UBEu dEXSqidTKspXndP8CAqAeI/r5hi9nKob9oper0K63iUcc8fu/RGPRgh9zluPrOFW jaga77fzRPs24ah0typNbL2h6vTF96wHN6CmcJm4UEFL2Z9EozPqCz65BzwCV6+C BWtLpq83neuhsAqiPlsUl4tVfN2rtImhBiHH1dYl+JQs+KImGf9EHvfIrn2qaRyq QJAE7H4fNQJjdv7/hjVCEbyPpp8HQ03K5eLD6TACAyiMKYZCfp9i55kbyT40/8W7 cbFaQCNZsSpvIUGPRs4h+cvz66DXvJjvc3fiObmC+5siAjVzZX3cQ== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 4/8] i2c/aspeed: Fix DMA receive first-byte handling for block reads Date: Mon, 10 Aug 2026 13:57:42 -0500 Message-ID: <20260810185748.1253-5-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260810185748.1253-1-mikail.sadic@ibm.com> References: <20260810185748.1253-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=RsP16imK c=1 sm=1 tr=0 ts=6a7a1f35 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=82TwdL3_f4vI9uiogJoA:9 X-Proofpoint-GUID: sNgpppKu-6A8fJVbs6ez-kFmg5jMzS0Y X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfX1rAhdP1/G+tB Tlo7NyQpoTbpf67k/hvRwYo1TPPYziYcrdoj/8gS9LBO07xS8+0B4Euufo5fdtviX1ehJEE1KpQ wEMJXCLoaKAPJIt75M20Mhcjub4iO2QFT3AdF6ntfwKG0zWnrULUexYqoVep2E+cqXoBVK8z1qX HOdHpVYIJDeAdhQMO3S7vkln2xy8uugGyt/RAqMeZfM7SS5kwCu2ZPKV+nKk9NiQ+mAqtlNmLb+ 1vFvXxaucxdiKCYyYX7jCYeVVRm2JQSuOFvM7I+CicJTSzO9h23Iwi/FSjmB3TAZOWKUnaR/tv4 ibgPepuaaiZnEhNUynUrsBvkrQPDGk6t0FvWnj3cvSEugml6aRybTStH5Bhw+wz/4Esam6vRt2p UnwtPPRCDPWGUL5AKU59sgqXUJfIWqK8kqixEFpTWCXxfasA6zCKWNIqgRwKNo2XvMAN5J8OlTb zUTt8jUf5JmIYWMkL+A== X-Proofpoint-ORIG-GUID: F_99vDrTzkMQVPIu1BP6UJWqfFJfnlHZ X-Proofpoint-Spam-Info: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfXzdo9o+3tiR9e HUostSzMFyxMl9xRoNWpheoMGwXRjlXiquHu4Y1RgWQ9AAxXIoYnBnW+Dn/PnXAwXXh3AZnmruQ ar5+z8WZR86xxnxTTJWCvNCGzdlg9xM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-10_04,2026-08-10_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 suspectscore=0 clxscore=1015 malwarescore=0 phishscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608100158 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=mikail.sadic@ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1786388361002158501 Content-Type: text/plain; charset="utf-8" An SMBus block read (I2C_M_RECV_LEN) reads the block length from the first received byte. The Linux/U-Boot aspeed I2C driver obtains that first byte from the I2CC_STS_AND_BUFF register (modelled here as reg_byte_buf), even when the transfer uses DMA. The DMA receive path, however, only wrote received data to DRAM and never updated reg_byte_buf, so block reads read a stale/zero length. Mirror the first DMA-received byte into reg_byte_buf so that I2C_M_RECV_LEN transfers using DMA report the correct block length. This is required for the ucd9000 driver, which uses i2c_smbus_read_block_data(). Signed-off-by: Mikail Sadic --- hw/i2c/aspeed_i2c.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 27afcaecee..facb54d27e 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -365,6 +365,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) uint32_t reg_pool_ctrl =3D aspeed_i2c_bus_pool_ctrl_offset(bus); uint32_t reg_byte_buf =3D aspeed_i2c_bus_byte_buf_offset(bus); uint32_t reg_dma_len =3D aspeed_i2c_bus_dma_len_offset(bus); + bool first_dma_byte; int pool_rx_count =3D SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, RX_SIZE) + 1; =20 @@ -391,6 +392,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) } =20 aspeed_i2c_set_rx_dma_dram_offset(bus); + first_dma_byte =3D true; while (bus->regs[reg_dma_len]) { MemTxResult result; =20 @@ -407,6 +409,11 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) return; } =20 + /* Mirror first byte to reg_byte_buf for I2C_M_RECV_LEN. */ + if (first_dma_byte) { + SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, d= ata); + first_dma_byte =3D false; + } bus->dma_dram_offset++; bus->regs[reg_dma_len]--; /* In new mode, keep track of how many bytes we RXed */ --=20 2.53.0 From nobody Wed Aug 26 06:37:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1786388429; cv=none; d=zohomail.com; s=zohoarc; b=kB6hbgIRXhceeOB1qOVHJcG+FvYxdcEdAidq5mgfsIFWt5Qza7ElJbph3HC1tfzLy8Eh1/YQm3wkC39cUQ56YW5WzTnYA1byLpdwmmD7rhVZorVbMsvFo/80fn+6aXRiH7HoDgQH/ogIwp8qlQlCeTDSNFVUWlW1T8vVQ+sb2Zg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786388429; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8Aux4Nt9AqJZJwSbt1118cnbfcrSHGWwBveD1cl72L4=; b=jpju9v6+Aihkf4cSw89WYmLeosNOPb7YUjNOnbGzXH2hxlOfzHSIPh8WIADKYMjUQfaZ34SUSnFF57M0fdoKihaHr7EkmhBAohotSK1o6qVJoqIvGG3WlMKO4CTHmSxq4RmorCyyDfLe5a72XCcBBWMDlJSHRUOBHGeYYZEfViw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786388429103995.4927081326897; Mon, 10 Aug 2026 12:00:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wtVCZ-0001UH-Nt; Mon, 10 Aug 2026 14:58:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCY-0001Tf-4A; Mon, 10 Aug 2026 14:58:22 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCV-0003Qj-VJ; Mon, 10 Aug 2026 14:58:21 -0400 Received: from pps.filterd (m0360072.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67AGW6WL2192690; Mon, 10 Aug 2026 18:57:58 GMT Received: from ppma12.dal12v.mail.ibm.com (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4fwvnw15jt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:57 +0000 (GMT) Received: from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1]) by ppma12.dal12v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id 67AIQHG9026180; Mon, 10 Aug 2026 18:57:56 GMT Received: from smtprelay06.wdc07v.mail.ibm.com ([172.16.1.73]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 4fxespx752-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:56 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay06.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67AIvtQ062980358 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Aug 2026 18:57:55 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D867C5805E; Mon, 10 Aug 2026 18:57:54 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3ED805805C; Mon, 10 Aug 2026 18:57:54 +0000 (GMT) Received: from IBM-MFS.ibm.com (unknown [9.61.24.176]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 10 Aug 2026 18:57:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=8Aux4Nt9AqJZJwSbt 1118cnbfcrSHGWwBveD1cl72L4=; b=awwU7fIwy1OVQvXz67bOBBtgMoE5v5DGA NN2Kdx4fIsLZV3M5+/ZveGPUVdkQXff3g4xecj6QwTR2hs9PAX1ePpO22AKGK2JO QWEgxE/rdioREsDfPPavXmglNf9y2tjhfq/5YOgPvOviXv5sCFbp6+SoGR125D1w bWULwBJ68Rgg+8T17Ujtkp2gWbsP8eH7o56WxNAtNj5GOFZ7gcNNsjaCzIYJSvBb 0RzxDO5ZxN48G672X9bQSN5bUhUJIlUXz1UDjSXaFVQS0Xo6iGgW2SqW43nIWFui 8DCHJXkEYomShE540doWWoY2KRB745sd3OcsCzN9FJRax4WBwcTiQ== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 5/8] hw/sensor: Add UCD90320 model Date: Mon, 10 Aug 2026 13:57:43 -0500 Message-ID: <20260810185748.1253-6-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260810185748.1253-1-mikail.sadic@ibm.com> References: <20260810185748.1253-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=RsP16imK c=1 sm=1 tr=0 ts=6a7a1f36 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=YwPlQgHYUhtu6dumBzMA:9 X-Proofpoint-GUID: T9LReHCHUiwlAihAjN5wwiCjx_iRjM6Z X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfXxCZGFH4GF5r/ L5+Tge5KQFeyKrN73uCCek/kivQG91ePbLPeoFokIsxHBACMJEkRdE2U6VYh3OjGr4kk/Pxq+sG 0KMhkUaV4CGFrmYTOQcs3zzHmteMjqadgU/Q6jINkukLnxEs9cRNw26MNk3ZQLNMQeI8X9LkLpP DXH4/ErqgGX/gpBDFHBBhxrNrsjWexKW9X8GpHeVPQofB3IIJfXEKI08scUOzW/7eX9uGujMF0r Eu/3Hmgvoef23MEx7MMc6PdUhMo3Rl2WjtxiPLTxKP93z9y/mYxeOmEN0SW8PpL8MRpCFOKZ3MM 51alEO8IBHzgrCI6nxLlkcL2BYmG6CqqVEtVIm4w4LbC1GVX04YVlGX6WoIUoF9wen9p4wmK4L5 gOg/vbQKi4TB0AhsBpQcKaWcSUkidKZAoDMXHWzFweB9GPYrbTniEURrttvcPRrdju8HQVRIPDF nClOGTNkGVUwSVxqOzw== X-Proofpoint-ORIG-GUID: CzwbI_GKIspHmWRyQBxa2DC92CaoWqpU X-Proofpoint-Spam-Info: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfX4l9alsNNbun7 221ihhFrGhJBNnSz1cKko/nx8hfjAZ8TEytiEEqn5cjn2p4p6qbcyuYJwUQqb0+CUNm3oUIxu+W duEWcZhFjyAH1hh7YRLelke8Awqiqh0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-10_04,2026-08-10_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 suspectscore=0 clxscore=1015 malwarescore=0 phishscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608100158 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=mikail.sadic@ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1786388431289158501 Content-Type: text/plain; charset="utf-8" Add a PMBus device model for the TI-UCD90320 24-rail power sequencer. Configures 24 pages with linear vout mode and responds to the vendor-specific UCD9000_DEVICE_ID, NUM_PAGES, MONITOR_CONFIG, and MFR_STATUS commands, allowing the Linux ucd9000 driver to bind and create hwmon sysfs entries. Signed-off-by: Mikail Sadic --- MAINTAINERS | 1 + docs/specs/index.rst | 1 + docs/specs/ucd90320.rst | 36 +++++++++ hw/sensor/ucd90320.c | 169 ++++++++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/sensor/Kconfig | 4 + hw/sensor/meson.build | 1 + 7 files changed, 213 insertions(+) create mode 100644 docs/specs/ucd90320.rst create mode 100644 hw/sensor/ucd90320.c diff --git a/MAINTAINERS b/MAINTAINERS index 902db77218..ec415cb8e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4063,6 +4063,7 @@ F: hw/i2c/pmbus_device.c F: hw/sensor/adm1272.c F: hw/sensor/isl_pmbus_vr.c F: hw/sensor/max34451.c +F: hw/sensor/ucd90320.c F: include/hw/i2c/pmbus_device.h F: include/hw/sensor/isl_pmbus_vr.h F: tests/qtest/adm1272-test.c diff --git a/docs/specs/index.rst b/docs/specs/index.rst index b7909a108a..4de65e2fdf 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -39,4 +39,5 @@ guest hardware that is specific to QEMU. riscv-iommu riscv-aia aspeed-intc + ucd90320 iommu-testdev diff --git a/docs/specs/ucd90320.rst b/docs/specs/ucd90320.rst new file mode 100644 index 0000000000..fdc0878c75 --- /dev/null +++ b/docs/specs/ucd90320.rst @@ -0,0 +1,36 @@ +Texas Instruments UCD90320 Power Sequencer +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The UCD90320 is a 24-rail PMBus power sequencer. QEMU models it as a PMBus +device (``"ucd90320"``) so the Linux ``ucd9000`` driver can bind and create +``hwmon`` sysfs entries. + +The model configures 24 PMBus pages (one per rail) with ``VOUT_MODE =3D 0x= 00`` +(linear, exponent 0). ``READ_VOUT`` and ``MFR_STATUS`` return zero on all +pages. + +Vendor-specific commands handled: + ++------+---------------------------+--------------------------------------= ------+ +| Code | Name | Response = | ++=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D+ +| 0xD5 | ``UCD9000_MONITOR_CONFIG``| Block: one byte ``0x00`` = | ++------+---------------------------+--------------------------------------= ------+ +| 0xD6 | ``UCD9000_NUM_PAGES`` | Byte: ``24`` = | ++------+---------------------------+--------------------------------------= ------+ +| 0xF3 | ``UCD9000_MFR_STATUS`` | Block: four bytes ``0x00 0x00 0x00 0x= 00`` | ++------+---------------------------+--------------------------------------= ------+ +| 0xFD | ``UCD9000_DEVICE_ID`` | Block: ASCII string ``"UCD90320"`` = | ++------+---------------------------+--------------------------------------= ------+ + +``DEVICE_ID`` uses the vendor-specific code ``0xFD`` rather than the stand= ard +``PMBUS_IC_DEVICE_ID`` (``0xAD``), matching the Linux ``ucd9000`` probe +sequence. + +The UCD90320 is instantiated automatically in the ``huygens-bmc`` machine = on +I2C bus 5 at address ``0x11``. To instantiate on a different Aspeed machin= e: + +.. code-block:: c + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), + "ucd90320", 0x11); diff --git a/hw/sensor/ucd90320.c b/hw/sensor/ucd90320.c new file mode 100644 index 0000000000..6d4f828448 --- /dev/null +++ b/hw/sensor/ucd90320.c @@ -0,0 +1,169 @@ +/* + * Texas Instruments UCD90320 24-Rail PMBus Power Sequencer + * + * Copyright 2026 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/i2c/pmbus_device.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" + +#define TYPE_UCD90320 "ucd90320" + +/* UCD90320 has 24 sequenced power-rail pages */ +#define UCD90320_NUM_PAGES 24 + +/* Vendor-specific command codes (not in the standard PMBus register table= ) */ +#define UCD9000_MONITOR_CONFIG 0xd5 +#define UCD9000_NUM_PAGES 0xd6 +#define UCD9000_MFR_STATUS 0xf3 +#define UCD9000_DEVICE_ID 0xfd + +#define UCD90320_DEVICE_ID_LEN 8 +#define UCD90320_MFR_STATUS_LEN 4 + +typedef struct UCD90320State { + PMBusDevice parent; + + /* Reset values for the vendor-specific block-read commands. */ + uint8_t device_id[UCD90320_DEVICE_ID_LEN]; + uint8_t monitor_config; + uint8_t mfr_status[UCD90320_MFR_STATUS_LEN]; +} UCD90320State; + +#define UCD90320(obj) OBJECT_CHECK(UCD90320State, (obj), TYPE_UCD90320) + +static void ucd90320_send_block(PMBusDevice *pmdev, + const uint8_t *data, uint8_t len) +{ + int i; + + pmdev->out_buf[len + pmdev->out_buf_len] =3D len; + for (i =3D len - 1; i >=3D 0; i--) { + pmdev->out_buf[i + pmdev->out_buf_len] =3D data[len - 1 - i]; + } + pmdev->out_buf_len +=3D len + 1; +} + +static uint8_t ucd90320_read_byte(PMBusDevice *pmdev) +{ + UCD90320State *s =3D UCD90320(pmdev); + + switch (pmdev->code) { + case UCD9000_DEVICE_ID: + ucd90320_send_block(pmdev, s->device_id, sizeof(s->device_id)); + pmbus_idle(pmdev); + return 0; + case UCD9000_NUM_PAGES: + pmbus_send8(pmdev, UCD90320_NUM_PAGES); + pmbus_idle(pmdev); + return 0; + + case UCD9000_MONITOR_CONFIG: + ucd90320_send_block(pmdev, &s->monitor_config, + sizeof(s->monitor_config)); + pmbus_idle(pmdev); + return 0; + case UCD9000_MFR_STATUS: + ucd90320_send_block(pmdev, s->mfr_status, sizeof(s->mfr_status)); + pmbus_idle(pmdev); + return 0; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: reading from unsupported register: 0x%02x\n", + __func__, pmdev->code); + break; + } + return 0xFF; +} + +static int ucd90320_write_data(PMBusDevice *pmdev, const uint8_t *buf, + uint8_t len) +{ + if (len =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: writing empty data\n", __func_= _); + return -1; + } + + pmdev->code =3D buf[0]; + + if (len =3D=3D 1) { + return 0; + } + + return 0; +} + +static void ucd90320_exit_reset(Object *obj, ResetType type) +{ + PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); + UCD90320State *s =3D UCD90320(obj); + + pmdev->capability =3D 0x20; /* PEC supported */ + + for (int i =3D 0; i < UCD90320_NUM_PAGES; i++) { + pmdev->pages[i].operation =3D 0x80; /* on */ + pmdev->pages[i].on_off_config =3D 0x1a; + pmdev->pages[i].vout_mode =3D 0x00; /* linear mode, exponent= =3D0 */ + pmdev->pages[i].read_vout =3D 0; /* rails off, pgood=3D0 */ + } + + memcpy(s->device_id, "UCD90320", sizeof(s->device_id)); + s->monitor_config =3D 0x00; + memset(s->mfr_status, 0x00, sizeof(s->mfr_status)); +} + +static void ucd90320_init(Object *obj) +{ + PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); + uint64_t flags =3D PB_HAS_VOUT | PB_HAS_VOUT_MODE | + PB_HAS_STATUS_MFR_SPECIFIC; + + for (int i =3D 0; i < UCD90320_NUM_PAGES; i++) { + pmbus_page_config(pmdev, i, flags); + } +} + +static const VMStateDescription vmstate_ucd90320 =3D { + .name =3D TYPE_UCD90320, + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (const VMStateField[]) { + VMSTATE_PMBUS_DEVICE(parent, UCD90320State), + VMSTATE_UINT8_ARRAY(device_id, UCD90320State, UCD90320_DEVICE_ID_L= EN), + VMSTATE_UINT8(monitor_config, UCD90320State), + VMSTATE_UINT8_ARRAY(mfr_status, UCD90320State, + UCD90320_MFR_STATUS_LEN), + VMSTATE_END_OF_LIST() + } +}; + +static void ucd90320_class_init(ObjectClass *klass, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + PMBusDeviceClass *k =3D PMBUS_DEVICE_CLASS(klass); + + dc->desc =3D "Texas Instruments UCD90320 24-Rail Power Sequencer"; + dc->vmsd =3D &vmstate_ucd90320; + k->write_data =3D ucd90320_write_data; + k->receive_byte =3D ucd90320_read_byte; + k->device_num_pages =3D UCD90320_NUM_PAGES; + rc->phases.exit =3D ucd90320_exit_reset; +} + +static const TypeInfo ucd90320_types[] =3D { + { + .name =3D TYPE_UCD90320, + .parent =3D TYPE_PMBUS_DEVICE, + .instance_size =3D sizeof(UCD90320State), + .instance_init =3D ucd90320_init, + .class_init =3D ucd90320_class_init, + }, +}; + +DEFINE_TYPES(ucd90320_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 82e0bc2e70..ac44740547 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -555,6 +555,7 @@ config ASPEED_SOC select LED select PMBUS select MAX31785 + select UCD90320 select FSI_APB2OPB_ASPEED select AT24C select PCI_EXPRESS diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig index bc6331b4ab..135ffa7d5d 100644 --- a/hw/sensor/Kconfig +++ b/hw/sensor/Kconfig @@ -43,3 +43,7 @@ config ISL_PMBUS_VR config MAX31785 bool depends on PMBUS + +config UCD90320 + bool + depends on PMBUS diff --git a/hw/sensor/meson.build b/hw/sensor/meson.build index 420fdc3359..c0583161d3 100644 --- a/hw/sensor/meson.build +++ b/hw/sensor/meson.build @@ -8,3 +8,4 @@ system_ss.add(when: 'CONFIG_MAX34451', if_true: files('max3= 4451.c')) system_ss.add(when: 'CONFIG_LSM303DLHC_MAG', if_true: files('lsm303dlhc_ma= g.c')) system_ss.add(when: 'CONFIG_ISL_PMBUS_VR', if_true: files('isl_pmbus_vr.c'= )) system_ss.add(when: 'CONFIG_MAX31785', if_true: files('max31785.c')) +system_ss.add(when: 'CONFIG_UCD90320', if_true: files('ucd90320.c')) --=20 2.53.0 From nobody Wed Aug 26 06:37:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1786388433; cv=none; d=zohomail.com; s=zohoarc; b=PKrQ2JxMVVqrrQkDuL9EvO0hSJyYA4DYWpMcNOSclZX9rMYJIe2GZrs7qustUj6J1A70LcNR0QCaHy8ToTZPWZDN2u2PquFMvGANPjFuhLdna6TPxc0Ggaj0DvCuZiUhKZL0K+Jc8XWqQfVsHJZZdYwG/xbtBiRlVGXorPJivsU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786388433; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=A/pSzArHwzYAVbVTsZslFykHVroRDdEe/J5hEkPi4u4=; b=JXyQdK3GoPd1t2eIalZmV+hJV7ltlqUHjMOCvuHZTx2jJO4GlbDg0Q78IekXO3rqoBM8JGiNpvrVY4dekncyZpL709n/gNMpYtBfBi8UTl0zA86XiFxPTT6v+pA8KVzPPhC3mAuE+BWsiIR1EtqrZXgBcfu7KyWzRptXj29xx1g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786388433527867.7847385397089; Mon, 10 Aug 2026 12:00:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wtVDK-0001hV-D3; Mon, 10 Aug 2026 14:59:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCx-0001Zk-LF; Mon, 10 Aug 2026 14:58:48 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCv-0003Ux-N5; Mon, 10 Aug 2026 14:58:47 -0400 Received: from pps.filterd (m0353729.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67AGVivr292592; Mon, 10 Aug 2026 18:57:59 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4fwvjysmkf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:58 +0000 (GMT) Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id 67AIuLHR019209; Mon, 10 Aug 2026 18:57:57 GMT Received: from smtprelay07.wdc07v.mail.ibm.com ([172.16.1.74]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4fxg9gx00r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:57 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay07.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67AIvtsb27329136 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Aug 2026 18:57:55 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8584D58051; Mon, 10 Aug 2026 18:57:55 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E49FC5805F; Mon, 10 Aug 2026 18:57:54 +0000 (GMT) Received: from IBM-MFS.ibm.com (unknown [9.61.24.176]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 10 Aug 2026 18:57:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=A/pSzArHwzYAVbVTs ZslFykHVroRDdEe/J5hEkPi4u4=; b=Yh5ovoPwLvlGGsfgmhE1TH6DfFTNGRiYH HwJea3zvEL0zvi8wydJ1uQqqvqPqR/VPjETxxTQ71+6RmhsHuPEoOIIuOORP/toH tMwRBxQv1r0bkUPcQl5EFlojq9ngY4LK7lM8qG2nCJ7M5XW8BX84caVJ2osrGYGl IRIsdTq0CfZL4MudanXrvsId20Oj5BXbdIz9y2Ji91KFMPD29+kl8kpfLK6lL1zC Ah75nBlNPs/UgyYxoV/Bab43JRkSnnsZ75RejymXL/pFF+P63CeykevqaNXxz32L KYdNKTbY9kzYp32u3wcgK6FIeJTkzL4RMZ2iZEVKFwcTL9F2p9pRw== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 6/8] ufs: Make the logical block size configurable and answer absent LUNs Date: Mon, 10 Aug 2026 13:57:44 -0500 Message-ID: <20260810185748.1253-7-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260810185748.1253-1-mikail.sadic@ibm.com> References: <20260810185748.1253-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfX0jjF3VWhqurd 5qVO8EZmcHO0NebAe01q/R2LSYZGl79A1hnO++LvCQHW4mMUel80q2zYyWGirYMeAcGCwlg+p8D ZdtrlXpwfxklXNjdDV7S77tUpD3xk2rbWbr3h4My7LlKQHLFP1KoR1lLrLykPrzmJ4qxQlo3fx/ 8Zjo6i/G6m6bveu4KwbSz5NDWQ4SdnxJwCMs7DzWbaVizDSNhGhryM/J9wjFCgp9EJZymyTO7Lj KZjki5uFXm0RnWIDncK/8ffmCwiQPAL7hV84tJeF1lOzhYcAD3LYnSgdVyI8/f9Ztb4DgaXgMPs JeoWzFvL2i6tfFSrWKS1338PUv3C6QINzs9gWpz+us5io/BIlPAk45KPzR1DVGaurs/VQnYMzsa Qg2cnlibFXLW3WATissffmYd+dCkDYKRyQdnA3X4b5CR9fekpELosf6BqxGEnnzqOjAscxIChlu tiwzOqH1lQod5IR+Vhw== X-Proofpoint-Spam-Info: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfX4fKgumst5EvU 5fJ3LcMaJjJDroFYvJ/mmfeGxv5g95nM6tKUkoWNKV/6wPUrx8CfhTM+rFRflqWf/uNY2iZknON ibRKVofiODrtWsamhWUW8Kznkezuca4= X-Authority-Analysis: v=2.4 cv=RqD16imK c=1 sm=1 tr=0 ts=6a7a1f36 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=H40MSsQeoNOp76yvAOYA:9 X-Proofpoint-GUID: S6HDOnoAnohTrwBFgTAwDEtVo-dVFaw7 X-Proofpoint-ORIG-GUID: ejWYIxqZuGDw52ZN7CghYzwaf09sKKrJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-10_04,2026-08-10_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608100158 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1786388435357158500 Content-Type: text/plain; charset="utf-8" Two things the ufs-lu model hardcodes that hardware does not. The logical block size is fixed at UFS_BLOCK_SIZE (4096), both in the unit descriptor the logical unit reports and in the block size of the scsi-hd backing it. UFS does not require that: the unit descriptor carries a base-2 exponent, and 512-byte blocks are common on real hardware and in images built for it. Add a 'logical-block-size' property that sets both, defaulting to UFS_BLOCK_SIZE so the ufs PCI device keeps the geometry and the property set it has today. Restrict it to powers of two from 512 bytes to UFS_BLOCK_SIZE, and reject a drive shorter than one block, which would otherwise realize a unit reporting zero blocks. An INQUIRY addressed to a logical unit that is not mapped fails the request outright. SPC has a specific answer for this case: return the standard INQUIRY data with the peripheral qualifier and device type saying that no device is present on that logical unit, with GOOD status, so that a host enumerating logical units can tell an absent unit from a transport error. hw/scsi/scsi-bus.c already answers this way for a target's unsupported logical units. Do the same for an unmapped ufs-lu, using TYPE_NO_LUN. Commands other than a standard INQUIRY still fail, now with LOGICAL UNIT NOT SUPPORTED sense data rather than an unadorned request failure. The invalid-LUN trace point is unchanged. Both are needed by the AST2700 UFS controller added later in this series: the OpenBMC images it boots are laid out for 512-byte sectors, and U-Boot logs an OCS failure for every unpopulated logical unit while probing it. Signed-off-by: Mikail Sadic --- hw/ufs/ufs.h | 3 +++ hw/ufs/lu.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++--- hw/ufs/ufs.c | 2 +- 3 files changed, 68 insertions(+), 4 deletions(-) diff --git a/hw/ufs/ufs.h b/hw/ufs/ufs.h index aa8361d93d..47d1c72ef3 100644 --- a/hw/ufs/ufs.h +++ b/hw/ufs/ufs.h @@ -21,6 +21,7 @@ #define UFS_MAX_MCQ_QNUM 32 #define UFS_BLOCK_SIZE_SHIFT 12 #define UFS_BLOCK_SIZE (1 << UFS_BLOCK_SIZE_SHIFT) +#define UFS_MIN_BLOCK_SIZE 512 =20 typedef struct UfsBusClass { BusClass parent_class; @@ -80,6 +81,7 @@ typedef UfsReqResult (*UfsScsiOp)(struct UfsLu *, UfsRequ= est *); typedef struct UfsLu { DeviceState qdev; uint8_t lun; + uint32_t logical_block_size; UnitDescriptor unit_desc; SCSIBus bus; SCSIDevice *scsi_dev; @@ -303,6 +305,7 @@ void ufs_build_query_response(UfsRequest *req); void ufs_complete_req(UfsRequest *req, UfsReqResult req_result); void ufs_wb_update_avail_buffer(UfsHc *u); void ufs_init_wlu(UfsLu *wlu, uint8_t wlun); +UfsReqResult ufs_emulate_absent_lun(UfsRequest *req); bool ufs_realize(UfsHc *u, DeviceState *dev, AddressSpace *dma_as, Error **errp); void ufs_unrealize(UfsHc *u); diff --git a/hw/ufs/lu.c b/hw/ufs/lu.c index eeca865eb5..b1aba79a53 100644 --- a/hw/ufs/lu.c +++ b/hw/ufs/lu.c @@ -308,6 +308,44 @@ static int ufs_emulate_wlun_inquiry(UfsRequest *req, u= int8_t *outbuf, return SCSI_INQUIRY_LEN; } =20 +/* + * A logical unit that is not mapped answers a standard INQUIRY as "not + * connected" with GOOD status, as hardware does, so that a host bus scan + * skips it instead of reporting a controller error. Any other command is + * rejected. + */ +UfsReqResult ufs_emulate_absent_lun(UfsRequest *req) +{ + QEMU_UNINITIALIZED uint8_t outbuf[SCSI_INQUIRY_LEN]; + uint8_t sense_buf[UFS_SENSE_SIZE]; + uint8_t scsi_status; + int len =3D 0; + + if (req->req_upiu.sc.cdb[0] =3D=3D INQUIRY && + !(req->req_upiu.sc.cdb[1] & 0x1)) { + memset(outbuf, 0, sizeof(outbuf)); + outbuf[0] =3D TYPE_NO_LUN; + outbuf[3] =3D 0x2; + outbuf[4] =3D SCSI_INQUIRY_LEN - 5; + len =3D SCSI_INQUIRY_LEN; + scsi_status =3D GOOD; + } else { + scsi_build_sense(sense_buf, SENSE_CODE(LUN_NOT_SUPPORTED)); + scsi_status =3D CHECK_CONDITION; + } + + len =3D MIN(len, (int)req->data_len); + if (scsi_status =3D=3D GOOD && len > 0 && + dma_buf_read(outbuf, len, NULL, req->sg, MEMTXATTRS_UNSPECIFIED) != =3D + MEMTX_OK) { + return UFS_REQUEST_FAIL; + } + + ufs_build_scsi_response_upiu(req, sense_buf, sizeof(sense_buf), len, + scsi_status); + return UFS_REQUEST_SUCCESS; +} + static UfsReqResult ufs_emulate_scsi_cmd(UfsLu *lu, UfsRequest *req) { uint8_t lun =3D lu->lun; @@ -394,6 +432,8 @@ static UfsReqResult ufs_process_scsi_cmd(UfsLu *lu, Ufs= Request *req) static const Property ufs_lu_props[] =3D { DEFINE_PROP_DRIVE("drive", UfsLu, conf.blk), DEFINE_PROP_UINT8("lun", UfsLu, lun, 0), + DEFINE_PROP_UINT32("logical-block-size", UfsLu, logical_block_size, + UFS_BLOCK_SIZE), }; =20 static bool ufs_add_lu(UfsHc *u, UfsLu *lu, Error **errp) @@ -435,7 +475,7 @@ static void ufs_init_lu(UfsLu *lu) lu->unit_desc.length =3D sizeof(UnitDescriptor); lu->unit_desc.descriptor_idn =3D UFS_QUERY_DESC_IDN_UNIT; lu->unit_desc.lu_enable =3D 0x01; - lu->unit_desc.logical_block_size =3D UFS_BLOCK_SIZE_SHIFT; + lu->unit_desc.logical_block_size =3D ctz32(lu->logical_block_size); lu->unit_desc.unit_index =3D lu->lun; lu->unit_desc.logical_block_count =3D cpu_to_be64(brdv_len / (1 << lu->unit_desc.logical_block_size)); @@ -455,6 +495,25 @@ static bool ufs_lu_check_constraints(UfsLu *lu, Error = **errp) return false; } =20 + if (!is_power_of_2(lu->logical_block_size)) { + error_setg(errp, "logical-block-size must be a power of 2, not %" + PRIu32, lu->logical_block_size); + return false; + } + + if (lu->logical_block_size < UFS_MIN_BLOCK_SIZE || + lu->logical_block_size > UFS_BLOCK_SIZE) { + error_setg(errp, "logical-block-size must be between %d and %d byt= es", + UFS_MIN_BLOCK_SIZE, UFS_BLOCK_SIZE); + return false; + } + + if (blk_getlength(lu->conf.blk) < lu->logical_block_size) { + error_setg(errp, "drive is smaller than one %" PRIu32 "-byte block= ", + lu->logical_block_size); + return false; + } + return true; } =20 @@ -475,8 +534,10 @@ static void ufs_init_scsi_device(UfsLu *lu, BlockBacke= nd *blk, Error **errp) scsi_dev =3D qdev_new("scsi-hd"); object_property_add_child(OBJECT(&lu->bus), "ufs-scsi", OBJECT(scsi_de= v)); =20 - qdev_prop_set_uint32(scsi_dev, "physical_block_size", UFS_BLOCK_SIZE); - qdev_prop_set_uint32(scsi_dev, "logical_block_size", UFS_BLOCK_SIZE); + qdev_prop_set_uint32(scsi_dev, "physical_block_size", + lu->logical_block_size); + qdev_prop_set_uint32(scsi_dev, "logical_block_size", + lu->logical_block_size); qdev_prop_set_uint32(scsi_dev, "scsi-id", 0); qdev_prop_set_uint32(scsi_dev, "lun", lu->lun); if (!qdev_prop_set_drive_err(scsi_dev, "drive", blk, errp)) { diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index 36c674af32..016876eb63 100644 --- a/hw/ufs/ufs.c +++ b/hw/ufs/ufs.c @@ -1083,7 +1083,7 @@ static UfsReqResult ufs_exec_scsi_cmd(UfsRequest *req) =20 if (!is_wlun(lun) && (lun >=3D UFS_MAX_LUS || u->lus[lun] =3D=3D NULL)= ) { trace_ufs_err_scsi_cmd_invalid_lun(lun); - return UFS_REQUEST_FAIL; + return ufs_emulate_absent_lun(req); } =20 switch (lun) { --=20 2.53.0 From nobody Wed Aug 26 06:37:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1786388367; cv=none; d=zohomail.com; s=zohoarc; b=JtFW2uEc04YfyE7XOhIm9jV1T93tqTlu+fKWHM9yvXl+UeKDd9xPR0h3jEg6gJVwoUte7Lm+ywsHUiTRvDAdddvcY5gDA7frK/sn1g4itkStW/ayu+9Dby4VorEI/OhxbBajp21CvuK213TjGT8nSmBfKnuEXhgfbdX+jJNN8/4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786388367; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AqhPQ1Q9hfplNQ2nSzeEDUlFwpKQrrNt7URNcAzMZlI=; b=IVuCIX5Wsjai5O94qXNw3Ki/SLWOG3ZLJB3XrZBL5vqRM16JUbqXbhndiaCEoIESB3bd+Oec3aecL59XhtJX7zWv2ElON692VFp+yb9ExeW+4jKAuzv2icP+TPzblVbF6mm+gWrLX/wsWgQX3mXdHDP6s8SdeeQlfTlZCrB9MT4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786388366987448.95258730529747; Mon, 10 Aug 2026 11:59:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wtVCx-0001ZU-5C; Mon, 10 Aug 2026 14:58:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCv-0001Z2-K3; Mon, 10 Aug 2026 14:58:45 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCt-0003UV-9y; Mon, 10 Aug 2026 14:58:45 -0400 Received: from pps.filterd (m0353729.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67AGVtnv292855; Mon, 10 Aug 2026 18:57:59 GMT Received: from ppma13.dal12v.mail.ibm.com (dd.9e.1632.ip4.static.sl-reverse.com [50.22.158.221]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4fwvjysmke-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:58 +0000 (GMT) Received: from pps.filterd (ppma13.dal12v.mail.ibm.com [127.0.0.1]) by ppma13.dal12v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id 67AIuLno031725; Mon, 10 Aug 2026 18:57:57 GMT Received: from smtprelay04.dal12v.mail.ibm.com ([172.16.1.6]) by ppma13.dal12v.mail.ibm.com (PPS) with ESMTPS id 4fxh0g5wek-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:57 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay04.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67AIvupT30671558 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Aug 2026 18:57:56 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3135358051; Mon, 10 Aug 2026 18:57:56 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9253E5805A; Mon, 10 Aug 2026 18:57:55 +0000 (GMT) Received: from IBM-MFS.ibm.com (unknown [9.61.24.176]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 10 Aug 2026 18:57:55 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=AqhPQ1Q9hfplNQ2nS zeEDUlFwpKQrrNt7URNcAzMZlI=; b=If2ZGqk7DO35SdZcz3t2SD4o5cEDiHNJ0 OfEF3sYwaKBjcy1PRJ1l5YOnGyMmqihOgtFX89CUb5nORJB57sv6Pt0zFdJl3GwF ulwpo8gcsCWzud1Woa3mXc0Bt9DBSaRtckYe/jgdbohw/pjnl63bcSpQ601USXyc H4N1n30b2zRnI7qmJJjWbyRD4QL4+GyifY+1p5rGVwLwkKPVe9cif4KklFms0C7X ctDBMc2oifAqGCj7ksefB1UMvZT4XgWjzKRED8B9k9+My7YdxCL2yK1HkxUY5siN hAiypJ/UC3mOI5JHu9SfAip1SHqwcVtg47NKQnkw58B79cteiRckA== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 7/8] ufs/aspeed: Add AST2700 UFS host controller Date: Mon, 10 Aug 2026 13:57:45 -0500 Message-ID: <20260810185748.1253-8-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260810185748.1253-1-mikail.sadic@ibm.com> References: <20260810185748.1253-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfX3ZvfY4b9RI8q k5GCsFt/K1o259L5O6d2Ilw2lgCrafGNdQ0rTTbrwbib9QyQficD+qIdSYPiI0zFqGdBQg7hHlu p/ksuSLAAOtBgx7qKpUajN7Zf1tbXzmauq1xA9b9Kx/f9M4trdxb59Du/3xjIqasiJ/glrPuRuQ DrFpKFNrbgJ+41oEHih5DgjiH9FKMsdMxzz+Rsdy8F5qlKugZhD/82YFPkvyuMhXlUNgD23HYaF jKR6DKmJVKuJy2FVGtYn7tsMsqHqm4miOtptjy0aJZyWAEcXNF5d7f09Q6yhXCLX+ctUx3tmwzP tbD9G1g+Kbh2x82uwjQCzyodK3IUOhcq4k81n+Hu68o6Rdrwxhg/urzuLY3n8BwfS4IIN79ryHw PzPbLzt2T3k3xDWKkMi1Q7nznvy3Y1Q+2yyfmTj1fAAip8fCKTb+s74oXWHOx6IYVwJMzkPUWuF aZviWxlmv+05qU2Weug== X-Proofpoint-Spam-Info: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfXwJ+PTvhoPexe klXwJO4FZeuq7Sf6B3JOlhclgkJyR/xR4TLURJcxfiMsuiB8dlVadv29C7wFuBzKI0GDRiR+oU0 3E4L/U0sTXOYi/+YWB3vtPot2SpZNTM= X-Authority-Analysis: v=2.4 cv=RqD16imK c=1 sm=1 tr=0 ts=6a7a1f36 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=hD80L64hAAAA:8 a=ATOKqi0wAkDwqrHMCoMA:9 X-Proofpoint-GUID: u9OUWINL-Buua42nQFQh0N3VoybuUwRs X-Proofpoint-ORIG-GUID: AoxkxqbdErwQZa0bkWVQT0vCexm0PqaK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-10_04,2026-08-10_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608100158 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1786388368884158500 Content-Type: text/plain; charset="utf-8" The AST2700 carries a UFS host controller (aspeed,ufshc-m31-16nm) at 0x12c08200 on IRQ 118, used by the OpenBMC image to reach its root filesystem. Add 'aspeed-ufs' as a subclass of the generic sysbus UFS controller. The sysbus device supplies the MMIO region, the interrupt, the DMA address space and the controller properties, so the only thing left to model is the UFSHCI version: the AST2700 reports 2.0, while the core reports 4.1, which makes the U-Boot and Linux drivers run 4.x-only probe steps this model does not implement. Wire the controller into the AST2700 SoC and select UFS_SYSBUS, so an Aspeed target no longer depends on the PCI UFS device being configured to get a UFS controller. The UFS bus only exists once the controller is realized, so the board creates the logical unit for the first backend drive after SoC realize rather than through a controller drive property. AspeedMachineClass gains a ufs_block_size field for machines whose image geometry differs from the ufs-lu default; zero leaves the default in place. Signed-off-by: Mikail Sadic --- MAINTAINERS | 2 ++ docs/specs/aspeed-ufs.rst | 46 +++++++++++++++++++++++++ docs/specs/index.rst | 1 + include/hw/arm/aspeed.h | 1 + include/hw/arm/aspeed_soc.h | 3 ++ include/hw/ufs/aspeed_ufs.h | 15 +++++++++ hw/arm/aspeed.c | 25 ++++++++++++++ hw/arm/aspeed_ast27x0.c | 13 +++++++ hw/ufs/aspeed_ufs.c | 67 +++++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/ufs/meson.build | 1 + 11 files changed, 175 insertions(+) create mode 100644 docs/specs/aspeed-ufs.rst create mode 100644 include/hw/ufs/aspeed_ufs.h create mode 100644 hw/ufs/aspeed_ufs.c diff --git a/MAINTAINERS b/MAINTAINERS index ec415cb8e4..4b335c5dc0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2700,6 +2700,8 @@ M: Jeuk Kim S: Supported F: hw/ufs/* F: include/block/ufs.h +F: include/hw/ufs/aspeed_ufs.h +F: docs/specs/aspeed-ufs.rst F: tests/qtest/ufs-test.c =20 megasas diff --git a/docs/specs/aspeed-ufs.rst b/docs/specs/aspeed-ufs.rst new file mode 100644 index 0000000000..2ab7e7e771 --- /dev/null +++ b/docs/specs/aspeed-ufs.rst @@ -0,0 +1,46 @@ +ASPEED AST2700 UFS Host Controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The AST2700 SoC includes a UFS host controller identified in the device tr= ee +as ``aspeed,ufshc-m31-16nm``, mapped at ``0x12c08200`` (IRQ SPI 118). + +QEMU models it as ``aspeed-ufs``, a subclass of the generic sysbus UFS +controller ``sysbus-ufs`` (``hw/ufs/ufs-sysbus.c``), which in turn wraps t= he +transport-independent UFS core (``hw/ufs/ufs.c`` and ``hw/ufs/lu.c``) that +also backs the PCI UFS device. The sysbus device provides the MMIO region, +the interrupt line, the DMA address space and the controller properties; t= he +core implements the UFSHCI registers, the UTP transfer and task list +processing, the UPIU and query handling and the SCSI logical-unit logic. + +The only AST2700-specific behaviour ``aspeed-ufs`` adds is the controller +version register value ``0x00000200``, the UFSHCI 2.0 interface the hardwa= re +reports. + +The clock/reset wrapper at ``0x12c08000`` (``aspeed,ast2700-ufscnr``) is l= eft +as an ``UnimplementedDevice``. + +Logical units +------------- + +Storage is attached through ``ufs-lu`` devices on the controller's UFS bus +(``ufs-bus.0``), exactly as for the PCI UFS device. The Huygens OpenBMC im= age +is laid out for 512-byte sectors, so its logical unit is created with +``logical-block-size=3D512``. + +Usage +----- + +Attach a UFS image as logical unit 0 of the controller's UFS bus: + +.. code-block:: console + + qemu-system-aarch64 -M huygens-bmc \ + -nodefaults \ + -blockdev node-name=3Dfmc0,driver=3Dfile,filename=3Dimage-bmc \ + -device w25q01jvq,bus=3Dssi.0,cs=3D0,drive=3Dfmc0 \ + -blockdev node-name=3Dufs0,driver=3Dfile,filename=3Dufs.img \ + -device ufs-lu,bus=3Dufs-bus.0,drive=3Dufs0,lun=3D0,logical-block-size= =3D512 \ + -display none -serial mon:stdio + +Please check :doc:`../../system/arm/aspeed` for more details on the +``huygens-bmc`` machine. diff --git a/docs/specs/index.rst b/docs/specs/index.rst index 4de65e2fdf..dd0cdec8d4 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -40,4 +40,5 @@ guest hardware that is specific to QEMU. riscv-aia aspeed-intc ucd90320 + aspeed-ufs iommu-testdev diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index a00238ed74..dedc784926 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -62,6 +62,7 @@ struct AspeedMachineClass { uint32_t uart_default; bool sdhci_wp_inverted; bool vbootrom; + uint32_t ufs_block_size; }; =20 /* diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 41dc04e293..8a562d47ec 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -35,6 +35,7 @@ #include "hw/gpio/aspeed_gpio.h" #include "hw/gpio/aspeed_sgpio.h" #include "hw/sd/aspeed_sdhci.h" +#include "hw/ufs/aspeed_ufs.h" #include "hw/usb/hcd-ehci.h" #include "qom/object.h" #include "hw/misc/aspeed_lpc.h" @@ -118,6 +119,7 @@ struct AspeedSoCState { AspeedAPB2OPBState fsi[2]; AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM]; + SysbusUfsState ufs; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" @@ -298,6 +300,7 @@ enum { ASPEED_DEV_PRIC0, ASPEED_DEV_PRIC1, ASPEED_DEV_OTP, + ASPEED_DEV_UFS, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/include/hw/ufs/aspeed_ufs.h b/include/hw/ufs/aspeed_ufs.h new file mode 100644 index 0000000000..6b9f85498a --- /dev/null +++ b/include/hw/ufs/aspeed_ufs.h @@ -0,0 +1,15 @@ +/* + * ASPEED AST2700 UFS Host Controller + * + * Copyright 2026 IBM Corp. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ASPEED_UFS_H +#define ASPEED_UFS_H + +#include "hw/ufs/ufs-sysbus.h" + +#define TYPE_ASPEED_UFS "aspeed-ufs" + +#endif /* ASPEED_UFS_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a48c442058..b70a1326a1 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -187,6 +187,31 @@ static void aspeed_machine_init(MachineState *machine) aspeed_connect_serial_hds_to_uarts(bmc); qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); =20 + /* + * If the SoC instantiated a UFS host controller (AST2700), attach the + * first backend drive to it as logical unit 0. The controller and its + * UFS bus only exist once the SoC has been realized, so the ufs-lu is + * created here rather than through a controller drive property. + */ + if (object_resolve_path_component(OBJECT(bmc->soc), "ufs")) { + DriveInfo *ufs_dinfo =3D drive_get(IF_NONE, 0, 0); + + if (ufs_dinfo) { + DeviceState *ufs_lu =3D qdev_new(TYPE_UFS_LU); + + qdev_prop_set_uint8(ufs_lu, "lun", 0); + if (amc->ufs_block_size) { + qdev_prop_set_uint32(ufs_lu, "logical-block-size", + amc->ufs_block_size); + } + qdev_prop_set_drive_err(ufs_lu, "drive", + blk_by_legacy_dinfo(ufs_dinfo), + &error_fatal); + qdev_realize_and_unref(ufs_lu, BUS(&bmc->soc->ufs.ufs.bus), + &error_fatal); + } + } + if (defaults_enabled()) { aspeed_board_init_flashes(&bmc->soc->fmc, bmc->fmc_model ? bmc->fmc_model : amc->fmc_m= odel, diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index b908d7d4ff..1ee8f3a210 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -46,6 +46,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_GIC_REDIST] =3D 0x12280000, [ASPEED_DEV_SDMC] =3D 0x12C00000, [ASPEED_DEV_SCU] =3D 0x12C02000, + [ASPEED_DEV_UFS] =3D 0x12c08200, [ASPEED_DEV_RTC] =3D 0x12C0F000, [ASPEED_DEV_TIMER1] =3D 0x12C10000, [ASPEED_DEV_PCIE_PHY0] =3D 0x12C15000, @@ -129,6 +130,7 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_EHCI2] =3D 37, [ASPEED_DEV_PCIE0] =3D 56, [ASPEED_DEV_PCIE1] =3D 57, + [ASPEED_DEV_UFS] =3D 118, [ASPEED_DEV_LPC] =3D 192, [ASPEED_DEV_IBT] =3D 192, [ASPEED_DEV_KCS] =3D 192, @@ -533,6 +535,8 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0= ], TYPE_SYSBUS_SDHCI); =20 + object_initialize_child(obj, "ufs", &s->ufs, TYPE_ASPEED_UFS); + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); =20 @@ -1039,6 +1043,15 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_EMMC)); =20 + /* UFS */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ufs), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ufs), 0, + sc->memmap[ASPEED_DEV_UFS]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ufs), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_UFS)); + /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), &error_abort); diff --git a/hw/ufs/aspeed_ufs.c b/hw/ufs/aspeed_ufs.c new file mode 100644 index 0000000000..bfe540b929 --- /dev/null +++ b/hw/ufs/aspeed_ufs.c @@ -0,0 +1,67 @@ +/* + * ASPEED AST2700 UFS Host Controller + * + * The AST2700 host controller (aspeed,ufshc-m31-16nm) is the generic sysb= us + * UFS controller, so this model only overrides the UFSHCI version. + * + * The clock/reset wrapper at 0x12c08000 (aspeed,ast2700-ufscnr) is modell= ed + * elsewhere as an UnimplementedDevice. + * + * Copyright 2026 IBM Corp. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/ufs/aspeed_ufs.h" + +/* UFSHCI 2.0, against the 4.1 the core reports */ +#define ASPEED_UFS_HCI_VERSION 0x00000200 + +OBJECT_DECLARE_TYPE(AspeedUfsState, AspeedUfsClass, ASPEED_UFS) + +struct AspeedUfsState { + SysbusUfsState parent_obj; +}; + +struct AspeedUfsClass { + DeviceClass parent_class; + + DeviceRealize parent_realize; +}; + +static void aspeed_ufs_realize(DeviceState *dev, Error **errp) +{ + ERRP_GUARD(); + AspeedUfsClass *ac =3D ASPEED_UFS_GET_CLASS(dev); + SysbusUfsState *s =3D SYSBUS_UFS(dev); + + ac->parent_realize(dev, errp); + if (*errp) { + return; + } + + s->ufs.reg.ver =3D ASPEED_UFS_HCI_VERSION; +} + +static void aspeed_ufs_class_init(ObjectClass *oc, const void *data) +{ + AspeedUfsClass *ac =3D ASPEED_UFS_CLASS(oc); + DeviceClass *dc =3D DEVICE_CLASS(oc); + + device_class_set_parent_realize(dc, aspeed_ufs_realize, + &ac->parent_realize); + dc->desc =3D "ASPEED UFS Host Controller"; +} + +static const TypeInfo aspeed_ufs_types[] =3D { + { + .name =3D TYPE_ASPEED_UFS, + .parent =3D TYPE_SYSBUS_UFS, + .instance_size =3D sizeof(AspeedUfsState), + .class_size =3D sizeof(AspeedUfsClass), + .class_init =3D aspeed_ufs_class_init, + } +}; + +DEFINE_TYPES(aspeed_ufs_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index ac44740547..14a076f4f9 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -557,6 +557,7 @@ config ASPEED_SOC select MAX31785 select UCD90320 select FSI_APB2OPB_ASPEED + select UFS_SYSBUS select AT24C select PCI_EXPRESS select PCI_EXPRESS_ASPEED diff --git a/hw/ufs/meson.build b/hw/ufs/meson.build index a84627b96a..9266a580f5 100644 --- a/hw/ufs/meson.build +++ b/hw/ufs/meson.build @@ -1,3 +1,4 @@ system_ss.add(when: 'CONFIG_UFS', if_true: files('ufs.c', 'lu.c')) system_ss.add(when: 'CONFIG_UFS_PCI', if_true: files('ufs-pci.c')) system_ss.add(when: 'CONFIG_UFS_SYSBUS', if_true: files('ufs-sysbus.c')) +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_ufs.c')) --=20 2.53.0 From nobody Wed Aug 26 06:37:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1786388445; cv=none; d=zohomail.com; s=zohoarc; b=M8Bel17b3iqiN+ESIaBmAph+gkVcBwUKYsBUe0sMkoGThIiexiSIwdSe/D0Zt9lMRFLLsv8y3anc1Pz6ED+85lNWfRpNgaomxWbK9HCrvlnezDSVN5H9i4bOaVDGbajteAfFGpKKTUOwon7LpGuF6S17vlh2HjX600s2xC3xSI8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786388445; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=frjU5hh7Boe9s9buiQCwbH8wAJyNjuI+Nq0e6POoIgM=; b=mQtMCw+daagEr0X6Quo2rDnqtJoRoio8FwS/FjMgus9uEHR+rAnG/9gMgHtVyVGxxO16Faz0gYqarXRYEWPbY/8BeK3NHXjHQVA9QI/GQrkpkrYer2x19uRT0PoaE1wzlf31ISWVC6epiRXxMCSRBe6ZFEOl/Y84dkjILOaddUw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786388445172112.34651176863201; Mon, 10 Aug 2026 12:00:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wtVDM-0001pG-Ud; Mon, 10 Aug 2026 14:59:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCy-0001c6-HO; Mon, 10 Aug 2026 14:58:48 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wtVCv-0003Uz-QE; Mon, 10 Aug 2026 14:58:48 -0400 Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67AGVgnX2154436; Mon, 10 Aug 2026 18:58:00 GMT Received: from ppma21.wdc07v.mail.ibm.com (5b.69.3da9.ip4.static.sl-reverse.com [169.61.105.91]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4fwvm9hnh1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:59 +0000 (GMT) Received: from pps.filterd (ppma21.wdc07v.mail.ibm.com [127.0.0.1]) by ppma21.wdc07v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id 67AIfKI3022881; Mon, 10 Aug 2026 18:57:58 GMT Received: from smtprelay04.dal12v.mail.ibm.com ([172.16.1.6]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4fxfsjp2cs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Aug 2026 18:57:58 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay04.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 67AIvuWc30671564 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Aug 2026 18:57:57 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DA6595805A; Mon, 10 Aug 2026 18:57:56 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3F0D45805C; Mon, 10 Aug 2026 18:57:56 +0000 (GMT) Received: from IBM-MFS.ibm.com (unknown [9.61.24.176]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 10 Aug 2026 18:57:56 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=frjU5hh7Boe9s9bui QCwbH8wAJyNjuI+Nq0e6POoIgM=; b=SeBPSncOz+x43/GqJVKvqbJgJmtkKulxH cUWh0FwDgq+wt0y1WMQk6u4EMR8hPxgs20pzIZLDUeLGdSXTAVG86hstjpZxt0KK BldaBQu2cp7c+1NQMIblmn7790onqrx/EKqqI2Xu7SkM6lw+6s9xZiS0UWrkin0E qEXW2Uj1tZLX9josmMckq6esZegpXdL0DqQOZWyB04eQBniFBJKtYECUUmLBf5zE I0+OCvZJ8ofC6XkiCho0eBI8moCzuJIZ0lW4WkiAynSpgnCReyjEdswQG+2xmyCi j4oHkt8le2c9oqTFVZ3uYu+PHKqzC0wSP87V9uCWg8Nsimh/92AIg== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 8/8] arm/aspeed: Add AST2700 Huygens machine Date: Mon, 10 Aug 2026 13:57:46 -0500 Message-ID: <20260810185748.1253-9-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260810185748.1253-1-mikail.sadic@ibm.com> References: <20260810185748.1253-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfX1Nm3l74o0BZg 7sclHXECaWHjGfz7gYwYzJvMIxcbbjY3qpO26KXf/KPVPQr5fU+dchmanaj7o47pgLU6z1DogUO 1xpQWQeLKGLhpLgCS9P2Hwjty0crFblbIVbmDdJr6KnVwMj6V8vLzelQ8WGAZeKOzqTFKK3l3hJ utVei+K8lhJHmOUhfaLckqDrtNKehHAeTpJbpe7ubJl4OVzz/oYsrVg2SEyDO/5T3ruRlpj1uoU XLlUs9V+rSXT7/iOwv1RkLV4FreXhQ1afkL/KFhqRiELdDOiceWqPH7Hx4maDe/bQBDMVP29aPX SWuOW/DVDL20FLJ89bajYzNp/2x2+cM9BHVD9+GIngipDt2I7w6QXe56AX8XrAAnPXpvjKRdOkc BiF6ip3hRKR9PxycwrvcldWH2xm+J8fxeIrEJ3e4+EO4x/ZdGX6AyLCPjru+7hxAd90fBwQgd0B C/T1uTcXUC5mDT2HqUQ== X-Proofpoint-ORIG-GUID: thfjwy4ddAjuMpH2B_sxAW_woIMRZd3l X-Proofpoint-Spam-Info: AW1haW4tMjYwODEwMDE1OCBTYWx0ZWRfXx/7Sk4yI8icP 5DkcwBOsr4TckbzOKpyqWJVkNWKT2WEOTzwlaRqx4SsRqI4U4vlxG6fkeRGqoty+3C0QpH2EjPO NZeUMYluD5JuR+Ht2SYybkfnSgPhRrY= X-Authority-Analysis: v=2.4 cv=IfK3n2qa c=1 sm=1 tr=0 ts=6a7a1f37 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=7rK_Fc8NI2sx5OKxegoA:9 X-Proofpoint-GUID: puHLc3i163Z5PkuTa5ACCuN3m33Ni7Da X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-10_04,2026-08-10_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608100158 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1786388447301158500 Content-Type: text/plain; charset="utf-8" Huygens is the IBM POWER12 server platform. The BMC is built around the Aspeed AST2700 A2 SoC and handles power sequencing, thermal management, VPD access and host firmware boot for the POWER host processors. Add a 'huygens-bmc' machine that instantiates the AST2700 SoC with the board-specific configuration needed to boot the OpenBMC Linux image: the FMC/SPI flash models, the I2C topology (BMC, system and chassis VPD EEPROMs, the UCD90320 power sequencer and temperature sensors) and the network controllers. Signed-off-by: Mikail Sadic --- docs/system/arm/aspeed.rst | 50 ++++++- hw/arm/aspeed_ast27x0_huygens.c | 241 ++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 290 insertions(+), 2 deletions(-) create mode 100644 hw/arm/aspeed_ast27x0_huygens.c diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 2d51ceeb84..4e42b1edee 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -271,8 +271,8 @@ configuration file for OTP memory: done > otpmem.img fi =20 -Aspeed 2700 family boards (``ast2700-evb``, ``ast2700fc``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D +Aspeed 2700 family boards (``ast2700-evb``, ``ast2700fc``, ``huygens-bmc``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D =20 The QEMU Aspeed machines model BMCs of Aspeed evaluation boards. They are based on different releases of the Aspeed SoC : @@ -285,6 +285,7 @@ AST2700 SoC based machines : =20 - ``ast2700-evb`` Aspeed AST2700 Evaluation board (Cortex-A35) - ``ast2700fc`` Aspeed AST2700 Evaluation board (Cortex-A35 + C= ortex-M4) +- ``huygens-bmc`` Aspeed AST2700 IBM Huygens POWER12 BMC =20 Supported devices ----------------- @@ -312,6 +313,8 @@ Supported devices * PECI Controller (minimal) * I3C Controller * Internal Bridge Controller (SLI dummy) + * UFS Host Controller (aspeed,ufshc-m31-16nm) - ``huygens-bmc`` only + * FSI APB-to-OPB bridge with CFAM-S mailbox =20 Missing devices --------------- @@ -440,6 +443,49 @@ Use ``tio`` or another terminal emulator to connect to= the consoles: $ tio /dev/pts/56 $ tio /dev/pts/57 =20 +Booting the huygens-bmc machine +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The IBM Huygens BMC is based on the AST2700 A2 SoC. Its storage is +split across two images: + +* the FMC (SPI NOR) flash image (``image-bmc``) holds U-Boot, the Linux + kernel and the FIT image; +* the UFS image (``ufs.img``) holds the root filesystem. + +Both images can be built from the OpenBMC project tree. + +To boot the machine, attach the flash image to the FMC device and the +root filesystem image to a UFS logical unit. ``-nodefaults`` is used so the +board does not also create a default flash at chip-select 0, and the conso= le +is wired explicitly since ``-nodefaults`` disables the implicit one: + +.. code-block:: bash + + $ qemu-system-aarch64 -M huygens-bmc \ + -nodefaults \ + -blockdev node-name=3Dfmc0,driver=3Dfile,filename=3Dimage-bmc \ + -device w25q01jvq,bus=3Dssi.0,cs=3D0,drive=3Dfmc0 \ + -blockdev node-name=3Dufs0,driver=3Dfile,filename=3Dufs.img \ + -device ufs-lu,bus=3Dufs-bus.0,drive=3Dufs0,lun=3D0,logical-block-= size=3D512 \ + -display none -serial mon:stdio + +The FMC flash sits on chip-select 0 of the ``ssi.0`` bus and the UFS logic= al +unit on ``ufs-bus.0``. The Huygens image is laid out for 512-byte sectors, +hence ``logical-block-size=3D512``. + +The machine instantiates three ``ftgmac100`` Ethernet controllers, which +are wired up by the board. To expose them with user networking, add three +``-nic user`` options to the command above: + +.. code-block:: bash + + -nic user \ + -nic user \ + -nic user + +The default BMC console is ``uart12``. + =20 Aspeed Bridge IC and Platform Root of Trust processor family boards (``ast= 1030-evb``, ``ast1040-evb``, ``ast1060-evb``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/hw/arm/aspeed_ast27x0_huygens.c b/hw/arm/aspeed_ast27x0_huygen= s.c new file mode 100644 index 0000000000..424962c536 --- /dev/null +++ b/hw/arm/aspeed_ast27x0_huygens.c @@ -0,0 +1,241 @@ +/* + * IBM Huygens BMC + * + * Copyright 2026 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/machines-qom.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/nvram/eeprom_at24c.h" +#include "hw/i2c/i2c_mux_pca954x.h" +#include "hw/sensor/tmp105.h" + +/* SCU HW Strap1 */ +#define HUYGENS_BMC_HW_STRAP1 0x00000800 +/* SCUIO HW Strap1 */ +#define HUYGENS_BMC_HW_STRAP2 0x00000700 + +/* + * 2048-byte IPZ VPD image: + * VHDR, VTOC, VINI, VMPU, VSBP, VSYS, UTIL, DINF, VCEN + ECC + */ +static const uint8_t huygens_bmc_fruid[] =3D { + 0x00, 0x0f, 0x17, 0xba, 0x3a, 0xc9, 0x32, 0x31, 0x49, 0xb2, 0xde, 0x84, + 0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02, + 0x30, 0x31, 0x50, 0x54, 0x0e, 0x56, 0x54, 0x4f, 0x43, 0xd5, 0x00, 0x37, + 0x00, 0x74, 0x00, 0xa6, 0x05, 0x1d, 0x00, 0x50, 0x46, 0x08, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x84, 0x70, 0x00, 0x52, 0x54, + 0x04, 0x56, 0x54, 0x4f, 0x43, 0x50, 0x54, 0x62, 0x56, 0x49, 0x4e, 0x49, + 0xd5, 0x00, 0xab, 0x00, 0x84, 0x00, 0x85, 0x05, 0x21, 0x00, 0x56, 0x4d, + 0x50, 0x55, 0xff, 0x00, 0x2f, 0x01, 0xa4, 0x00, 0x5c, 0x05, 0x29, 0x00, + 0x56, 0x53, 0x42, 0x50, 0xff, 0x00, 0xd3, 0x01, 0x30, 0x00, 0x50, 0x05, + 0x0c, 0x00, 0x56, 0x53, 0x59, 0x53, 0xff, 0x00, 0x03, 0x02, 0x44, 0x01, + 0xff, 0x04, 0x51, 0x00, 0x55, 0x54, 0x49, 0x4c, 0xff, 0x00, 0x47, 0x03, + 0xe8, 0x00, 0xc5, 0x04, 0x3a, 0x00, 0x44, 0x49, 0x4e, 0x46, 0xff, 0x00, + 0x2f, 0x04, 0x30, 0x00, 0xb9, 0x04, 0x0c, 0x00, 0x56, 0x43, 0x45, 0x4e, + 0xff, 0x00, 0x5f, 0x04, 0x48, 0x00, 0xa7, 0x04, 0x12, 0x00, 0x50, 0x46, + 0x01, 0x00, 0x78, 0x84, 0x80, 0x00, 0x52, 0x54, 0x04, 0x56, 0x49, 0x4e, + 0x49, 0x44, 0x52, 0x10, 0x51, 0x45, 0x4d, 0x55, 0x20, 0x48, 0x55, 0x59, + 0x47, 0x45, 0x4e, 0x53, 0x20, 0x42, 0x4d, 0x43, 0x43, 0x45, 0x01, 0x20, + 0x56, 0x5a, 0x02, 0x20, 0x20, 0x46, 0x4e, 0x07, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x50, 0x4e, 0x07, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x53, 0x4e, 0x0c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x43, 0x43, 0x04, 0x20, 0x20, 0x20, 0x20, 0x48, + 0x45, 0x04, 0x20, 0x20, 0x20, 0x20, 0x43, 0x54, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x48, 0x57, 0x02, 0x00, 0x01, 0x42, 0x33, 0x06, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x42, 0x34, 0x01, 0x20, 0x42, 0x37, 0x0c, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x46, + 0x01, 0x00, 0x78, 0x84, 0xa0, 0x00, 0x52, 0x54, 0x04, 0x56, 0x4d, 0x50, + 0x55, 0x56, 0x5a, 0x02, 0x30, 0x31, 0x53, 0x4f, 0x02, 0x00, 0x00, 0x44, + 0x49, 0x04, 0x00, 0x00, 0x00, 0x00, 0x49, 0x4e, 0x80, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x02, 0x00, 0x00, 0x78, 0x84, + 0x2c, 0x00, 0x52, 0x54, 0x04, 0x56, 0x53, 0x42, 0x50, 0x44, 0x52, 0x10, + 0x56, 0x50, 0x44, 0x20, 0x52, 0x4f, 0x4f, 0x54, 0x20, 0x4e, 0x4f, 0x44, + 0x45, 0x20, 0x20, 0x20, 0x50, 0x41, 0x01, 0x59, 0x49, 0x4d, 0x04, 0x70, + 0x00, 0x10, 0x00, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x78, 0x84, + 0x40, 0x01, 0x52, 0x54, 0x04, 0x56, 0x53, 0x59, 0x53, 0x44, 0x52, 0x06, + 0x53, 0x59, 0x53, 0x54, 0x45, 0x4d, 0x42, 0x52, 0x02, 0x20, 0x20, 0x53, + 0x45, 0x07, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x53, 0x47, 0x07, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x54, 0x4d, 0x08, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x54, 0x4e, 0x08, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x4d, 0x4e, 0x07, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x49, 0x44, 0x02, 0x20, 0x20, 0x53, 0x55, 0x06, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x4e, 0x4e, 0x10, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x52, 0x47, 0x04, 0x20, 0x20, 0x20, 0x20, 0x52, 0x42, 0x04, 0x20, 0x20, + 0x20, 0x20, 0x57, 0x4e, 0x0c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x46, 0x56, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x41, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x41, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x41, 0x4b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x41, 0x54, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x42, 0x4e, 0x40, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x42, 0x41, 0x01, 0x20, 0x4d, + 0x4d, 0x01, 0x20, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x78, 0x84, + 0xe4, 0x00, 0x52, 0x54, 0x04, 0x55, 0x54, 0x49, 0x4c, 0x44, 0x30, 0x01, + 0x00, 0x44, 0x31, 0x01, 0x00, 0x44, 0x32, 0x01, 0x00, 0x44, 0x33, 0x01, + 0x00, 0x44, 0x34, 0x04, 0x00, 0x00, 0x00, 0x00, 0x44, 0x35, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x44, 0x36, 0x04, 0x00, 0x00, 0x00, 0x00, 0x44, 0x37, + 0x04, 0x00, 0x00, 0x00, 0x00, 0x44, 0x38, 0x08, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x44, 0x39, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x46, 0x30, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x46, 0x31, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x46, 0x32, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x33, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, + 0x34, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x35, + 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x36, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x37, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x38, 0x10, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x46, 0x39, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x02, + 0x00, 0x00, 0x78, 0x84, 0x2c, 0x00, 0x52, 0x54, 0x04, 0x44, 0x49, 0x4e, + 0x46, 0x52, 0x49, 0x04, 0x00, 0x00, 0x00, 0x00, 0x46, 0x4c, 0x14, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x46, 0x04, 0x00, 0x00, + 0x00, 0x00, 0x78, 0x84, 0x44, 0x00, 0x52, 0x54, 0x04, 0x56, 0x43, 0x45, + 0x4e, 0x44, 0x52, 0x06, 0x43, 0x45, 0x43, 0x20, 0x20, 0x20, 0x53, 0x45, + 0x07, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x54, 0x4d, 0x08, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x46, 0x43, 0x08, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x52, 0x47, 0x04, 0x20, 0x20, 0x20, + 0x20, 0x52, 0x42, 0x04, 0x20, 0x20, 0x20, 0x20, 0x50, 0x46, 0x03, 0x00, + /* ECC area */ + 0x00, 0x00, 0x78, 0x4d, 0x5d, 0x84, 0x8c, 0x0a, 0xf9, 0xed, 0x3d, 0x96, + 0x11, 0x4a, 0x45, 0x9a, 0xb6, 0xb2, 0xd9, 0x19, 0x43, 0x05, 0x0f, 0xdd, + 0xb5, 0xf9, 0x3d, 0x5b, 0x81, 0xb3, 0x79, 0xcb, 0x19, 0x48, 0xbb, 0xa2, + 0x57, 0x10, 0x6e, 0x39, 0x38, 0x85, 0x5e, 0xa3, 0x24, 0xbc, 0x02, 0x63, + 0x6b, 0x79, 0xa3, 0x6b, 0xed, 0xcd, 0x27, 0x4e, 0x79, 0x9f, 0x76, 0x4e, + 0x7b, 0x93, 0x2d, 0xf4, 0x4c, 0x51, 0x0e, 0x28, 0x46, 0x43, 0x2b, 0xd9, + 0x1b, 0x21, 0x21, 0xc8, 0xe4, 0x6e, 0x9b, 0x4e, 0x34, 0x7e, 0x6e, 0x82, + 0x1b, 0x09, 0x13, 0xf1, 0x40, 0x7b, 0x9f, 0x6d, 0x50, 0x3e, 0x65, 0x31, + 0x1f, 0x19, 0x6f, 0x61, 0x78, 0x27, 0x72, 0x7c, 0x59, 0x34, 0x7c, 0x05, + 0x58, 0x13, 0x6f, 0x78, 0x13, 0x56, 0x33, 0x19, 0x1e, 0x79, 0x17, 0x41, + 0x28, 0x58, 0x6d, 0x26, 0x01, 0x34, 0x7d, 0x68, 0x1d, 0x7e, 0x1c, 0x42, + 0x49, 0x2a, 0x11, 0x7c, 0x70, 0x1a, 0x66, 0x47, 0x68, 0x6e, 0x3f, 0x5e, + 0x6b, 0x6d, 0x25, 0x7e, 0x3e, 0x24, 0x39, 0x07, 0x3c, 0x6e, 0x5b, 0x5d, + 0x4e, 0x59, 0x79, 0x7d, 0x6f, 0x5f, 0x7f, 0x5f, 0x4b, 0x5f, 0x6d, 0x3e, + 0x58, 0x57, 0x1b, 0x19, 0x5d, 0x14, 0x43, 0x83, 0xfc, 0xe6, 0x49, 0x84, + 0x41, 0x28, 0x0b, 0x0a, 0x00, 0x5b, 0xec, 0x46, 0x13, 0x4d, 0x00, 0xdc, + 0x89, 0xab, 0xbb, 0x77, 0x77, 0x7e, 0xee, 0xff, 0xfd, 0xdf, 0xff, 0xbb, + 0xbf, 0xff, 0x77, 0x7f, 0xfe, 0xee, 0xff, 0xfd, 0xdf, 0xff, 0xbb, 0xbf, + 0xfe, 0x76, 0x7e, 0xca, 0xc8, 0x99, 0x51, 0xd7, 0x70, 0x00, 0x03, 0x26, + 0x9e, 0x4e, 0x7f, 0x13, 0x38, 0xbb, 0x3c, 0xbb, 0x00, 0x02, 0xa0, 0x0a, + 0xcb, 0x70, 0xb7, 0x9f, 0x2b, 0x79, 0xa4, 0x00, 0x07, 0x71, 0xad, 0x17, + 0x41, 0xd7, 0xb9, 0x8c, 0x6d, 0x08, 0x2c, 0x80, 0x04, 0x56, 0x6b, 0x9f, + 0x00, 0x9f, 0xbe, 0xdb, 0x71, 0x63, 0x01, 0xb8, 0xf0, 0x41, 0xc0, 0xe1, + 0x8d, 0x3a, 0x6f, 0xc0, 0x66, 0x5f, 0xb6, 0x4c, 0x2a, 0x5f, 0x06, 0x00, + /* Rest is 0x00 */ +}; +static const size_t huygens_bmc_fruid_len =3D sizeof(huygens_bmc_fruid); + +/* chassis1 VPD: huygens_bmc_fruid with VCEN.FC patched to "2E4C-001" */ +#define HUYGENS_CHASSIS1_FC_OFFSET 0x048a +static const uint8_t huygens_chassis1_fc[] =3D { + 0x32, 0x45, 0x34, 0x43, 0x2d, 0x30, 0x30, 0x31 +}; + +static void huygens_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + + /* I2C0: BMC EEPROM */ + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 8 * KiB); + + /* I2C5: UCD90320 power sequencer */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ucd90320", = 0x11); + + /* I2C6: chassis1 backplane VPD EEPROM */ + { + g_autofree uint8_t *ch1 =3D g_malloc(huygens_bmc_fruid_len); + memcpy(ch1, huygens_bmc_fruid, huygens_bmc_fruid_len); + memcpy(ch1 + HUYGENS_CHASSIS1_FC_OFFSET, + huygens_chassis1_fc, sizeof(huygens_chassis1_fc)); + at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x50, + 8 * KiB, ch1, huygens_bmc_fruid_len); + } + + /* I2C8: System VPD at 0x53 */ + at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x53, + 4 * KiB, huygens_bmc_fruid, huygens_bmc_fruid_le= n); + /* LCD EEPROM */ + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 8 * KiB); + + /* I2C9: System VPD redundant and op-panel devices */ + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), + 0x53, 8 * KiB); /* SYSVPD-redundant */ + + /* TMP275 temperature sensor (compatible with TMP105) */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), + TYPE_TMP105, 0x48); + + /* Op-panel EEPROM */ + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x51, 8 * KiB); + + /* PCA9552 LED controllers on bus 9 */ + aspeed_create_pca9552(soc, 9, 0x62); + aspeed_create_pca9552(soc, 9, 0x64); + aspeed_create_pca9552(soc, 9, 0x66); + + /* DPS310 pressure sensor */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "dps310", 0x= 76); +} + +static void aspeed_machine_huygens_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->alias =3D "ast2700-huygens"; + mc->desc =3D "Aspeed AST2700 A2 [IBM Huygens]"; + amc->soc_name =3D "ast2700-a2"; + amc->hw_strap1 =3D HUYGENS_BMC_HW_STRAP1; + amc->hw_strap2 =3D HUYGENS_BMC_HW_STRAP2; + amc->fmc_model =3D "w25q01jvq"; + amc->spi_model =3D "w25q512jv"; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; + amc->uart_default =3D ASPEED_DEV_UART12; + amc->i2c_init =3D huygens_bmc_i2c_init; + amc->vbootrom =3D true; + /* UFS LUN block size to match the OpenBMC image layout */ + amc->ufs_block_size =3D 512; + mc->default_ram_size =3D 2 * GiB; + aspeed_machine_class_init_cpus_defaults(mc); +} + +static const TypeInfo aspeed_ast27x0_huygens_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("huygens-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_huygens_class_init, + .interfaces =3D aarch64_machine_interfaces, + } +}; + +DEFINE_TYPES(aspeed_ast27x0_huygens_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 4233a800be..a237f1d04f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -75,6 +75,7 @@ arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: fil= es( 'aspeed_ast27x0-fc.c', 'aspeed_ast27x0-ssp.c', 'aspeed_ast27x0-tsp.c', + 'aspeed_ast27x0_huygens.c', 'aspeed_coprocessor_common.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) --=20 2.53.0