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Sat, 08 Aug 2026 22:48:42 -0700 (PDT) From: Itai Handler To: qemu-devel@nongnu.org Cc: kbusch@kernel.org, its@irrelevant.dk, foss@defmacro.it, qemu-block@nongnu.org, qemu-stable@nongnu.org, Itai Handler Subject: [PATCH] hw/nvme: fix cq_pending underflow that wedges pin-based interrupts Date: Sun, 9 Aug 2026 08:48:37 +0300 Message-Id: <20260809054837.67255-1-itai.handler@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=itai.handler@gmail.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 09 Aug 2026 07:45:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1786276069789158500 Content-Type: text/plain; charset="utf-8" n->cq_pending counts the completion queues that hold CQEs the host has not acknowledged yet. With pin-based interrupts it is what keeps the line asserted while any queue still has unacknowledged CQEs: nvme_irq_deassert() clears the vector's bit in irq_status only when the count drops to zero. The accounting is not symmetric. nvme_post_cqes() increments the counter once per empty -> non-empty transition of a CQ, but the two CQ head doorbell paths, nvme_process_db() and nvme_cq_notifier(), decrement it on every update that leaves the queue empty, including an update to a queue that was already empty. nvme_del_cq() gets this right and checks cq->tail !=3D cq->head before decrementing; the doorbell paths do not. A host that writes the CQ head doorbell without having consumed a CQE - a redundant write, e.g. from a completion path racing with another one that already drained the queue - thus decrements more often than the device incremented, and cq_pending goes negative. Once it is negative it never gets back to zero: nvme_irq_deassert() stops clearing irq_status, nvme_irq_check() keeps re-asserting the pin, and the guest takes an endless interrupt for an empty completion queue. Linux eventually gives up on the line irq 26: nobody cared (try booting with the "irqpoll" option) handlers: [<...>] nvme_irq Disabling IRQ #26 and all I/O to the device hangs. MSI-X guests are not affected, they never look at cq_pending. Only decrement when the queue actually had unacknowledged CQEs. That restores the pairing with the increment in nvme_post_cqes() and makes the counter unable to underflow. Cc: qemu-stable@nongnu.org Fixes: 83d7ed5c570d ("hw/nvme: fix pin-based interrupt behavior (again)") Signed-off-by: Itai Handler --- hw/nvme/ctrl.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index bd6ad64..655af08 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -4761,15 +4761,18 @@ static void nvme_cq_notifier(EventNotifier *e) { NvmeCQueue *cq =3D container_of(e, NvmeCQueue, notifier); NvmeCtrl *n =3D cq->ctrl; + bool pending; =20 if (!event_notifier_test_and_clear(e)) { return; } =20 + pending =3D cq->tail !=3D cq->head; + nvme_update_cq_head(cq); =20 if (cq->tail =3D=3D cq->head) { - if (cq->irq_enabled) { + if (cq->irq_enabled && pending) { n->cq_pending--; } =20 @@ -8509,6 +8512,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 uint16_t new_head =3D val & 0xffff; NvmeCQueue *cq; + bool pending; =20 qid =3D (addr - (0x1000 + (1 << 2))) >> 3; if (unlikely(nvme_check_cqid(n, qid))) { @@ -8563,13 +8567,14 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr add= r, int val) qemu_bh_schedule(cq->bh); } =20 + pending =3D cq->tail !=3D cq->head; cq->head =3D new_head; if (!qid && n->dbbuf_enabled) { stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIF= IED); } =20 if (cq->tail =3D=3D cq->head) { - if (cq->irq_enabled) { + if (cq->irq_enabled && pending) { n->cq_pending--; }