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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1786052290963158500 has_valid_slot_assignment() rejected any packet with two instructions assigned to the same slot. That is too strict. When a memory instruction is encoded before a slot-flexible instruction in a packet, the descending slot assignment places the memory op in slot 1 and the other in slot 0, then the "mem insns to slot 0" fixup moves the memory op to slot 0 as well, leaving both in slot 0. Such a packet is valid and executes correctly, but the uniqueness test flagged it as HEX_CAUSE_INVALID_PACKET, raising SIGILL in linux-user and a precise exception in system mode. For example this packet, with the load encoded first, was wrongly rejected: { r6 =3D memw(r3+#-4) r7 =3D #0x4ae6 } Replace the uniqueness test with a slot-exhaustion check: walk the instructions in encoding order handing out slots in strictly decreasing order and fail only if an instruction has no valid slot at or below the running slot. This accepts packets that legally share a slot while still rejecting genuinely unassignable packets, such as a memory instruction grouped with a duplex, or a load followed by an instruction that requires a high slot. Reviewed-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- target/hexagon/decode.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index 6eddcca26ed..e6bb7733be8 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -549,21 +549,35 @@ static bool decode_parsebits_is_loopend(uint32_t enco= ding32) return bits =3D=3D 0x2; } =20 +/* + * Check that the packet's instructions can be grouped into slots: walk th= em + * in encoding order handing out slots in strictly decreasing order, and f= ail + * if an instruction has no valid slot at or below the running slot. Two + * instructions may legally share a slot, so this does not require unique + * slots, only that every instruction fits. + */ static bool has_valid_slot_assignment(Packet *pkt) { - int used_slots =3D 0; - for (int i =3D 0; i < pkt->num_insns; i++) { - int slot_mask; - Insn *insn =3D &pkt->insn[i]; - if (decode_opcode_ends_loop(insn->opcode)) { + int i; + int slot =3D 3; + + for (i =3D 0; i < pkt->num_insns; i++) { + SlotMask valid_slots; + if (decode_opcode_ends_loop(pkt->insn[i].opcode)) { /* We overload slot 0 for endloop. */ continue; } - slot_mask =3D 1 << insn->slot; - if (used_slots & slot_mask) { + if (slot < 0) { return false; } - used_slots |=3D slot_mask; + valid_slots =3D get_valid_slots(pkt, i); + while (!(valid_slots & (1 << slot))) { + if (slot <=3D 0) { + return false; + } + slot--; + } + slot--; } return true; } --=20 2.34.1 From nobody Mon Sep 28 01:14:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1786052268; cv=none; d=zohomail.com; s=zohoarc; b=P7ZIix9J+QCz+x3vX3dj2d6mr0onYBzd2r9+IsxJhr06xaXP9XxsoNWr8lpk2PsmgEEigq+eEOlod7AJr7oK7Xcz+DzwV3UZnzZ2YA+gubo/BkGUvPr5eoR+CcvcqbXczDtLOWwtTbRgEKh0AKt/GzXNJ9TZ57SS+MQbwPl6ZZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786052268; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PCw+r03c1GCoMBqkJSeJiTXWTAy4S3oUw3qsrGuqlbI=; b=D/+YFpAKJJjWTQD8WE4ZSrKcRuAJylOB6i+DPJ1NURZLNxrenqJfD6OGwZ7rbG9UVvSMfk+2aZbbGR/lMDgUlm/cNWdGNinfcxrLKCu4Ca4gKCS/6a31R7DvDVSVOIj80ljrVOvp408bwua+9izJb4y96wB/IpSDcfNXdSwaPd8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786052268362325.305905732498; Thu, 6 Aug 2026 14:37:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ws5m8-00052D-RO; Thu, 06 Aug 2026 17:37:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ws5lq-00050s-2h for qemu-devel@nongnu.org; Thu, 06 Aug 2026 17:36:58 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ws5ln-00005r-6u for qemu-devel@nongnu.org; Thu, 06 Aug 2026 17:36:57 -0400 Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 676L8Akm2815661 for ; Thu, 6 Aug 2026 21:36:54 GMT Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fvy6hruvp-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 06 Aug 2026 21:36:53 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-ca124bf0189so1097253a12.0 for ; Thu, 06 Aug 2026 14:36:53 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1786052271034158500 valid-slots: packets that legally share a slot and were wrongly rejected before the fix (load and transfer, load encoded first; dczeroa packed last with three transfers). invalid-slots: unassignable packets that must still be rejected: store + duplex, load + indirect jump, three logical ops competing for slots 2 and 3, and five ops for four slots. Reviewed-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- tests/tcg/hexagon/invalid-slots.c | 72 +++++++++++++++++++++++++++++++ tests/tcg/hexagon/valid-slots.c | 62 ++++++++++++++++++++++++++ tests/tcg/hexagon/Makefile.target | 1 + 3 files changed, 135 insertions(+) create mode 100644 tests/tcg/hexagon/valid-slots.c diff --git a/tests/tcg/hexagon/invalid-slots.c b/tests/tcg/hexagon/invalid-= slots.c index 607027f314d..f2dace2e541 100644 --- a/tests/tcg/hexagon/invalid-slots.c +++ b/tests/tcg/hexagon/invalid-slots.c @@ -55,6 +55,75 @@ static int test_invalid_slots(void) return sig; } =20 +/* Load then indirect jump, load encoded first: no high slot left for jump= . */ +static int test_invalid_slots_highslot(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + "r3 =3D #mem\n" + ".word 0x91834006\n" /* { r6 =3D memw(r3+#0); */ + ".word 0x529fc000\n" /* jumpr r31 } */ + "1:\n" + "%0 =3D r0\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "r3", "r6", "memory"); + + return sig; +} + +/* + * Three predicate-logical ops: each is restricted to slots 2 and 3, so the + * fourth-and-fifth-slot-free packet still has only two slots for three op= s. + * No change-of-flow is involved, so the only reason to reject it is the s= lot + * conflict. + */ +static int test_invalid_slots_crslot23(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + ".word 0x6b024100\n" /* { p0 =3D and(p1, p2); */ + ".word 0x6b224103\n" /* p3 =3D or(p1, p2); */ + ".word 0x6b42c301\n" /* p1 =3D xor(p2, p3) } */ + "1:\n" + "%0 =3D r0\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "p0", "p1", "p3", "memory"); + + return sig; +} + +/* Three transfers plus a duplex: five ops for four slots. */ +static int test_invalid_slots_five(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + ".word 0x78004020\n" /* { r0 =3D #1; */ + ".word 0x78004041\n" /* r1 =3D #2; */ + ".word 0x78004062\n" /* r2 =3D #3; */ + ".word 0x28452856\n" /* r5 =3D #4; r6 =3D #5 } */ + "1:\n" + "%0 =3D r0\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "r2", "r5", "r6", "memory"); + + return sig; +} + int main() { struct sigaction act; @@ -65,6 +134,9 @@ int main() assert(sigaction(SIGILL, &act, NULL) =3D=3D 0); =20 assert(test_invalid_slots() =3D=3D SIGILL); + assert(test_invalid_slots_highslot() =3D=3D SIGILL); + assert(test_invalid_slots_crslot23() =3D=3D SIGILL); + assert(test_invalid_slots_five() =3D=3D SIGILL); =20 puts("PASS"); return EXIT_SUCCESS; diff --git a/tests/tcg/hexagon/valid-slots.c b/tests/tcg/hexagon/valid-slot= s.c new file mode 100644 index 00000000000..70d9b0b6acf --- /dev/null +++ b/tests/tcg/hexagon/valid-slots.c @@ -0,0 +1,62 @@ +/* + * Regression tests for valid packets that qemu incorrectly rejected as + * invalid. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +int err; + +#include "hex_test.h" + +/* volatile to keep the load from being optimized away */ +static volatile int buf[2] =3D { 0x1234, 0 }; + +/* Load and register transfer in one packet, load encoded first. */ +static int32_t load_imm_pair(void) +{ + int32_t out; + /* { r6 =3D memw(r3+#-4); r7 =3D #0x4ae6 } */ + asm volatile( + "{ r3 =3D %1 }\n\t" + ".word 0x97837fe6\n\t" + ".word 0x7845dcc7\n\t" + "{ %0 =3D r6 }\n\t" + : "=3Dr"(out) : "r"(&buf[1]) : "r3", "r6", "r7"); + return out; +} + +static int32_t dcbuf[8] __attribute__((aligned(32))); + +/* Slot-0-only op (dczeroa) packed last with three transfers. */ +static void slot0_restricted(int32_t *out) +{ + asm volatile( + "{ %0 =3D #0x11\n\t" + " %1 =3D #0x22\n\t" + " %2 =3D #0x33\n\t" + " dczeroa(%3) }\n\t" + : "=3Dr"(out[0]), "=3Dr"(out[1]), "=3Dr"(out[2]) + : "r"(dcbuf) : "memory"); +} + +int main() +{ + int32_t r[3]; + + check32(load_imm_pair(), 0x1234); + + dcbuf[0] =3D 0x5a5a5a5a; + slot0_restricted(r); + check32(r[0], 0x11); + check32(r[1], 0x22); + check32(r[2], 0x33); + check32(dcbuf[0], 0); /* dczeroa cleared the line */ + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index a2a0ffc69b2..80e56f7d055 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -51,6 +51,7 @@ HEX_TESTS +=3D scatter_gather HEX_TESTS +=3D hvx_misc HEX_TESTS +=3D hvx_histogram HEX_TESTS +=3D invalid-slots +HEX_TESTS +=3D valid-slots HEX_TESTS +=3D invalid-encoding HEX_TESTS +=3D multiple-writes HEX_TESTS +=3D unaligned_pc --=20 2.34.1 From nobody Mon Sep 28 01:14:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1786052268; cv=none; d=zohomail.com; s=zohoarc; b=YgLXAdeHPkJfyANv9TFmwp8/M7VjclZQ885q6xJiszm30j2I6Ami/DAQc1RNNXnvoqq8Rf7mUEvmlAPQv6k2+GUH4OzQ7ZLvhExiC/iRDnnfXTK2HwMvys8KSxGFMoIlZGIu2uND8I4AyV867IrPs4LDtX/wzuAc9QE2ATXXpCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786052268; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MgKDSvMkQWxq1eZm1scEXLKXMuEvnmA0HSurJZK7kDY=; b=ZmXzZoc2LuX23vy1Lmiz99zX/KcvHcBSUo24b01FFafv9/RQBop8ziBnjBrf2vRiVCY18U1gNkNAQpjloqBCcuWs4h2pbaYMONVPz6mYHQ9feAewKJVIurCxVdQ1QHPGAdPuYEycDjOLXRwDvCxMlfK18n6lhAvWTeGbdJkwFEU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786052268120335.971701375261; Thu, 6 Aug 2026 14:37:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ws5mB-00052C-5y; Thu, 06 Aug 2026 17:37:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ws5ls-00051D-Fr for qemu-devel@nongnu.org; Thu, 06 Aug 2026 17:37:01 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ws5lo-00005f-4K for qemu-devel@nongnu.org; Thu, 06 Aug 2026 17:36:58 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 676L8cRV3077830 for ; Thu, 6 Aug 2026 21:36:52 GMT Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fvy6h8wv6-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 06 Aug 2026 21:36:52 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-38dc085b0a7so3912876a91.2 for ; Thu, 06 Aug 2026 14:36:52 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1786052271193158500 The idef-parser emitters write the destination in place, so when a packet is short-circuited and get_result_gpr() returns hex_gpr[] itself, an instruction naming one register as both source and destination reads back a value it already overwrote. `Rd32=3Dcmpy(Rs32,Rt32):<<1:rnd:sat` with Rs =3D=3D Rd is an example. Give a source reg that aliases a destination its own copy of the register value. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/genptr.h | 1 + target/hexagon/genptr.c | 11 ++++++ tests/tcg/hexagon/read_write_overlap.c | 47 ++++++++++++++++++++++++++ target/hexagon/gen_tcg_funcs.py | 15 ++++++++ target/hexagon/hex_common.py | 12 +++++++ 5 files changed, 86 insertions(+) diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index 45ee038ca94..5d096774102 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -36,6 +36,7 @@ void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t sr= c, uint32_t slot); TCGv gen_read_reg(TCGv result, int num); TCGv gen_read_preg(TCGv pred, uint8_t num); TCGv get_result_gpr(DisasContext *ctx, int rnum); +TCGv gen_unalias_gpr_src(TCGv src, TCGv dst); TCGv get_result_pred(DisasContext *ctx, int pnum); void gen_pred_write(DisasContext *ctx, int pnum, TCGv val); void gen_set_usr_field(DisasContext *ctx, int field, TCGv val); diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 3f310377097..12813f48bf9 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -91,6 +91,17 @@ TCGv get_result_gpr(DisasContext *ctx, int rnum) } } =20 +TCGv gen_unalias_gpr_src(TCGv src, TCGv dst) +{ + if (src !=3D dst) { + return src; + } + + TCGv tmp =3D tcg_temp_new(); + tcg_gen_mov_tl(tmp, src); + return tmp; +} + static TCGv_i64 get_result_gpr_pair(DisasContext *ctx, int rnum) { TCGv_i64 result =3D tcg_temp_new_i64(); diff --git a/tests/tcg/hexagon/read_write_overlap.c b/tests/tcg/hexagon/rea= d_write_overlap.c index 95c54ccd63c..7eaf75f545a 100644 --- a/tests/tcg/hexagon/read_write_overlap.c +++ b/tests/tcg/hexagon/read_write_overlap.c @@ -115,12 +115,59 @@ static void test_swiz(void) check32(swiz(0x11223344), 0x44332211); } =20 +#define CMPY(NAME, ASM) \ +static inline uint32_t NAME##_rd_eq_rs(uint32_t x, uint32_t y) \ +{ \ + uint32_t res; \ + asm("r7 =3D %1\n\t" \ + ASM("r7", "%2") "\n\t" \ + "%0 =3D r7\n\t" \ + : "=3Dr"(res) : "r"(x), "r"(y) : "r7"); \ + return res; \ +} \ +static inline uint32_t NAME##_rd_eq_rt(uint32_t x, uint32_t y) \ +{ \ + uint32_t res; \ + asm("r7 =3D %2\n\t" \ + ASM("%1", "r7") "\n\t" \ + "%0 =3D r7\n\t" \ + : "=3Dr"(res) : "r"(x), "r"(y) : "r7"); \ + return res; \ +} + +#define CMPY_RND_SAT(RS, RT) "r7 =3D cmpy(" RS "," RT "):rnd:sat" +#define CMPY_S1_RND_SAT(RS, RT) "r7 =3D cmpy(" RS "," RT "):<<1:rnd:sat" +#define CMPYC_RND_SAT(RS, RT) "r7 =3D cmpy(" RS "," RT "*):rnd:sat" +#define CMPYC_S1_RND_SAT(RS, RT) "r7 =3D cmpy(" RS "," RT "*):<<1:rnd:sat" + +CMPY(cmpyrs_s0, CMPY_RND_SAT) +CMPY(cmpyrs_s1, CMPY_S1_RND_SAT) +CMPY(cmpyrsc_s0, CMPYC_RND_SAT) +CMPY(cmpyrsc_s1, CMPYC_S1_RND_SAT) + +static void test_cmpy(void) +{ + check32(cmpyrs_s0_rd_eq_rs(0x32195ce2, 0xef862430), 0x011b105b); + check32(cmpyrs_s0_rd_eq_rt(0x32195ce2, 0xef862430), 0x011b105b); + check32(cmpyrs_s1_rd_eq_rs(0x32195ce2, 0xef862430), 0x023520b5); + check32(cmpyrs_s1_rd_eq_rt(0x32195ce2, 0xef862430), 0x023520b5); + check32(cmpyrsc_s0_rd_eq_rs(0x32195ce2, 0xef862430), 0x0d0f09e8); + check32(cmpyrsc_s0_rd_eq_rt(0x32195ce2, 0xef862430), 0x0d0f09e8); + check32(cmpyrsc_s1_rd_eq_rs(0x32195ce2, 0xef862430), 0x1a1f13d0); + check32(cmpyrsc_s1_rd_eq_rt(0x32195ce2, 0xef862430), 0x1a1f13d0); + + /* Both halves saturate */ + check32(cmpyrs_s1_rd_eq_rs(0x80008000, 0x80008000), 0x7fff0000); + check32(cmpyrsc_s1_rd_eq_rs(0x7fff8001, 0x80017fff), 0x00008000); +} + int main() { test_insert(); test_insert_rp(); test_asr_r_svw_trun(); test_swiz(); + test_cmpy(); =20 puts(err ? "FAIL" : "PASS"); return err ? EXIT_FAILURE : EXIT_SUCCESS; diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 6d5d99cee3a..43e68077495 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -75,6 +75,21 @@ def gen_tcg_func(f, tag, regs, imms): f.write(f" int {hex_common.imm_name(immlett)} =3D insn->immed[{= i}];\n") =20 if hex_common.is_idef_parser_enabled(tag): + gpr_operands =3D [ + hex_common.get_register(tag, regtype, regid) + for regtype, regid in regs + if hex_common.get_register(tag, regtype, regid).may_alias_gpr() + ] + dests =3D [reg for reg in gpr_operands if reg.is_written()] + for reg in gpr_operands: + if reg.is_written() or not reg.is_read(): + continue + src =3D reg.reg_tcg() + for dest in dests: + f.write(hex_common.code_fmt(f"""\ + {src} =3D gen_unalias_gpr_src({src}, {dest.reg_tcg()}); + """)) + declared =3D [] ## Handle registers for regtype, regid in regs: diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index d91a653c3d4..09a025ba13e 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -388,6 +388,8 @@ def decl_reg_num(self, f, regno): """)) def idef_arg(self, declared): declared.append(self.reg_tcg()) + def may_alias_gpr(self): + return False def helper_arg(self): return HelperArg( self.helper_proto_type(), @@ -495,6 +497,8 @@ def is_new(self): return False =20 class GprDest(Register, Single, Dest): + def may_alias_gpr(self): + return True def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ @@ -510,6 +514,8 @@ def analyze_write(self, f, tag, regno): """)) =20 class GprSource(Register, Single, OldSource): + def may_alias_gpr(self): + return True def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ @@ -531,6 +537,8 @@ def analyze_read(self, f, regno): """)) =20 class GprReadWrite(Register, Single, ReadWrite): + def may_alias_gpr(self): + return True def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ @@ -557,6 +565,8 @@ def analyze_write(self, f, tag, regno): """)) =20 class ControlDest(Register, Single, Dest): + def may_alias_gpr(self): + return True def decl_reg_num(self, f, regno): f.write(code_fmt(f"""\ const int {self.reg_num} =3D insn->regno[{regno}] + HEX_REG_S= A0; @@ -593,6 +603,8 @@ def analyze_read(self, f, regno): """)) =20 class ModifierSource(Register, Single, OldSource): + def may_alias_gpr(self): + return True def decl_reg_num(self, f, regno): f.write(code_fmt(f"""\ const int {self.reg_num} =3D insn->regno[{regno}] + HEX_REG_M0; --=20 2.34.1