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Thu, 06 Aug 2026 10:27:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 1/6] target/arm: Add FGWTE3_EL3 Date: Thu, 6 Aug 2026 10:27:04 -0700 Message-ID: <20260806172709.333300-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806172709.333300-1-richard.henderson@linaro.org> References: <20260806172709.333300-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786037303517158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpu-features.h | 5 +++++ target/arm/cpu.h | 2 +- target/arm/helper.c | 20 ++++++++++++++++++++ 4 files changed, 27 insertions(+), 1 deletion(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 391c0e322b..34592679e4 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -385,6 +385,7 @@ typedef enum CPAccessResult { /* Indexes into fgt_write[] */ #define FGTREG_HFGWTR 0 #define FGTREG_HDFGWTR 1 +#define FGTREG_FGWTE3 2 /* Indexes into fgt_exec[] */ #define FGTREG_HFGITR 0 =20 diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index fb5ed25ad0..75f0fc4169 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1467,6 +1467,11 @@ static inline bool isar_feature_aa64_asid2(const ARM= ISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) !=3D 0; } =20 +static inline bool isar_feature_aa64_fgwte3(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR4, FGWTE3) !=3D 0; +} + /* * Note the E2H0 ID fields is signed, increasingly negative as more * isn't implemented. diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c0492c8dfb..a471b87aa5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -553,7 +553,7 @@ typedef struct CPUArchState { * FEAT_FGT2 will add more elements to these arrays. */ uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ - uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ + uint64_t fgt_write[3]; /* HFGWTR, HDFGWTR, FGWTE3 */ uint64_t fgt_exec[1]; /* HFGITR */ =20 /* RME registers */ diff --git a/target/arm/helper.c b/target/arm/helper.c index af45234ad2..853daf2e39 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6331,6 +6331,22 @@ static const ARMCPRegInfo fpmr_reginfo[] =3D { } }; =20 +static void fgwte3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* All bits are W1S and can only be cleared by cpu reset. */ + env->cp15.fgt_write[FGTREG_FGWTE3] |=3D value; +} + +static const ARMCPRegInfo fgwte3_reginfo[] =3D { + { .name =3D "FGWTE3_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 5, + .access =3D PL3_RW, .resetvalue =3D 0, + .writefn =3D fgwte3_write, .raw_writefn =3D raw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_write[FGTREG_FGWTE3]) + }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7642,6 +7658,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, ccsidr2_reginfo); } =20 + if (cpu_isar_feature(aa64_fgwte3, cpu)) { + define_arm_cp_regs(cpu, fgwte3_reginfo); + } + define_pm_cpregs(cpu); define_gcs_cpregs(cpu); } --=20 2.43.0 From nobody Wed Aug 26 20:44:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786037297; cv=none; d=zohomail.com; s=zohoarc; b=TJdEYT93Nz75wdUxsehZdupOv5eLkb0MT0sGFeFApelV8k+z+VmxD1cPMkYkI9paijms7GSc5ivKFFkZtyXfsvMDy9uRveCuMa5DKagQI1ytXCiCXrpImIeRB+J8Nt1Brgp3gQrjYhOaqyjevZ5sjk//7eMtm5bu5Wem7cyH+2o= ARC-Message-Signature: i=1; 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Thu, 06 Aug 2026 10:27:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 2/6] target/arm: Add FGWTE3_EL3 bit definitions Date: Thu, 6 Aug 2026 10:27:05 -0700 Message-ID: <20260806172709.333300-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806172709.333300-1-richard.henderson@linaro.org> References: <20260806172709.333300-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786037299388158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 34592679e4..2c9927b1d9 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -689,6 +689,30 @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) =20 +FIELD(FGWTE3_EL3, ACTLR_EL3, 0, 1) +FIELD(FGWTE3_EL3, AFSR0_EL3, 1, 1) +FIELD(FGWTE3_EL3, AFSR1_EL3, 2, 1) +FIELD(FGWTE3_EL3, AMAIR_EL3, 3, 1) +FIELD(FGWTE3_EL3, AMAIR2_EL3, 4, 1) +FIELD(FGWTE3_EL3, GCSCR_EL3, 5, 1) +FIELD(FGWTE3_EL3, GCSPR_EL3, 6, 1) +FIELD(FGWTE3_EL3, GPCCR_EL3, 7, 1) +FIELD(FGWTE3_EL3, GPTBR_EL3, 8, 1) +FIELD(FGWTE3_EL3, MAIR_EL3, 9, 1) +FIELD(FGWTE3_EL3, MAIR2_EL3, 10, 1) +FIELD(FGWTE3_EL3, MDCR_EL3, 11, 1) +FIELD(FGWTE3_EL3, MECID_RL_A_EL3, 12, 1) +FIELD(FGWTE3_EL3, MPAM3_EL3, 13, 1) +FIELD(FGWTE3_EL3, PIR_EL3, 14, 1) +FIELD(FGWTE3_EL3, SCTLR_EL3, 15, 1) +FIELD(FGWTE3_EL3, SCTLR2_EL3, 16, 1) +FIELD(FGWTE3_EL3, SPMROOTCR_EL3, 17, 1) +FIELD(FGWTE3_EL3, TCR_EL3, 18, 1) +FIELD(FGWTE3_EL3, TPIDR_EL3, 19, 1) +FIELD(FGWTE3_EL3, TTBR0_EL3, 20, 1) +FIELD(FGWTE3_EL3, VBAR_EL3, 21, 1) +FIELD(FGWTE3_EL3, GPCBW_EL3, 22, 1) + FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */ /* Which fine-grained trap bit register to check, if any */ FIELD(FGT, TYPE, 10, 3) --=20 2.43.0 From nobody Wed Aug 26 20:44:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 06 Aug 2026 10:27:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 3/6] target/arm: Add FGWTE3 FGT bit definitions Date: Thu, 6 Aug 2026 10:27:06 -0700 Message-ID: <20260806172709.333300-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806172709.333300-1-richard.henderson@linaro.org> References: <20260806172709.333300-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786037323702158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 2c9927b1d9..9f2532fe66 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -728,6 +728,9 @@ FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uin= t64_t */ #define DO_BIT(REG, BITNAME) \ FGT_##BITNAME =3D FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT =20 +#define DO_EL3_BIT(REG, BITNAME) \ + FGT_##BITNAME =3D FGT_##REG | R_##REG##_EL3_##BITNAME##_SHIFT + /* Some bits have reversed sense, so 0 means trap and 1 means not */ #define DO_REV_BIT(REG, BITNAME) \ FGT_##BITNAME =3D FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT @@ -787,6 +790,7 @@ typedef enum FGTBit { FGT_HDFGRTR =3D FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), FGT_HDFGWTR =3D FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), FGT_HFGITR =3D FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), + FGT_FGWTE3 =3D FGT_W | (FGTREG_FGWTE3 << R_FGT_IDX_SHIFT), =20 /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ DO_BIT(HFGRTR, AFSR0_EL1), @@ -919,10 +923,37 @@ typedef enum FGTBit { DO_REV_BIT(HFGITR, NGCSPUSHM_EL1), DO_REV_BIT(HFGITR, NGCSEPP), DO_BIT(HFGITR, ATS1E1A), + + /* Trap bits in FGWTE3_EL3, starting from bit 0 */ + DO_EL3_BIT(FGWTE3, ACTLR_EL3), + DO_EL3_BIT(FGWTE3, AFSR0_EL3), + DO_EL3_BIT(FGWTE3, AFSR1_EL3), + DO_EL3_BIT(FGWTE3, AMAIR_EL3), + DO_EL3_BIT(FGWTE3, AMAIR2_EL3), + DO_EL3_BIT(FGWTE3, GCSCR_EL3), + DO_EL3_BIT(FGWTE3, GCSPR_EL3), + DO_EL3_BIT(FGWTE3, GPCCR_EL3), + DO_EL3_BIT(FGWTE3, GPTBR_EL3), + DO_EL3_BIT(FGWTE3, MAIR_EL3), + DO_EL3_BIT(FGWTE3, MAIR2_EL3), + DO_EL3_BIT(FGWTE3, MDCR_EL3), + DO_EL3_BIT(FGWTE3, MECID_RL_A_EL3), + DO_EL3_BIT(FGWTE3, MPAM3_EL3), + DO_EL3_BIT(FGWTE3, PIR_EL3), + DO_EL3_BIT(FGWTE3, SCTLR_EL3), + DO_EL3_BIT(FGWTE3, SCTLR2_EL3), + DO_EL3_BIT(FGWTE3, SPMROOTCR_EL3), + DO_EL3_BIT(FGWTE3, TCR_EL3), + DO_EL3_BIT(FGWTE3, TPIDR_EL3), + DO_EL3_BIT(FGWTE3, TTBR0_EL3), + DO_EL3_BIT(FGWTE3, VBAR_EL3), + DO_EL3_BIT(FGWTE3, GPCBW_EL3), } FGTBit; =20 #undef DO_BIT +#undef DO_EL3_BIT #undef DO_REV_BIT +#undef DO_TLBINXS_BIT =20 typedef struct ARMCPRegInfo ARMCPRegInfo; =20 --=20 2.43.0 From nobody Wed Aug 26 20:44:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786037328; cv=none; d=zohomail.com; s=zohoarc; b=OpS+gmpHbnkdIEtDnY1bJSs4YNtmfrnjrjd4CZWyum+o2WeAHOWqut3YBH9cWpZuC1NPTkxOjrhJZw3PQcHrJ1I7Kq5SGqkpdyl2BtweUPhQUStFr4Q33wSyXsJIdBQVuwXDm4gJUmcEDTPLRkmfYoVhbZiIBsEeK3Fl+TBva0A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786037328; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 06 Aug 2026 10:27:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 4/6] target/arm: Implement FGWTE3 traps Date: Thu, 6 Aug 2026 10:27:07 -0700 Message-ID: <20260806172709.333300-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806172709.333300-1-richard.henderson@linaro.org> References: <20260806172709.333300-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786037329717158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/op_helper.c | 40 +++++++++++++++++++++++----------- target/arm/tcg/translate-a64.c | 16 +++++++++++++- 2 files changed, 42 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index c4433be2ed..73cae9b9ad 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -1066,13 +1066,15 @@ const void *HELPER(access_check_cp_reg)(CPUARMState= *env, uint32_t key, * Fine-grained traps also are lower priority than undef-to-EL1, * higher priority than trap-to-EL3, and we don't care about priority * order with other EL2 traps because the syndrome value is the same. + * + * FGWTE3 traps are exclusively traps to EL3 on registers that are + * only accessible to EL3, so there's no possibility of a trap to EL2. + * So we can handle these checks here too. */ - if (arm_fgt_active(env, arm_current_el(env))) { + if (ri->fgt) { uint64_t trapword =3D 0; unsigned int idx =3D FIELD_EX32(ri->fgt, FGT, IDX); unsigned int bitpos =3D FIELD_EX32(ri->fgt, FGT, BITPOS); - bool rev =3D FIELD_EX32(ri->fgt, FGT, REV); - bool nxs =3D FIELD_EX32(ri->fgt, FGT, NXS); bool trapbit; =20 if (ri->fgt & FGT_EXEC) { @@ -1085,19 +1087,31 @@ const void *HELPER(access_check_cp_reg)(CPUARMState= *env, uint32_t key, assert(idx < ARRAY_SIZE(env->cp15.fgt_write)); trapword =3D env->cp15.fgt_write[idx]; } + trapbit =3D extract64(trapword, bitpos, 1); =20 - if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) { + if ((ri->access & ~PL3_RW) =3D=3D 0) { /* - * If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for - * TLBI maintenance insns does *not* apply to the nXS variant. + * EL3 cpreg -- must be FGWTE3, and FGWTE3_EL3 can only be + * set from AArch64, and if the feature is enabled. */ - trapbit =3D 0; - } else { - trapbit =3D extract64(trapword, bitpos, 1); - } - if (trapbit !=3D rev) { - res =3D CP_ACCESS_TRAP_EL2; - goto fail; + if (trapbit) { + res =3D CP_ACCESS_TRAP_EL3; + goto fail; + } + } else if (arm_fgt_active(env, arm_current_el(env))) { + bool nxs =3D FIELD_EX32(ri->fgt, FGT, NXS); + bool rev =3D FIELD_EX32(ri->fgt, FGT, REV); + if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) { + /* + * If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for + * TLBI maintenance insns does *not* apply to the nXS vari= ant. + */ + trapbit =3D 0; + } + if (trapbit !=3D rev) { + res =3D CP_ACCESS_TRAP_EL2; + goto fail; + } } } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1780490065..0931c92307 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2886,6 +2886,7 @@ static void handle_sys(DisasContext *s, bool isread, { uint32_t key =3D ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); + bool need_helper =3D false; bool need_exit_tb =3D false; bool nv_trap_to_el2 =3D false; bool nv_redirect_reg =3D false; @@ -2999,7 +3000,20 @@ static void handle_sys(DisasContext *s, bool isread, ri =3D redirect_cpreg(s, key, isread); } =20 - if (ri->accessfn || (ri->fgt && s->fgt_active)) { + if (ri->accessfn) { + need_helper =3D true; + } else if (ri->fgt) { + /* + * EL3-only access means this must be an FGWTE3 trap (which are + * always active); otherwise it's an FGT trap to EL2. + */ + if ((ri->access & ~PL3_RW) =3D=3D 0) { + need_helper =3D dc_isar_feature(aa64_fgwte3, s); + } else { + need_helper =3D s->fgt_active; + } + } + if (need_helper) { /* Emit code to perform further access permissions checks at * runtime; this may result in an exception. */ --=20 2.43.0 From nobody Wed Aug 26 20:44:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786037307; cv=none; d=zohomail.com; s=zohoarc; b=BDd8lbyrQwXaogfY/MezV+xN+YUBLyM/BrVUurOz2knIdztJzwr1h7ynPWxszeJv4xHTMknkK8XGcmPk6OPMuZ3Q+JpMoJ7ergLc8zWGt2HPhDsNaxH2y+zrqRRMiyW+qVVeUXTeQeQ28hPYFdLT4RjRH8pWSQFrJccmWlKONGI= ARC-Message-Signature: i=1; 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Thu, 06 Aug 2026 10:27:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 5/6] target/arm: Set fgt in cpregs for FGWTE3 Date: Thu, 6 Aug 2026 10:27:08 -0700 Message-ID: <20260806172709.333300-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806172709.333300-1-richard.henderson@linaro.org> References: <20260806172709.333300-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786037313611158501 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs-gcs.c | 5 +++-- target/arm/helper.c | 49 ++++++++++++++++++++++------------------- 2 files changed, 29 insertions(+), 25 deletions(-) diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index e31827342d..9c9ae9cd71 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -97,7 +97,7 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[2]) }, { .name =3D "GCSCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_GCSCR_EL3, .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[3]) }, =20 { .name =3D "GCSPR_EL0", .state =3D ARM_CP_STATE_AA64, @@ -119,7 +119,8 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, { .name =3D "GCSPR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, - .access =3D PL3_RW, .writefn =3D gcspr_write, + .access =3D PL3_RW, .fgt =3D FGT_GCSPR_EL3, + .writefn =3D gcspr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, =20 { .name =3D "GCSPUSHM", .state =3D ARM_CP_STATE_AA64, diff --git a/target/arm/helper.c b/target/arm/helper.c index 853daf2e39..c88af981e2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1013,7 +1013,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .resetvalue =3D 0 }, { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[3]), + .access =3D PL3_RW, .fgt =3D FGT_MAIR_EL3, + .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[3]), .resetvalue =3D 0 }, /* * For non-long-descriptor page tables these are PRRR and NMRR; @@ -3685,7 +3686,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .type =3D ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, .resetvalue =3D 0, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_MDCR_EL3, .writefn =3D mdcr_el3_write, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el3) }, { .name =3D "SDCR", .type =3D ARM_CP_ALIAS | ARM_CP_IO, @@ -4435,11 +4436,11 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.mvbar) }, { .name =3D "TTBR0_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .resetvalue =3D 0, + .access =3D PL3_RW, .fgt =3D FGT_TTBR0_EL3, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[3]) }, { .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_TCR_EL3, /* no .writefn needed as this can't cause an ASID change */ .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[3]) }, @@ -4461,7 +4462,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_MON]) }, { .name =3D "VBAR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .writefn =3D vbar_write, + .access =3D PL3_RW, .fgt =3D FGT_VBAR_EL3, .writefn =3D vbar_write, .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue =3D 0 }, { .name =3D "CPTR_EL3", .state =3D ARM_CP_STATE_AA64, @@ -4470,20 +4471,20 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[3]) }, { .name =3D "TPIDR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL3_RW, .resetvalue =3D 0, + .access =3D PL3_RW, .fgt =3D FGT_TPIDR_EL3, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[3]) }, { .name =3D "AMAIR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL3_RW, .fgt =3D FGT_AMAIR_EL3, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR0_EL3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL3_RW, .fgt =3D FGT_AFSR0_EL3, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL3_RW, .fgt =3D FGT_AFSR1_EL3, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 #ifndef CONFIG_USER_ONLY @@ -5051,15 +5052,17 @@ static void gpcbw_write(CPUARMState *env, const ARM= CPRegInfo *ri, static const ARMCPRegInfo rme_reginfo[] =3D { { .name =3D "GPCCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 6, - .access =3D PL3_RW, .writefn =3D gpccr_write, .resetfn =3D gpccr_res= et, + .access =3D PL3_RW, .fgt =3D FGT_GPCCR_EL3, + .writefn =3D gpccr_write, .resetfn =3D gpccr_reset, .fieldoffset =3D offsetof(CPUARMState, cp15.gpccr_el3) }, { .name =3D "GPCBW_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 5, - .access =3D PL3_RW, .writefn =3D gpcbw_write, + .access =3D PL3_RW, .fgt =3D FGT_GPCBW_EL3, .writefn =3D gpcbw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.gpcbw_el3) }, { .name =3D "GPTBR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 4, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.gptb= r_el3) }, + .access =3D PL3_RW, .fgt =3D FGT_GPTBR_EL3, + .fieldoffset =3D offsetof(CPUARMState, cp15.gptbr_el3) }, { .name =3D "MFAR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 5, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mfar= _el3) }, @@ -5169,7 +5172,7 @@ static const ARMCPRegInfo mec_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a1_el2) }, { .name =3D "MECID_RL_A_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 1, .crn =3D 10, .crm =3D 10, - .access =3D PL3_RW, .accessfn =3D mecid_access, + .access =3D PL3_RW, .accessfn =3D mecid_access, .fgt =3D FGT_MECID_R= L_A_EL3, .writefn =3D mecid_write, .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_rl_a_el3) }, { .name =3D "VMECID_P_EL2", .state =3D ARM_CP_STATE_AA64, @@ -6119,7 +6122,7 @@ static const ARMCPRegInfo sctlr2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[2]) }, { .name =3D "SCTLR2_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, - .access =3D PL3_RW, .writefn =3D sctlr2_el3_write, + .access =3D PL3_RW, .fgt =3D FGT_SCTLR2_EL3, .writefn =3D sctlr2_el3= _write, .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, }; =20 @@ -6245,7 +6248,7 @@ static const ARMCPRegInfo s1pie_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[2]) }, { .name =3D "PIR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 10, .crm =3D 2, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_PIR_EL3, .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[3]) }, { .name =3D "PIRE0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 2, .crn =3D 10, .crm =3D 2, @@ -6303,7 +6306,7 @@ static const ARMCPRegInfo aie_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.mair2_el[2]) }, { .name =3D "MAIR2_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_MAIR2_EL3, .fieldoffset =3D offsetof(CPUARMState, cp15.mair2_el[3]) }, =20 { .name =3D "AMAIR2_EL1", .state =3D ARM_CP_STATE_AA64, @@ -6319,7 +6322,7 @@ static const ARMCPRegInfo aie_reginfo[] =3D { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AMAIR2_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_AMAIR2_EL3, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 @@ -7047,7 +7050,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D arm_feature(env, ARM_FEATURE_AARCH64) }, { .name =3D "SCTLR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL3_RW, + .access =3D PL3_RW, .fgt =3D FGT_SCTLR_EL3, .raw_writefn =3D raw_write, .writefn =3D sctlr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[3]), .resetvalue =3D cpu->reset_sctlr }, @@ -7422,8 +7425,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ACTLR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL3_RW, .fgt =3D FGT_ACTLR_EL3, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; define_arm_cp_regs(cpu, auxcr_reginfo); if (cpu_isar_feature(aa32_ac2, cpu)) { --=20 2.43.0 From nobody Wed Aug 26 20:44:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 06 Aug 2026 10:27:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 6/6] target/arm: Enable FEAT_FGWTE3 for -cpu max Date: Thu, 6 Aug 2026 10:27:09 -0700 Message-ID: <20260806172709.333300-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806172709.333300-1-richard.henderson@linaro.org> References: <20260806172709.333300-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786037273758158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/cpu64.c | 1 + docs/system/arm/emulation.rst | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 9cd2200823..4b9d01420a 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1462,6 +1462,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj) =20 t =3D GET_IDREG(isar, ID_AA64MMFR4); t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR4, FGWTE3, 1); /* v9.4: FEAT_FGWTE3 */ SET_IDREG(isar, ID_AA64MMFR4, t); =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 3400de6b76..392db5ccf9 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -78,6 +78,7 @@ the following architecture extensions: - FEAT_FAMINMAX (Floating-point maximum and minimum absolute value instruc= tions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FGT (Fine-Grained Traps) +- FEAT_FGWTE3 (Fine-Grained Write Trap EL3) - FEAT_FHM (Floating-point half-precision multiplication instructions) - FEAT_FP (Floating Point extensions) - FEAT_FP16 (Half-precision floating-point data processing) --=20 2.43.0