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[174.21.93.59]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d0aa4ec8c7sm34280735ad.80.2026.08.06.09.39.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 09:39:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1786034381; x=1786639181; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=JQVXlhf8twHyD4IKFKJt8HG/wz/ubfI6lRd4dbnWJZY=; b=aT4xbk8ellZmCHbPnsb7esxbNihke+wo/weCirO84tcEwp7xK0qV7KFj4nl7ds4oA3 QX3MQwTR5jayKh7AKHtQZ8e8hPDXVmS7HiOxo4JEOY+xe2cJuRIB4DLOs+4dgmXtFTX2 zfxedPzxtEfJFxfY1rlGOFXskTl2LeXS8govIllDC4U961RldoeAgCRLuJs8bgSCbyCL IUX/zZivpR+VrK5O1bZTlXm8n+hqVNWA/uHcR/AAEpxuVMsSHIZfE3FE4emTGTHaOfxd 5vLi4U51RdTb4X2xtJBqIFs+e1sh8nA5sVv0DARKt8zFElrtBsP4CJoLVGuJLFd067wh +cgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786034381; x=1786639181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=JQVXlhf8twHyD4IKFKJt8HG/wz/ubfI6lRd4dbnWJZY=; b=KIMMEqgwfPdhvU0lmgTD+oYSBOfm0zoOyRpRKyQ0RrwHP8JmtpbVCBP6VAQy351isa upT38D754fahck/tiz+IYCnCfuPaIlbb2K78101mIdqOS2xiul9nDDjg8Y4jArdw70ta HA9x9A4Ek2FvbtYBLxAjnAUZuvFZ8iGxAy3YmT6nSErfiXaA4SPe3VJTVIaLwnI/UtTo zskGgwg9+nRyzloxVLZXFtRJyWHydH9bKc6vIghBT2nH9MhqrUqKnrEEMxKzbLz1F1/S OE9zfO0hvvId3Dq6Rpc/P5hhRARVzhydziaAeNmiFxpCJqDTylqQfEoPG6Umf+pUCI0y tYuw== X-Gm-Message-State: AOJu0YxPtn4TZbrZ+fpfgV70HBPB/0RC9rhpqMVs+rgyI/mYZRUKGWve tpmj7wwM3NwT1ozkwabMUKhn7IVZQkH6pVSLtUxetomsUNl4VsLeo0MiCVKZJMJusV10nvN+An/ yXZRZ X-Gm-Gg: AR+sD10AxDZoIDG+a5j7lLH2Zco/ipwqpg9NBbNnIjbv95ZsZAoEtqdR9aoka1+UOUy WNKgpLgRUtQNLkUtUyoxRGoWIxXVlgv3VCzbC8zMKjCdMO7/ime3ojhgZQT2sQa//UBwFa54677 PhjyG9sZ8mNAE+GQUN+2hse+pQQuFC8s2zOfdHSw3+k+xgk84Sea9RsH0WVLc0E3nwvJplYKA1K /HaHO3zjjmAgTSMyasKIa+sNgPO/5Rxrqq3wkCtglF1BDorZ/HAqImrVB7220mnBQXyy95Z0o/D 8NdINFa4D9XqrxSvVNU24oy0v0+b1y+E9SEZPcPqyiwamHAiN1qdBZJE7Ll4qFIZcMYCQtVCgZ6 Mriums4unNlQ3qGx3SK3DkUqFyCT82uA1FQIuSqX0BdfeiLzBcEJdAyEVeQTxfH8XTh9uIcz7Ja aMoc8pvqrVU37qtVnNLVqQJyd8Tr99LMUCMRnOIKKA9mjgocxJ96YQK8X/vnb3VM/N89lJOSaAQ 9+jV98gusuZ9Xa+0js54YG+3yOdhiLK X-Received: by 2002:a17:902:f54d:b0:2ca:ecf6:9104 with SMTP id d9443c01a7336-2d0ca711c8emr175409245ad.4.1786034381514; Thu, 06 Aug 2026 09:39:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 1/7] target/arm: Tidy cpu_max_initfn Date: Thu, 6 Aug 2026 09:39:33 -0700 Message-ID: <20260806163939.328201-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806163939.328201-1-richard.henderson@linaro.org> References: <20260806163939.328201-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786034475770158500 Content-Type: text/plain; charset="utf-8" Once we have eliminated hwaccel_enabled, only tcg and qtest remain. We don't really need to test for it anymore, but convert the if to and assert. Remove an assert on aarch64_enabled that is directly protected by a preceding if. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu-max.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 88b7c04633..089f514bd8 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -203,9 +203,9 @@ static void cpu_max_initfn(Object *obj) return; } =20 - if (tcg_enabled() || qtest_enabled()) { - aarch64_aa32_a57_init(obj, !aarch64_enabled); - } + assert(tcg_enabled() || qtest_enabled()); + + aarch64_aa32_a57_init(obj, !aarch64_enabled); =20 if (!aarch64_enabled) { aa32_max_features(cpu); @@ -218,8 +218,7 @@ static void cpu_max_initfn(Object *obj) */ cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); #endif - } else if (tcg_enabled()) { - assert(aarch64_enabled); + } else { /* * '-cpu max' for TCG: we currently do this as * "A57 with extra things" --=20 2.43.0 From nobody Mon Sep 28 01:15:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786034438; cv=none; d=zohomail.com; s=zohoarc; b=NfFjgyJDirXTGBcuxLWMvgO3j32WvslPDfHNn2PZ8DGVXIlnEwWitn0RgZI6CgxPDeRQX+9QRjGvsz/LSKhnzkXngHjPGbWZHeTbM2dffO6IhTtp+egdhgLV3CZgWq49ma6WXBBMZhOpK1nZGD3I+1bmv+XraIS7r7j5ZjA1z5M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786034438; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LaQaHfv4P6MPUegXLFMZw8cHU7pJYmdlkVEOwBnBYgg=; b=lBDRosUAH1vJByR3FJBIor6HaYx3mAqz2pLDBMM0YtAwiUovQNoTGm1Sfu39Eb197ATDUjOrKqNs9yKB4dMh5LmCwiANMCmkT8hs3UTkp/vNU7/MX003qa2HsHGZbR1ej9hYBlqZFpFFvD+v92PGaSBB5rvPg74tSI6/4J53pCk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786034438657558.3836530839899; Thu, 6 Aug 2026 09:40:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ws18H-0006m7-5b; Thu, 06 Aug 2026 12:39:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ws18E-0006kC-2T for qemu-devel@nongnu.org; Thu, 06 Aug 2026 12:39:46 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ws18B-0000Ho-Qz for qemu-devel@nongnu.org; Thu, 06 Aug 2026 12:39:45 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-2cad8076b01so30031265ad.2 for ; Thu, 06 Aug 2026 09:39:43 -0700 (PDT) Received: from stoup.. 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[174.21.93.59]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d0aa4ec8c7sm34280735ad.80.2026.08.06.09.39.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 09:39:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1786034382; x=1786639182; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=LaQaHfv4P6MPUegXLFMZw8cHU7pJYmdlkVEOwBnBYgg=; b=j2jB4lBlGpdWd9TH9GJtUlesZiKkoUfQAH7YGpX2onvpvFJfRs1OqC9/DIJVZcPZKt Ifiy7Cc7m1qN19CkC99a1JWY2fEvfWKabirZKLezKALs2LYblimeYMAwVrXaiopF97ON fDAiAAWcZRl3NImXnilxh+In2Pvtwq/tgJ9p3CeIOICFwjHs52GUhMw4WTrCISAoX4fY uCnIDjBW5KDpb/Q9DsKDONjiq5kMy/BswEmxWmVthu+b9Ay1LLtIYVUjnIfayResxHon 6PSYAYjlocjxD1iZB4z9I5+T2EvS6i07EWe5SWe+VlpZinRX804L1gU66oLY26g8TlSS FPrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786034382; x=1786639182; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=LaQaHfv4P6MPUegXLFMZw8cHU7pJYmdlkVEOwBnBYgg=; b=e0QFttPI3O1dOrvBoGvyrU9UXcgbpfdKPDE++9kvT8Q3D3De5H7ViCLrUHQZRTZaku DylPW2bqLQT8PHjQfyTdYMERqUScpIaDpfQbajlUVJIa/GySKfmzf+W8nFz25ufN3/XH AWRXOyymultiAaL3wAoNT1yAaAErGQY5P+5ZQYeOM54L6JfTtC8R2ZAZXSH6dqmzt83N 2p5Gsd6lu1G+sqvUtQEa7HA64rjcXoTzc1llYFkxAHwmmWqDJi3fjKwOhibECfCMkyF3 SNWvs3vbskiWZPi6WTvyHhyGRfvWvx9dVzzmIG7XxOYBR6xnRIx0VjzT9gLxNYaNP6wz Jb4g== X-Gm-Message-State: AOJu0YwZc8TFfzDtztECI/B16+Ypx7YebPXIUUZwXrTUaZVoSzHkS6WJ U8cJJ6Bx+SEhUTBuvLEfAMbaFxA5CPkxWPPrGMXjbtsJ4eyrkWaFbCMYR2meE5qjOnyyGWoNJ7M gGpE8 X-Gm-Gg: AR+sD10jcxIHNSiOrYMaCyNMJfXUBn6Dh/13WdhjCmiXDXcUlw4xD67mJIK4NcQmN2r 7anx9JmElgLgV3g+BsqFpGr1Yh9l7zv1FF2/rCgRO5qK25BLv+Pa3nhFLle4iFiN1mDR8ovYWGo NqrU4oN2IwIMh4Y+0njPpUs4JWEnxy38qXUMZP44K/ExhVdmFqIAACuVcmvUMcJLLRknHx+PpIO VKgBEngW250S8ckO+0ovZaKHgIUH6MisSHgDHpYLM0HN0LlBGzVR1ftzqNqfCtbhaaWOYCqqKa6 8EarcpUSzT/f2Dud98p1ncEZlQOEfHRhN7T9gBXpRKfPPO/HmVaGpHQVoe2TrANxzZWBupia5t4 DQ9tXUWKQlE5SJPc/yF15eUgzWUiLDSTqODTj9Z0FgVN3ncwMGbwJJGUu8G6M5O69Ub5YRKoNOI xsbJyxiTzXDPC8xrxToCUxXYBHgmptqJkMOT73D31ZOHFVHmLn53I2jPzHNzPwRp4cwitmXfE/g zKIKEW8xCtRnKfD+yR6 X-Received: by 2002:a17:902:fdad:b0:2bf:9760:b94d with SMTP id d9443c01a7336-2d0ca7fd072mr206644015ad.15.1786034382419; Thu, 06 Aug 2026 09:39:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 2/7] target/arm: Pass ARMCPU to aarch64_aa32_a57_init Date: Thu, 6 Aug 2026 09:39:34 -0700 Message-ID: <20260806163939.328201-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806163939.328201-1-richard.henderson@linaro.org> References: <20260806163939.328201-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786034439839158500 Content-Type: text/plain; charset="utf-8" There's no reason to pass Object when ARMCPU is more appropriate. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 2 +- target/arm/cpu-max.c | 5 ++--- target/arm/cpu64.c | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4026f67579..9c9196475b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1813,7 +1813,7 @@ void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); -void aarch64_aa32_a57_init(Object *obj, bool aa32_only); +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only); void aarch64_host_initfn(Object *obj); =20 /* Return true if the gdbstub is presenting an AArch64 CPU */ diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index 089f514bd8..d7f2500353 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -16,9 +16,8 @@ #include "target/arm/internals.h" #include "target/arm/cpregs.h" =20 -void aarch64_aa32_a57_init(Object *obj, bool aa32_only) +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only) { - ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; const bool aarch64_enabled =3D !aa32_only; =20 @@ -205,7 +204,7 @@ static void cpu_max_initfn(Object *obj) =20 assert(tcg_enabled() || qtest_enabled()); =20 - aarch64_aa32_a57_init(obj, !aarch64_enabled); + aarch64_aa32_a57_init(cpu, !aarch64_enabled); =20 if (!aarch64_enabled) { aa32_max_features(cpu); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2816735577..e3ee0253a0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -688,7 +688,7 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **err= p) =20 static void aarch64_a57_initfn(Object *obj) { - aarch64_aa32_a57_init(obj, false); + aarch64_aa32_a57_init(ARM_CPU(obj), false); } =20 static void aarch64_a53_initfn(Object *obj) --=20 2.43.0 From nobody Mon Sep 28 01:15:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786034400; cv=none; d=zohomail.com; s=zohoarc; b=hggyZ61CG5bKi8TK5DBVWTJ5WzSyYRgXCCjHq9tDJAPQ4U8HsxgrLHU6wUZuwwGjejPyCYdJSp7bvPbReI0MI3vtv9H4XvMuiHy1uVFbUjIyKWRuBzuAE2lxu8PxQ9Ps/fnRKFSUiCvPqk0ZoWbb1Fhj4mJsL/fe9QUtHY/uCt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786034400; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ncF+VrF48oEXQiurXrwt2lRSm4bmf+7Q7x/Xk+zd/VY=; b=AuZaKQBUO4SHXXMLVjVmSQUAR/mq7D1Ra4MZ3Y9Phh2xK5PsnrkjC/PrEwiVtWOmw8Ct4Ck6NZX9CVWdfVmcIt0q8llUti+P1qFZo3i52PJUL01PsbLU5aslxMMMFpl1NUsEUMbleUwRXAl16Lv2SqorMrSCYNxuxsvb9CI7pys= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786034399922334.41338582699484; Thu, 6 Aug 2026 09:39:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ws18J-0006nC-Ek; Thu, 06 Aug 2026 12:39:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ws18E-0006kX-Qp for qemu-devel@nongnu.org; Thu, 06 Aug 2026 12:39:46 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ws18C-0000ID-QP for qemu-devel@nongnu.org; Thu, 06 Aug 2026 12:39:46 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2d02b4c3601so28540055ad.3 for ; Thu, 06 Aug 2026 09:39:44 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 2 +- target/arm/cpu-max.c | 5 ++--- target/arm/cpu64.c | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 9c9196475b..5e7f41a50d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1813,7 +1813,7 @@ void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); -void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only); +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa64_enabled); void aarch64_host_initfn(Object *obj); =20 /* Return true if the gdbstub is presenting an AArch64 CPU */ diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index d7f2500353..bdacfb21d3 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -16,10 +16,9 @@ #include "target/arm/internals.h" #include "target/arm/cpregs.h" =20 -void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa32_only) +void aarch64_aa32_a57_init(ARMCPU *cpu, bool aarch64_enabled) { ARMISARegisters *isar =3D &cpu->isar; - const bool aarch64_enabled =3D !aa32_only; =20 cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -204,7 +203,7 @@ static void cpu_max_initfn(Object *obj) =20 assert(tcg_enabled() || qtest_enabled()); =20 - aarch64_aa32_a57_init(cpu, !aarch64_enabled); + aarch64_aa32_a57_init(cpu, aarch64_enabled); =20 if (!aarch64_enabled) { aa32_max_features(cpu); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e3ee0253a0..faaf3ab879 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -688,7 +688,7 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **err= p) =20 static void aarch64_a57_initfn(Object *obj) { - aarch64_aa32_a57_init(ARM_CPU(obj), false); + aarch64_aa32_a57_init(ARM_CPU(obj), true); } =20 static void aarch64_a53_initfn(Object *obj) --=20 2.43.0 From nobody Mon Sep 28 01:15:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786034432; cv=none; d=zohomail.com; s=zohoarc; b=RAwoBHhZKFk7O2eq3n+6YiqPPe45CDukYYah8EDxrkjBioXZuIr8K2f3ChudIozee4KmGRSQf4jOYHAVofm3i9fWVqaYVjtyVKyFL2sRMJfUN984tEqHGU2NKTfQaSlkxNq+9HLsiUVWZtAXM/qFcGfTk1HoaYtINj/08GOlvnU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786034432; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EkXaE1LdHjxR5+SLCaE45VZ8+LEX5aQ8OT/h3czPRdQ=; b=FoV0a3gi8Mwfs1XYVjGvRcLdgYtk+HZBPNH3LQaabUkltyYjzIyBpqjFr1X6ldHoCKwIlQ/9Rs77Dw2bsLit1RVGZ/+DBsMZ+AU7/FUuSOqj4wE9FU+Sp6FboB+ma2TGxHG0zUcIwswZz3EgkivUBiBC4sKWElh0e0OU1F3ZjsM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786034432270312.54776705798156; Thu, 6 Aug 2026 09:40:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ws18J-0006mp-9q; Thu, 06 Aug 2026 12:39:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ws18F-0006kc-7u for qemu-devel@nongnu.org; Thu, 06 Aug 2026 12:39:48 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ws18D-0000Id-Pk for qemu-devel@nongnu.org; Thu, 06 Aug 2026 12:39:47 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2cfbbdfa60bso23476135ad.3 for ; Thu, 06 Aug 2026 09:39:45 -0700 (PDT) Received: from stoup.. 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Thu, 06 Aug 2026 09:39:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 4/7] target/arm: Sink aarch64_aa32_a57_init into aarch64_max_tcg_initfn Date: Thu, 6 Aug 2026 09:39:36 -0700 Message-ID: <20260806163939.328201-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260806163939.328201-1-richard.henderson@linaro.org> References: <20260806163939.328201-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1786034433785158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu-max.c | 3 +-- target/arm/tcg/cpu64.c | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index bdacfb21d3..cfcc46eb9d 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -203,9 +203,8 @@ static void cpu_max_initfn(Object *obj) =20 assert(tcg_enabled() || qtest_enabled()); =20 - aarch64_aa32_a57_init(cpu, aarch64_enabled); - if (!aarch64_enabled) { + aarch64_aa32_a57_init(cpu, false); aa32_max_features(cpu); #ifdef CONFIG_USER_ONLY /* diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 8a3ebf6321..2c0b7c1be4 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1167,6 +1167,8 @@ void aarch64_max_tcg_initfn(Object *obj) uint64_t t; uint32_t u; =20 + aarch64_aa32_a57_init(cpu, true); + SET_IDREG(isar, CLIDR, 0x8200123); /* 64KB L1 dcache */ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); 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So far, the cpu types both exactly match "max". Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/sbsa-ref.c | 2 ++ hw/arm/virt.c | 2 ++ target/arm/tcg/cpu64.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 484b90053e..56d08f605c 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -913,6 +913,8 @@ static void sbsa_ref_class_init(ObjectClass *oc, const = void *data) ARM_CPU_TYPE_NAME("neoverse-v1"), ARM_CPU_TYPE_NAME("neoverse-n2"), ARM_CPU_TYPE_NAME("max"), + ARM_CPU_TYPE_NAME("max-v8"), + ARM_CPU_TYPE_NAME("max-v9"), NULL, }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 219597cabd..34cab9017c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -4143,6 +4143,8 @@ static GPtrArray *virt_get_valid_cpu_types(const Mach= ineState *ms) g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v8"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max-v9"))); } if (target_aarch64()) { g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53"))); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 2c0b7c1be4..556fa9fa3c 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1462,6 +1462,8 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, + { .name =3D "max-v8", .initfn =3D aarch64_max_tcg_initfn }, + { .name =3D "max-v9", .initfn =3D aarch64_max_tcg_initfn }, }; =20 static void aarch64_cpu_register_types(void) --=20 2.43.0 From nobody Mon Sep 28 01:15:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786034467; cv=none; d=zohomail.com; s=zohoarc; b=h7us4GGCKVZUXTi7XpXinUmMYzjmJuvwsP+mL+Ww9jg8l7h5U0S56n/DjQn1v7kFlMCi5zpt7qBmFaApzLpkGjmX1/AVNHoyOptlYYtmMKqzxKZeygOsRjvXWUS0W1qZQrXrhNPcP0GuT3oO/Y6HBWtcfzHEPEW3Ta9jOlCntCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786034467; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3JOD9P96ewq1kt9dQtTWRUzN+g3g91eOzCcajcg6XGs=; b=LniBQtLOod2P9hxe/rpbBzD2Uhaj6+iG3BCuckIKfTjGpzJvRpS+NQp1vTXOF1JIsXkn0qj6rQN+35k2RpKyeROrehqiis2ke28iCABvPitRRut6BTYMGAtMtd0KGgRnkt6/HoYjy41bH0JD3vR5qbprxRsRedxda92sazIyBfU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17860344672851006.9106705631199; Thu, 6 Aug 2026 09:41:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ws18O-0006oj-0j; Thu, 06 Aug 2026 12:39:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ws18H-0006mg-NS for qemu-devel@nongnu.org; Thu, 06 Aug 2026 12:39:51 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ws18G-0000JZ-92 for qemu-devel@nongnu.org; Thu, 06 Aug 2026 12:39:49 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-2caced6038eso15413635ad.0 for ; Thu, 06 Aug 2026 09:39:47 -0700 (PDT) Received: from stoup.. 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These tests must use Armv8. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tests/qtest/arm-cpu-features.c | 4 ++-- tests/functional/aarch64/test_virt_aarch64_off.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index cb4d01fd46..7348fb8d28 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -493,8 +493,8 @@ static void test_query_cpu_model_expansion(const void *= data) sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); =20 - /* TCG allows us to turn off AArch64 on the 'max' CPU type */ - assert_set_feature(qts, "max", "aarch64", false); + /* TCG allows us to turn off AArch64 on the 'max-v8' CPU type */ + assert_set_feature(qts, "max-v8", "aarch64", false); } =20 qtest_quit(qts); diff --git a/tests/functional/aarch64/test_virt_aarch64_off.py b/tests/func= tional/aarch64/test_virt_aarch64_off.py index 13d8b73b0d..73c9a4109c 100755 --- a/tests/functional/aarch64/test_virt_aarch64_off.py +++ b/tests/functional/aarch64/test_virt_aarch64_off.py @@ -18,9 +18,9 @@ class ArmVirtMachine(LinuxKernelTest): def test_arm_virt(self): self.set_machine('virt') # KVM aarch64=3Doff requires a host CPU that supports it, so - # restrict the test to TCG only + # restrict the test to TCG ARMv8. self.require_accelerator('tcg') - self.vm.add_args('-cpu', 'max,aarch64=3Doff') + self.vm.add_args('-cpu', 'max-v8,aarch64=3Doff') =20 kernel_path =3D self.ASSET_KERNEL.fetch() =20 --=20 2.43.0 From nobody Mon Sep 28 01:15:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1786034493; cv=none; d=zohomail.com; s=zohoarc; b=jmKA3ntQnSXePd8R0ADs1BDx+ZofYqfM/0+6B+9u2PRpjTo1IkzY2X+pfc8aQZ000tjSXWEp55gnzzTaLVOGMZcK7ZhZm7e9KYUYtsK7074Sr4ZeUrteG3vopeQ1ZsdHeFtwuayU8n3EUJ5GN9qYaKjNskEhCC4d+XxCkPxvp7U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1786034493; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GrbyJ2r1hxRgJ5HumO1lxxfAhm91/uPN2Af2Cbfu+1g=; b=TVNQANl+Qoj86BrEK93B6tlIqLi6hKs/AHQlGDjI242dodHna/4YJWDkxKn/GgLh959ZcDeC+kKCnKTmFD66w5RrdIMEbs+boihM4qK2+5IqR59Of4gI5a0kWjXUQuL6McMyW2589B2oJcbyDaNynHdFvOrGh6XCSgHYvsPX5tI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1786034493654356.6155989332764; Thu, 6 Aug 2026 09:41:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ws18P-0006ph-Jq; Thu, 06 Aug 2026 12:39:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ws18K-0006nm-R5 for qemu-devel@nongnu.org; Thu, 06 Aug 2026 12:39:53 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ws18G-0000Jz-Gs for qemu-devel@nongnu.org; Thu, 06 Aug 2026 12:39:52 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2cfff5f88dbso35402385ad.3 for ; Thu, 06 Aug 2026 09:39:48 -0700 (PDT) Received: from stoup.. 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Do not include the prohibited v8 features in "max-v9". In tcg mode, define "max" as "max-v9". Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/cpu-max.c | 2 +- target/arm/tcg/cpu64.c | 408 ++++++++++++++++++++-------------- target/arm/tcg/stubs32.c | 2 +- docs/system/arm/emulation.rst | 11 +- 5 files changed, 253 insertions(+), 172 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5e7f41a50d..2ced0b1c2c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1809,7 +1809,7 @@ void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **er= rp); void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); -void aarch64_max_tcg_initfn(Object *obj); +void aarch64_max_v9_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c index cfcc46eb9d..e6872c1c8d 100644 --- a/target/arm/cpu-max.c +++ b/target/arm/cpu-max.c @@ -220,7 +220,7 @@ static void cpu_max_initfn(Object *obj) * '-cpu max' for TCG: we currently do this as * "A57 with extra things" */ - aarch64_max_tcg_initfn(obj); + aarch64_max_v9_tcg_initfn(obj); } } =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 556fa9fa3c..5eeb6712da 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1156,13 +1156,11 @@ static void aarch64_neoverse_n2_initfn(Object *obj) } =20 /* - * -cpu max: a CPU with as many features enabled as our emulation supports. - * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; - * this only needs to handle 64 bits. + * -cpu max-v8: an ARMv8 CPU with as many features enabled as + * our emulation supports. */ -void aarch64_max_tcg_initfn(Object *obj) +static void aarch64_max_v8_tcg_initfn_aa64(ARMCPU *cpu) { - ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; uint64_t t; uint32_t u; @@ -1226,203 +1224,148 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, CTR_EL0, DIC, 1); cpu->ctr =3D t; =20 + /* + * Below, note the revision from which the feature is OPTIONAL. + */ t =3D GET_IDREG(isar, ID_AA64ISAR0); - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* FEAT_LSE, FEAT_LSE1= 28 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* v8.0: FEAT_PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* v8.0: FEAT_SHA1 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* v8.1: FEAT_SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* v8.0: FEAT_CRC32 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* v8.0: FEAT_LSE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* v8.0: FEAT_RDM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* v8.1: FEAT_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* v8.1: FEAT_SM3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* v8.1: FEAT_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* v8.1: FEAT_DotProd = */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* v8.1: FEAT_FHM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.1: FEAT_FlagM2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* v8.3: FEAT_TLBIRANG= E */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* v8.4: FEAT_RNG */ SET_IDREG(isar, ID_AA64ISAR0, t); =20 t =3D GET_IDREG(isar, ID_AA64ISAR1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* v8.1: FEAT_DPB2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); /* v8.= 2 */ t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF= 16 */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* v8.2: FEAT_JSCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* v8.2: FEAT_FCMA */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* v8.2: FEAT_LRCPC2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* v8.4: FEAT_FRINTTS = */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* v8.0: FEAT_SB */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* v8.0: FEAT_SPECRES = */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* v8.2: FEAT_EBF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* v8.0: FEAT_DGH */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* v8.1: FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* v8.6: FEAT_XS */ SET_IDREG(isar, ID_AA64ISAR1, t); =20 t =3D GET_IDREG(isar, ID_AA64ISAR2); - t =3D FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* FEAT_RPRES */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* FEAT_CSSC, FEAT_CMP= BR */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* FEAT_LUT */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* FEAT_ATS1A */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* v8.6: FEAT_RPRES */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* v8.7: FEAT_MOPS */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* v8.7: FEAT_HBC */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* v8.6: FEAT_WFxT */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v8.7: FEAT_CSSC */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* v8.8: FEAT_ATS1A */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 - t =3D GET_IDREG(isar, ID_AA64ISAR3); - t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* FEAT_FAMINMAX */ - t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* FEAT_FPRCVT */ - SET_IDREG(isar, ID_AA64ISAR3, t); - t =3D GET_IDREG(isar, ID_AA64PFR0); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ - t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* v8.2: FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* v8.2: FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* v8.3: FEAT_DoubleFa= ult */ + t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); /* v8.2: FEAT_SVE */ + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* v8.3: FEAT_SEL2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* v8.3: FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* v8.0: FEAT_CSV2_3 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* v8.0: FEAT_CSV3 */ SET_IDREG(isar, ID_AA64PFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR1); - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* v8.4: FEAT_BTI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* v8.0: FEAT_SSBS2 */ /* * Begin with full support for MTE. This will be downgraded to MTE=3D0 * during realize if the board provides no tag memory, much like * we do for EL2 with the virtualization=3Don property. */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ - t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ - t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* FEAT_SME2 */ - t =3D FIELD_DP64(t, ID_AA64PFR1, RNDR_TRAP, 1); /* FEAT_RNG_TRAP */ - t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ - t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ - t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* FEAT_GCS */ - /* FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* v8.5: FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* v8.3: FEAT_DoubleFa= ult */ + t =3D FIELD_DP64(t, ID_AA64PFR1, RNDR_TRAP, 1); /* v8.4: FEAT_RNG_TRAP= */ + t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* v8.0: FEAT_CSV2_3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* v8.7: FEAT_NMI */ + /* v8.7: FEAT_MTE_NO_ADDRESS_TAGS + FEAT_MTE_CANONICAL_TAGS */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTEX, 1); SET_IDREG(isar, ID_AA64PFR1, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR2); - t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* FEAT_FPMR */ - t =3D FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* FEAT_MTE_TAGGED_FAR= */ - t =3D FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* FEAT_MTE_STORE= _ONLY */ - t =3D FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* FEAT_MTE_PERM */ + t =3D FIELD_DP64(t, ID_AA64PFR2, MTEFAR, 1); /* v8.7: FEAT_MTE_TAGG= ED_FAR */ + t =3D FIELD_DP64(t, ID_AA64PFR2, MTESTOREONLY, 1); /* v8.7: FEAT_MTE_S= TORE_ONLY */ + t =3D FIELD_DP64(t, ID_AA64PFR2, MTEPERM, 1); /* v8.7: FEAT_MTE_PERM= */ SET_IDREG(isar, ID_AA64PFR2, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR0); - t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supporte= d */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ - t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* v8.1: FEAT_LPA: 52 b= its */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* v8.0: FEAT_TGran16= K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* v8.0: FEAT_S2TGran= 4K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* v8.0: FEAT_S2TGran= 64K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* v8.0: FEAT_S2TGran= 4K */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* v8.5: FEAT_FGT */ + t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* v8.5: FEAT_ECV */ SET_IDREG(isar, ID_AA64MMFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* FEAT_AFP */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* FEAT_CMOW */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* v8.0: FEAT_HAFDBS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* v8.0: FEAT_VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* v8.0: FEAT_VHE */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* v8.1: FEAT_HPDS2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* v8.0: FEAT_LOR */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* v8.1: FEAT_PAN3 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* v8.1: FEAT_XNX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* v8.0: FEAT_ETS2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* v8.6: FEAT_HCX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* v8.6: FEAT_AFP */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* v8.7: FEAT_TIDCP1 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* v8.7: FEAT_CMOW */ SET_IDREG(isar, ID_AA64MMFR1, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR2); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* FEAT_NV2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* v8.1: FEAT_TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* v8.1: FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* v8.1: FEAT_IESB */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* v8.1: FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* v8.3: FEAT_NV2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* v8.3: FEAT_TTST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* v8.2: FEAT_LSE2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* v8.3: FEAT_IDST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* v8.3: FEAT_S2FWB */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* v8.3: FEAT_TTL */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* v8.3: FEAT_BBML2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* v8.2: FEAT_EVT2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* v8.4: FEAT_E0PD */ SET_IDREG(isar, ID_AA64MMFR2, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR3); - t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* FEAT_S1PIE */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* FEAT_S2PIE */ - t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* v8.0: FEAT_TCR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* v8.0: FEAT_SCTLR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* v8.2: FEAT_FPACC_= SPEC */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* v8.8: FEAT_S1PIE */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* v8.8: FEAT_S2PIE */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* v8.8: FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 - t =3D GET_IDREG(isar, ID_AA64MMFR4); - t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* FEAT_ASID2 */ - SET_IDREG(isar, ID_AA64MMFR4, t); - t =3D GET_IDREG(isar, ID_AA64ZFR0); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* FEAT_BF16, FEAT_EBF= 16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* FEAT_SVE_B16B16 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 2); /* v8.2: FEAT_EBF16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* v8.1: FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* v8.2: FEAT_F32MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* v8.2: FEAT_F64MM */ SET_IDREG(isar, ID_AA64ZFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64DFR0); - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ - t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* v8.7: FEAT_Debugv8p= 8 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* v8.4: FEAT_PMUv3p5 = */ + t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* v8.5: FEAT_HPMN0 */ SET_IDREG(isar, ID_AA64DFR0, t); =20 - t =3D GET_IDREG(isar, ID_AA64SMFR0); - t =3D FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* FEAT_SSVE_FEXPA */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* FEAT_SME_MOP4 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* FEAT_SSVE_AES */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* FEAT_SSVE_FP8DOT2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* FEAT_SSVE_FP8DOT4 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* FEAT_SSVE_FP8FMA */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, BI32I32, 1); /* FEAT_SME2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F32, 1); /* FEAT_SME_F8F32 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F16, 1); /* FEAT_SME_F8F16 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F16, 1); /* FEAT_SME_F16F16 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, B16B16, 1); /* FEAT_SME_B16B16 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* FEAT_SME2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 2); /* FEAT_SME2p1 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, LUTv2, 1); /* FEAT_SME_LUTv2 */ - t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ - SET_IDREG(isar, ID_AA64SMFR0, t); - - t =3D GET_IDREG(isar, ID_AA64FPFR0); - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* FEAT_FP8 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* FEAT_FP8 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM4, 1); /* FEAT_F8F16MM */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM8, 1); /* FEAT_F8F32MM */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP2, 1); /* FEAT_FP8DOT2 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP4, 1); /* FEAT_FP8DOT4 */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8FMA, 1); /* FEAT_FP8FMA */ - t =3D FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* FEAT_FP8 */ - SET_IDREG(isar, ID_AA64FPFR0, t); - - /* Replicate the same data to the 32-bit id registers. */ - aa32_max_features(cpu); - #ifdef CONFIG_USER_ONLY /* * For usermode -cpu max we can use a larger and more efficient DCZ @@ -1431,20 +1374,149 @@ void aarch64_max_tcg_initfn(Object *obj) cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ set_dczid_bs(cpu, 7); /* 512 bytes */ #endif - cpu->gm_blocksize =3D 6; /* 256 bytes */ =20 + /* v8.2: FEAT_SVE */ cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); - cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; + aarch64_add_sve_properties(OBJECT(cpu)); + object_property_add(OBJECT(cpu), "sve-max-vq", "uint32", + cpu_max_get_sve_max_vq, cpu_max_set_sve_max_vq, + NULL, NULL); =20 - aarch64_add_pauth_properties(obj); - aarch64_add_sve_properties(obj); + /* v8.2: FEAT_PAuth2 */ + aarch64_add_pauth_properties(OBJECT(cpu)); + + /* v8.4: FEAT_MTE2 */ + cpu->gm_blocksize =3D 6; /* 256 bytes */ + + /* v8.6: FEAT_LPA2 */ + qdev_property_add_static(DEVICE(cpu), &arm_cpu_lpa2_property); +} + +static void aarch64_max_v8_tcg_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + aarch64_max_v8_tcg_initfn_aa64(cpu); + + /* Replicate the same data to the 32-bit id registers. */ + aa32_max_features(cpu); +} + +/* + * -cpu max-v9: an ARMv9 CPU with as many features enabled as + * our emulation supports. + */ +void aarch64_max_v9_tcg_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; + uint64_t t; + + /* Armv9.0 is based on a minimum of Armv8.5. */ + aarch64_max_v8_tcg_initfn_aa64(cpu); + + /* + * Armv9.0 does not support AArch32 except at EL0, + * therefore indicate EL1 through EL3 are AArch64-only. + */ + t =3D GET_IDREG(isar, ID_AA64PFR0); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL1, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL2, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, EL3, 1); + SET_IDREG(isar, ID_AA64PFR0, t); + + /* v9.0 prohibits FEAT_DoubleLock. */ + FIELD_DP64_IDREG(isar, ID_AA64DFR0, DOUBLELOCK, -1); + isar->dbgdevid =3D FIELD_DP32(isar->dbgdevid, DBGDEVID, DOUBLELOCK, 0); + + /* + * Below, note the revision from which the feature is OPTIONAL. + */ + t =3D GET_IDREG(isar, ID_AA64ISAR0); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 3); /* v9.3: FEAT_LSE128 */ + SET_IDREG(isar, ID_AA64ISAR0, t); + + t =3D GET_IDREG(isar, ID_AA64ISAR2); + t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2); /* v9.3: FEAT_CMPBR */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* v9.2: FEAT_LUT */ + SET_IDREG(isar, ID_AA64ISAR2, t); + + t =3D GET_IDREG(isar, ID_AA64ISAR3); + t =3D FIELD_DP64(t, ID_AA64ISAR3, FAMINMAX, 1); /* v9.2: FEAT_FAMINMAX= */ + t =3D FIELD_DP64(t, ID_AA64ISAR3, FPRCVT, 1); /* v9.5: FEAT_FPRCVT */ + SET_IDREG(isar, ID_AA64ISAR3, t); + + t =3D GET_IDREG(isar, ID_AA64PFR1); + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* v9.3: FEAT_GCS */ + SET_IDREG(isar, ID_AA64PFR1, t); + + t =3D GET_IDREG(isar, ID_AA64PFR2); + t =3D FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */ + SET_IDREG(isar, ID_AA64PFR2, t); + + t =3D GET_IDREG(isar, ID_AA64MMFR3); + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */ + SET_IDREG(isar, ID_AA64MMFR3, t); + + t =3D GET_IDREG(isar, ID_AA64MMFR4); + t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* v9.4: FEAT_ASID2 */ + SET_IDREG(isar, ID_AA64MMFR4, t); + + t =3D GET_IDREG(isar, ID_AA64ZFR0); + t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); /* v9.2: FEAT_SVE2p1 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMUL= L128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitP= erm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, B16B16, 1); /* v9.2: FEAT_SVE_B16B= 16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* v9.0: FEAT_SVE_SHA3= */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* v9.0: FEAT_SVE_SM4 = */ + SET_IDREG(isar, ID_AA64ZFR0, t); + + t =3D GET_IDREG(isar, ID_AA64SMFR0); + t =3D FIELD_DP64(t, ID_AA64SMFR0, SFEXPA, 1); /* v9.4: FEAT_SSVE_FEX= PA */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SMOP4, 1); /* v9.4: FEAT_SME_MOP4= */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* v9.5: FEAT_SSVE_AES= */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* v9.2: FEAT_SSVE_FP8= DOT2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* v9.2: FEAT_SSVE_FP8= DOT4 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* v9.2: FEAT_SSVE_FP8= FMA */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, BI32I32, 1); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* v9.2: FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F32, 1); /* v9.2: FEAT_SME_F8F3= 2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F16, 1); /* v9.2: FEAT_SME_F8F1= 6 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F16, 1); /* v9.2: FEAT_SME_F16F= 16 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16B16, 1); /* v9.2: FEAT_SME_B16B= 16 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* v9.2: FEAT_SME2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* v9.2: FEAT_SME_F64F= 64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* v9.2: FEAT_SME_I16I= 64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 2); /* v9.2: FEAT_SME2p1 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, LUTv2, 1); /* v9.2: FEAT_SME_LUTv= 2 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* v9.2: FEAT_SME_FA64= */ + SET_IDREG(isar, ID_AA64SMFR0, t); + + t =3D GET_IDREG(isar, ID_AA64FPFR0); + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* v9.2: FEAT_FP8 */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* v9.2: FEAT_FP8 */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM4, 1); /* v9.2: FEAT_F8F16MM = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8MM8, 1); /* v9.2: FEAT_F8F32MM = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP2, 1); /* v9.2: FEAT_FP8DOT2 = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8DP4, 1); /* v9.2: FEAT_FP8DOT4 = */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8FMA, 1); /* v9.2: FEAT_FP8FMA */ + t =3D FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* v9.2: FEAT_FP8 */ + SET_IDREG(isar, ID_AA64FPFR0, t); + + /* v9.2: FEAT_SME */ + cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; aarch64_add_sme_properties(obj); - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, - cpu_max_set_sve_max_vq, NULL, NULL); + + /* v9.1: FEAT_RME; v9.5: FEAT_RME_GPC3 */ object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rm= e); + + /* v9.4: FEAT_RME_GPC2 */ object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, cpu_max_set_l0gptsz, NULL, NULL); - qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); } =20 static const ARMCPUInfo aarch64_cpus[] =3D { @@ -1462,8 +1534,8 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, - { .name =3D "max-v8", .initfn =3D aarch64_max_tcg_initfn }, - { .name =3D "max-v9", .initfn =3D aarch64_max_tcg_initfn }, + { .name =3D "max-v8", .initfn =3D aarch64_max_v8_tcg_initf= n }, + { .name =3D "max-v9", .initfn =3D aarch64_max_v9_tcg_initf= n }, }; =20 static void aarch64_cpu_register_types(void) diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c index 78f819ef6f..939cea7189 100644 --- a/target/arm/tcg/stubs32.c +++ b/target/arm/tcg/stubs32.c @@ -28,7 +28,7 @@ void aarch64_host_initfn(Object *obj) g_assert_not_reached(); } =20 -void aarch64_max_tcg_initfn(Object *obj) +void aarch64_max_v9_tcg_initfn(Object *obj) { g_assert_not_reached(); } diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 9930974a50..3400de6b76 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -229,7 +229,16 @@ to the `Arm Architecture Reference Manual for A-profil= e architecture When a specific named CPU is being emulated, only those features which are present in hardware for that CPU are emulated. (If a feature is not in the list above then it is not supported, even if the real -hardware should have it.) The ``max`` CPU enables all features. +hardware should have it.) + +The ``max-v8`` CPU enables all of the listed Armv8-A architecture +extensions but none of the Armv9-A architecture extensions. + +The ``max-v9`` CPU enables all of the listed extensions except for +those that are prohibited by the Armv9-A architecture: FEAT_AA32EL1, +FEAT_AA32EL2, FEAT_AA32EL3, and FEAT_DoubleLock. + +The ``max`` CPU is an alias for ``max-v9`` under TCG emulation. =20 R-profile CPU architecture support =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.43.0