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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1785954384793158500 Content-Type: text/plain; charset="utf-8" Add documentation regarding how QEMU handles Debug versions 0.13 and 1.0. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- docs/specs/index.rst | 1 + docs/specs/riscv-debug.rst | 68 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 docs/specs/riscv-debug.rst diff --git a/docs/specs/index.rst b/docs/specs/index.rst index b7909a108a..181773515d 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -38,5 +38,6 @@ guest hardware that is specific to QEMU. rocker riscv-iommu riscv-aia + riscv-debug aspeed-intc iommu-testdev diff --git a/docs/specs/riscv-debug.rst b/docs/specs/riscv-debug.rst new file mode 100644 index 0000000000..e6dcad7d38 --- /dev/null +++ b/docs/specs/riscv-debug.rst @@ -0,0 +1,68 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +.. _riscv-debug: + +RISC-V Debug support for RISC-V CPUs +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Up until QEMU version 11.1 RISC-V CPUs historically supports Debug version +0.13 via a "debug" flag that is enabled by default in the default rv64 +CPU. + +Starting on QEMU 11.2, RISC-V CPUs supports also Debug version 1.0, enabled +via the "sdtrig" flag like a regular extension. The default setting for r= v64 +is still Debug 0.13 (debug =3D on, sdtrig =3D off), + +The "sdtrig" flag precedes "debug", i.e. if both are enabled the CPU will +implement Debug 1.0. In short: + +.. list-table:: "debug" and "sdtrig" flags and enabled Debug version + :widths: 25 25 25 + :header-rows: 1 + + * - debug + - sdtrig + - Enabled Debug version + * - on + - off + - 0.13 + * - on + - on + - 1.0 + * - off + - on + - 1.0 + * - off + - off + - All Debug versions disabled + + +Debug 0.13 to 1.0 code/design changes +------------------------------------- + +The effort done in QEMU version 11.2 to support Debug versions 0.13 and +1.0 together was based in section 1.2.1.2 "Incompatible Changes from 0.13 +to 1.0" from the ratified `1.0 spec`_. Here's how the proposed changes in +that section were implemented in QEMU 11.2: + +Changes that aren't applicable due to either being SBI related or not pres= ent/supported in QEMU: + * "Make haltsum0 optional if there is only one hart." + * "System bus autoincrement only happens if an access actually takes p= lace (sbdata0)." + * "Require debugger to poll dmactive after lowering it." + +Already implemented in the legacy Debug 0.13 base code: + * "When a selected trigger is disabled, tdata2 and tdata3 can be writt= en with any value supported by any of the types this trigger supports." + * "tcontrol fields only apply to breakpoint traps, not any trap." + +All "hitN" fields are hardwired 0 thus no changes made: + * "If version is greater than 0, then hit0 (previously called mcontrol= 6.hit) now contains 0 when a trigger fires more than one instruction after = the instruction that matched. (This information is now reflected in hit1.)" + +QEMU doesn't support encoding sizes greater than 64 bit so no change made: + * "If version is greater than 0, then the encodings of size for sizes = greater than 64 bit have changed." + +Changes made in the 0.13 codebase to support Debug 1.0: + * "Add pending to icount." + * "If version is greater than 0, then bit 20 of mcontrol6 is no longer= used for timing information. (Previously the bit was called mcontrol6.timi= ng.)" + + +.. _1.0 spec: https://docs.riscv.org/reference/debug/v1.0/_attachments/ris= cv-debug-specification.pdf --=20 2.43.0