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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1785954410940158500 Content-Type: text/plain; charset="utf-8" We need to set the 'pending' bit when 'count' reaches 0, clearing it right after the trigger fires. This is 1.0 exclusive behavior so no changes are needed when running Debug 0.13. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/tcg/debug.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index 3c0fe70101..2191928761 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -77,6 +77,11 @@ static int access_size[SIZE_NUM] =3D { [6 ... 15] =3D -1, }; =20 +static bool debug_trigger_version_1_0(CPURISCVState *env) +{ + return riscv_cpu_cfg(env)->ext_sdtrig; +} + static inline target_ulong extract_trigger_type(CPURISCVState *env, target_ulong tdata1) { @@ -684,6 +689,17 @@ itrigger_set_count(CPURISCVState *env, int index, int = value) ITRIGGER_COUNT, value); } =20 +static inline void +itrigger_set_pending(CPURISCVState *env, int index, int val) +{ + if (!debug_trigger_version_1_0(env)) { + return; + } + + env->tdata1[index] =3D set_field(env->tdata1[index], + ITRIGGER_PENDING, val); +} + static bool check_itrigger_priv(CPURISCVState *env, int index) { target_ulong tdata1 =3D env->tdata1[index]; @@ -735,8 +751,25 @@ void helper_itrigger_match(CPURISCVState *env) } itrigger_set_count(env, i, count--); if (!count) { + /* + * From the 1.0 spec: "When pending is set, the trigger + * fires just before any further instructions are executed + * in a mode where the trigger is enabled. As the trigger + * fires, pending is cleared." + * + * And: "This bit becomes set when count is decremented + * from 1 to 0. It is cleared when the trigger fires, + * which will happen just before executing the next + * instruction in one of the enabled modes". + * + * Note that itrigger_set_pending() is a no-op if we're + * running debug 0.13. + */ + itrigger_set_pending(env, i, 1); + env->itrigger_enabled =3D riscv_itrigger_enabled(env); do_trigger_action(env, i); + itrigger_set_pending(env, i, 0); } } } --=20 2.43.0