Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/gen_tcg_hvx.h | 62 ++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 3cb52c761ae..97c373c10bf 100644
--- a/target/hexagon/gen_tcg_hvx.h
+++ b/target/hexagon/gen_tcg_hvx.h
@@ -355,6 +355,68 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
 #define fGEN_TCG_V6_vabsdiffw(SHORTCODE) \
     fGEN_TCG_VEC_ABSDIFF(MO_32, tcg_gen_gvec_smax, tcg_gen_gvec_smin)
 
+#define fGEN_TCG_VEC_AVG(VECE, SHIFT_FN) \
+    do { \
+        intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
+        tcg_gen_gvec_and(MO_64, tmpoff, VuV_off, VvV_off, \
+                         VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+        tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \
+                         VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+        SHIFT_FN(VECE, VdV_off, VdV_off, 1, \
+                 VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+        tcg_gen_gvec_add(VECE, VdV_off, tmpoff, VdV_off, \
+                         VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+    } while (0)
+
+#define fGEN_TCG_V6_vavgub(SHORTCODE) \
+    fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavguh(SHORTCODE) \
+    fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavguw(SHORTCODE) \
+    fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavgb(SHORTCODE) \
+    fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_sari)
+
+#define fGEN_TCG_V6_vavgh(SHORTCODE) \
+    fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_sari)
+
+#define fGEN_TCG_V6_vavgw(SHORTCODE) \
+    fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_sari)
+
+#define fGEN_TCG_VEC_AVGRND(VECE, SHIFT_FN) \
+    do { \
+        intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
+        tcg_gen_gvec_or(MO_64, tmpoff, VuV_off, VvV_off, \
+                        VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+        tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \
+                         VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+        SHIFT_FN(VECE, VdV_off, VdV_off, 1, \
+                 VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+        tcg_gen_gvec_sub(VECE, VdV_off, tmpoff, VdV_off, \
+                         VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \
+    } while (0)
+
+#define fGEN_TCG_V6_vavgubrnd(SHORTCODE) \
+    fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavguhrnd(SHORTCODE) \
+    fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavguwrnd(SHORTCODE) \
+    fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_shri)
+
+#define fGEN_TCG_V6_vavgbrnd(SHORTCODE) \
+    fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_sari)
+
+#define fGEN_TCG_V6_vavghrnd(SHORTCODE) \
+    fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_sari)
+
+#define fGEN_TCG_V6_vavgwrnd(SHORTCODE) \
+    fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_sari)
+
 /* Vector shift right - various forms */
 #define fGEN_TCG_V6_vasrh(SHORTCODE) \
     do { \
-- 
2.34.1

On Wed, Aug 5, 2026 at 11:52 AM Brian Cain <brian.cain@oss.qualcomm.com> wrote:
>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
>  target/hexagon/gen_tcg_hvx.h | 62 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)

Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>