From nobody Mon Aug 24 09:08:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1785948313; cv=none; d=zohomail.com; s=zohoarc; b=W6RgMy+S89cQ6pIQeyNg12p7HkQCvZav0SQZnbHyAt8t1SQwwag7c458gKeJAoHekFQmX87JXVylZybshLlLLu9XVf4vcTBaoMpx9OniQUoh8oUrX9Hpx6ba+2tRdTw+k3QcOa0GgLTv1PY+xyvh8p3UrKq8MvlvohuGUnsfUF0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785948313; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9Gykh+5P8EC5j4uZxNdjyOMe+zEXw26y8NMVO5QDhqI=; b=BeZ/bE0woTOATabp5FmAR71xvpIYawfw51UH0WdUUCmO8k6ThglTth9T6QQl5MqVVx7jh6jCecgkgKNTUEmCHs9vorGFBUBEufehmg4hk+CKX1NlwtBvQTvELAfvl4e2UVt+KN/iQLaUFiXZDozE00Ge0NTpTGZkmZG5tCzBqEM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785948313866779.3302693325633; Wed, 5 Aug 2026 09:45:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wreik-0008H0-7T; Wed, 05 Aug 2026 12:43:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wreii-0008GZ-PN for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:43:56 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wreih-0001uv-AU for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:43:56 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2cc73e322dbso14994305ad.1 for ; Wed, 05 Aug 2026 09:43:54 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3158644a195sm16719065eec.13.2026.08.05.09.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 09:43:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1785948234; x=1786553034; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=9Gykh+5P8EC5j4uZxNdjyOMe+zEXw26y8NMVO5QDhqI=; b=nilC5DGA50nOibx5tzh7GmnP5tK3pQOF62tT50jIPflRqB7ZKK8IahmJlE7opRV/y7 /MKLFN9wLyrIGFooDIrOu7N1L88tegErcCPlqPkX0gmf679W4L/XwX0RCEGTWw5seDBF MBvKpPXjzvrd9HSAlu2/Z6SIR2pO/2X5f58htBAmm2u1SPhrKYMlcWpo/+kIwWwBiTPp bH5BxEHZQVRnQzBcBLZknWFA/qKcLZTIAG0TE2SLrSuc9YuutVlJpgncKyz9vbmVUN6v lVOO8KEBpliEMw0SBVeFqfNx+5lQ+9lceCmfe2u58ycQQKjw0Z2/Z2RZ0g/8vNj/yv8M 8ccg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785948234; x=1786553034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=9Gykh+5P8EC5j4uZxNdjyOMe+zEXw26y8NMVO5QDhqI=; b=p8AFfr0xhq00dkopLIOgZdGHSTzFA4uDzFZoVQQHnF/Tfd4XWD5zhy0gkY/wlqM3Rq 0c/kD31pwcAi9h2SgMj8WSthM9NNPQfIWuD5HT4HGvRvu+s5ZndU2GWosMN9/orH05dz W13kl0R78dLNQwUNA7VYFQAnGGBKiOu5Q3LBvodTq2OoblUEFKUSl9k4q5dF/CvFq0So tgbSbNB1m0k/NfZcKpL7hm8GxqiduoDhLwTnHApTpMfIs47L+Zt6CiVaT5904UtLv1nx rPPwChM2DRTy2bsXKCLUpG9CAr4LXnqUUuZeTo7LRZ1btsa3Tuz5PzKiyLbevU6sj+ho tN6w== X-Gm-Message-State: AOJu0YyK14OZ8a6MBVLY8V0Jsx97EwTe2Ch8s7HC3ASKAfXQ12/sTwsF Qr3eE0KYGa2zLVh1yWDF9ohpev+47FOGwXxRwpMhEl6R2NldREfYudbORd+FrLVJM4+6JbczohQ 1nCUuU0v4fPfpMzNRjg+Z/mF7b13Atp9NjrPVAAiuNmRxhu8qpfvJIwzPn5lpAL5ZWbVUZn7F63 /9oIDbSQrQ3JzDvORGe1gFsV66xWxdhMFUWzShQPsS8pCHpFEe X-Gm-Gg: AR+sD11SbR3utYdusqhicBSr91gMpL5j+nLlvd7uRsfZj5Hkv8AYITxKb7ItKJVR7nz SQRe6RGrVFKi4439EV8zmW47S8YKpcsyWgI1rByLIhXpnjy84jGwSWoqqBsNjvYZwh61I6PIerL cu2y6WSC90XVJJYRHet0NSMkYaVmPFcTJtEa+Akv3q5FTOZ1dNKRANNtnPP36iHA/HB8DvPtMKV 8tQ0ckqsCz5bnKZifmDeNijxQRCayzXLgPnbrdNCuXSLRnIt0NxtMg7WCOJFWc68JjZQfGAH6FM FrIwMkTk0pLJTFuVZxC52cp6bHXNlVI4D+ZrUJEsEiiO6cHWPQWXHDkI9I2H/l7eYELybNJHDCH nnomnUU0FbabGPghghD7Faeo7jepNGHdRkX1kbhoHR499c845/bNkPbxS6n64iAGopr/cO34iD1 lQjkwx8Mkwb7rlILGd1PW4IQ2j+8DQsc/3AokWImIKgK0GspwgcirFTN8g2WNpsaEBDu+yGklBF 1o5esKw+3y7eAC/F3tTuCnXjQ== X-Received: by 2002:a05:6a20:a111:b0:3bf:7eb5:9459 with SMTP id adf61e73a8af0-3cb85ef9202mr8570160637.20.1785948233862; Wed, 05 Aug 2026 09:43:53 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang , Max Chou , Alistair Francis Subject: [PATCH v7 1/8] target/riscv: Add Zicclsm CPU option Date: Thu, 6 Aug 2026 00:43:38 +0800 Message-ID: <20260805164345.698208-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805164345.698208-1-frank.chang@sifive.com> References: <20260805164345.698208-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1785948315220158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add Zicclsm CPU option so that user can turn on/off misaligned loads and stores support. Signed-off-by: Frank Chang Reviewed-by: Max Chou Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg_fields.h.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 9eb47af0a76..f8c27a574f8 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -139,6 +139,8 @@ BOOL_FIELD(has_priv_1_11) /* Always enabled for TCG if has_priv_1_11 */ BOOL_FIELD(ext_ziccrse) =20 +BOOL_FIELD(ext_zicclsm) + /* Vendor-specific custom extensions */ BOOL_FIELD(ext_xtheadba) BOOL_FIELD(ext_xtheadbb) --=20 2.43.0 From nobody Mon Aug 24 09:08:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1785948355; cv=none; d=zohomail.com; s=zohoarc; b=dfnPGvnUFUQfCWbJLD9zsGP/9zrirI2x3zIbgO/vLFFfDMU8hmG7iiq+lHjyTl2OrcPj0xcff+np+i1rkkavlF8RQBvn2bD24g9jbdf5VU+LX+w/ZjycWs0Q8CRnV+JLjMXVHNpocCTWylzix9WYJE1ejnAqgIw3Nlq6SkxnNRI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785948355; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZpEZ+qwUWzKX/pdopbU/v27JKSx+5w4HgXw/8RsqiZk=; b=QjTZALphwuEh3YIZwmBntFbWCh8Ml4JO1lcdwKsc888l8RqhY173uLf8iLfxuRlHouMaznTUjO/hgWw33I4tRcey2FTG2gpoVrYHVe9K3xiHmOchO3ko19hqcqGhinLBk7tK3dC0KiCCk5J/qTDj7OPw0rtDuC2xiMLIWipVJyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785948355597782.89731411727; Wed, 5 Aug 2026 09:45:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrein-0008Hy-2o; Wed, 05 Aug 2026 12:44:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wreil-0008HT-T0 for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:43:59 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wreik-0001vv-Aq for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:43:59 -0400 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-382ef647e20so1353672a91.1 for ; Wed, 05 Aug 2026 09:43:57 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3158644a195sm16719065eec.13.2026.08.05.09.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 09:43:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1785948237; x=1786553037; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ZpEZ+qwUWzKX/pdopbU/v27JKSx+5w4HgXw/8RsqiZk=; b=QJ5DqNqLgNejK8+G0tfozXLapG8MxUjKNQ0AxzAuMnnH+pApTj8tAm4wQWByGc6/A4 GlHYPqfx+h/i+1G4zhDqNu1pbztls4vOo9IRhxo7t2ye6PZAJO4UsW7hMlQ/zXzdUEVe bM/Rk/X2j4IkGbG10HVf4LD2dcCbMHmajAotj0XhtYSxk+ENPHv+4uvCErT63SZjvCn3 hKItCYcURE2KVnA3/RaffpACqU5k5xFSvm0P5o6bqnQvkityY8yCOHLfDRbLAj8sqK// bXlJg0Rh9If+OSGl/f6SbTOxRH779hs4IJ7n0UU/Egt0okdPEiTb0/5J/l88+WBypLtC Mo/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785948237; x=1786553037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=ZpEZ+qwUWzKX/pdopbU/v27JKSx+5w4HgXw/8RsqiZk=; b=DLiRAGXxHccwQBeg88QBaZSbeiolxuwBGUqxU769uhQUl+GrFPohVToexe0eVVXFw6 57MLZ8UvxXsxCGJaiK5pM6dMeMHJ3pq3F0vOyhS0W+XaZt9lETr7XtQNzF/iEGQfoTUN NTmEUWI263UiR+R6GYjRxSRQTobYv0LQCnRiK6JEwHAsle7tI4iEE9oSUCa5PpIfcydi 6rh/nrfZ/1avoJp48NRTNmFgYy9O9sBtRX2va6UToxo0G6AZgtFoN/JFEwI0ICswx1gF fCxlgHLUKd07LASwKN7XbTBOeRDBeyUp55mcf7Xt13HrOym7vNoiAffzGnQYtRWtqCtR Ppmw== X-Gm-Message-State: AOJu0Yz18g+nVn6X0Ulc5f7FXsOV5r5x8dgmGHiEthN9uFIIBbAGG/Iz 0L3L1Nyr1r8f2uaCME4fVKWTKK0Fe6RAprEVwWr3/QFDVvVhfiH5vkg8G5K7PbfAyuwOIlK/C2z zL+xUSkyxPQhBBFG35aalAhoruJKHLqbR8QKct3i2n0dLbb/ZUsK9GVCADUV3uPm43EfONGQPo3 QG5E/4Cp0DPPRkJsEYgmUQlkdvyUKK8y0/ir/7gc0ReuyHSM93 X-Gm-Gg: AR+sD116CAc9f3tdEyS0LuAcBWJMqmuFjrqNK/uOZatqs9tCRnrqteyc5YnjHKRLoBM KLmmm0w7hckwC+Clx210XSnRmTZNTEs6FlQ0yB5NHOpu5681DZ7/zeApvrakU3feS8CUIOkMrwu lo+o+gG4CoGWqV1pWC5ge5V9ZjuW1/pn4ji2ykAE+QGXfzNK1BZeuIWo01BIa4TEeHdyduq/lpl lfyUIqDNUJtAV5qFOdak7dCgV8uAhmOWmylpbsva96G9wMym7+DiC8pr0FNE3aGxTAByJYnqjIx dwtENnRv6BZg+65Gj0APQXDU11z55WUshwbWiZwCwYc+mkNhEhyBatURzAKmpZDWLxCwN6nwHNQ +aClyYEFyJU75l6JCBfHomeMV67jAiQBGpv49m+C683lDzfKp4CHR0NhPWZFm1Zzp/K7F/ibb9G ssjw0npcncVKVOyGDk07xCRBY44w26w61tc6mKTug51qRQ+o+US23GzwsLp+ffgugkXJWw6ccjx jZocs1x7IOvQqI= X-Received: by 2002:a17:90b:53cf:b0:38e:5964:97a8 with SMTP id 98e67ed59e1d1-3903c5bf453mr9300636a91.16.1785948236783; Wed, 05 Aug 2026 09:43:56 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang , Alistair Francis Subject: [PATCH v7 2/8] target/riscv: Enable Zicclsm for the compatible CPUs Date: Thu, 6 Aug 2026 00:43:39 +0800 Message-ID: <20260805164345.698208-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805164345.698208-1-frank.chang@sifive.com> References: <20260805164345.698208-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1785948357328158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang To support Zicclsm, let's enable Zicclsm for the following compatible CPUs: - Base 32 CPU (to be backward compatible) - Base 64 CPU (to be backward compatible) - XuanTie (T-Head) C908 - Tenstorrent Ascalon - Ventana Veyron V1 - XiangShan Kunminghu - MIPS P8700 (ISA doesn't include Zicclsm, but their datasheet claims that it has unaligned load/store support in hardware) Signed-off-by: Frank Chang Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a82e6563bf..7ee89f6fc4b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3268,6 +3268,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zicbom =3D true, .cfg.ext_zicbop =3D true, .cfg.ext_zicboz =3D true, + .cfg.ext_zicclsm =3D true, .cfg.ext_zicntr =3D true, .cfg.ext_zicsr =3D true, .cfg.ext_zifencei =3D true, @@ -3340,6 +3341,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zicbom =3D true, .cfg.ext_zicbop =3D true, .cfg.ext_zicboz =3D true, + .cfg.ext_zicclsm =3D true, .cfg.ext_zicntr =3D true, .cfg.ext_zicsr =3D true, .cfg.ext_zifencei =3D true, @@ -3426,6 +3428,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zbs =3D true, .cfg.ext_zkt =3D true, .cfg.ext_zbkc =3D true, + .cfg.ext_zicclsm =3D true, .cfg.ext_zicsr =3D true, .cfg.ext_zifencei =3D true, .cfg.ext_zihintpause =3D true, @@ -3469,6 +3472,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zicbom =3D true, .cfg.ext_zicbop =3D true, .cfg.ext_zicboz =3D true, + .cfg.ext_zicclsm =3D true, .cfg.ext_zicntr =3D true, .cfg.ext_zicond =3D true, .cfg.ext_zicsr =3D true, @@ -3518,6 +3522,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { =20 /* ISA extensions */ .cfg.mmu =3D true, + .cfg.ext_zicclsm =3D true, .cfg.ext_zifencei =3D true, .cfg.ext_zicsr =3D true, .cfg.pmp =3D true, @@ -3577,6 +3582,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { * The RISC-V Instruction Set Manual: Volume I * Unprivileged Architecture */ + .cfg.ext_zicclsm =3D true, .cfg.ext_zicntr =3D true, .cfg.ext_zihpm =3D true, .cfg.ext_zihintntl =3D true, @@ -3633,6 +3639,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU, .priv_spec =3D PRIV_VERSION_1_12_0, .cfg.max_satp_mode =3D VM_1_10_SV48, + .cfg.ext_zicclsm =3D true, .cfg.ext_zifencei =3D true, .cfg.ext_zicsr =3D true, .cfg.mmu =3D true, --=20 2.43.0 From nobody Mon Aug 24 09:08:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1785948318; cv=none; d=zohomail.com; s=zohoarc; b=cuyyoK/L7HOC0Tk568O9NMhfUHHeTTpNVa4/rsu5wahTVlfbYXfJWWjpER18bBQe6f1qbDdpCC2cMtMpAk4mUFq03URjdZcOenptToke+PFfXOwfYvNt41u4teHmzSDOMlYQ8yL0SMBcUzQc1hwwtRu5/y0mAfJx8uyZHpOvvPU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785948318; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GcM9CWd/ht3d20xl8qsrrISWs+dRJAPurFgEz0tOvKM=; b=Fy+qOdPCfJFqtx7xLeJF/1ycSu5nPagf65jJCXXoP6huQuJl3RMs2Z1qq0JkyC89LeN+H29Zkbxq9xlmedl7rtYSye//XjkPOI93GK7uHPtGzx3Mwe6vUAlJ8NgI3VuXXBC0W2S/BjRPSYGeAqruUHQ3ezBWKFycjqUcXWDnaTI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785948318863680.882776295263; Wed, 5 Aug 2026 09:45:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wreiq-0008Iy-It; Wed, 05 Aug 2026 12:44:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wreio-0008IH-Ew for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:02 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wreim-0001wa-Td for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:02 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-c96b08cdd1cso921943a12.0 for ; Wed, 05 Aug 2026 09:44:00 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3158644a195sm16719065eec.13.2026.08.05.09.43.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 09:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1785948239; x=1786553039; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=GcM9CWd/ht3d20xl8qsrrISWs+dRJAPurFgEz0tOvKM=; b=nXLiSCFwvEjVes3ni5KY3w14CZj9l7UMYhK8W1XOH4eaa9l30KFHFFBJBpKD4/wRSo ACGUMXb9zDPQBqArmKurHmDjJLDDR0/EnYtmEn87ADqZZIAJhqjLnzQrRadQk0vkPF9Z s7TszKKXIN1kvQ2n2wZ8qlg+Iqy3jt//1MFc2HCtx+9l4fEYEgAEsoSGMpvxAGxmku1S s1eRE6RHZJSAXelTHt7wNMpojHtaf1gF/TdwKbhWueD089RfDs1rDaYedNmlWPcj5JDj vGa6Re9wIMfGW7gR93PX5RbTRv+3C0V+ZMVX7MaTQbcMcts9a07Y61eXWY4Ws3cDW9WR U1cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785948239; x=1786553039; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=GcM9CWd/ht3d20xl8qsrrISWs+dRJAPurFgEz0tOvKM=; b=oXQDlkB64nEHYsJKAUj1NQxS0RCOrmKzlr+dEO45FjQz1fQ4Tb6Mbv3FkN/9CJsqIf PWC96hZxfZgYuBvGfAqc8MpAkGn0EmNQjbxHO2/Ry6hAPmnuG6S6Bbskj5gyEdGExk/V 4HSoZl/hNgDGYyCUsrCpRgki3Fi/xh7W5WzvFi+ZaApPYoEG2n24ni07H8cUQDXWvYJC K3xwefiFFwyMGQW6Y2wKkGzAlOwUN+lspluaHteIDvm4rb0X3nmgGqiaq3PhKsYaOvav cEi0xbypwDWjKHaBV5El39L7R3Q8E4xt/0PzDZIe+CAlAmdeMA7CUNZQ8xhslDFa+xek ZVRw== X-Gm-Message-State: AOJu0YzBUrWFWQGYW0c6p5ZO+z7+olcBjys257qqa7KUTR5FQ+2AhK9s DPg/gaU/VA/N7t9jyiMcKCFylUaXEuhEf+tL23V5zBCap+6lhvBoKj9tNDu8577SsDglpwli8CV FRqGgz6VSL/j0q/w76u0zgthlI1Pk5A1198AlMAFdidVROLufn6PtnxJah1eZcX3FovKwd36EOH wWdBdFa+WRuF0BMxv1zjGhRd3pFfQ8E/4FF9Zo89iCJzM31aIj X-Gm-Gg: AR+sD122538/9Amdk/A+CAV3u0X2Nww84GfAd2kFX83dP1NFfS2ufb0BG8Vle47PsCS 3Qdmu/EjHgs9Kn+XVx3cQv/uIj5nGu5xUByQjS2InsRFsJBwa80KAIEhMPRm2fGJekK7yU+XDdF 79Xv+BNHLi5giRLf9IvzoP1Z+M0uZF0KWdc7CcmWBO5Ium1kgMp2gwWUwKsThXYyY6Rxh9TyFRN S7tw3UsJtYHd7Qq89Jj2YWJCtLSMNhrsqUi2mdgnDIROrlHNd5m+Cy8C3iJKNG4ZX4mw7aGM21F 5TCSVZf0aztuoXOdFR879xfCsx52YlZ9JLTEeXE5BydXjoj1ucb00pEhBl7++GK4WquqWlGepHQ CXSMbFXgV7G0wkCIen3dShlQCXxZfDQjxPNZLl6u+wJy+YlZzawzkb1elLESmLmyTxUpChc0Qya ElnMQqvaRNizdjvwjSumAxYO84DJrxmZ1o5CwMktj4sJCYw6/Y6YtFqe2gUSz2t9gEA5aW5eb4w sFlW2QA2MqO9Y0= X-Received: by 2002:a05:6a21:2293:b0:3c3:994f:b4f5 with SMTP id adf61e73a8af0-3cb85eefa11mr11170785637.28.1785948239470; Wed, 05 Aug 2026 09:43:59 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang Subject: [PATCH v7 3/8] hw/riscv: sifive_u: Align ROM reset vector data Date: Thu, 6 Aug 2026 00:43:40 +0800 Message-ID: <20260805164345.698208-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805164345.698208-1-frank.chang@sifive.com> References: <20260805164345.698208-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1785948321177158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang The SiFive U ROM reset vector data needs proper 8-byte alignment for RV64 ld instructions. The misaligned load will cause exception when Zicclsm is supported as SiFive U CPU doesn't support hardware misaligned loads and stores. Add padding to ensure start_addr and fdt_load_addr are placed at 8-byte aligned offsets and adjust the load instruction offsets to match the new data layout. Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza --- hw/riscv/sifive_u.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 99423ef472d..57a57c96e16 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -564,19 +564,20 @@ static void sifive_u_machine_init(MachineState *machi= ne) 0, 0, 0x00028067, /* jr t0 */ + 0x00000000, /* padding for alignment */ start_addr, /* start: .dword */ start_addr_hi32, fdt_load_addr, /* fdt_laddr: .dword */ fdt_load_addr_hi32, - 0x00000000, /* fw_dyn: */ }; + if (riscv_is_32bit(&s->soc.u_cpus)) { - reset_vec[4] =3D 0x0202a583; /* lw a1, 32(t0) */ - reset_vec[5] =3D 0x0182a283; /* lw t0, 24(t0) */ + reset_vec[4] =3D 0x0242a583; /* lw a1, 36(t0) */ + reset_vec[5] =3D 0x01c2a283; /* lw t0, 28(t0) */ } else { - reset_vec[4] =3D 0x0202b583; /* ld a1, 32(t0) */ - reset_vec[5] =3D 0x0182b283; /* ld t0, 24(t0) */ + reset_vec[4] =3D 0x0242b583; /* ld a1, 36(t0) */ + reset_vec[5] =3D 0x01c2b283; /* ld t0, 28(t0) */ } =20 =20 --=20 2.43.0 From nobody Mon Aug 24 09:08:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1785948354; cv=none; d=zohomail.com; s=zohoarc; b=EMchzBvOY+LZaAiDZeKtRhXEg9wzr3JVB2M85e8unhBkdefOGJb1C257CyjzeVhVLK3zHw9kU0g/dZkGYQ/K3cnSlYkDezwe3Td6++U/yUCOn4yohduSXFOWQonEy4RDO87n+R/IFyCRZqFdSZAfFy6BthPt1XJCPxtps/v4EWU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785948354; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=l24jeh6mL402UPS1PQ1PqKY5L+GWjbvAW1P9ttSr/yU=; b=RjYw4Gze7xO+OCeYVz5xa2ELNa6tIGN+BMeXPnEQHTkVGZolGrP6RVjUeBG0rNosRXrhaDs4iMdigWoQPA/9TJP+Sr2NZkX05CpSODTmBGEC24pxR/Y3pu0oAL6PBCabIwJCDXWtwO+lYymDBsNO4OCgnvU1Ba6xfBNXHhvIJ/M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178594835446533.66989978157346; Wed, 5 Aug 2026 09:45:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wreiu-0008Jx-0w; Wed, 05 Aug 2026 12:44:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wreis-0008Jg-7m for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:06 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wreip-0001xw-Pv for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:05 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-c9fe3c9bd5fso51597a12.0 for ; Wed, 05 Aug 2026 09:44:03 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3158644a195sm16719065eec.13.2026.08.05.09.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 09:44:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1785948242; x=1786553042; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=l24jeh6mL402UPS1PQ1PqKY5L+GWjbvAW1P9ttSr/yU=; b=iws64pnaAVNrGkNF8T9kUiQnzyT62oVma39VGLsZLtLO9YJrRp0tjC6ANBemLKtRPg D7+I6bx2+3bYLuycmLy4TECUg94AbbR0MoMjlKGTTMxLP1k47ujxSrk6B0v4/qIah3O4 x0+dx0yvbuOuvZ/Q2l/CXD0i6ENOQIudUfn4Dbf91QwOlow+Ne9V3ibFUG4WmbE8ZzN3 hZCmHIN5EArr/2nD18bLSdnlhWf381xgiQkLmmD2mgeiyvbCu0ZjY5jY6oqG6TX9/qA6 UnTN2OstSY4UYQUOXwUBAfN+irWM7FezQkp6qZl+EzTa5EA7ImNB7Y84oUVZRvlUs4pe CMSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785948242; x=1786553042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=l24jeh6mL402UPS1PQ1PqKY5L+GWjbvAW1P9ttSr/yU=; b=N1papmjMYyF0iaRaYWyLc3j6htsCeXNjvD+MKMqj0dHsjFN3J1wp2UjOzeEyWZCvSg VzKFwsjPwERFxrGTlpotZuz2fOBd0GMCt+4UZrslcIbcey1C7Y1A8/Gr/Donn41jDCMJ EA5MWte0El50TNtYjvFVpv8pg9At1D4hBGfVFgV7+2XmsJpEsB7KorCajWeeJbwAP4tz GYb6U2KRY3BL2tH+ePaOC8jnIgZs4r+iSysknFuWs3YpS8QmPBKUjoQqQ6W4goo2oMH4 YP+v9ZPAa4zO83iHv81zYa2wRxfP3m1x2T/e1qxy8f4zJSm++WkIvDzO7OshR+bYypPS 8Pyg== X-Gm-Message-State: AOJu0YztcbkqHTJgktDpXpowXOZdUUeAPhUcmJ3QBjba5PJivR59FxZ2 iCix4I97lfpOnzFC8TbUF7hW3JjgRhJocHswXoKX9+E5eFVdRqIjh0GW4Se51QQaqiDMP9oqvEm zh0aWCwXRdtNUB41/Rf+QuXABdJEfhrvC/EMSx7HjrXygL2qCOL64tJIK1CQ5iAGRQviQzhszVy BAfRlFihDD0kOWeteQmK16VKAoIucF+xz2+ra3gBpnfkyKfK2y X-Gm-Gg: AR+sD133qbMOmefvnVVsybS27+SyTJo+QYK+tMglCaGWBpYoLhphkn5/h6m83E8MriA iPPEQJwqzd8t0ZyeeEb7VRPkBTUZoEgf8odY4QGGLkFPH8PtPYlb9a8xGqkWLJCWCAAEAp+W0Lm tPywDfpZ7nO38HoATIuufod6ES5BjcM8PijwBcCjdpciOr6ckjPqKFd07bOZimbk6EF5hwiCB60 lMPd0N47gYLxuZDV+qjkEcBe/q6/khH+TtecucKSFX/dzeJEsnI/Guc2M9qai3HpGC0lIN7w9TS /6eJ224TzXA+T1r1G6fd8MSjWWjQ55aVJXJHsMEor0S026Os7t3RhDE6dU2GCgJ5OwEp+aJ//pM KhZ2HpBzHRmEYTpQaU7notIPSY6n/1wJdwnVENbx1hMwEglI6jYoDbHu6bR/2jvZaK4gSKV76N+ k9pwpIsfO3g7frFTTl6PVA1u20GmcZNRlr+pxVPisbmcnnjRnlYSzOXMH/ZwxBFlN3RiEptguBX L+37803mBhM6F8= X-Received: by 2002:a05:6a21:6e97:b0:3b4:6af4:bdd5 with SMTP id adf61e73a8af0-3cb9c2374dfmr509366637.15.1785948242361; Wed, 05 Aug 2026 09:44:02 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang , Max Chou , Alistair Francis Subject: [PATCH v7 4/8] target/riscv: Support raising misaligned exceptions for scalar loads/stores Date: Thu, 6 Aug 2026 00:43:41 +0800 Message-ID: <20260805164345.698208-5-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805164345.698208-1-frank.chang@sifive.com> References: <20260805164345.698208-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1785948355307158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang When the Zicclsm extension is not enabled, raise misaligned load/store exceptions for misaligned accesses from scalar load/store instructions. Signed-off-by: Frank Chang Reviewed-by: Max Chou Reviewed-by: Alistair Francis --- target/riscv/tcg/insn_trans/trans_rvi.c.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/tcg/insn_trans/trans_rvi.c.inc b/target/riscv/tcg= /insn_trans/trans_rvi.c.inc index e47b16a7fa2..cc1b5dbbadc 100644 --- a/target/riscv/tcg/insn_trans/trans_rvi.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvi.c.inc @@ -413,6 +413,9 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemO= p memop) if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } + if (!ctx->cfg_ptr->ext_zicclsm) { + memop |=3D MO_ALIGN; + } decode_save_opc(ctx, 0); if (get_xl(ctx) =3D=3D MXL_RV128) { out =3D gen_load_i128(ctx, a, memop); @@ -524,6 +527,9 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, Mem= Op memop) if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } + if (!ctx->cfg_ptr->ext_zicclsm) { + memop |=3D MO_ALIGN; + } decode_save_opc(ctx, 0); if (get_xl(ctx) =3D=3D MXL_RV128) { return gen_store_i128(ctx, a, memop); --=20 2.43.0 From nobody Mon Aug 24 09:08:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1785948362; cv=none; d=zohomail.com; s=zohoarc; b=YfZEPvz9l2jNvOrHO/YnlCNaK0egl89inTu3Uc03uu1A1RZ70BVFIT2LjjLASxzG0OOJ293bsRqiIZvgvYaiclECKMiq96PcqnaM2q1fm+9LGFjtQFmMZMxMUKunrE8AvvSN4V34iBgne1B+aG1NYj/WblVapZtT1ltQ6VXTVL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785948362; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fQC/YI21g4WDDTrfzNXtxzDhPQ+c5T/h+/PxMuIADQc=; b=M83lVNH9KOmfTTas9kQK0czYnKEHvZCfDxh9hQF8w/70itwPxWDsl6G40WstKXZp5Ob0IJzgIvO3UmUJ/DINtzfs+C1R8MyJ8tlf5ulu5WslT0RY7ErNV5AC2vD4pZW+afmudLWm7EZylZj/6K6i7sgyP72X/qLYMcQ+00ZSKSw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785948362496452.5465913892049; Wed, 5 Aug 2026 09:46:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wreiu-0008L3-PP; Wed, 05 Aug 2026 12:44:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wreiu-0008K8-1q for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:08 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wreis-0001yN-F1 for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:07 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2cea3004256so15725305ad.0 for ; Wed, 05 Aug 2026 09:44:06 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3158644a195sm16719065eec.13.2026.08.05.09.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 09:44:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1785948245; x=1786553045; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=fQC/YI21g4WDDTrfzNXtxzDhPQ+c5T/h+/PxMuIADQc=; b=ObVOttRDi/4Ld/op2t7A+i4jl5ozG4L42VT0vGt0luomG3iojiDreoHNqAQFcIgHfu 7qjdlB9nbS8pLyFf+cFo+ebZdZUWgXTIXYKLrN/2DalNveNlhDHvivniq6p7lwDObwTh EiPIFmhukLlqEBlvM6iGIUWKmXaH2dcpd6aS1zsroc7MnXBSIF83S0AUhh14UulgeiRz bHCkz3GUFkcHKrKc68QqxMHSXlFJxQgydhb7Ccc9nImAoII75n1n7k7M5gb2iIESb2f1 u0+coC4xNvVt/OgK54Nxv+kdvVpZJ5cMmqS/yPorHhqPhtmuNL1aMcAcWMnVDy2LrWgR aPgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785948245; x=1786553045; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=fQC/YI21g4WDDTrfzNXtxzDhPQ+c5T/h+/PxMuIADQc=; b=R/OIT3ZpKg6l8IQHdTDwP7KN1xHpeIEeipAX/Zs8CzkeXp5ti0q2WrF5dkBQkmm3S/ bX/OKimeiGj6EHxrPAXbMnydVSORkF6w4ALRZCNe0nUjXk85iunM/zqrLhkCatAvjRfE xSZMML/nXy/Hpp8PypXRas8/OBsA8L60D0eZy0HaSOSRHX/eU2IcclAoasU/QuFCxm68 gvVSpeRUt8zYhzZZU+uAH76TNlDbO6rb0kTF1mqIMhVntAxwCzzf35gt8P7IQBPhZmeb hagTlR57xz9HgoA660i9e+drLlSwWnneBFZXxIZ5VXjRFD157ky3NmrqJsmkd5v8QxF7 6czw== X-Gm-Message-State: AOJu0YxMBPnnUxu2wBVo2211z3GfVm6bbsZUpMysT4pvQFlZk5zyaDkz PcgtXHZVQ5QMw8XUNEe/MLhQhEkTuGiUjtTauonfqxOrSF4EYb7M7r1Hax+dfs7RtcF9xmtiyRC hCy9IWRD0+932t6VNlv0T6MQed+TYJ7Ad3+VZwGFBQoHQE0PFod2P0nyKehE1vlh3AwJaNQWKjx j4nEXoMBIQMwBHYX9BpY9UBl2DYQl4rIhLk5creah29mu1AjrV X-Gm-Gg: AR+sD10npQcEcMloG+HC6Q6dt9wb3vn+fzSxk4gj+itpUA+F/be7vqqzRBRngDdTP8G BHSA7vU6pBpnkPFCY5jptBB473P6LBuUM8GP4JJt6HqchC3vpLKFGWVncanmcBWgs0pG/9+Vi1s wt4W3QjvSd9uHycyYudbA/gu/QesyKQyifT7PbWXPIO3AwwzkVni0vya06gg9K7YC7Qtg/DmqF6 xb3yiNxXlLqylLfjWbss/UQg6ioQEF3ShSrrR++xdRnEpwM5CegKo2dDeniVbD0yWcd5AXL77Dj BDdm44qru30AEFscWvfwcgPuV5YRXgoPoCrh9EGYD/0Pntcgr85e7/E3GPZkObxbSC98ZXONvHn lVdCrEcFu1w+sZh4Le4ScLRa1S2mZp1CTDF/EnPlPjSS9tZ4oqVtGZKACR0A1bock7sE2EXokUI FNfiFTYx76h279nhK3/g7t1UATxE2EAXGt/Ap3oYnqdRfqwyC7XvNHZ6t0XZFxWs+lhKuRormvj GDDba+h1s4BqT7B X-Received: by 2002:a05:6a20:e347:b0:3bd:3800:7538 with SMTP id adf61e73a8af0-3cb85ffdacamr9379164637.33.1785948245005; Wed, 05 Aug 2026 09:44:05 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang Subject: [PATCH v7 5/8] target/riscv: Support raising misaligned exceptions for floating-point loads/stores Date: Thu, 6 Aug 2026 00:43:42 +0800 Message-ID: <20260805164345.698208-6-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805164345.698208-1-frank.chang@sifive.com> References: <20260805164345.698208-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1785948363444158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang When the Zicclsm extension is not enabled, raise misaligned load/store exceptions for misaligned accesses from floating-point load/store instructions (RVF, RVD, Zfh). Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/insn_trans/trans_rvd.c.inc | 6 ++++++ target/riscv/tcg/insn_trans/trans_rvf.c.inc | 6 ++++++ target/riscv/tcg/insn_trans/trans_rvzfh.c.inc | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/target/riscv/tcg/insn_trans/trans_rvd.c.inc b/target/riscv/tcg= /insn_trans/trans_rvd.c.inc index 3b9a745520a..1be2bee9465 100644 --- a/target/riscv/tcg/insn_trans/trans_rvd.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvd.c.inc @@ -61,6 +61,9 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) memop |=3D MO_ATOM_IFALIGN; } memop |=3D ctx->mo_endianness; + if (!ctx->cfg_ptr->ext_zicclsm) { + memop |=3D MO_ALIGN; + } =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); @@ -86,6 +89,9 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) memop |=3D MO_ATOM_IFALIGN; } memop |=3D ctx->mo_endianness; + if (!ctx->cfg_ptr->ext_zicclsm) { + memop |=3D MO_ALIGN; + } =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); diff --git a/target/riscv/tcg/insn_trans/trans_rvf.c.inc b/target/riscv/tcg= /insn_trans/trans_rvf.c.inc index e935523c93c..481f7282da7 100644 --- a/target/riscv/tcg/insn_trans/trans_rvf.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvf.c.inc @@ -52,6 +52,9 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } + if (!ctx->cfg_ptr->ext_zicclsm) { + memop |=3D MO_ALIGN; + } =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); @@ -75,6 +78,9 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } + if (!ctx->cfg_ptr->ext_zicclsm) { + memop |=3D MO_ALIGN; + } =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); diff --git a/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc b/target/riscv/t= cg/insn_trans/trans_rvzfh.c.inc index f36b46c2118..88711fb0769 100644 --- a/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc @@ -50,6 +50,9 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 memop |=3D ctx->mo_endianness; + if (!ctx->cfg_ptr->ext_zicclsm) { + memop |=3D MO_ALIGN; + } decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -75,6 +78,9 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 memop |=3D ctx->mo_endianness; + if (!ctx->cfg_ptr->ext_zicclsm) { + memop |=3D MO_ALIGN; + } decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { --=20 2.43.0 From nobody Mon Aug 24 09:08:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1785948324; cv=none; d=zohomail.com; s=zohoarc; b=exJBmIZ8fK6ziy3ksGdAAEz3bCbZiXZ003BQXGGhh1WkKCEnx28Dc6wkA7jO3p+e5qocuI3MciX3HiDV6j0baO43p/31tORDOl81S1V4+DFCGCX57XhdOjPKW78cWvPBXC4qmDiiMUpanQxDd6SFggctIK+nE3M7P5vszLASktc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785948324; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=goBibbm903IrHGlQ25HxbHDhM5i9maTD/frlb0Y55Zo=; b=LDOI3UZP4r6IqU704mfgerzTi0sU4NeUwuIfMxGjBFP6OhDiS7hNOYdGt59aA/RJvXxCtHByYc547C/rR20exa8tE+FLul/X3fhymCnbI9UWwrjBH84i6e4HX28UH4mXTStckNdiyfgxY2Yk3FNPcQEbETz8Jj26j5+sSYyCud0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785948324105626.0731257420815; Wed, 5 Aug 2026 09:45:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wreiz-0008Ml-JW; Wed, 05 Aug 2026 12:44:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wreix-0008Lw-Eh for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:11 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wreiv-0001yz-KH for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:11 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-2ccf2360620so12945845ad.3 for ; Wed, 05 Aug 2026 09:44:09 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3158644a195sm16719065eec.13.2026.08.05.09.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 09:44:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1785948248; x=1786553048; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=goBibbm903IrHGlQ25HxbHDhM5i9maTD/frlb0Y55Zo=; b=GsBz0SYnqttbSOfd3cZpGDBaLMaER6E5QPvOOem+LxXLCgZbqf/Rsyxhd/Xt3+Irwr 90tEUAgdTfNjZEoXbOORB6TOjeNPIRW5j673Xft8azc0Eep+Qs9tMpYYnVpbrVzLlaPc f3gX6IHAwhGKm6dL+7lC70bg+q3oAImz5OtWCUXrTNmSBWdoBKYTmaDv0KD+zy/GBGMT xATFTB13UZr3TbW0D8fOzCD9dB/+WtUmKGIyUX6g4/w5OpT6oW5CdRIjRXhKSuUdybSN dJueebclhr7y/URLClKXqAI4+MQp0XiDO5q3Cq+4IhOQ+VRO38z51RvrRVmoQRCdtX0u zO5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785948248; x=1786553048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=goBibbm903IrHGlQ25HxbHDhM5i9maTD/frlb0Y55Zo=; b=P60OwR/fi1LrQNGhtD/NI+sKkIo/ZJFruRIsvyEkluuzXroyKgu1210zbeSFPH8Vuk z53BuhM1qurqGTsL6y/3AIlqYbs2waPijaiWdKvMXh3Lccu+FL0//LLdFWVyJlczlK27 t4NB2Ru6kKhWXmvjIdflwRIggtcOKPUahanPbTRb6b/y/vK2++i5Kwc2nyFy+/NQqPX3 Hqj9QUnv5DIVp3tKAasUru8m05cY42qXxFbzaaD7l+H6/YKWa1DGYCCANL7kBvlNAa9D SzPXNKhZjKnGOBlhgrb1IlK2sAOAYv644coywsrVstswyzXuT5wgiXOqyXkDZ+9YqRht +hnQ== X-Gm-Message-State: AOJu0YwSyD/HVgyjzetKbCouPZ82mcrAIpNyukej+9fK5hcjErJVcIo9 DOP4f4tHYLLNRErCrbHEindjPDVUuUzscl93BmnrNOEZHVoQ7tpG9oX9FNs7f2jrKmGbUViz6Wg HK6aAXXfbBMxuZbvQfDdznw50Ic4t0v/4eCsELnJ9Wirr5zshowKlbm803BJIMNJ56eMs/t9ZD0 2FDLNCCcde6qrd36C716mPOD1yRBlI5k/ZhJ/9s7N5+v63N/14 X-Gm-Gg: AR+sD12Fg1vNnkvhKOd4sOjeActFzbEaFMDCpJaSaRMsinXJ1c3D16EBbMEum9Y7FXG OYBjwtTg1XNnlTYYMzX17QwXfFpOvKPmdG0m+z+plP5T414+4pCyja73vDuGB5v9yhGInHEkgZc sdpBziSRiH+C9OKvXK2tAgN3Y6MNhfzdH6GdyaDuQ9/URuj2msTsK/n95nbTSvhVCfDXpv6/F/K yL7dJd4NkmlD9TIG0RtsRzyO80KHMPzaeWh1cTeP4fz0fAZtp6kRLgVZpyGYgJZwXQZFGE4FoEn 0A4Br0QmJ0FurFRSann7dtrobjyXULQTXjonOgxAPKMZoL3t/U+hEM4J/UJtIdS2IzOOsZV0L/1 5LKU5gib3cHG4Bt+3bSLl6p6JdzhsBPyE3kcWwtU3ITmVCCuiZTxnd7uZjylzXJuaz3I9ruGNl0 pkHgbSm6nCrwd9izGQiHUps1mE2J41KuO02ki3AueSNXw8eyqh5ddE4l7NOKM8BHzRaaLvCpnCp DdWVmyLpM0knWYi+da7sruQlw== X-Received: by 2002:a17:902:ebc3:b0:2d0:8b28:51ab with SMTP id d9443c01a7336-2d0ca712e65mr100338095ad.7.1785948247894; Wed, 05 Aug 2026 09:44:07 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang , Max Chou , Alistair Francis Subject: [PATCH v7 6/8] target/riscv: Support raising misaligned exceptions for vector loads/stores Date: Thu, 6 Aug 2026 00:43:43 +0800 Message-ID: <20260805164345.698208-7-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805164345.698208-1-frank.chang@sifive.com> References: <20260805164345.698208-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1785948325210158501 Content-Type: text/plain; charset="utf-8" From: Frank Chang When the Zicclsm extension is not enabled, raise misaligned load/store exceptions for misaligned accesses from vector load/store instructions. We will skip the host fast-path and fall back to the slow TLB-path to raise misaligned load/store exceptions for the misaligned accesses when Zicclsm extension is disabled. Signed-off-by: Frank Chang Reviewed-by: Max Chou Acked-by: Alistair Francis --- target/riscv/tcg/insn_trans/trans_rvv.c.inc | 18 +++++- target/riscv/tcg/vector_helper.c | 65 ++++++++++++++++----- 2 files changed, 65 insertions(+), 18 deletions(-) diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg= /insn_trans/trans_rvv.c.inc index 23262b1d036..a22e2cae6ce 100644 --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc @@ -1191,26 +1191,38 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t = rs1, uint32_t nf, * Use the helper function if either: * - vstart is not 0. */ - bool use_helper_fn =3D !s->vstart_eq_zero; =20 if (!use_helper_fn) { uint32_t size =3D s->cfg_ptr->vlenb * nf; TCGv_i64 t8 =3D tcg_temp_new_i64(); MemOp atomicity =3D MO_ATOM_NONE; + MemOp alignment =3D MO_UNALN; + + /* + * If Zicclsm is disabled, require alignment based on element size. + * Use MO_ALIGN_* based on log2_esz (0 =3D MO_UNALN, 1 =3D MO_ALIG= N_2, etc). + */ + if (!s->cfg_ptr->ext_zicclsm) { + alignment =3D log2_esz << MO_ASHIFT; + } + if (log2_esz =3D=3D 0) { atomicity =3D MO_ATOM_NONE; } else { atomicity =3D MO_ATOM_IFALIGN_PAIR; } + for (int i =3D 0; i < size; i +=3D 8) { TCGv addr =3D get_address(s, rs1, i); if (is_load) { - tcg_gen_qemu_ld_i64(t8, addr, s->mem_idx, MO_LEUQ | atomic= ity); + tcg_gen_qemu_ld_i64(t8, addr, s->mem_idx, + MO_LEUQ | atomicity | alignment); tcg_gen_st_i64(t8, tcg_env, vreg_ofs(s, vd) + i); } else { tcg_gen_ld_i64(t8, tcg_env, vreg_ofs(s, vd) + i); - tcg_gen_qemu_st_i64(t8, addr, s->mem_idx, MO_LEUQ | atomic= ity); + tcg_gen_qemu_st_i64(t8, addr, s->mem_idx, + MO_LEUQ | atomicity | alignment); } if (i =3D=3D size - 8) { tcg_gen_movi_i32(cpu_vstart, 0); diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_hel= per.c index e321ca26161..e28d8a3d9fd 100644 --- a/target/riscv/tcg/vector_helper.c +++ b/target/riscv/tcg/vector_helper.c @@ -199,20 +199,34 @@ static inline void vext_set_elem_mask(void *v0, int i= ndex, ((uint64_t *)v0)[idx] =3D deposit64(old, pos, 1, value); } =20 +static inline MemOpIdx vext_make_memop_idx(CPURISCVState *env, size_t size) +{ + int mmu_idx =3D riscv_env_mmu_index(env, false); + MemOp memop =3D size_memop(size) | mo_endian_env(env); + + if (!riscv_cpu_cfg(env)->ext_zicclsm) { + memop |=3D MO_ALIGN; + } + + return make_memop_idx(memop, mmu_idx); +} + /* elements operations for load and store */ typedef void vext_ldst_elem_fn_tlb(CPURISCVState *env, abi_ptr addr, uint32_t idx, void *vd, uintptr_t retad= dr); typedef void vext_ldst_elem_fn_host(void *vd, uint32_t idx, void *host); =20 -#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ +#define GEN_VEXT_TLB_LD_ELEM(NAME, ETYPE, H, LDSUF) \ static inline QEMU_ALWAYS_INLINE \ void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ uint32_t idx, void *vd, uintptr_t retaddr) \ { \ ETYPE *cur =3D ((ETYPE *)vd + H(idx)); \ - *cur =3D cpu_##LDSUF##_data_ra(env, addr, retaddr); \ + MemOpIdx oi =3D vext_make_memop_idx(env, sizeof(ETYPE)); \ + *cur =3D cpu_##LDSUF##_mmu(env, addr, oi, retaddr); \ } \ - \ + +#define GEN_VEXT_HOST_LD_ELEM(NAME, ETYPE, H, LDSUF) \ static inline QEMU_ALWAYS_INLINE \ void NAME##_host(void *vd, uint32_t idx, void *host) \ { \ @@ -220,20 +234,27 @@ void NAME##_host(void *vd, uint32_t idx, void *host) = \ *cur =3D (ETYPE)LDSUF##_p(host); \ } =20 -GEN_VEXT_LD_ELEM(lde_b, uint8_t, H1, ldub) -GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw_le) -GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl_le) -GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq_le) +GEN_VEXT_TLB_LD_ELEM(lde_b, uint8_t, H1, ldb) +GEN_VEXT_TLB_LD_ELEM(lde_h, uint16_t, H2, ldw) +GEN_VEXT_TLB_LD_ELEM(lde_w, uint32_t, H4, ldl) +GEN_VEXT_TLB_LD_ELEM(lde_d, uint64_t, H8, ldq) =20 -#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ +GEN_VEXT_HOST_LD_ELEM(lde_b, uint8_t, H1, ldub) +GEN_VEXT_HOST_LD_ELEM(lde_h, uint16_t, H2, lduw_le) +GEN_VEXT_HOST_LD_ELEM(lde_w, uint32_t, H4, ldl_le) +GEN_VEXT_HOST_LD_ELEM(lde_d, uint64_t, H8, ldq_le) + +#define GEN_VEXT_TLB_ST_ELEM(NAME, ETYPE, H, STSUF) \ static inline QEMU_ALWAYS_INLINE \ void NAME##_tlb(CPURISCVState *env, abi_ptr addr, \ uint32_t idx, void *vd, uintptr_t retaddr) \ { \ ETYPE data =3D *((ETYPE *)vd + H(idx)); \ - cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ + MemOpIdx oi =3D vext_make_memop_idx(env, sizeof(ETYPE)); \ + cpu_##STSUF##_mmu(env, addr, data, oi, retaddr); \ } \ - \ + +#define GEN_VEXT_HOST_ST_ELEM(NAME, ETYPE, H, STSUF) \ static inline QEMU_ALWAYS_INLINE \ void NAME##_host(void *vd, uint32_t idx, void *host) \ { \ @@ -241,10 +262,15 @@ void NAME##_host(void *vd, uint32_t idx, void *host) = \ STSUF##_p(host, data); \ } =20 -GEN_VEXT_ST_ELEM(ste_b, uint8_t, H1, stb) -GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw_le) -GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl_le) -GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq_le) +GEN_VEXT_TLB_ST_ELEM(ste_b, uint8_t, H1, stb) +GEN_VEXT_TLB_ST_ELEM(ste_h, uint16_t, H2, stw) +GEN_VEXT_TLB_ST_ELEM(ste_w, uint32_t, H4, stl) +GEN_VEXT_TLB_ST_ELEM(ste_d, uint64_t, H8, stq) + +GEN_VEXT_HOST_ST_ELEM(ste_b, uint8_t, H1, stb) +GEN_VEXT_HOST_ST_ELEM(ste_h, uint16_t, H2, stw_le) +GEN_VEXT_HOST_ST_ELEM(ste_w, uint32_t, H4, stl_le) +GEN_VEXT_HOST_ST_ELEM(ste_d, uint64_t, H8, stq_le) =20 static inline QEMU_ALWAYS_INLINE void vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_t= lb, @@ -398,7 +424,16 @@ vext_page_ldst_us(CPURISCVState *env, void *vd, target= _ulong addr, probe_pages(env, addr, size, ra, access_type, mmu_index, &host, &flags, true); =20 - if (flags =3D=3D 0) { + bool misaligned =3D addr & (esz - 1); + + /* + * Allow the host fast-pash when: + * 1. Page permission/pmp/watchpoint are checked and we have a conti= gous + * host mapping. + * 2. Zicclsm is enabled or load/store is not a misaligned access. + * Otherwise, we will fall back to the slow TLB-path. + */ + if (flags =3D=3D 0 && (riscv_cpu_cfg(env)->ext_zicclsm || !misaligned)= ) { if (nf =3D=3D 1) { vext_continuous_ldst_host(env, ldst_host, vd, evl, env->vstart, host, esz, is_load); --=20 2.43.0 From nobody Mon Aug 24 09:08:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1785948289; cv=none; d=zohomail.com; s=zohoarc; b=mTpnvLwKogu3QrWDmu9sMvtrp/5W2NzAfqS35Zp/T93eGXdx6bJrVUvgjYrhjatdsEORnO3Mm1zxx6gdnarTmc8vprfoMrUr3W75JJYfdQoPwW39iX8CslJHdbeSfJYKe0QxjYZkcXOimKbaGowWSXTAtdy9m/Hq14N6AFDk9Pc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785948289; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=O5v+4E6AH085JvEW/ulDh5E/YMq66y/1MyNCyiZh4NQ=; b=cJsQl1HQLH8tx/Q1DSTTCpswpHSOtQYqkp+PTunVUGFYpjIpnbDB3felsUDEBHsT7nO4QbXGqVXtQjuL8JXWRQQFxDoySzuyjGoAh695Sh4z2lzHgAkFxb81geOFaA4v1S5qg/3qLR+mOi4qlXiPVisv8SYz5SNVyXjFacZJ8qQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785948289559919.6524771709733; Wed, 5 Aug 2026 09:44:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrej1-0008NO-6g; Wed, 05 Aug 2026 12:44:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wreiz-0008Mq-MG for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:13 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wreiy-0001zO-6X for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:13 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2cea3004256so15727315ad.0 for ; Wed, 05 Aug 2026 09:44:11 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3158644a195sm16719065eec.13.2026.08.05.09.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 09:44:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1785948251; x=1786553051; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=O5v+4E6AH085JvEW/ulDh5E/YMq66y/1MyNCyiZh4NQ=; b=QmYnb3iwLhmBi58VIng7FQyHeN+hnyQzIJoudahIw291lkPePDY5I1lI9jwgU44pOZ iEP/sAEIXCHgARIabhDR7+Kz45rOOVoKXM+HJmorY1U7GVLbnhfvjJunK5gEkeE9SVbw atRqAirXSulMvoZt1396OOzqbU58hmjx/F6vVeY4Ljn2vM2RJQupAdLtZO8KzvxIxU8x rVw2MNB95Wo2xatM0CdMvQDyl580QS5Xt2aNSWGSrhqyXGoQ0lgE8YmHNi2l2xcvsqeS 0As/nI19VORS5N44kbefNzHT3FyfVur+7a9v7yIRaXcAOzW6ZVue3CwWuWZxq+fRvBcd 4fEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785948251; x=1786553051; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=O5v+4E6AH085JvEW/ulDh5E/YMq66y/1MyNCyiZh4NQ=; b=ZF1b0sgYVrNua/k9eTiK8/FppnEdJhEmZ/WRVcTScgO4JOL9FRz2d4/li4fmarhCX3 +uaBJ4WHXCTcF0TrdxardH5aTruVlcsTe1/AXE0lLpYjyvI8IizkmhAXpqPsW9Qz06xJ Ti9ORGqAbLYpYAN/kF6pI+g4Eg0yxyM+CeGFsnfsnYdurnlho04V6gGJv5vbnt2H0r4f F2pAnGF9yLxhEVrYcrTEoH9r2uiNZFTrsPH7U/Xg9LSdoP95ElyvwObQ2FVyRpGhDiMy tZZBqpKpykMIM3TGePimnruyr5sQ8ZGdIUV/syywEPwnljli9IlNVZK2mmM7nEzBfT5W 2umw== X-Gm-Message-State: AOJu0YzrgBZK2/4HPu8XVjL2R0W/CqH6u6UKLTxZZy5M2IV0S9uFQoWA c7CQ1ucXes7/H/gURPTYBeFIvmw+UcY40+sGquYePH3s66Ls7ZYxAL3SQw6OsC9eQ/4DYfGvey8 om4XichPBieHMm5kMR5Cyq+1Pzf/U/Uha5nYOekQPfmHgBTrQN7K0BUDScDQbDQrSQv5QlqiJsl ts5vrCB/b3YoHHSsuN77uTT2v00WoysyHNg3jU5T+8+XIq0+Bk X-Gm-Gg: AR+sD11qq/A8Sz2o/tW2Wq5P9srxbtt3F8I7omGQyX6YItd1o+DzjOV/Sqbqgq1784h 8d1BuNi1Likpffxog0mBD3YqqN6OOy8Cu3IGvnBtXdP7Cg4bpvSmSUu0Jd6k9uVZsIvvbxxQ72L R24vcM9JVfz1koV+ruqmNwwnbuQReUo48/2ZFuEwYwr5Xe16PsPmiuYjHcX/23BUfTMNIyqNIL4 4o1jRYghD9TwhxsOS+YXLjXcBM/Hk1cMSpYiFsBEi6ZvbX6kQXZgB7oc458/H9sllP/9785cQgo YZaJ9F7L+meKhH4+8/FnOo+RJX6Gkqu1n96IFYEeBXvdSJkWDHFi6A+9YQBRFqGeJlRVADFUksb k36d/kMnVEuhcJSmJFQ7TmPms3yLSWckMdzCeikBflO9vUH3wqzMxLxWzl6Cuyu7xXAF75wxXxX jH2tOcV3aMPTYvTSOeeF3RcTv/SdcOT20VpDpAKg90vqjj77HwbmBseqCQsneIe0BovO+U2CRja WsKPmaRzbndpUg= X-Received: by 2002:a17:902:f60c:b0:2cc:6329:b7ba with SMTP id d9443c01a7336-2d0ca7835a7mr98497315ad.16.1785948250541; Wed, 05 Aug 2026 09:44:10 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang Subject: [PATCH v7 7/8] target/riscv: Expose Zicclsm as a CPU property and update RVA22U64 profile Date: Thu, 6 Aug 2026 00:43:44 +0800 Message-ID: <20260805164345.698208-8-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805164345.698208-1-frank.chang@sifive.com> References: <20260805164345.698208-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1785948291119158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang Update Zicclsm ISA string and expose it as a CPU property to allow user to turn on/off Zicclsm extension. In addition, Zicclsm extension is mandatory for the RVA22U64 profile. Previously, Zicclsm was enabled automatically when has_priv_1_11 was true. Now that Zicclsm has been converted to an explicit CPU option, it must be explicitly added to the RVA22U64 profile's extension list to ensure the profile remains compliant with the specification. Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7ee89f6fc4b..19b93f9c979 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -164,7 +164,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), ISA_INTERNAL_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, has_priv_1_= 11), ISA_INTERNAL_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, has_priv_1_11= ), - ISA_INTERNAL_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_1= 1), + ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, ext_zicclsm), ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, ext_ziccrse), ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp), ISA_EXT_DATA_ENTRY(zicfiss, PRIV_VERSION_1_13_0, ext_zicfiss), @@ -2237,6 +2237,7 @@ static RISCVCPUProfile RVA22U64 =3D { CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz), + CPU_CFG_OFFSET(ext_zicclsm), =20 /* mandatory named features for this profile */ CPU_CFG_OFFSET(ext_zic64b), --=20 2.43.0 From nobody Mon Aug 24 09:08:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1785948325; cv=none; d=zohomail.com; s=zohoarc; b=ES8mMeGbj9Dcs8SVD/O3rw0dKD9WNneRE8jiktBmlcJ3f1d7IM9gHXPgrQlMomUTJmOwN4s4U5pzffDzKfjrtGbtQ2tSCbkqAtQZYfdf1LRZq9OM40wxMJWSFtEgLzJvwTuAIRRKoA6G7Ok0Om6Ff5Vo3n4FzF637QzCFvYvmm4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785948325; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DkGanTBZjokH12OxbvFYUsLKpt3IuwRYqkdHv+CL65A=; b=fTcbbLBfg32pvD0TVZ2Vpk5a0FkVyEXQ9guHu3Y5DX7xYDLaYx+rFD/aOIGHHyBSNdhs9Wp34wQDO/kIuyvjP0QOc22eWgrn6ZPoJsHw6QRJa5FNg9RW3JSU18o9Uu+gmbUCRQRpVpFmFmFkxIolseZp5YffLZ7YLDsSO6PY6vQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785948325568262.5825415285176; Wed, 5 Aug 2026 09:45:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrej4-0008OO-Ji; Wed, 05 Aug 2026 12:44:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wrej3-0008Nu-9l for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:17 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wrej0-0001zs-T1 for qemu-devel@nongnu.org; Wed, 05 Aug 2026 12:44:17 -0400 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-38e3efab7e0so78670a91.0 for ; Wed, 05 Aug 2026 09:44:14 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3158644a195sm16719065eec.13.2026.08.05.09.44.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 09:44:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1785948253; x=1786553053; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=DkGanTBZjokH12OxbvFYUsLKpt3IuwRYqkdHv+CL65A=; b=ZLXDXPEnlAig0LvUQSMzl3svZTbaOM3IaJwSJqB27OWc2GW9nZ1IvlB2w70kqDyy86 eFSeTQnY/5dVdUMMfwFdlSdizO/a4Inye/fhT1Ynk7cBG+9tr5bc0aoPlkMWYkdD4Nw1 UWre3RQP1P+uorUfgOrUdNa9UZSC+l8ipS7kDFu4A6uCsvgVeIdHycnG/L0pYOO3MOgT 7z1qhzE45gMSAkJeU6qUd1MqfZtQDgVrTyWRJ4o9uEE3bEt3x0IvAXR7qwtUKPZ6/NkG 7dy095dOVTsbSNYJnCvfW59m9woT3sMQyBpC4P6CeEQ4uMk0zCC3ZztEYkWOvGiR0Cz8 2tcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785948253; x=1786553053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=DkGanTBZjokH12OxbvFYUsLKpt3IuwRYqkdHv+CL65A=; b=rOSUtqJz52d7SHomdguQgXPAqThZ72m6CgqDTwOOW8VdpqE9P3sdeYS6AN0P0SpUex 1IcLH7D0swVjL5iyArO1yerwhl+S1jP2DQr0QenZZJSGDXZZ31YEM6IZyR4CBy2GW/TI BDRRi/4pk+k3dnCIJouDL/LymkTlwFT2liVZcTR5c4JYk6e1whVhBL3sJYJnzQVmMRxe XqaOCGxDlofL6tYAjTU41nIfXFB1qDdmD/xUvhFqTdi+WZNjuAPw5Y/gn/n9Q1h9wcou m3G8xqvVGwti3yVcYwbyj+bEID249IZu1EFJfRbUKGiUxWNrQgiWnwMaF/ZTLcAbexRJ J4+w== X-Gm-Message-State: AOJu0YzcAtO+tQ1/kILBJAb2iDG6Xcr2SNJLif4Bu8O8GlsPOGvdXhAG +J8Bl2KJIVjw5itg1yEuX+UXVQjHIV0bU4vYJSCTNT6UGc0UIHMpad/JsYvPSENrxHk69p6d+QU yaT3NNLlJn0sTvvZs3f5ybaolcQr3qxncgCb9J+Lv6dcOhZe5AX2n5AX52I+XDP6PLyUrOwL8w2 zo+l/AtjSnOt4RbNn+wuPMHs+O+PTGgQW2ljj6NXNoqLXuhk9b X-Gm-Gg: AR+sD103nx54qixoFYVFivm9SLuFdnUXiVSToXG2YMofoMRLFKpypFs2lwXGYigOnh6 rLI2Lv+Q9lhYYrRV+uquMBDiJUyVMeck0Fz87AH3v8ZpOJvBXrztDyji5E9I6ZADxk+PQcT8wnN X8WhKpRo1I+CDiEDWtzhBoe7PIf6B64Ktiq6CPt9bMZTwosft+s3Be+3RqD+Gh37ZwRLKjToTyn o9u6QZGL5Fs501wBq/gTxAZNDN73rPVoYvG2vnWT6kgDDxTXj3ASqfsTYk+H/IhoHjavQHicwCN JKDdDgE+PAJtQjuoTds2VJSGE/cfZvmCvPNwkyxBGCmwCfckc3dN05k9/H5iuw6ZqrPKjqyos95 0RVtazUDM0FrxQ1M6abQZzv/VGjuTidnboQpAJIDBDNh3JKzDZXtLh2JFBux4rNNWny/O9dCNdU Zi6WspN4DnetP65EjURPBe5zQPL9AQqUDwiHeYXzTqvEG60VSpn2EE4q+K66gNkh5UQ68MX6u+K +ZLi5n1/6x7LBs= X-Received: by 2002:a17:90b:578f:b0:380:86d8:8162 with SMTP id 98e67ed59e1d1-39083b3dab1mr243749a91.18.1785948253164; Wed, 05 Aug 2026 09:44:13 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang Subject: [PATCH v7 8/8] tests/tcg/riscv64: Add test for Zicclsm Date: Thu, 6 Aug 2026 00:43:45 +0800 Message-ID: <20260805164345.698208-9-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805164345.698208-1-frank.chang@sifive.com> References: <20260805164345.698208-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1785948327217158501 Content-Type: text/plain; charset="utf-8" From: Frank Chang Cover scalar, floating-point, vector, and segmented misaligned accesses with Zicclsm enabled and disabled. Clean up both generated test binaries. To build and run the tests: make -C build/tests/tcg/riscv64-softmmu \ CC=3Driscv64-unknown-elf-gcc LD=3Driscv64-unknown-elf-ld \ test-zicclsm test-zicclsm-off make -C build/tests/tcg/riscv64-softmmu \ run-test-zicclsm run-test-zicclsm-off To clean the generated binaries and objects: make -C build/tests/tcg/riscv64-softmmu clean Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza --- tests/tcg/riscv64/Makefile.softmmu-target | 22 ++ tests/tcg/riscv64/test-zicclsm.S | 368 ++++++++++++++++++++++ 2 files changed, 390 insertions(+) create mode 100644 tests/tcg/riscv64/test-zicclsm.S diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/= Makefile.softmmu-target index 82be8a2c915..908fd008e4c 100644 --- a/tests/tcg/riscv64/Makefile.softmmu-target +++ b/tests/tcg/riscv64/Makefile.softmmu-target @@ -41,5 +41,27 @@ comma:=3D , run-test-crc32: test-crc32 $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=3Dtrue $(QEMU_OPTS)$<) =20 +# Zicclsm: misaligned load/store support. Assemble one source twice: the +# default build expects every misaligned access to succeed (zicclsm=3Dtrue= ), +# the -DZICCLSM_DISABLED build expects every one to trap (zicclsm=3Dfalse). +ZICCLSM_MARCH =3D -march=3Drv64gcv_zfh +CLEANFILES +=3D test-zicclsm test-zicclsm-off + +test-zicclsm: test-zicclsm.S $(LINK_SCRIPT) + $(CC) $(CFLAGS) $(ZICCLSM_MARCH) $< -Wa,--noexecstack -c -o test-zicclsm.o + $(LD) $(LDFLAGS) test-zicclsm.o -o $@ + +test-zicclsm-off: test-zicclsm.S $(LINK_SCRIPT) + $(CC) $(CFLAGS) $(ZICCLSM_MARCH) -DZICCLSM_DISABLED $< -Wa,--noexecstack = -c -o test-zicclsm-off.o + $(LD) $(LDFLAGS) test-zicclsm-off.o -o $@ + +EXTRA_RUNS +=3D run-test-zicclsm +run-test-zicclsm: test-zicclsm + $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=3Dtrue$(comma)zfh=3Dtrue$= (comma)zicclsm=3Dtrue $(QEMU_OPTS)$<) + +EXTRA_RUNS +=3D run-test-zicclsm-off +run-test-zicclsm-off: test-zicclsm-off + $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=3Dtrue$(comma)zfh=3Dtrue$= (comma)zicclsm=3Dfalse $(QEMU_OPTS)$<) + # We don't currently support the multiarch system tests undefine MULTIARCH_TESTS diff --git a/tests/tcg/riscv64/test-zicclsm.S b/tests/tcg/riscv64/test-zicc= lsm.S new file mode 100644 index 00000000000..a2f217c0d1e --- /dev/null +++ b/tests/tcg/riscv64/test-zicclsm.S @@ -0,0 +1,368 @@ +/* + * Test the Zicclsm extension (misaligned load/store support). + * + * This single source is assembled twice: + * - test-zicclsm : run on a CPU with zicclsm=3Dtrue. Every misalig= ned + * scalar integer, floating-point and vector + * load/store must complete WITHOUT raising a trap. + * - test-zicclsm-off : built with -DZICCLSM_DISABLED and run on a CPU = with + * zicclsm=3Dfalse. Every misaligned access must r= aise a + * misaligned load/store exception, with the corre= ct + * mcause and mtval. + * + * Zicclsm governs all regular scalar loads/stores (integer and F/D/Zfh + * floating-point) as well as vector element loads/stores. Floating-point + * loads/stores (flh/flw/fld, fsh/fsw/fsd) are therefore exercised here. + * + * Atomic (A/Zacas/...) accesses are intentionally excluded: they always + * require natural alignment regardless of Zicclsm. Likewise cm.push/cm.p= op + * (Zcmp) are excluded, as they are not regular loads/stores. + * + * Register conventions (persist across the whole test; the trap handler o= nly + * clobbers t0-t4): + * s1 =3D expected mcause for the pending misaligned access + * s2 =3D expected mtval (the misaligned address) + * s3 =3D trap counter (incremented by the handler) + * s4 =3D base address of the aligned data buffer + * s5 =3D snapshot of s3 taken before an access, used to check the delta + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + .option norelax + .option norvc + +/* RISC-V exception causes (see target/riscv/cpu_bits.h). */ +#define CAUSE_LOAD_MISALIGNED 0x4 +#define CAUSE_STORE_MISALIGNED 0x6 + +/* + * EXPECT sets up the expectation for the access that immediately follows = and + * snapshots the trap counter. + * \cause =3D expected mcause if the access traps + * \off =3D byte offset from the buffer base; also the expected mtval + */ + .macro EXPECT cause, off + li s1, \cause + addi s2, s4, \off + mv s5, s3 + .endm + +/* + * CHECK validates the outcome of the preceding access. + * - When Zicclsm is disabled, exactly one trap must have fired. + * - When Zicclsm is enabled, no trap must have fired. + */ + .macro CHECK +#ifdef ZICCLSM_DISABLED + addi s5, s5, 1 + bne s3, s5, fail +#else + bne s3, s5, fail +#endif + .endm + +/* In the enabled case, also verify the value returned by scalar loads. */ + .macro CHECK_VALUE value +#ifndef ZICCLSM_DISABLED + li t0, \value + bne a2, t0, fail +#endif + .endm + +/* Verify bytes written by an enabled scalar store. */ + .macro CHECK_BYTE off, value +#ifndef ZICCLSM_DISABLED + lbu t0, \off(s4) + li t1, \value + bne t0, t1, fail +#endif + .endm + + .text + .global _start +_start: + /* Install the trap handler. */ + lla t0, trap + csrw mtvec, t0 + + /* Enable the FP (FS) and Vector (VS) unit state so F/D/V instructions + * do not trap as illegal. 0x6600 =3D FS[14:13]=3D11 | VS[10:9]=3D11. */ + li t0, 0x6600 + csrs mstatus, t0 + + /* Initialise persistent state. */ + li s3, 0 /* trap counter */ + lla s4, buf /* aligned buffer base */ + + /* + * ---- Scalar integer loads ---- + * lh/lhu need 2-byte alignment; lw/lwu 4-byte; ld 8-byte. + */ + EXPECT CAUSE_LOAD_MISALIGNED, 1 + lh a2, 1(s4) + CHECK + CHECK_VALUE 0x2211 + EXPECT CAUSE_LOAD_MISALIGNED, 1 + lhu a2, 1(s4) + CHECK + CHECK_VALUE 0x2211 + + EXPECT CAUSE_LOAD_MISALIGNED, 1 + lw a2, 1(s4) + CHECK + CHECK_VALUE 0x44332211 + EXPECT CAUSE_LOAD_MISALIGNED, 3 + lw a2, 3(s4) + CHECK + CHECK_VALUE 0x66554433 + EXPECT CAUSE_LOAD_MISALIGNED, 1 + lwu a2, 1(s4) + CHECK + CHECK_VALUE 0x44332211 + + EXPECT CAUSE_LOAD_MISALIGNED, 1 + ld a2, 1(s4) + CHECK + CHECK_VALUE 0x8877665544332211 + EXPECT CAUSE_LOAD_MISALIGNED, 3 + ld a2, 3(s4) + CHECK + CHECK_VALUE 0xaa99887766554433 + EXPECT CAUSE_LOAD_MISALIGNED, 7 + ld a2, 7(s4) + CHECK + CHECK_VALUE 0xeeddccbbaa998877 + + /* + * ---- Scalar integer stores ---- + */ + li t6, 0x1122334455667788 + EXPECT CAUSE_STORE_MISALIGNED, 1 + sh t6, 1(s4) + CHECK + CHECK_BYTE 1, 0x88 + CHECK_BYTE 2, 0x77 + + EXPECT CAUSE_STORE_MISALIGNED, 1 + sw t6, 1(s4) + CHECK + CHECK_BYTE 1, 0x88 + CHECK_BYTE 2, 0x77 + CHECK_BYTE 3, 0x66 + CHECK_BYTE 4, 0x55 + EXPECT CAUSE_STORE_MISALIGNED, 3 + sw t6, 3(s4) + CHECK + CHECK_BYTE 3, 0x88 + CHECK_BYTE 4, 0x77 + CHECK_BYTE 5, 0x66 + CHECK_BYTE 6, 0x55 + + EXPECT CAUSE_STORE_MISALIGNED, 1 + sd t6, 1(s4) + CHECK + CHECK_BYTE 1, 0x88 + CHECK_BYTE 2, 0x77 + CHECK_BYTE 3, 0x66 + CHECK_BYTE 4, 0x55 + CHECK_BYTE 5, 0x44 + CHECK_BYTE 6, 0x33 + CHECK_BYTE 7, 0x22 + CHECK_BYTE 8, 0x11 + EXPECT CAUSE_STORE_MISALIGNED, 7 + sd t6, 7(s4) + CHECK + CHECK_BYTE 7, 0x88 + CHECK_BYTE 8, 0x77 + CHECK_BYTE 9, 0x66 + CHECK_BYTE 10, 0x55 + CHECK_BYTE 11, 0x44 + CHECK_BYTE 12, 0x33 + CHECK_BYTE 13, 0x22 + CHECK_BYTE 14, 0x11 + + /* + * ---- Floating-point loads ---- + * flh needs 2-byte alignment; flw 4-byte; fld 8-byte. Their alignment + * is governed by Zicclsm just like the scalar integer forms. + */ + EXPECT CAUSE_LOAD_MISALIGNED, 1 + flh fa0, 1(s4) + CHECK + + EXPECT CAUSE_LOAD_MISALIGNED, 1 + flw fa0, 1(s4) + CHECK + EXPECT CAUSE_LOAD_MISALIGNED, 3 + flw fa0, 3(s4) + CHECK + + EXPECT CAUSE_LOAD_MISALIGNED, 1 + fld fa0, 1(s4) + CHECK + EXPECT CAUSE_LOAD_MISALIGNED, 7 + fld fa0, 7(s4) + CHECK + + /* + * ---- Floating-point stores ---- + */ + EXPECT CAUSE_STORE_MISALIGNED, 1 + fsh fa0, 1(s4) + CHECK + + EXPECT CAUSE_STORE_MISALIGNED, 1 + fsw fa0, 1(s4) + CHECK + EXPECT CAUSE_STORE_MISALIGNED, 3 + fsw fa0, 3(s4) + CHECK + + EXPECT CAUSE_STORE_MISALIGNED, 1 + fsd fa0, 1(s4) + CHECK + EXPECT CAUSE_STORE_MISALIGNED, 7 + fsd fa0, 7(s4) + CHECK + + /* + * ---- Vector unit-stride loads / stores ---- + * A base address that is not aligned to the element size (SEW) is + * misaligned for the first element access. + */ + vsetvli t1, x0, e16, m1, ta, ma + EXPECT CAUSE_LOAD_MISALIGNED, 1 + addi a0, s4, 1 + vle16.v v0, (a0) + CHECK + EXPECT CAUSE_STORE_MISALIGNED, 1 + addi a0, s4, 1 + vse16.v v0, (a0) + CHECK + + vsetvli t1, x0, e32, m1, ta, ma + EXPECT CAUSE_LOAD_MISALIGNED, 1 + addi a0, s4, 1 + vle32.v v0, (a0) + CHECK + EXPECT CAUSE_STORE_MISALIGNED, 3 + addi a0, s4, 3 + vse32.v v0, (a0) + CHECK + + vsetvli t1, x0, e64, m1, ta, ma + EXPECT CAUSE_LOAD_MISALIGNED, 1 + addi a0, s4, 1 + vle64.v v0, (a0) + CHECK + EXPECT CAUSE_STORE_MISALIGNED, 7 + addi a0, s4, 7 + vse64.v v0, (a0) + CHECK + + /* + * ---- Vector strided loads / stores ---- + */ + vsetvli t1, x0, e32, m1, ta, ma + li a1, 8 /* stride in bytes */ + EXPECT CAUSE_LOAD_MISALIGNED, 1 + addi a0, s4, 1 + vlse32.v v0, (a0), a1 + CHECK + EXPECT CAUSE_STORE_MISALIGNED, 1 + addi a0, s4, 1 + vsse32.v v0, (a0), a1 + CHECK + + /* ---- Vector indexed loads / stores ---- */ + /* + * Zero indices keep the first element at the deliberately misaligned bas= e. + */ + vmv.v.i v1, 0 + EXPECT CAUSE_LOAD_MISALIGNED, 1 + addi a0, s4, 1 + vluxei32.v v0, (a0), v1 + CHECK + EXPECT CAUSE_STORE_MISALIGNED, 1 + addi a0, s4, 1 + vsuxei32.v v0, (a0), v1 + CHECK + + /* ---- Vector segmented loads / stores ---- */ + EXPECT CAUSE_LOAD_MISALIGNED, 1 + addi a0, s4, 1 + vlseg2e32.v v0, (a0) + CHECK + EXPECT CAUSE_STORE_MISALIGNED, 1 + addi a0, s4, 1 + vsseg2e32.v v0, (a0) + CHECK + + /* + * ---- Vector whole-register load ---- + * Only the whole-register *load* forms carry an element width + * (vl1re32.v =3D> EEW=3D32), so only they enforce alignment when Zicclsm= is + * off. The whole-register store form (vs1r.v) is defined as EEW=3D8 + * (byte granular) and therefore never faults on misalignment, so it is + * not exercised here. + */ + EXPECT CAUSE_LOAD_MISALIGNED, 1 + addi a0, s4, 1 + vl1re32.v v1, (a0) + CHECK + + /* Success. */ + li a0, 0 + j _exit + + /* + * Trap handler: validate mcause and mtval against the expectation, bump + * the trap counter, then skip past the faulting instruction. The + * instruction length is decoded from its low two bits (0b11 =3D> 4 bytes, + * otherwise a 2-byte compressed instruction). + */ + .balign 4 +trap: + csrr t0, mcause + bne t0, s1, fail + csrr t1, mtval + bne t1, s2, fail + addi s3, s3, 1 + + csrr t0, mepc + lhu t2, 0(t0) + andi t3, t2, 3 + li t4, 3 + bne t3, t4, 1f + addi t0, t0, 4 /* 32-bit instruction */ + j 2f +1: + addi t0, t0, 2 /* 16-bit compressed instruction */ +2: + csrw mepc, t0 + mret + +fail: + li a0, 1 +_exit: + lla a1, semiargs + li t0, 0x20026 /* ADP_Stopped_ApplicationExit */ + sd t0, 0(a1) + sd a0, 8(a1) + li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */ + .balign 16 + slli zero, zero, 0x1f + ebreak + srai zero, zero, 0x7 + j . + + .data + .balign 16 +semiargs: + .space 16 + .balign 64 +buf: + .byte 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 + .byte 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff + .space 240 --=20 2.43.0