Switched to a new branch '20260805164345.698208-1-frank.chang@sifive.com'
Applying: target/riscv: Add Zicclsm CPU option
Applying: target/riscv: Enable Zicclsm for the compatible CPUs
Applying: hw/riscv: sifive_u: Align ROM reset vector data
Applying: target/riscv: Support raising misaligned exceptions for scalar loads/stores
Applying: target/riscv: Support raising misaligned exceptions for floating-point loads/stores
Applying: target/riscv: Support raising misaligned exceptions for vector loads/stores
Applying: target/riscv: Expose Zicclsm as a CPU property and update RVA22U64 profile
Applying: tests/tcg/riscv64: Add test for Zicclsm
Warning: Permanently added 'github.com' (ED25519) to the list of known hosts.
To github.com:patchew-project/qemu
 + d7e43e5de9...407cb59c5b patchew/20260805164345.698208-1-frank.chang@sifive.com -> patchew/20260805164345.698208-1-frank.chang@sifive.com (forced update)