From nobody Wed Aug 26 20:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1785943930; cv=none; d=zohomail.com; s=zohoarc; b=Z8KHDm7h8Wq/qye6Ljd1krFUehOJpf7Nw+NjpSvW3GVCgC8SgKOgXcS/CohA256qUqWRurCl4NXY8t9i7ofFiUsu2uL+h0yz05pQL8P3KAOaOz6uu+vjbcu/BAFveJRs6GlDgfYImLhnrj6CaT+3AzHijrIHB5DPul3QIt+zyD0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785943930; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gOu86j/s+4k/C1Vcjz8sgwYcvvMNp55MwKcmmYQitoI=; b=AVQl7hSUvm5fdU6KysgWrZVGvMzJcYSHJNSINMWEqtjSWReAw33SIIVr1qUNndThSpvQv9CytnnlglREf6DhDfVshHzsgfbPPl2EI2o8BK0mLmc0B9OokaUWlPicw/na5I3fCzNVmPwd43MrCbaJt7GxVOyqheVt7euqrWjG1IM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785943930193908.2230348713439; Wed, 5 Aug 2026 08:32:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrdZO-0005mH-FI; Wed, 05 Aug 2026 11:30:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wrdZM-0005lM-Tr for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:12 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wrdZK-0007bn-Gs for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:12 -0400 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-495c49f8eccso753152b6e.3 for ; Wed, 05 Aug 2026 08:30:10 -0700 (PDT) Received: from HPE-2MQ6131DV6.ams.hpecorp.net ([170.85.99.9]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae75ce1bsm2185614b6e.15.2026.08.05.08.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 08:30:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785943809; x=1786548609; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=gOu86j/s+4k/C1Vcjz8sgwYcvvMNp55MwKcmmYQitoI=; b=I/L6e0hf5U/0/mwtjWfJkJNnsAh/ju0e3YxGfn5/15ECblat+vbqDU8F2fizRC06Xl DW59fk6Gmg/AF6k8meiJ+o4TIZF2odbT8K9nGA8uVOt+zBub7XlNs0ygtWc0JRvodARz 3gO0NC2NqssljbjYxuC7nuJpsvrmH8gouVUSzjhxpbNY+4zOpveAEa6LRQKebZWzE/E8 brMqChQeod9B/ZMoBeFaCtbRwb/zM7M3gaH2rDqIBEX+YKT1nIzJ4zAFeyli+kFM97dt 9QxGjZTND32Rb7h9zVgAiX8Ny+PcT1g7jyiTDzf/a0ejIeTOM8e5xxWk3CX5xfGPMmVX DwsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785943809; x=1786548609; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=gOu86j/s+4k/C1Vcjz8sgwYcvvMNp55MwKcmmYQitoI=; b=M+esX7lvovo49VvldVpmoOtgnBVeEbavPvnsRXkaCDvcgLCdtg29KMeQ67pcH0a2Bm VPWal1fQ4mRVzSngZ+dr93DpAdqNp4JLdF7XtB+1YKwFkDGNjHLMn5372HM+mn7Cqe51 VMynrx7fWwfapWCWQatAQV/xa5TIwpRleRfXIlcKYrxxOVMLiijeFaW+cUkLsE/I2qLf t4CxG1i/AewK3hVk7+GqKK/KzXqUk1YHHV5HeNLqjs8B5I6YG7XdwQwgV8Naie37ULZ/ 0nIhZf8udDia+yLVmTWIrt5p6tzqh43xkutaq8FUWvd+azviXqG/vark/OnbQPjMvmUc Ur7Q== X-Gm-Message-State: AOJu0YymIKu3Z1TmnQS0czknp5mGN+eJ3Sqfrc/gNct1i2oihqt6LrwW WH3v75StZsWGQCU8DaHbCM3JqUWs3nEXK6ptHczJZeGJY711KW7tPFbEYUbVQeUz X-Gm-Gg: AR+sD13WCdLH4ZOkel5Sw9y1VnN+qMCsJ5UMTHmiqqXk/9sNkUB8nUDNjaP/eNbGXnR grXUuaNESjsK5JfMjR8oWlXPXd1/tQ7weLt6CokErviwzgZ5+KhZfRv9sE+pWw/pxoFZ2mhCOwn 4FObv0wdtjBpY808Q57IVSbzH2FDeUgQtrfd4xQJ+MwfUziMHWiCvK4NrT5hv4eMfFGEZho8GXB G88bqdUcdjPIrxaBWed53WxZ04otIYCV5QMf5TdJIezRaHwWmiX77KjzfORhjgWwPSmJouz/vM5 aod7Bn98jUzJkQbdzV68XzD1RtI/dfkick3L/f2Lje+Tb9EtxpFeJRCfFzsBiu2uxYjYIJtgjNh RZGCcPh4Slcw+9kWNnb6n6GuMSnUTaRfSDnXTy9PxYWQ10N4uBSe6f74B4gXHPkTrVjBS4eriHa IJ0Fvo531GAEQhXWkipZX0wsKgilZBl4cxVm4mxiV2lF4pBpYvwC4nsrZo57AE0KH2EOEy/u2x3 +6QJUBYkynr X-Received: by 2002:a05:6808:5384:b0:493:a850:d93a with SMTP id 5614622812f47-4afadf13c46mr4411643b6e.6.1785943809066; Wed, 05 Aug 2026 08:30:09 -0700 (PDT) From: Simon Xu To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Owen Giles , Peter Maydell , Pierrick Bouvier , Robert Elliott , Simon Xu Subject: [PATCH v2 1/9] target/arm/tcg/cpu-v7m.c: add cortex-m85 model Date: Wed, 5 Aug 2026 10:29:57 -0500 Message-ID: <20260805153005.9989-2-simonxhy0404@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260805153005.9989-1-simonxhy0404@gmail.com> References: <20260805153005.9989-1-simonxhy0404@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=simonxhy0404@gmail.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785943933136158500 Content-Type: text/plain; charset="utf-8" Add Arm Cortex-M85 CPU, modeld after the existing M55 CPU. The new M85 feature PACBTI is not implemented in QEMU and the midr value is based off the r1p1 product revision identifier. Arm Cortex-M85 TRM: https://developer.arm.com/documentation/101924/0101/ Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu --- target/arm/tcg/cpu-v7m.c | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index dc249ce1f1..a1e62a20f8 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -237,6 +237,45 @@ static void cortex_m55_initfn(Object *obj) cpu->ctr =3D 0x8303c003; } =20 +static void cortex_m85_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; + + /* QEMU currently does not support the PACBTI feature */ + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_V8_1M); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x411fd231; /* r1p1 */ + cpu->revidr =3D 0; + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + /* These are the MVFR* values for the FPU + full MVE configuration */ + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x12100211; + cpu->isar.mvfr2 =3D 0x00000040; + SET_IDREG(isar, ID_PFR0, 0x20000030); + SET_IDREG(isar, ID_PFR1, 0x00000230); + SET_IDREG(isar, ID_DFR0, 0x10200000); + SET_IDREG(isar, ID_AFR0, 0x00000000); + SET_IDREG(isar, ID_MMFR0, 0x00111040); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x01000000); + SET_IDREG(isar, ID_MMFR3, 0x00000011); + SET_IDREG(isar, ID_ISAR0, 0x01103110); + SET_IDREG(isar, ID_ISAR1, 0x02212000); + SET_IDREG(isar, ID_ISAR2, 0x20232232); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); + SET_IDREG(isar, CLIDR, 0x00000000); /* caches not implemented */ + cpu->ctr =3D 0x8303c003; +} + static const TCGCPUOps arm_v7m_tcg_ops =3D { /* ARM processors have a weak memory model */ .guest_default_memory_order =3D 0, @@ -290,6 +329,8 @@ static const ARMCPUInfo arm_v7m_cpus[] =3D { .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m55", .initfn =3D cortex_m55_initfn, .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m85", .initfn =3D cortex_m85_initfn, + .class_init =3D arm_v7m_class_init }, }; =20 static void arm_v7m_cpu_register_types(void) --=20 2.53.0 From nobody Wed Aug 26 20:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1785943951; cv=none; d=zohomail.com; s=zohoarc; b=VGmK1l/TE7BuKa+gi+tIMQ3l+Ng7jcls7B/i3ozfGRjzTkXakbs7b1NFOHqkTS2s2sQywnOSkV6AjE0wevc2ejdE7E6K4VdSxhvk0TI/OcPzYXrYO2KUx9tFa0Hp1fJWnK6ODfh5IM7CkjLvDrbfoGD2n+Yu335pore60jq6tgw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785943951; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4xZSFW/3ru0OkV2HgMsI1LCVRBUpnAQblZnopJOlyMw=; b=GhXqRf7p6QOTaTYfGm3BzXdMN8QIxOSWKmJnYy1MtnvzotYLQ8qWrhBOBU45lUa38+3jyksg6B4GDivuq0mBfCYAJKFmJjZPwLCqatmnmuGi6GkVs5XcEuYhgtUwHBV6o5CuqkZNxXAzP97foK/iCmRX5cNWICICBTlKKMjr1is= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785943951477693.8606652628619; Wed, 5 Aug 2026 08:32:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrdZR-0005mh-Q2; Wed, 05 Aug 2026 11:30:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wrdZO-0005lu-5D for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:14 -0400 Received: from mail-oi1-x22d.google.com ([2607:f8b0:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wrdZL-0007c4-Ky for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:13 -0400 Received: by mail-oi1-x22d.google.com with SMTP id 5614622812f47-48a0ca07c38so723194b6e.2 for ; Wed, 05 Aug 2026 08:30:11 -0700 (PDT) Received: from HPE-2MQ6131DV6.ams.hpecorp.net ([170.85.99.9]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae75ce1bsm2185614b6e.15.2026.08.05.08.30.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 08:30:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785943810; x=1786548610; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=4xZSFW/3ru0OkV2HgMsI1LCVRBUpnAQblZnopJOlyMw=; b=itPtlJdmW/oh+G1m1mbcjm/Tr7RX3X03I2Y8eIguwbK/5095sqrFg5L80/sk35evPU ZWC5BG8d6+7+T9z4DPDYs3XW39msqMvNnykiSilSB0MhXJecaPtJ+9ToYkbh5Uyu5XEs O37qGXxvcbZs+I58bJj0GXt8XHTkyEYq9B7GSWjh/XhPiyWHzdY4X6fZ78NuTx9jTD+R zylMwESSIz/nHd067+Ho5x6vf5/tT1ubnepYnQ+z0iH/9AaBiUzgE8KPVyJA/y5TLR8A dHEVWNSD978OPUP/rGi140S9Xy9PJsbYsHielrRJvFUIPr+ZQ2qqxJ+v4dx6AiNYeFFO 9Eiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785943810; x=1786548610; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=4xZSFW/3ru0OkV2HgMsI1LCVRBUpnAQblZnopJOlyMw=; b=iFIE7gEtdNml2byeVP/UUSgLz88sGzgbr7SI9dvVdxzyWXQj8Iae4E93/qiVsk9y7S so0Hme/OUT99Vvqlzey9US/IA+zO5cHWo+MZ3A4D1BzODqIw1hDurI+HeA0Lq8S4uXAd 5YJyrZ3m7HpHEd2SzTRNgfk/CotXsFsU3bwls5lFUtVMYmqzr7yEr7KQyU6dMLm6Zd01 wEUxf484p/nW4FsR5itv0SCzY/ir1q3gYi5WAfkc6hTAOhRrYNfegnxJCf75tq5OaJzL XR4Wmfddej9lGxZz9PVb8bVqeeuOD8s9RzT62vbLubCoX6oEJ1V7BD63EdnBrS/qxcrS m62g== X-Gm-Message-State: AOJu0YzrOZnFIqX+9CiEW4KMqW6KyvXf1Hrq0yBlYqcRWGmBovAezgKT CjKPiJjfcdDEauxbKWEj7ZrjeTpCa+7lMSq4DIvWp6vmuO7tYHHpldjojjaxJQ2m X-Gm-Gg: AR+sD10cjKMon5YtWEN+8sETTB7JyqMEEg4XtNCjqWKpZz1mdErZPo1ZjwMkGI53+nQ 2Ss1Vml0eGPFZCLTP+jhJ5xqt7L02SC5MEtFZNtr6mXqQkUnhARpK5f1LaXBjCXAivJ1kKC9f2m FsiqFxEkpVA5Sq/6fDakkGMqfHJematXopx7V1FgiMysKjWLITPn/9ueUZFCxsicwFf/nD5oZ7C CXt7/cgXTpuMXuN8r7u80LgDuf7JZ5riDN06NkSG3Ryk2hg5u8w9opfg7n/L9UoHBypV3EsRsL4 w7GbRN7FFixHyVM7RCIv6+ZyQqNPLrggUL7Bwc2TWbdFCINhRkkmJAj0QlGQgPUKA8bQwkhMvSA sUqkJPgGy6s0vjErczicP0Al7mHo5jPpATYLvavcjmToc64jWNROfbTFc1Nf22fIYMic5dbZzfb jfzguwiKQhnxuwP5zuytI6BcNzR880/kfNxyr4R83L+GDBoBkUSvSpW6R84v+Yp+9/+cznfxbK9 bLSgtVME8Xx X-Received: by 2002:a05:6808:3a0f:b0:4a3:f4b7:cbdf with SMTP id 5614622812f47-4afadf93109mr4011031b6e.15.1785943810244; Wed, 05 Aug 2026 08:30:10 -0700 (PDT) From: Simon Xu To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Owen Giles , Peter Maydell , Pierrick Bouvier , Robert Elliott , Simon Xu Subject: [PATCH v2 2/9] hw/arm/armsse: add Arm Corstone SSE-310 Date: Wed, 5 Aug 2026 10:29:58 -0500 Message-ID: <20260805153005.9989-3-simonxhy0404@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260805153005.9989-1-simonxhy0404@gmail.com> References: <20260805153005.9989-1-simonxhy0404@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=simonxhy0404@gmail.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785943953155158500 Content-Type: text/plain; charset="utf-8" Add baseline Arm Corstone SSE-310 model. Device list changes between SSE-310 and SSE-300: New NPU0 Power Policy Unit and Configuration interface. All other devices are the same. Update comments in include/hw/arm/armsse.h to include SSE-300 and SSE-310 and their respective documentations. New SSE-310 IRQ mapping. sys_version and iidr values from the "SSE-310 with M85 and U55 FPGA" documentation for the mps3-an555. Refractor comments and code pertaining to both the SSE-300 and SSE-310. Arm Corstone SSE-310 TRM: https://developer.arm.com/documentation/102778/0000/ Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell --- v1 -> v2 Split v1 armsse patch into multiple patches for armsse and iotkit files Update comments in armsse.h to include SSE-300 and SSE-310 Remove sys_config2 property Add SSE-310 to iotkit files in next few patches --- hw/arm/armsse.c | 208 +++++++++++++++++++++++++++++++- include/hw/arm/armsse-version.h | 2 + include/hw/arm/armsse.h | 9 +- 3 files changed, 211 insertions(+), 8 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index ddb210c895..1847c73322 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -26,7 +26,7 @@ #include "hw/core/qdev-clock.h" =20 /* - * The SSE-300 puts some devices in different places to the + * The SSE-300 and SSE-310 put some devices in different places to the * SSE-200 (and original IoTKit). We use an array of these structs * to define how each variant lays out these devices. (Parts of the * SoC that are the same for all variants aren't handled via these @@ -118,6 +118,18 @@ static const Property sse300_properties[] =3D { DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), }; =20 +static const Property sse310_properties[] =3D { + DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 21), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), + DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), + DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), +}; + static const ARMSSEDeviceInfo iotkit_devices[] =3D { { .name =3D "timer0", @@ -480,6 +492,146 @@ static const ARMSSEDeviceInfo sse300_devices[] =3D { } }; =20 +static const ARMSSEDeviceInfo sse310_devices[] =3D { + { + .name =3D "timer0", + .type =3D TYPE_SSE_TIMER, + .index =3D 0, + .addr =3D 0x48000000, + .ppc =3D 0, + .ppc_port =3D 0, + .irq =3D 3, + }, + { + .name =3D "timer1", + .type =3D TYPE_SSE_TIMER, + .index =3D 1, + .addr =3D 0x48001000, + .ppc =3D 0, + .ppc_port =3D 1, + .irq =3D 4, + }, + { + .name =3D "timer2", + .type =3D TYPE_SSE_TIMER, + .index =3D 2, + .addr =3D 0x48002000, + .ppc =3D 0, + .ppc_port =3D 2, + .irq =3D 5, + }, + { + .name =3D "timer3", + .type =3D TYPE_SSE_TIMER, + .index =3D 3, + .addr =3D 0x48003000, + .ppc =3D 0, + .ppc_port =3D 5, + .irq =3D 27, + }, + { + .name =3D "s32ktimer", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 0, + .addr =3D 0x4802f000, + .ppc =3D 1, + .ppc_port =3D 0, + .irq =3D 2, + .slowclk =3D true, + }, + { + .name =3D "s32kwatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 0, + .addr =3D 0x5802e000, + .ppc =3D NO_PPC, + .irq =3D NMI_0, + .slowclk =3D true, + }, + { + .name =3D "watchdog", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 0, + .addr =3D 0x48040000, + .size =3D 0x2000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysinfo", + .type =3D TYPE_IOTKIT_SYSINFO, + .index =3D 0, + .addr =3D 0x48020000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysctl", + .type =3D TYPE_IOTKIT_SYSCTL, + .index =3D 0, + .addr =3D 0x58021000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "SYS_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 1, + .addr =3D 0x58022000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "CPU0CORE_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 2, + .addr =3D 0x58023000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "MGMT_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 3, + .addr =3D 0x58028000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "DEBUG_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 4, + .addr =3D 0x58029000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "NPU0_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 5, + .addr =3D 0x5802a000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "NPU0_CFG", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 6, + .addr =3D 0x40004000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D NULL, + } +}; + /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ static const bool sse200_irq_is_common[32] =3D { [0 ... 5] =3D true, @@ -507,6 +659,20 @@ static const bool sse300_irq_is_common[32] =3D { /* 30, 31: reserved */ }; =20 +static const bool sse310_irq_is_common[32] =3D { + [0 ... 5] =3D true, + /* 6-8: reserved */ + [9 ... 12] =3D true, + /* 13: reserved */ + [14] =3D true, + /* 15: reserved */ + [16] =3D true, + /* 17-26: reserved */ + [27] =3D true, + /* 28, 29: per-CPU CTI interrupts */ + /* 30, 31: reserved */ +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -574,6 +740,28 @@ static const ARMSSEInfo armsse_variants[] =3D { .devinfo =3D sse300_devices, .irq_is_common =3D sse300_irq_is_common, }, + { + .name =3D TYPE_SSE310, + .sse_version =3D ARMSSE_SSE310, + .cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m85"), + .sram_banks =3D 2, + .sram_bank_base =3D 0x21000000, + .num_cpus =3D 1, + .sys_version =3D 0x7e10043b, + .iidr =3D 0x74e0043b, + .cpuwait_rst =3D 0, + .has_mhus =3D false, + .has_cachectrl =3D false, + .has_cpusecctrl =3D true, + .has_cpuid =3D true, + .has_cpu_pwrctrl =3D true, + .has_sse_counter =3D true, + .has_tcms =3D true, + .props =3D sse310_properties, + .props_count =3D ARRAY_SIZE(sse310_properties), + .devinfo =3D sse310_devices, + .irq_is_common =3D sse310_irq_is_common, + } }; =20 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) @@ -604,6 +792,14 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, con= st ARMSSEInfo *info) sys_config =3D deposit32(sys_config, 4, 5, s->sram_addr_width); sys_config =3D deposit32(sys_config, 16, 3, 3); /* CPU0 =3D Cortex= -M55 */ break; + case ARMSSE_SSE310: + sys_config =3D 0; + sys_config =3D deposit32(sys_config, 0, 4, info->sram_banks); + sys_config =3D deposit32(sys_config, 4, 5, s->sram_addr_width); + sys_config =3D deposit32(sys_config, 10, 1, 0); /* No CoreSight So= C */ + sys_config =3D deposit32(sys_config, 11, 2, 0); /* Basic level PI = */ + sys_config =3D deposit32(sys_config, 16, 3, 4); /* CPU0 =3D Cortex= -M85 */ + break; default: g_assert_not_reached(); } @@ -1205,7 +1401,7 @@ static void armsse_realize(DeviceState *dev, Error **= errp) qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI"= , 0)); =20 - /* The SSE-300 has a System Counter / System Timestamp Generator */ + /* The SSE-300/SSE-310 has a System Counter / System Timestamp Generat= or */ if (info->has_sse_counter) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->sse_counter); =20 @@ -1225,12 +1421,12 @@ static void armsse_realize(DeviceState *dev, Error = **errp) } =20 if (info->has_tcms) { - /* The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_000= 0 */ - memory_region_init_ram(&s->itcm, NULL, "sse300-itcm", 512 * KiB, e= rrp); + /* The SSE-300/SSE-310 has an ITCM at 0x0000_0000 and a DTCM at 0x= 2000_0000 */ + memory_region_init_ram(&s->itcm, NULL, "itcm", 512 * KiB, errp); if (*errp) { return; } - memory_region_init_ram(&s->dtcm, NULL, "sse300-dtcm", 512 * KiB, e= rrp); + memory_region_init_ram(&s->dtcm, NULL, "dtcm", 512 * KiB, errp); if (*errp) { return; } @@ -1461,7 +1657,7 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * 0x50010000: L1 icache control registers * 0x50011000: CPUSECCTRL (CPU local security control registers) * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block - * The SSE-300 has an extra: + * The SSE-300 and SSE-310 have an extra: * 0x40012000 and 0x50012000: CPU_PWRCTRL register block */ if (info->has_cachectrl) { diff --git a/include/hw/arm/armsse-version.h b/include/hw/arm/armsse-versio= n.h index 60780fa984..6b498cb334 100644 --- a/include/hw/arm/armsse-version.h +++ b/include/hw/arm/armsse-version.h @@ -25,6 +25,7 @@ enum { ARMSSE_IOTKIT =3D 0, ARMSSE_SSE200 =3D 200, ARMSSE_SSE300 =3D 300, + ARMSSE_SSE310 =3D 310 }; =20 static inline bool armsse_version_valid(uint32_t sse_version) @@ -33,6 +34,7 @@ static inline bool armsse_version_valid(uint32_t sse_vers= ion) case ARMSSE_IOTKIT: case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: return true; default: return false; diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index bdf2d4db8e..6aa1363ccf 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -11,12 +11,16 @@ =20 /* * This is a model of the Arm "Subsystems for Embedded" family of - * hardware, which include the IoT Kit and the SSE-050, SSE-100 and - * SSE-200. Currently we model: + * hardware, which include the IoT Kit and the SSE-050, SSE-100, + * SSE-200, SSE-300, and SSE-310. Currently we model: * - the Arm IoT Kit which is documented in * https://developer.arm.com/documentation/ecm0601256/latest * - the SSE-200 which is documented in * https://developer.arm.com/documentation/101104/latest/ + * - the SSE-300 which is documented in + * https://support.arm.com/documentation/101773/latest/ + * - the SSE-310 which is documented in=20 + * https://support.arm.com/documentation/102778/latest/ * * The IoTKit contains: * a Cortex-M33 @@ -127,6 +131,7 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, #define TYPE_IOTKIT "iotkit" #define TYPE_SSE200 "sse-200" #define TYPE_SSE300 "sse-300" +#define TYPE_SSE310 "sse-310" =20 /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs --=20 2.53.0 From nobody Wed Aug 26 20:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1785943877; cv=none; d=zohomail.com; s=zohoarc; b=SSb6si/nfCpOP8Pex1DbN21Nhzkg2uMAEu8NBDb6iFQy3uJJqE397eXsLdPER+NkMCq6JIjmt/0TgBAfqsFJCB5xmexV8NFiF2YsCgBU18Rb6NfoDFMBB/OuwneMmBustE3KFKBhg8LoNLFyiKLWBbi0KsR1AvERXMBiFGRxvX4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785943877; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=U5wniPKlQoQZB3yHDOIaDg0QUeR+XLP5hn1xDhtt0jA=; b=hX+v1/i+mWRIwakTH4Ny+KNrD+IAAqJYEOCaQQRoNuiVs7ZjRwvczKf1TRn+AZq5nUDib2fNo8yEEbXqLwALb5JuFpcgxAYiDefyX0TiZ4yXnWBVEjQVYwScxr5TtYphkE4jO2pZk+lz8/On4MrKVHiSyQR7bENNvF6bk5mLsaY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785943877222291.07673899095016; Wed, 5 Aug 2026 08:31:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrdZX-0005oC-Rj; Wed, 05 Aug 2026 11:30:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wrdZR-0005n3-WE for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:18 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wrdZN-0007cp-N6 for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:15 -0400 Received: by mail-oi1-x229.google.com with SMTP id 5614622812f47-495c49f8eccso753206b6e.3 for ; Wed, 05 Aug 2026 08:30:13 -0700 (PDT) Received: from HPE-2MQ6131DV6.ams.hpecorp.net ([170.85.99.9]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae75ce1bsm2185614b6e.15.2026.08.05.08.30.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 08:30:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785943812; x=1786548612; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=U5wniPKlQoQZB3yHDOIaDg0QUeR+XLP5hn1xDhtt0jA=; b=BPYFNxeqA6p1iRAMX2RfvW7CCbRSWJ4ND7VvN4++CCZFGm+Kb8FUh7T4rn7HUisLhK 1zD+MbQuDSL8DLCXejHNsaYfOLlFNhXH8QexJmhiO+zj3KG95LYciKLUfqDjUTSg0OqC 6LFoeOxurCYqr2AwgohzX/NlDXd7ZoC2RfWrvLMFrmtdxoJEqbUi1pIVmiWp/DxM3s0X gxYYN+6iH/8mkUuz3PQgrd2/Dh3IBH32KBAV5QPwrZH/zH2BHZDymLigH1j6/7lq/kuM Fr+9ZdS2TszXLy3OG7uDWScz8gR2aWZm1Zi+bknnlZrVviPUdey/v12HJU5mv5aAoyPC wyZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785943812; x=1786548612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=U5wniPKlQoQZB3yHDOIaDg0QUeR+XLP5hn1xDhtt0jA=; b=XnvnknXlEN4hK0KJqCY33ejtf6fDDg5aUIyQ89lWFr/diCuUAMDXPBRYU9h/r70H13 YusAVF1XpCw6KRytY+u2sO5Fs6FtnGNZtlZwaZA7rm/eMjDJnH6yplmrjc6z+oSvSFt3 Gq1Tra9IAVpDOS99itwEkLfZKPMYGl/uxzTvVHYRMp8OCruuml5JhB1HCVMPM7dMarw+ LRcjWrbgVxoU20y3a1krcwg9yhfM5puGbswk4pwlrc300IPlKjNNGUBmL3wCdXeYDtXj XRDnMjG7x5I/fsppRvRIVIwqgX7+wVu/pDGli4ZI/DO+bZ+fXZARNYG/DiP7pZxwDCQB GrjA== X-Gm-Message-State: AOJu0YxAMwy4p2n5gvR1xisZFlJeeFsmfMTGpq0tUUTEFDvDwDxb61Kb OGKbXBjdv6g1A2thdFiH29WI0DVKI0Gp7M7/xPf2UuESYuq7MSJ+sOWneFP37Hjj X-Gm-Gg: AR+sD13TZe0ja7FWm1iXfr21fUAxk8k4ctAY5/QdDLdD4PHnjxb5fFXy1J7x79REV+J B/6MN9uIQWL56lCbv1X+JdA4Vc/HevlyAWCiEV21GXOD3CgA5RVIlVM9AXs5Fe7HGw7cACK8yOc GzFQ7HorNaZCpfxC/Ig1qXmn1oevXnUeEa3gfa2NfGRR3E6TZD0VM4e9Enl8pSyFS30kUr/l77T wkU0GapHre8mF8baifmvJFPAbOI6dRGEGzsfSjYEKkdbKyshoDFxgXI7b+mwyuZrF8OqbU45ryh 694BKsHwmxs0HM7mKVMn8CizRM357xpzPHXswBhUVmjy08NHHxSVZLlHSYtCUAmtTuN2idndnsD d7w5c6M7mcLcneICdeNZf5+QVwJ2FevAXsXd/O85rOXAT9lL3WzW3Zs9nlhrexGG4u3Q8zzAsWA Zu9Sx8S5cj9uhj3fslOXPxGC353m4zBRcIFBv64ZmmRyClY314gCoWrocfqWAkbXzd/DKkFMXFg jTzt2dh7LAfWg== X-Received: by 2002:a05:6808:6907:b0:479:ead7:2a5b with SMTP id 5614622812f47-4afae0e3e59mr4066940b6e.16.1785943812197; Wed, 05 Aug 2026 08:30:12 -0700 (PDT) From: Simon Xu To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Owen Giles , Peter Maydell , Pierrick Bouvier , Robert Elliott , Simon Xu Subject: [PATCH v2 3/9] hw/misc/iotkit-sysctl.c: add SSE-310 support Date: Wed, 5 Aug 2026 10:29:59 -0500 Message-ID: <20260805153005.9989-4-simonxhy0404@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260805153005.9989-1-simonxhy0404@gmail.com> References: <20260805153005.9989-1-simonxhy0404@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=simonxhy0404@gmail.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785943880259158500 Content-Type: text/plain; charset="utf-8" Add SSE-310 case statements for reads and writes. Add new SSE-310 PIDR and CLIDR values. Add new SSE-310 PPUINTSTAT register as RAZ with LOG_UMIMP on reads and RO on writes. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu --- v1 -> v2 Add PPUINTSTAT register Make sure comments don't separate case statements --- hw/misc/iotkit-sysctl.c | 89 ++++++++++++++++++++++++++++++--- include/hw/misc/iotkit-sysctl.h | 1 + 2 files changed, 82 insertions(+), 8 deletions(-) diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index dff89c677f..bdf59b5f85 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -51,6 +51,7 @@ REG32(CPUWAIT, 0x118) REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */ REG32(WICCTRL, 0x120) REG32(EWCTRL, 0x124) +REG32(PPUINTSTAT, 0x128) REG32(PWRCTRL, 0x1fc) FIELD(PWRCTRL, PPU_ACCESS_UNLOCK, 0, 1) FIELD(PWRCTRL, PPU_ACCESS_FILTER, 1, 1) @@ -87,6 +88,12 @@ static const int sse200_sysctl_id[] =3D { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; =20 +static const int sse310_sysctl_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0x54, 0xb8, 0x4b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + /* * Set the initial secure vector table offset address for the core. * This will take effect when the CPU next resets. @@ -118,6 +125,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->scsecctrl; break; default: @@ -130,6 +138,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->fclk_div; break; default: @@ -142,6 +151,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->sysclk_div; break; default: @@ -154,6 +164,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->clock_force; break; default: @@ -180,6 +191,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->initsvtor1; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -192,6 +204,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->cpuwait; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: /* In SSE300 this is reserved (for INITSVTOR2) */ goto bad_offset; default: @@ -208,6 +221,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->nmi_enable; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: /* In SSE300 this is reserved (for INITSVTOR3) */ goto bad_offset; default: @@ -221,7 +235,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->wicctrl; break; case ARMSSE_SSE300: - /* In SSE300 this offset is CPUWAIT */ + case ARMSSE_SSE310: + /* In SSE300 and SSE310 this offset is CPUWAIT */ r =3D s->cpuwait; break; default: @@ -236,19 +251,36 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwad= dr offset, r =3D s->ewctrl; break; case ARMSSE_SSE300: - /* In SSE300 this offset is NMI_ENABLE */ + case ARMSSE_SSE310: + /* In SSE300 and SSE310 this offset is NMI_ENABLE */ r =3D s->nmi_enable; break; default: g_assert_not_reached(); } break; + case A_PPUINTSTAT: + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + case ARMSSE_SSE300: + goto bad_offset; + case ARMSSE_SSE310: + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PPUINTSTAT unimplemented\n"); + r =3D s->ppuintstat; + break; + default: + g_assert_not_reached(); + } + break; case A_PWRCTRL: switch (s->sse_version) { case ARMSSE_IOTKIT: case ARMSSE_SSE200: goto bad_offset; case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->pwrctrl; break; default: @@ -261,6 +293,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->pdcm_pd_sys_sense; break; default: @@ -273,7 +306,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_SSE200: goto bad_offset; case ARMSSE_SSE300: - r =3D s->pdcm_pd_cpu0_sense; + case ARMSSE_SSE310: + r =3D s->pdcm_pd_cpu0_sense; =20 break; default: g_assert_not_reached(); @@ -287,6 +321,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->pdcm_pd_sram0_sense; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -300,6 +335,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->pdcm_pd_sram1_sense; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -313,6 +349,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->pdcm_pd_sram2_sense; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->pdcm_pd_vmr0_sense; break; default: @@ -327,6 +364,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D s->pdcm_pd_sram3_sense; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: r =3D s->pdcm_pd_vmr1_sense; break; default: @@ -342,6 +380,9 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, case ARMSSE_SSE300: r =3D sse200_sysctl_id[(offset - A_PID4) / 4]; break; + case ARMSSE_SSE310: + r =3D sse310_sysctl_id[(offset - A_PID4) / 4]; + break; default: g_assert_not_reached(); } @@ -367,7 +408,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, =20 static void cpuwait_write(IoTKitSysCtl *s, uint32_t value) { - int num_cpus =3D (s->sse_version =3D=3D ARMSSE_SSE300) ? 1 : 2; + int num_cpus =3D (s->sse_version =3D=3D ARMSSE_SSE300 || + s->sse_version =3D=3D ARMSSE_SSE310) ? 1 : 2; int i; =20 for (i =3D 0; i < num_cpus; i++) { @@ -418,7 +460,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, case A_INITSVTOR0: switch (s->sse_version) { case ARMSSE_SSE300: - /* SSE300 has a LOCK bit which prevents further writes when se= t */ + case ARMSSE_SSE310: + /* SSE300 and SSE310 have a LOCK bit which prevents further wr= ites */ if (s->initsvtor0 & R_INITSVTOR0_LOCK_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "IoTKit INITSVTOR0 write when register locke= d\n"); @@ -443,6 +486,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, cpuwait_write(s, value); break; case ARMSSE_SSE300: + case ARMSSE_SSE310: /* In SSE300 this is reserved (for INITSVTOR2) */ goto bad_offset; default: @@ -457,7 +501,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->wicctrl =3D value; break; case ARMSSE_SSE300: - /* In SSE300 this offset is CPUWAIT */ + case ARMSSE_SSE310: + /* In SSE300 and SSE310 this offset is CPUWAIT */ cpuwait_write(s, value); break; default: @@ -485,6 +530,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemente= d\n"); s->scsecctrl =3D value; break; @@ -498,6 +544,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented= \n"); s->fclk_div =3D value; break; @@ -511,6 +558,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplement= ed\n"); s->sysclk_div =3D value; break; @@ -524,6 +572,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemen= ted\n"); s->clock_force =3D value; break; @@ -540,6 +589,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, set_init_vtor(1, s->initsvtor1); break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -554,7 +604,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->ewctrl =3D value; break; case ARMSSE_SSE300: - /* In SSE300 this offset is NMI_ENABLE */ + case ARMSSE_SSE310: + /* In SSE300 and SSE310 this offset is NMI_ENABLE */ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplement= ed\n"); s->nmi_enable =3D value; break; @@ -562,12 +613,25 @@ static void iotkit_sysctl_write(void *opaque, hwaddr = offset, g_assert_not_reached(); } break; + case A_PPUINTSTAT: + switch (s->sse_version) { + case ARMSSE_IOTKIT: + case ARMSSE_SSE200: + case ARMSSE_SSE300: + goto bad_offset; + case ARMSSE_SSE310: + goto ro_offset; + default: + g_assert_not_reached(); + } + break; case A_PWRCTRL: switch (s->sse_version) { case ARMSSE_IOTKIT: case ARMSSE_SSE200: goto bad_offset; case ARMSSE_SSE300: + case ARMSSE_SSE310: if (!(s->pwrctrl & R_PWRCTRL_PPU_ACCESS_UNLOCK_MASK)) { qemu_log_mask(LOG_GUEST_ERROR, "IoTKit PWRCTRL write when register locked\n= "); @@ -585,6 +649,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, goto bad_offset; case ARMSSE_SSE200: case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n= "); s->pdcm_pd_sys_sense =3D value; @@ -599,6 +664,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, case ARMSSE_SSE200: goto bad_offset; case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl PDCM_PD_CPU0_SENSE unimplemented\= n"); s->pdcm_pd_cpu0_sense =3D value; @@ -617,6 +683,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->pdcm_pd_sram0_sense =3D value; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -632,6 +699,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->pdcm_pd_sram1_sense =3D value; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: goto bad_offset; default: g_assert_not_reached(); @@ -647,6 +715,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->pdcm_pd_sram2_sense =3D value; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl PDCM_PD_VMR0_SENSE unimplemented\= n"); s->pdcm_pd_vmr0_sense =3D value; @@ -665,6 +734,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->pdcm_pd_sram3_sense =3D value; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl PDCM_PD_VMR1_SENSE unimplemented\= n"); s->pdcm_pd_vmr1_sense =3D value; @@ -683,6 +753,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, s->nmi_enable =3D value; break; case ARMSSE_SSE300: + case ARMSSE_SSE310: /* In SSE300 this is reserved (for INITSVTOR3) */ goto bad_offset; default: @@ -734,6 +805,7 @@ static void iotkit_sysctl_reset(DeviceState *dev) s->clock_force =3D 0; s->nmi_enable =3D 0; s->ewctrl =3D 0; + s->ppuintstat =3D 0; s->pwrctrl =3D 0x3; s->pdcm_pd_sys_sense =3D 0x7f; s->pdcm_pd_sram0_sense =3D 0; @@ -769,7 +841,8 @@ static bool sse300_needed(void *opaque) { IoTKitSysCtl *s =3D IOTKIT_SYSCTL(opaque); =20 - return s->sse_version =3D=3D ARMSSE_SSE300; + return s->sse_version =3D=3D ARMSSE_SSE300 || + s->sse_version =3D=3D ARMSSE_SSE310; } =20 static const VMStateDescription iotkit_sysctl_sse300_vmstate =3D { diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index ce72258a84..8e1cf0012d 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -53,6 +53,7 @@ struct IoTKitSysCtl { uint32_t initsvtor1; uint32_t nmi_enable; uint32_t ewctrl; + uint32_t ppuintstat; uint32_t pwrctrl; uint32_t pdcm_pd_sys_sense; uint32_t pdcm_pd_sram0_sense; --=20 2.53.0 From nobody Wed Aug 26 20:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1785943877; cv=none; d=zohomail.com; s=zohoarc; b=HnuN4jWCEXKSmeBYxKMWNmUieyFS372A05KM11KzpdN6m7RBOlMl08NJiUYbKPKq8EAMrD6QgIcnzTTu7JtvPCnCBPUW0j80UOPrgXZQ9WkWTG40Dgg9gl/0oG8Th4fek9RopVJGX2nPCA49XpsyMHZo2ezF+b8Dow6N5FRn9w0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785943877; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PoXfMDRAQIj+y4/BPWtH1Tl3SZCP6UaSej1RFcIEr2g=; b=XMYvDQAJYu2ZcnCtHKP62mexh7xeCZLyzAu0Q6qwn3+pLte6dty/4iLKinyMHwQcfJF90fl8CUlYLT/AoaJ7w3ZLVdkP/qSvK/DuvFIGvq8UBLWs922HHX6T+h/aIVcvzjG3jf3OnXt2wDZWvnqvX1eaSpAV8C+o+dcZu3WugqE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785943877124276.01959513296947; Wed, 5 Aug 2026 08:31:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrdZb-0005qb-S7; Wed, 05 Aug 2026 11:30:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wrdZU-0005nQ-26 for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:20 -0400 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wrdZR-0007dJ-NT for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:18 -0400 Received: by mail-oi1-x22a.google.com with SMTP id 5614622812f47-4896ae35be9so384412b6e.0 for ; Wed, 05 Aug 2026 08:30:15 -0700 (PDT) Received: from HPE-2MQ6131DV6.ams.hpecorp.net ([170.85.99.9]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae75ce1bsm2185614b6e.15.2026.08.05.08.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 08:30:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785943814; x=1786548614; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=PoXfMDRAQIj+y4/BPWtH1Tl3SZCP6UaSej1RFcIEr2g=; b=POHWM1ewxHIkMhmxdfM22pg2ttz9Ev9AfgMMQUhQIcl7XJMSmMSNM7LJymWjQbCZTX o2b1dCWY5JUrPACdC2aLHw8wc7HtkOoenaPKsGkXIMYi9YEg3dBJqb4P+yH7rQc8u7yK Lg8C2lEQsJFZatl5INmaKmCPcyQMHe0FpK/TteAVA0dGNJEH7nZwWDWt8NIowAhaMOhM 1GLeJE9uG6TPTjOsaRkxYE27AQhuY55Nh4g0Eh3N9G7CcDanRUc5U+QgF0Ge+T5zNS65 IHCk3M5m9kIIgaCMA2PzcfWKnuqGImadSYd7bSWqI0LgRqBmcxW9jWrvgPcRXYQ0LucN p8cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785943814; x=1786548614; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=PoXfMDRAQIj+y4/BPWtH1Tl3SZCP6UaSej1RFcIEr2g=; b=FUgapa/uCiwEbsk5Q8CJIx6uYRoX61aIl1FttZSBUaUsft5GXbnWAYHVqI1Sid9hJZ FDxgWYT42DKuymaHLjhT2b2/1VAgpM8l5yPlJBq37ckkfeWzKB7CBcyiu2/si5DgQeZQ C5PjOLNo69+5L4i51vXuj6m6jtpOJELuA3ZG0RzqCgodRqW1Wq/RHLK09h8lAS7WUYy0 zfA7ZzdONTJqsXR9gLHNT/Do4o8ZahfR8e6YOnx2COEMEsEMbrUqqYpjphBOrPVNfyUK /us1wwCqfEgA/N/2d4i7cyouFZ1EEC+PYsuB8OtgR2FAnWOzHShTqve8HV/yI0Qh/hsh StKA== X-Gm-Message-State: AOJu0YxKBZlw/SHExQB349xvopxW+zXhcYq8Z76I75KnlKOaYssW4jFH DMmjKhANMq5r2lO2yfC+28hEkzf004PVEgF56PvlNzVfzUg9s/SVAid4IJ0ezerQ X-Gm-Gg: AR+sD13Wtoi8bj63I2gs/BfWPc6NTlxFh9D6I1bYwQ1zoKU4H9X/UbrOLrlQPiTe2gO F0JqGZxYmTwP/doFih8DpcYW2OYMLQcobWoGmRBxC2boJ52K7+pIY1BAuQufWPhzOqQELRqeEBo 1ILxt2iTQ3TevbaUPC+PlTM6yS3nUSeG2AhT1+scN9cAGagMuGUmo7j/2CfVCBgjOz6fz6aoeRT ATdFPUceihicJrZkGIGvcauFh/Ho8N/bizTEKTlJjHvuwre6xjmKc7O1evWkmBPyKey6KQA488V vtm+QBUqCC4E2LV7NzNhOybk7Z+xYoEjMYtNQAHbEqkPsBvP4BywEb6BtTb8ub9RRf5a2iffHSr UJ9IQBCXVMVIP1BXmnSfQTtqcZt4wvJBmECgep8l4R/hQI+jSG9SqbcQnROMQqV/UmMDzy+YPuC tF6LlNf6MwN+dFNDE1L/OKZXFxJsiPLaHv7HcjLAe+RjPcMnp7J0Bs+GeGOrHDdW5YT4imhkR4I olxC5nfqZC2 X-Received: by 2002:a05:6808:444c:b0:4ab:6662:4e97 with SMTP id 5614622812f47-4afae1e8f4fmr3995544b6e.16.1785943813687; Wed, 05 Aug 2026 08:30:13 -0700 (PDT) From: Simon Xu To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Owen Giles , Peter Maydell , Pierrick Bouvier , Robert Elliott , Simon Xu Subject: [PATCH v2 4/9] hw/misc/iotkit-secctl.c: fix AHB secure read Date: Wed, 5 Aug 2026 10:30:00 -0500 Message-ID: <20260805153005.9989-5-simonxhy0404@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260805153005.9989-1-simonxhy0404@gmail.com> References: <20260805153005.9989-1-simonxhy0404@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=simonxhy0404@gmail.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785943880152158500 Content-Type: text/plain; charset="utf-8" Fix AHB secure privilege to read AHB instead of APB. Fixes: b3717c23e1c0 ("hw/misc/iotkit-secctl: Add handling for PPCs") Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell --- v1 -> v2 Noticed this bug in the secure read function --- hw/misc/iotkit-secctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 54bfe1ba59..93753c2ced 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -195,7 +195,7 @@ static MemTxResult iotkit_secctl_s_read(void *opaque, h= waddr addr, case A_AHBSPPPCEXP1: case A_AHBSPPPCEXP2: case A_AHBSPPPCEXP3: - r =3D s->apbexp[offset_to_ppc_idx(offset)].sp; + r =3D s->ahbexp[offset_to_ppc_idx(offset)].sp; break; case A_APBSPPPC0: case A_APBSPPPC1: --=20 2.53.0 From nobody Wed Aug 26 20:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1785943932; cv=none; d=zohomail.com; s=zohoarc; b=oJZ8oX1hKRMXD9lTCZmat5ajB8hpqdW0quheqPKgAROmCUwtr9LIiIYWH6GXLQ29T56JDsWrBYLi0C4lfi8OCF0q7UDNuEvkYdXaBE7W2CZUPl5XwjRbqJP2b3uunYO7R5z/CpOcPM4LnCI5eINaTw4EcKJT5Gz1GAkupvCcUg0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785943932; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ceor1s7HR8GNDcyh7kwDT8r2E1Lvax6O+6vcMQOKk04=; b=CiU8GHwPraSGuqabhOmKsJlBLbg6hnqbtO1QCPAFITDY/yQiC4UYMmoATMz1KyHTGdZQIaE2rLcIuaye62vKgyj0a8yA1O+xtLYSdstD31qvey7fzBSdCaP5p9hw8uAcKyFpRv0fD27F8qN9QsrLL/VXdHFkFBi7IydWKcsDDRE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785943931998240.06166222600268; Wed, 5 Aug 2026 08:32:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrdZf-0005qc-CN; Wed, 05 Aug 2026 11:30:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wrdZV-0005o0-Sv for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:21 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wrdZR-0007dN-OZ for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:20 -0400 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-4af81963f35so459654b6e.0 for ; Wed, 05 Aug 2026 08:30:15 -0700 (PDT) Received: from HPE-2MQ6131DV6.ams.hpecorp.net ([170.85.99.9]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae75ce1bsm2185614b6e.15.2026.08.05.08.30.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 08:30:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785943815; x=1786548615; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ceor1s7HR8GNDcyh7kwDT8r2E1Lvax6O+6vcMQOKk04=; b=nwLBbdx5CGluiUXjftLIP5KvyqUktfo/PubRKNtK4uudVLLLplNVDhM9kdl54o232P oRqtOvwo2CO5uBFw37ydz4KrrV+gQDpt94tbK45l4kCF3mGICWOkJwaEmHzqYJCvhm6m g/npMNJFNzDqaOPgExLSny9URyo2MQh4Lja71etawYDyY9JcgK7pahr6VP3eDVB/wYtD /avBwhEUqXho3V6RuFLIBkifc8BoH1UMCkrfonWZRAA0vVELwSumWbMBtrQtxKDqo/Xc 7M7bBzPq4hsAkx/dFRthZXIaJGtUVJBuG5rPZf2cAb+ccRjHu45vjo3b3xPeik0q+ZZy c7eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785943815; x=1786548615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=ceor1s7HR8GNDcyh7kwDT8r2E1Lvax6O+6vcMQOKk04=; b=qe7ofbjr/PXvttvqPuf8B2O+PKmYtmh0Q4Jr3sf1LxoWZQ8SKd9COYVAi2SigU2GUy BJDvVpJMxe1wLCrI3PlFn+hPKr5vNk3S9iUBaKiim2osMG3gnQXXuL6nUne1xhc2Alnh tZP2xemMcMaQ7seVaCTLcxHNDBm798p+sJbsC02+cwsriAbBa22qcX4A/kZ21lfsbUm8 ZN3OAaQk1ouCo7JYmRROf4zLrYS1l1p8jm5tmpsUbGn+9rmfDMxJdV0KTpeEoS02GoPf 0DvQVBAsoY+BXw++gUgvkugGnQ1SHGokWS17ZM6U5IYBwTzc8WY5zO65Trrxb03KP+oq K9Nw== X-Gm-Message-State: AOJu0Yztm36diy2k4+E1kuu6J0PiGfpn3hXAfNnTdlB8NTGku8Zbs/Iz yQ9DJPm0S8gSesXQTpG6MPg1EGYgh3XhbPkp7+uzp2br3F45/I+VctulQSh/TAzZ X-Gm-Gg: AR+sD10mcwzOswi+4dmye+VXPmaFIupYON8+vlOVL+DsfIUDyC3igT/JYMFCpwFDQGH 17xm9CPaXBdCwr2niNS/p7u9QcID3eOwmpNJuRzFHJIeG65OZ7UAqDX+kBAErrVAs3gi0CKzGaT Q5ZVQAYBoYrge51oUihxjtMM5QG8m0RZXJWksg5z1RxN3JzSIFlpntaGDZvqNvvHzzIVHRNLpdo 1skcTW9Zo7UEVjqwZbvACpbbxFRaBUi58VYg4SW1jt3mstgptcRDsIr/6SnJA3h9CnhCrOo5VF2 3PHpZZFVe4oTazjm85a8JTcGFJeiKBqUDn/OY/nvyi2QD3hiajCp/Xwpj0a5yU+z14D81GjeMoa H9G1OyOARoCYeEoj3p1mdeSFrzqIp7qbZOnNWaJ4tMHUJNm8EgB8bMnUTt3ER2A8HBJdzNhnx5j EMic7ToXPTclTKBJjnPOdDFAp/SP3a+3ZRNEbW8I57fRvE5I57nOKoGiYXHzxQuXjT+/JVOZtC6 1+QgLmKx7pw X-Received: by 2002:a05:6808:1986:b0:4a3:fb6c:9adf with SMTP id 5614622812f47-4afae067fe6mr4614720b6e.12.1785943814706; Wed, 05 Aug 2026 08:30:14 -0700 (PDT) From: Simon Xu To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Owen Giles , Peter Maydell , Pierrick Bouvier , Robert Elliott , Simon Xu Subject: [PATCH v2 5/9] hw/misc/iotkit-secctl.c: add SSE-310 support Date: Wed, 5 Aug 2026 10:30:01 -0500 Message-ID: <20260805153005.9989-6-simonxhy0404@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260805153005.9989-1-simonxhy0404@gmail.com> References: <20260805153005.9989-1-simonxhy0404@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=simonxhy0404@gmail.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785943938686158500 Content-Type: text/plain; charset="utf-8" Add SSE-310 secure and non-secure ID registers. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell --- v1 -> v2 With the bug fix from the previous patch=09 --- hw/misc/iotkit-secctl.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 93753c2ced..9f6fb81088 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -109,6 +109,18 @@ static const uint8_t iotkit_secctl_ns_sse300_idregs[] = =3D { 0x0d, 0xf0, 0x05, 0xb1, }; =20 +static const uint8_t iotkit_secctl_s_sse310_idregs[] =3D { + 0x04, 0x00, 0x00, 0x00, + 0x52, 0xb8, 0x3b, 0x00, + 0x0d, 0xf0, 0x05, 0xb1, +}; + +static const uint8_t iotkit_secctl_ns_sse310_idregs[] =3D { + 0x04, 0x00, 0x00, 0x00, + 0x53, 0xb8, 0x3b, 0x00, + 0x0d, 0xf0, 0x05, 0xb1, +}; + =20 /* The register sets for the various PPCs (AHB internal, APB internal, * AHB expansion, APB expansion) are all set up so that they are @@ -232,6 +244,9 @@ static MemTxResult iotkit_secctl_s_read(void *opaque, h= waddr addr, case ARMSSE_SSE300: r =3D iotkit_secctl_s_sse300_idregs[(offset - A_PID4) / 4]; break; + case ARMSSE_SSE310: + r =3D iotkit_secctl_s_sse310_idregs[(offset - A_PID4) / 4]; + break; default: r =3D iotkit_secctl_s_idregs[(offset - A_PID4) / 4]; break; @@ -499,6 +514,9 @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, = hwaddr addr, case ARMSSE_SSE300: r =3D iotkit_secctl_ns_sse300_idregs[(offset - A_PID4) / 4]; break; + case ARMSSE_SSE310: + r =3D iotkit_secctl_ns_sse310_idregs[(offset - A_PID4) / 4]; + break; default: r =3D iotkit_secctl_ns_idregs[(offset - A_PID4) / 4]; break; --=20 2.53.0 From nobody Wed Aug 26 20:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1785943983; cv=none; d=zohomail.com; s=zohoarc; b=IRnre9nShC07BDULALaTuUmjfmWL8UHhh0KoX4jvGSuzuRI2oVFHSQlP2ckrgQQddTssWeLrVolnDCXv/t535v+LBbcyvcZHujg0I0iftQbdWirWdxnNd7ScFjoGx2AY5MbSnSjHMnSDLtRR/EOvJ5K/4Qb/D0zOaLIn8XilU54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785943983; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=k9yZcr4UWJCAebKRS40Pd2Dm5YZ9z3Ekl/CFHK6Os1I=; b=RKRgLDI/DedpYgSJEHtekbfaCOBsmXimMlYSGywONHHFFf4e0GwQjrN7sMDcXOSkObkjESKZy2j0XuHAmee8FDijk2m7qxrUEvpayPIvzXo86BCl1QRcUMx7PwCjbAb/Dej3KKtuiQnOF4TtmenuUftljyKTqFgp0PPjb+TiLws= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785943983622709.4969020592606; Wed, 5 Aug 2026 08:33:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrdZg-0005rL-Ij; Wed, 05 Aug 2026 11:30:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wrdZV-0005o9-VG for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:23 -0400 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wrdZR-0007do-OF for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:20 -0400 Received: by mail-oi1-x231.google.com with SMTP id 5614622812f47-495b27007d0so727899b6e.1 for ; Wed, 05 Aug 2026 08:30:16 -0700 (PDT) Received: from HPE-2MQ6131DV6.ams.hpecorp.net ([170.85.99.9]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae75ce1bsm2185614b6e.15.2026.08.05.08.30.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 08:30:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785943816; x=1786548616; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=k9yZcr4UWJCAebKRS40Pd2Dm5YZ9z3Ekl/CFHK6Os1I=; b=QrlwnLafuaqnM55PR5Sjk7qN5KVbc7Cc7/eX89eEd0CUzPxX9W02emAJKbIt6O05l7 ldSuGtu12QKd2oCukkaFiwVIEFsgB8WrI8stJ+qb5D6T1nkS4TH6fiwiL85pwCH2rckd sK+WnoF2JR55LUq1Glekd26OpwE5TfyaQtIHJ0q/c2zA82sNycTxUNRKQzGAGYgQbcyA rGhhnwWespxqmqqMHNwf85xpjnR7u2U5CLvD+TM9LaKxXmaALfmw1sGaXlZxSYmmybF1 Qu4i43xMdI4HQotYJ0X449OyDa4ijK8SzDeNmJgkIQn1WUV6sMQHCOqEAi4sLIYuawbU JZ6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785943816; x=1786548616; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=k9yZcr4UWJCAebKRS40Pd2Dm5YZ9z3Ekl/CFHK6Os1I=; b=AdHPpX1hQcTjA0rbc24qglrvWDRT32BWvLiWwnDKqI5oIxsIA3NXi/dBAWWzPDHEoF aeknEdc+nsuyfGXWPh7/pp987RUsPc5SxCw9MeVykclF8x9DxxiVkecGB/FPHHBvhU/D 34Kzx1n5ouWY8bZ5M8eRi/CNyu7ZP+cRRJALRMTWaUx5CLoi0ryaj1kMfeRaiKFblDG0 +MvTilko8WOHRMxJw2aGAhLYtglFwjfJ+Yq2zMRCwrmUj1DS1AJNm9tAkwPB7DQR/V75 uK+jEDzhOlYf41HbpuSajht9UtrDFtO2kxu34OvOzNXhBv8xHAsNWENpw2K1h8MmIfgt w71w== X-Gm-Message-State: AOJu0Yw3ukZFwPFobLJNC4Jpjb+TX2HAl9f7okoeI3U1/Pn+EOmW3p6U Ez/gpO4kr4Ad5k5MZyoSvxi7eh2QhyN6ihlbB1/lVBgooY3jXSrJ/zG6/bcGo8Iy X-Gm-Gg: AR+sD13nK1xJggbeCUlXZmfg4rLRZVJn5Dk2XR9qiwtvuOFYh114PL2x6okgQUIOwIs 9Uy7vPxFQY1GaW1/rNi3o4ATaqhTiwE54QMFydRBIyLu0xeaaKGe+EU4dtLvWC3rZr7jYvaHMxJ qJ+V5fsj1xD3Kl6HtPZ9RfGnAtQWJaXRhns6HC7O3VUkgJZeS/8fNohkhBTwZngc+KAx0URG51y 4Pp9irmjuEiYu8eoJK08z7NgsqPG/OE2hxfHQ5v2rTR3BqE1xDMUkUk05UCmd44ZRjn2vtLjC4G RoNYWkB8cJ3i+tTwrbn6ZL0NUEArXMjyFhuM4PmkB5FO95YeUC1wZ955Wib6OLlCgapBt//HYhu wYG2gq42O03a6w2sIlKZLCZq3c041zS5GL9esiM+EWa3+lSwd2/47kS++mceB1/RbXYIJjW9syg QML9Vg/mf5QJKVwmFvAzXq5tucZgnMexgY9ITLfLcK8j7SGOg0w+uRdZBIYXuu2QjjNlEhX6DwZ Z/+Hcr/b4QE X-Received: by 2002:a05:6808:3985:b0:494:18ad:8a5b with SMTP id 5614622812f47-4afae0171a6mr4579392b6e.17.1785943815737; Wed, 05 Aug 2026 08:30:15 -0700 (PDT) From: Simon Xu To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Owen Giles , Peter Maydell , Pierrick Bouvier , Robert Elliott , Simon Xu Subject: [PATCH v2 6/9] hw/misc/iotkit-secctl.c: use GNU C case ranges Date: Wed, 5 Aug 2026 10:30:02 -0500 Message-ID: <20260805153005.9989-7-simonxhy0404@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260805153005.9989-1-simonxhy0404@gmail.com> References: <20260805153005.9989-1-simonxhy0404@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=simonxhy0404@gmail.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785943984296158501 Content-Type: text/plain; charset="utf-8" Replace case fall throughs with case ranges when register addresses are continous. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell --- v1 -> v2 Make long case statemens consistent with other iotkit files --- hw/misc/iotkit-secctl.c | 112 ++++++---------------------------------- 1 file changed, 16 insertions(+), 96 deletions(-) diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 9f6fb81088..2d06d6f80f 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -187,36 +187,24 @@ static MemTxResult iotkit_secctl_s_read(void *opaque,= hwaddr addr, case A_BRGINTEN: r =3D s->brginten; break; - case A_AHBNSPPCEXP0: - case A_AHBNSPPCEXP1: - case A_AHBNSPPCEXP2: - case A_AHBNSPPCEXP3: + case A_AHBNSPPCEXP0 ... A_AHBNSPPCEXP3: r =3D s->ahbexp[offset_to_ppc_idx(offset)].ns; break; case A_APBNSPPC0: case A_APBNSPPC1: r =3D s->apb[offset_to_ppc_idx(offset)].ns; break; - case A_APBNSPPCEXP0: - case A_APBNSPPCEXP1: - case A_APBNSPPCEXP2: - case A_APBNSPPCEXP3: + case A_APBNSPPCEXP0 ... A_APBNSPPCEXP3: r =3D s->apbexp[offset_to_ppc_idx(offset)].ns; break; - case A_AHBSPPPCEXP0: - case A_AHBSPPPCEXP1: - case A_AHBSPPPCEXP2: - case A_AHBSPPPCEXP3: + case A_AHBSPPPCEXP0 ... A_AHBSPPPCEXP3: r =3D s->ahbexp[offset_to_ppc_idx(offset)].sp; break; case A_APBSPPPC0: case A_APBSPPPC1: r =3D s->apb[offset_to_ppc_idx(offset)].sp; break; - case A_APBSPPPCEXP0: - case A_APBSPPPCEXP1: - case A_APBSPPPCEXP2: - case A_APBSPPPCEXP3: + case A_APBSPPPCEXP0 ... A_APBSPPPCEXP3: r =3D s->apbexp[offset_to_ppc_idx(offset)].sp; break; case A_SECMSCINTSTAT: @@ -228,18 +216,7 @@ static MemTxResult iotkit_secctl_s_read(void *opaque, = hwaddr addr, case A_NSMSCEXP: r =3D s->nsmscexp; break; - case A_PID4: - case A_PID5: - case A_PID6: - case A_PID7: - case A_PID0: - case A_PID1: - case A_PID2: - case A_PID3: - case A_CID0: - case A_CID1: - case A_CID2: - case A_CID3: + case A_PID4 ... A_CID3: switch (s->sse_version) { case ARMSSE_SSE300: r =3D iotkit_secctl_s_sse300_idregs[(offset - A_PID4) / 4]; @@ -389,10 +366,7 @@ static MemTxResult iotkit_secctl_s_write(void *opaque,= hwaddr addr, case A_BRGINTEN: s->brginten =3D value & 0xffff0000; break; - case A_AHBNSPPCEXP0: - case A_AHBNSPPCEXP1: - case A_AHBNSPPCEXP2: - case A_AHBNSPPCEXP3: + case A_AHBNSPPCEXP0 ... A_AHBNSPPCEXP3: ppc =3D &s->ahbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_ns_write(ppc, value); break; @@ -401,17 +375,11 @@ static MemTxResult iotkit_secctl_s_write(void *opaque= , hwaddr addr, ppc =3D &s->apb[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_ns_write(ppc, value); break; - case A_APBNSPPCEXP0: - case A_APBNSPPCEXP1: - case A_APBNSPPCEXP2: - case A_APBNSPPCEXP3: + case A_APBNSPPCEXP0 ... A_APBNSPPCEXP3: ppc =3D &s->apbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_ns_write(ppc, value); break; - case A_AHBSPPPCEXP0: - case A_AHBSPPPCEXP1: - case A_AHBSPPPCEXP2: - case A_AHBSPPPCEXP3: + case A_AHBSPPPCEXP0 ... A_AHBSPPPCEXP3: ppc =3D &s->ahbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_sp_write(ppc, value); break; @@ -420,10 +388,7 @@ static MemTxResult iotkit_secctl_s_write(void *opaque,= hwaddr addr, ppc =3D &s->apb[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_sp_write(ppc, value); break; - case A_APBSPPPCEXP0: - case A_APBSPPPCEXP1: - case A_APBSPPPCEXP2: - case A_APBSPPPCEXP3: + case A_APBSPPPCEXP0 ... A_APBSPPPCEXP3: ppc =3D &s->apbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_sp_write(ppc, value); break; @@ -444,18 +409,7 @@ static MemTxResult iotkit_secctl_s_write(void *opaque,= hwaddr addr, case A_BRGINTSTAT: case A_AHBNSPPC0: case A_AHBSPPPC0: - case A_PID4: - case A_PID5: - case A_PID6: - case A_PID7: - case A_PID0: - case A_PID1: - case A_PID2: - case A_PID3: - case A_CID0: - case A_CID1: - case A_CID2: - case A_CID3: + case A_PID4 ... A_CID3: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SecCtl S block write: " "read-only offset 0x%x\n", offset); @@ -482,34 +436,17 @@ static MemTxResult iotkit_secctl_ns_read(void *opaque= , hwaddr addr, case A_AHBNSPPPC0: r =3D 0; break; - case A_AHBNSPPPCEXP0: - case A_AHBNSPPPCEXP1: - case A_AHBNSPPPCEXP2: - case A_AHBNSPPPCEXP3: + case A_AHBNSPPPCEXP0 ... A_AHBNSPPPCEXP3: r =3D s->ahbexp[offset_to_ppc_idx(offset)].nsp; break; case A_APBNSPPPC0: case A_APBNSPPPC1: r =3D s->apb[offset_to_ppc_idx(offset)].nsp; break; - case A_APBNSPPPCEXP0: - case A_APBNSPPPCEXP1: - case A_APBNSPPPCEXP2: - case A_APBNSPPPCEXP3: + case A_APBNSPPPCEXP0 ... A_APBNSPPPCEXP3: r =3D s->apbexp[offset_to_ppc_idx(offset)].nsp; break; - case A_PID4: - case A_PID5: - case A_PID6: - case A_PID7: - case A_PID0: - case A_PID1: - case A_PID2: - case A_PID3: - case A_CID0: - case A_CID1: - case A_CID2: - case A_CID3: + case A_PID4 ... A_CID3: switch (s->sse_version) { case ARMSSE_SSE300: r =3D iotkit_secctl_ns_sse300_idregs[(offset - A_PID4) / 4]; @@ -560,10 +497,7 @@ static MemTxResult iotkit_secctl_ns_write(void *opaque= , hwaddr addr, } =20 switch (offset) { - case A_AHBNSPPPCEXP0: - case A_AHBNSPPPCEXP1: - case A_AHBNSPPPCEXP2: - case A_AHBNSPPPCEXP3: + case A_AHBNSPPPCEXP0 ... A_AHBNSPPPCEXP3: ppc =3D &s->ahbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_nsp_write(ppc, value); break; @@ -572,26 +506,12 @@ static MemTxResult iotkit_secctl_ns_write(void *opaqu= e, hwaddr addr, ppc =3D &s->apb[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_nsp_write(ppc, value); break; - case A_APBNSPPPCEXP0: - case A_APBNSPPPCEXP1: - case A_APBNSPPPCEXP2: - case A_APBNSPPPCEXP3: + case A_APBNSPPPCEXP0 ... A_APBNSPPPCEXP3: ppc =3D &s->apbexp[offset_to_ppc_idx(offset)]; iotkit_secctl_ppc_nsp_write(ppc, value); break; case A_AHBNSPPPC0: - case A_PID4: - case A_PID5: - case A_PID6: - case A_PID7: - case A_PID0: - case A_PID1: - case A_PID2: - case A_PID3: - case A_CID0: - case A_CID1: - case A_CID2: - case A_CID3: + case A_PID4 ... A_CID3: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SecCtl NS block write: " "read-only offset 0x%x\n", offset); --=20 2.53.0 From nobody Wed Aug 26 20:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1785943931; cv=none; d=zohomail.com; s=zohoarc; b=nZcPLD63cv5sgP/jRWN4sNYDYK6RbUIV7xvUNcriTLZ75wrK65F0sHrzaWaHkMzSiAPI6HtrmV4Cv/NM9FGoR88KbXyff3Mx5TsF6V3Vqj9yXji/BZlUBlpjCLwJSdxrkav/QpOBNRzsdzW2W1QDzLoJjCYTOaUxpC/760Xs3PU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785943931; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=crxdewcVbBrgQDKeQex5eE0LffBCS8D/h99Th7FYPOw=; b=aVg1V2zAeOjD+YCG38ObGBVPnfljfaen/YXXpngM3sFV5b5WJBxzXhRXB0jhavuwr/1LAy4rbZDHwz7n9mQymS00BgREVDyRMDCdacNcTijJWUo4DcDD5lfVXa6PbypSAftdWVZk/fL1aMrqM8qPzssVXKd94aVvZbnBx3Lbgr4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785943931017905.9631064893317; Wed, 5 Aug 2026 08:32:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrdZh-0005sU-G0; Wed, 05 Aug 2026 11:30:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wrdZY-0005pG-LD for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:25 -0400 Received: from mail-oi1-x234.google.com ([2607:f8b0:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wrdZV-0007e3-LQ for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:23 -0400 Received: by mail-oi1-x234.google.com with SMTP id 5614622812f47-4896ae35be9so384449b6e.0 for ; Wed, 05 Aug 2026 08:30:17 -0700 (PDT) Received: from HPE-2MQ6131DV6.ams.hpecorp.net ([170.85.99.9]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae75ce1bsm2185614b6e.15.2026.08.05.08.30.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 08:30:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785943817; x=1786548617; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=crxdewcVbBrgQDKeQex5eE0LffBCS8D/h99Th7FYPOw=; b=G6sEcaL9UDLqzEE4UFCbN6zGzNA+pHJy8V2ZgHMo8xx4PF1Cor3paxw3r+SCuxQDzl DVG/VdmDR+bQZ75wjTyPZpRP5cpl4fvHelgiucCoU9sTbUFURNfAHIYRGzefqJevZedf KiqQdj7b0HGXgBI0gCEbG1JVmB93ex8ETx3uz1S4n+/418bun4tEEd0PzQduH6MQfQ/A JEaWZTJAeU5Hx535Ztl4h97pQ1j6Q0Mz8ZMQ4ESGRpRpi7jjgaNTtfnAMIsOQMVGRAJx hUoSJ6Kx1Gy25932pl2+ukZhspsvpaX3m+FdMhzEBRWUojgtWbi1MPcjsFXpAkVgzr+n nOxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785943817; x=1786548617; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=crxdewcVbBrgQDKeQex5eE0LffBCS8D/h99Th7FYPOw=; b=Own8aiw/jOA/JRPEvm8/BkVtwIlUB1oB6NPe8j+uiaPUcGwO18cgwt6PiO0lxANqCM EYzOi3+a3pUpWUoiI0Kjr98/vPlIVPy0aRbgPGlVDRbbgS3WeTgS4Z+RnDRptzy0Rpkv RV3oEHe4TYiGAam1pZvW6JRzb5WqVAMGVq0jMrGUm1ty/dzGQy+REzzlqbaJs+F27d/g qoNDHzAGXyFVoCsjuspCbmrFwZW01RznysLL5RUCBBAD//Ua+bdCwhCeD04r17UPgLZ1 9dznokaXwUea4+SOsElP3RXNg7pokcm+LS5amsL9F3QGgu+mjb7OM4pe2lPepDV2M7Yg QEeA== X-Gm-Message-State: AOJu0YyJqP7amAmrI3cN71UKgz+7tRSyjqnjgY+lsOqDR1mszBwcAzVx FmuKuCILZxJvqY3t+slALWMGAq25NmI/W5zzJ5KgmropJbNZnPHk+2tyudN9958q X-Gm-Gg: AR+sD11xQBcWYmMqFwTGArtdS7IuWf90xeYwPhkXk7FnJZc0dWSGLrmkS/WYvBdoOFn zvf/XBAW0mdF41+0s8Ss+Rtgq+wUkJWlpuYrjZwCbcWyB62Nkqizf+SItcm49F05PcQrWOyTeIZ Ow4wr8wl+7fBno9u0R5FQQwi9YZFf1ea/5niFbJg1lI9MAF4XLXgpQsde64+RomEu7PtwqdUQpG MNv3m2UdHXhDhiMCzYk5GDzbtA9Z8SjjaXA+yWZxQE5fRAKIn4xEKmzM8F0chK1nk/s+K+JZYWo N7l06Hp72G7hJyJ7/LoaIyv/eoQSejxQr2o3YyIfkEwVlvPvqGIAN+EMB/keYQretTO7+c3PWJ0 VaiPsGzndwDYH9SK91r5nnChGPmTS7suzuQTKL/5sb6INzThqGE4hP4IG0h6Y7YwNLrEd1Iwath Ha+Ve3yCaf34/oKfAifNQla3U+qjrSS0LodC1dgCH99OSZ5BiApnq8QGfU4iplT6DS/UNaVFs= X-Received: by 2002:a05:6808:14d3:b0:4a4:c608:5088 with SMTP id 5614622812f47-4afae187e21mr4185710b6e.13.1785943816658; Wed, 05 Aug 2026 08:30:16 -0700 (PDT) From: Simon Xu To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Owen Giles , Peter Maydell , Pierrick Bouvier , Robert Elliott , Simon Xu Subject: [PATCH v2 7/9] hw/misc/iotkit-sysinfo.c: add SSE-310 support Date: Wed, 5 Aug 2026 10:30:03 -0500 Message-ID: <20260805153005.9989-8-simonxhy0404@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260805153005.9989-1-simonxhy0404@gmail.com> References: <20260805153005.9989-1-simonxhy0404@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=simonxhy0404@gmail.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785943933128158500 Content-Type: text/plain; charset="utf-8" Add SSE-310 PIDR and CIDR registers. Add sys_config2 register and always report 0 on read as we do not implement the NPU. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell --- v1 -> v2 Hard code sys_config2 to return 0 as we don't implement NPU0 --- hw/misc/iotkit-sysinfo.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index 19f089e6ee..f3d07f3247 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -31,6 +31,7 @@ REG32(SYS_VERSION, 0x0) REG32(SYS_CONFIG, 0x4) REG32(SYS_CONFIG1, 0x8) +REG32(SYS_CONFIG2, 0xc) REG32(IIDR, 0xfc8) REG32(PID4, 0xfd0) REG32(PID5, 0xfd4) @@ -58,6 +59,12 @@ static const int sysinfo_sse300_id[] =3D { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; =20 +static const int sysinfo_sse310_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0x58, 0xb8, 0x2b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr offset, unsigned size) { @@ -68,13 +75,22 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwadd= r offset, case A_SYS_VERSION: r =3D s->sys_version; break; - case A_SYS_CONFIG: r =3D s->sys_config; break; case A_SYS_CONFIG1: switch (s->sse_version) { case ARMSSE_SSE300: + case ARMSSE_SSE310: + return 0; + break; + default: + goto bad_read; + } + break; + case A_SYS_CONFIG2: + switch (s->sse_version) { + case ARMSSE_SSE310: return 0; break; default: @@ -84,6 +100,7 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr= offset, case A_IIDR: switch (s->sse_version) { case ARMSSE_SSE300: + case ARMSSE_SSE310: return s->iidr; break; default: @@ -95,6 +112,9 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr= offset, case ARMSSE_SSE300: r =3D sysinfo_sse300_id[(offset - A_PID4) / 4]; break; + case ARMSSE_SSE310: + r =3D sysinfo_sse310_id[(offset - A_PID4) / 4]; + break; default: r =3D sysinfo_id[(offset - A_PID4) / 4]; break; --=20 2.53.0 From nobody Wed Aug 26 20:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1785943982; cv=none; d=zohomail.com; s=zohoarc; b=Q7ctD+/OszfHchBNg44baEKvLqyF0aQk07qEfh3Sr1yWe3RjW+nctwpz1HYEGkV6Dkhafq6HbsaPBKbRMztNG0RuFeTqRDBVaE2LzjVZGjfoYc26LxxvfuBKnlPNsHrdYVscN9eUYsSn4sPObhJnDAMftEEdyQ5J99w0mYOlYVA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785943982; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ohcG8pgswlTjm53uOt+LoCB/5w9mw1ixcb2ML+/YikM=; b=LSieYqWZAwcNIIvfFvJIsj2ILFBGMs9qj29SDX43ARfe82N0PoiwXNo4iUdQdee57AVCwaSn6flxusSeVAxjvLaRt7fAWQrNObV2qNxaLQhI9SnZZeMRFu0w9uCMou5AzFnLvJ1Ik3AHpZaBYh/YcIrFWXLuEQAaXoTGzbpLcF0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17859439822551003.0066597032953; Wed, 5 Aug 2026 08:33:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrdZg-0005rZ-N8; Wed, 05 Aug 2026 11:30:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wrdZZ-0005pn-S6 for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:27 -0400 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wrdZT-0007eT-On for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:23 -0400 Received: by mail-oi1-x22a.google.com with SMTP id 5614622812f47-4a4c6081f9fso373387b6e.3 for ; Wed, 05 Aug 2026 08:30:18 -0700 (PDT) Received: from HPE-2MQ6131DV6.ams.hpecorp.net ([170.85.99.9]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae75ce1bsm2185614b6e.15.2026.08.05.08.30.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 08:30:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785943818; x=1786548618; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ohcG8pgswlTjm53uOt+LoCB/5w9mw1ixcb2ML+/YikM=; b=A1m4VbeSca9RcAWeW0h594eaUfEPykX6rJb4PuqohUQneaAamLRzxyzWT1CLFl+f/Z 8SjH1y2NsxRGV9hFLTWsONF4MrooSxEXmg5YRYcr9EhHl4Baf8mqHVnmpgoVrxbpL1hK kg2hZ/Jp5wJoBNAAVF0nqC3EO2c4D3NLBcWv1hksERPHgEF2dV/u3AGk+N451Mqo14Np 4knLWBeOgqob/EKcMZe0tCs7U3y9XlOM/JTUPEJYBS/Viu2n0EatBS0PJUYaQgGRMcN1 /rUR3fsJUsGhnjnfudhLO5WvYrMYyIU65V7p9HJ5sJot4cwMevWh4NGKc4yTfk3teouO qo0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785943818; x=1786548618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=ohcG8pgswlTjm53uOt+LoCB/5w9mw1ixcb2ML+/YikM=; b=iARwlkpJM3gsKLLz9qH4eay66UYQ6EUDEJhKNMBkhPXHIlmhVvjSlpZk2et1j9Jgnb 5HOyP1D5QghCbY/lG0pnZitLY1QLw0H/nxlBRcZrq1k38uJ6gMPINn4VT3FKDlLBB5af a0Z33dwJSBkOEET3OSC8fcVgWRq2od1AihlxE7LmGJUunXiE2ud0/yjSAD4knQgisKx4 Bt9SeX93Ce0LdQ7KcgnsBgWATAct7HFvzejWh5QCsHzOQVK4YhZjTMjoDayDdLveyyyY jx9S+b8cdPRnBfj0jwbzSehaZAHj7XVBxPCriLNG/dSzjlWLr01xauUfmYF2nwxHBD58 5oIw== X-Gm-Message-State: AOJu0YzY1s0Qpp5zw7/mTi7hMu3Z9qg2LvwksrrK3Si8hAdycJi/7cZk peAlQWRSNLFdTmPB3O7s6Tep9JsyrgFjnAnyGPNwC4Zzk+nu+a2xRb4TrCEcOXaw X-Gm-Gg: AR+sD10+eHtU3DRfof1jBzgeGi3vJeEyBhMlACWvIrWcOFjXNQCftBr2pKtu+oc6NlI lDnjn9R7zFnePydxJ2c3gV0q4P3XjEhzijK227JeSHChZyGM5L/gfhG7cgDww1gdXKvYH7FDVnH UlSwBHk1QRvkkgDFp7DocsOosLhD3SDGaoBNnoWP1QPg3c8BL0lDD11fzU6wjzODktkRnyr9yI3 2qxYeWLIVHiaNLAdizwypNthjHKk5nEwLm6XSrfktQC3ZZ3bo7CGil9i/oLMRj8EUI6nxyTRDkl fkFzUFkrTgo1LZlMI3Bcd9V7CAEyKkMdlzGvcBf7k/fv4blPVGTVGLy33ElN1TN1CQEvjOrXzvX lzZID3qoLwvThza0JdGHHgAb9d6jJ/lT3AVDn1x/3aRzP2ekEGOi1uCHuJ4Vwq+P92X2bTMIs3t xItm9VEkNXnVv1Xzi3ejo8C4h8uXwG4y1aabWM2YKENzVHdI+eVydZiP7d7ndNgMBindKnm72ER LblfXn63MvI0oT9Gm9DNhU= X-Received: by 2002:a05:6808:1919:b0:495:d7ec:b6be with SMTP id 5614622812f47-4afae193bedmr4734324b6e.18.1785943817591; Wed, 05 Aug 2026 08:30:17 -0700 (PDT) From: Simon Xu To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Owen Giles , Peter Maydell , Pierrick Bouvier , Robert Elliott , Simon Xu Subject: [PATCH v2 8/9] hw/arm/mps2-tz.c add Arm mps3-an555 board Date: Wed, 5 Aug 2026 10:30:04 -0500 Message-ID: <20260805153005.9989-9-simonxhy0404@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260805153005.9989-1-simonxhy0404@gmail.com> References: <20260805153005.9989-1-simonxhy0404@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=simonxhy0404@gmail.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785943984362158500 Content-Type: text/plain; charset="utf-8" Add mps3-an555 board modeled after the existing mps3-an547 board. Add UnimplementedDeivceState for timing adapters and qspi controllers in MPS2TZMachineState. Changes in AN555: Timing adapters in APB PPC EX0 instead of MPC. Additional QSPI controllers in AHB PPC EX0. Additional AHB PPC EX1 with DMA. Create standalone unimplemented devices for MPC instead of timing adapters. Include documentation for SSE-310 and mps3-an555. Arm mps3-an555 TRM: https://developer.arm.com/documentation/107642/latest/ Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu Reviewed-by: Peter Maydell --- v1 -> v2 Move board and application note documentation locations Revert MPS2TZ_NUMIRQ_MAX to 96 from 100 Fix timing adapter and MPC creation location Add QSPI controller to AHB PPC EX0 Add GPIOALT2 register to FPGAIO block in next patch --- docs/system/arm/mps2.rst | 6 +- hw/arm/mps2-tz.c | 153 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 154 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index a305935cc4..489a8b0fa7 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,5 +1,5 @@ -Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, = ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an53= 6``, ``mps3-an547``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, = ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an53= 6``, ``mps3-an547``, ``mps3-an555``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 These board models use Arm M-profile or R-profile CPUs. =20 @@ -31,6 +31,8 @@ FPGA images using M-profile CPUs: Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524 ``mps3-an547`` Cortex-M55 on an MPS3, as documented in Arm Application Note AN547 +``mps3-an555`` + Cortex-M85 on an MPS3, as documented in Arm Application Note AN555 =20 FPGA images using R-profile CPUs: =20 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index f101c1b7c3..2cb461ca71 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -1,5 +1,5 @@ /* - * ARM V2M MPS2 board emulation, trustzone aware FPGA images + * Arm V2M MPS2 and MPS3 board emulation, trustzone aware FPGA images * * Copyright (c) 2017 Linaro Limited * Written by Peter Maydell @@ -18,13 +18,17 @@ * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN= 547 + * "mps3-an555" -- Single Cortex-M85 as documented in Application Note AN= 555 * * Links to the TRM for the board itself and to the various Application * Notes which document the FPGA images can be found here: * https://developer.arm.com/products/system-design/development-boards/fpg= a-prototyping-boards/mps2 * - * Board TRM: + * MPS2 and MPS2+ Board TRM: * https://developer.arm.com/documentation/100112/latest/ + * MPS3 Board TRM: + * https://developer.arm.com/documentation/100765/latest/ + *=20 * Application Note AN505: * https://developer.arm.com/documentation/dai0505/latest/ * Application Note AN521: @@ -33,6 +37,8 @@ * https://developer.arm.com/documentation/dai0524/latest/ * Application Note AN547: * https://developer.arm.com/documentation/dai0547/latest/ + * Application Note AN555: + * https://developer.arm.com/documentation/107642/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Gu= ide * (ARM ECM0601256) for the details of some of the device layout: @@ -42,6 +48,8 @@ * https://developer.arm.com/documentation/101104/latest/ * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM: * https://developer.arm.com/documentation/101773/latest/ + * and the AN555 uses the SSE-310, whose layout is in the SSE-310 TRM: + * https://developer.arm.com/documentation/102778/latest/ */ =20 #include "qemu/osdep.h" @@ -85,6 +93,7 @@ typedef enum MPS2TZFPGAType { FPGA_AN521, FPGA_AN524, FPGA_AN547, + FPGA_AN555, } MPS2TZFPGAType; =20 /* @@ -153,6 +162,8 @@ struct MPS2TZMachineState { UnimplementedDeviceState gfx; UnimplementedDeviceState cldc; UnimplementedDeviceState usb; + UnimplementedDeviceState ta[3]; /* timing adatper */ + UnimplementedDeviceState qspi_controller[3]; PL031State rtc; PL080State dma[4]; TZMSC msc[4]; @@ -173,6 +184,7 @@ struct MPS2TZMachineState { #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547") +#define TYPE_MPS3TZ_AN555_MACHINE MACHINE_TYPE_NAME("mps3-an555") =20 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) =20 @@ -207,6 +219,15 @@ static const uint32_t an524_oscclk[] =3D { 23750000, }; =20 +static const uint32_t an555_oscclk[] =3D { + 24000000, + 25000000, + 30000000, + 50000000, + 24576000, + 23750000, +}; + static const RAMInfo an505_raminfo[] =3D { { .name =3D "ssram-0", .base =3D 0x00000000, @@ -1028,7 +1049,6 @@ static void mps2tz_common_init(MachineState *machine) { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, {= 38, 39, 45 } }, { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, {= 40, 41, 46 } }, { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, {= 124, 125, 126 } }, - { /* port 9 reserved */ }, { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, @@ -1082,7 +1102,63 @@ static void mps2tz_common_init(MachineState *machine) { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, {= 39, 40, 46 } }, { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, {= 41, 42, 47 } }, { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, {= 125, 126, 127 } }, + { /* port 9 reserved */ }, + { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, + { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, + }, + }, { + .name =3D "ahb_ppcexp0", + .ports =3D { + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x10= 00 }, + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x10= 00 }, + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x10= 00 }, + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x10= 00 }, + { /* port 4 USER AHB interface 0 */ }, + { /* port 5 USER AHB interface 1 */ }, + { /* port 6 USER AHB interface 2 */ }, + { /* port 7 USER AHB interface 3 */ }, + { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 4= 9 } }, + }, + }, + }; =20 + const PPCInfo an555_ppcs[] =3D { { + .name =3D "apb_ppcexp0", + .ports =3D { + { "sram-timing-adapter", make_unimp_dev, &mms->ta[0], 0x41= 700000, 0x1000 }, + { "qspi-timing-adapter", make_unimp_dev, &mms->ta[1], 0x41= 701000, 0x1000 }, + { "ddr4-timing-adapter", make_unimp_dev, &mms->ta[2], 0x41= 702000, 0x1000 }, + }, + }, { + .name =3D "apb_ppcexp1", + .ports =3D { + { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000, {}, + { .i2c_internal =3D true /* touchscreen */ } }, + { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000, {}, + { .i2c_internal =3D true /* audio conf */ } }, + { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53= } }, + { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54= } }, + { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55= } }, + { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000, {}, + { .i2c_internal =3D false /* shield 0 */ } }, + { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000, {}, + { .i2c_internal =3D false /* shield 1 */ } }, + { /* port 7 reserved */ }, + { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000, {}, + { .i2c_internal =3D true /* DDR4 EEPROM */ } }, + }, + }, { + .name =3D "apb_ppcexp2", + .ports =3D { + { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000= , 0x1000 }, + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 = }, + { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, {= 33, 34, 43 } }, + { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, {= 35, 36, 44 } }, + { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, {= 37, 38, 45 } }, + { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, {= 39, 40, 46 } }, + { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, {= 41, 42, 47 } }, + { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, {= 125, 126, 127 } }, { /* port 9 reserved */ }, { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, @@ -1099,6 +1175,24 @@ static void mps2tz_common_init(MachineState *machine) { /* port 6 USER AHB interface 2 */ }, { /* port 7 USER AHB interface 3 */ }, { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 4= 9 } }, + { /* port 9 reserved */ }, + { /* port 10 reserved */ }, + { /* port 11 reserved */ }, + { /* port 12 reserved */ }, + { "qspi-controller0", make_unimp_dev, &mms->qspi_controlle= r[0], + 0x41800000, 0x1000 }, + { "qspi-controller1", make_unimp_dev, &mms->qspi_controlle= r[1], + 0x41801000, 0x1000 }, + { "qspi-controller2", make_unimp_dev, &mms->qspi_controlle= r[2], + 0x41802000, 0x1000 }, + }, + }, { + .name =3D "ahb_ppcexp1", + .ports =3D { + { "dma0", make_dma, &mms->dma[0], 0x41200000, 0x1000, { 59= , 57, 58 } }, + { "dma1", make_dma, &mms->dma[1], 0x41201000, 0x1000, { 62= , 60, 61 } }, + { "dma2", make_dma, &mms->dma[2], 0x41202000, 0x1000, { 65= , 63, 64 } }, + { "dma3", make_dma, &mms->dma[3], 0x41203000, 0x1000, { 68= , 66, 67 } }, }, }, }; @@ -1117,6 +1211,10 @@ static void mps2tz_common_init(MachineState *machine) ppcs =3D an547_ppcs; num_ppcs =3D ARRAY_SIZE(an547_ppcs); break; + case FPGA_AN555: + ppcs =3D an555_ppcs; + num_ppcs =3D ARRAY_SIZE(an555_ppcs); + break; default: g_assert_not_reached(); } @@ -1200,6 +1298,12 @@ static void mps2tz_common_init(MachineState *machine) create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x= 1000); } =20 + if (mmc->fpga_type =3D=3D FPGA_AN555) { + create_unimplemented_device("SRAM MPC", 0x57000000, 0x1000); + create_unimplemented_device("QSPI MPC", 0x57001000, 0x1000); + create_unimplemented_device("DDR4 MPC", 0x57002000, 0x1000); + } + create_non_mpc_ram(mms); =20 if (mmc->fpga_type =3D=3D FPGA_AN524) { @@ -1447,6 +1551,41 @@ static void mps3tz_an547_class_init(ObjectClass *oc,= const void *data) mps2tz_set_default_ram_info(mmc); } =20 +static void mps3tz_an555_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m85"), + NULL + }; + + mc->desc =3D "ARM MPS3 with AN555 FPGA image for Cortex-M85"; + mc->default_cpus =3D 1; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; + mmc->fpga_type =3D FPGA_AN555; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m85"); + mc->valid_cpu_types =3D valid_cpu_types; + mmc->scc_id =3D 0x41055551; + mmc->sysclk_frq =3D 25 * 1000 * 1000; /* 25MHz */ + mmc->apb_periph_frq =3D 25 * 1000 * 1000; /* 25MHz */ + mmc->oscclk =3D an555_oscclk; + mmc->len_oscclk =3D ARRAY_SIZE(an555_oscclk); + mmc->fpgaio_num_leds =3D 10; + mmc->fpgaio_has_switches =3D true; + mmc->fpgaio_has_dbgctrl =3D true; + mmc->numirq =3D 96; + mmc->uart_overflow_irq =3D 48; + mmc->init_svtor =3D 0x00000000; + mmc->cpu0_mpu_s =3D mmc->cpu0_mpu_ns =3D 8; + mmc->sram_addr_width =3D 21; + mmc->raminfo =3D an547_raminfo; /* same as AN547*/ + mmc->armsse_type =3D TYPE_SSE310; + mmc->boot_ram_size =3D 512 * KiB; + mps2tz_set_default_ram_info(mmc); +} + static const TypeInfo mps2tz_info =3D { .name =3D TYPE_MPS2TZ_MACHINE, .parent =3D TYPE_MACHINE, @@ -1488,6 +1627,13 @@ static const TypeInfo mps3tz_an547_info =3D { .interfaces =3D arm_machine_interfaces, }; =20 +static const TypeInfo mps3tz_an555_info =3D { + .name =3D TYPE_MPS3TZ_AN555_MACHINE, + .parent =3D TYPE_MPS2TZ_MACHINE, + .class_init =3D mps3tz_an555_class_init, + .interfaces =3D arm_machine_interfaces, +}; + static void mps2tz_machine_init(void) { type_register_static(&mps2tz_info); @@ -1495,6 +1641,7 @@ static void mps2tz_machine_init(void) type_register_static(&mps2tz_an521_info); type_register_static(&mps3tz_an524_info); type_register_static(&mps3tz_an547_info); + type_register_static(&mps3tz_an555_info); } =20 type_init(mps2tz_machine_init); --=20 2.53.0 From nobody Wed Aug 26 20:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1785943877; cv=none; d=zohomail.com; s=zohoarc; b=LOxjBSYCHC2xTn5/TxTkr+BR6Wd2ikVvoWbtGyeNAvZofHqgM6rEcjJshHma5BmprmbUov15n8WVLP3c4dvSh2fFUzPMztAnFBRD38Bc3uwuWTWZr5VO4rqBNGPqycqlGCd9t7gvM5DGSCIJCMlrOQysojjHqhdGEULbWa1KKoU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785943877; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fU96bK353k5ADv3CzrrtydkHbKOwXgwzsqMVSvU+exo=; b=IDrYnJlhFuZayQbwQJjWzyb4i7sEpS74aoY4S1q2SQu+8Rff0e5E6+ntelslvKmyLABOdeCNObcMd9WmuPITfJJWKjwfX9IvSiF9uqNlH0CKZsGfiXYGgEyFlQUvaLQxWKHTO/7gr9YWWI3MCs91j7Go6KpAjNM3fhWWaRqUgeo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785943877090575.6322289890347; Wed, 5 Aug 2026 08:31:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wrdZg-0005qy-1d; Wed, 05 Aug 2026 11:30:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wrdZZ-0005pJ-MQ for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:25 -0400 Received: from mail-oi1-x234.google.com ([2607:f8b0:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wrdZV-0007eu-Ko for qemu-devel@nongnu.org; Wed, 05 Aug 2026 11:30:23 -0400 Received: by mail-oi1-x234.google.com with SMTP id 5614622812f47-495c63c4141so656804b6e.2 for ; Wed, 05 Aug 2026 08:30:20 -0700 (PDT) Received: from HPE-2MQ6131DV6.ams.hpecorp.net ([170.85.99.9]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4afae75ce1bsm2185614b6e.15.2026.08.05.08.30.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 08:30:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785943819; x=1786548619; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=fU96bK353k5ADv3CzrrtydkHbKOwXgwzsqMVSvU+exo=; b=gISDWt2D5HE+I4am/QWlUJXU5nxmaqig2VEP43pgS1WDbjF7GJBSMh7M/Zv/Nyyjg5 IuN7Vcise94j8XZKqNkFcrMmNESyHAlYqzHh6pxfakw4q+sLQDQqvv/wYLiYbHutui4o GjMhUXi5j4yXaiCCQCL0WAmNpEodSOYc8EM44QUrx4iD/9vGON53Thb0dBtQFtOEBaKl wxBT19EvlZWfGkun3gHu+hVhrH6V93XB/Kg6JNb8vV32CLq/5aBUMlbw0cRmcwA/dPuE mznZxerSWmhRWSqQGlxiTtM/d/Vmf1jh2pWWO8WBjK9vZwL6ynX7Yy2iYB3wLtHU43Wd Bb/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785943819; x=1786548619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=fU96bK353k5ADv3CzrrtydkHbKOwXgwzsqMVSvU+exo=; b=P2ZA/k5u0nHtnbEAbQNx2ozsMhaAycQ+iS5JBtbVSZGRrCKY8nDnP0FlQYy/yf46mJ zif1QhCJKt9j8Lvh7xjDj6k2kaRObsOfQys9bOE/4NFiK6Rk6eTCIjXcf7O4oRdcuPAw 1+MPe6mxVpfcoB5fW246KL8vvKRZnhmFFPf/aPSk1VjWvXjgVdjoa7SofmM6ag+WVzPs r33VQ5l7o8sl2u2UPBoBf/D/aJ9FsjI3vvvWQpPuAvOsTrJUNP/yhRMuRBMyy3DZBB5g nA4ACcve6v5cd/zhPItDPhzjmGDtiP6uzneIM2SUt7r39/ZWq3E8mQFA7dSiCO3KE9UO VZpg== X-Gm-Message-State: AOJu0Yx60eD/dMy+hdhpI0S8wpsIx/dhxcHXhn6NWJYh92bcqeKtgLmt UHQaH0fAE9dBJE5kVVi2hk9UqaTrJedseci/TkIpJwzevULLC//9X/bAel5wcd0D X-Gm-Gg: AR+sD11nWt+OYMULssgL73ZxAPlg/mL+VqzczxifQzxU2Utum1TzGxXb9bYBpr1Ldyg a04rRTyXtOu+lt9iqweWdIZFO81dXZ/zr5EnGxWV3qqO1a93yLG3S+Z0/TT0b9QnceyrdF0CbtT 0amuepsixKISYnVJ8P2SI2dcXcrij23UYcru/1GWM/8SnwCn4g1aXuQMmeKfcNkRiGKFFAgFQuI Igkicy0khm67DFG18QwpB4W1019Z5dAyimXE1i+pXQm6K0uIcdNODPKnvo0SgjdCkaqATVafGwm D0HtgEs3fL7ygg0QUWgRgV8A6ltH5SanscfDgvc0n7BW8QjTPPYoEdFSR6s16SLfZKB9bJjfZJe LrmMQCeHFwo33FX79vyht1APddEc2KdwerCRTYjDqDbCdTCoYxGalo93yPjas02sKOBDE01ReN8 n6s9VRIlY47zc3eWMZ1hZsutcMM1zL86TMsFU+WbwLvM4unSlimMnJpeOyHnKwizM/Nw5XGGJRT 09c4m1eM+hs X-Received: by 2002:a05:6808:2227:b0:495:d7ec:b6ae with SMTP id 5614622812f47-4afae16981emr4950546b6e.16.1785943818680; Wed, 05 Aug 2026 08:30:18 -0700 (PDT) From: Simon Xu To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Owen Giles , Peter Maydell , Pierrick Bouvier , Robert Elliott , Simon Xu Subject: [PATCH v2 9/9] hw/misc/mps2-fpgaio.c: add GPIOALT2 register Date: Wed, 5 Aug 2026 10:30:05 -0500 Message-ID: <20260805153005.9989-10-simonxhy0404@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260805153005.9989-1-simonxhy0404@gmail.com> References: <20260805153005.9989-1-simonxhy0404@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=simonxhy0404@gmail.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785943880205158500 Content-Type: text/plain; charset="utf-8" Add GPIOALT2 register for new an555 board. Implement register access as RW with LOG_UNIMP for writes. Add "has-gpioalt2" property to make each board configurable. Reviewed-by: Owen Giles Reviewed-by: Robert Elliott Signed-off-by: Simon Xu --- hw/arm/mps2-tz.c | 7 +++++++ hw/misc/mps2-fpgaio.c | 13 +++++++++++++ include/hw/misc/mps2-fpgaio.h | 2 ++ 3 files changed, 22 insertions(+) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 2cb461ca71..d9f64880f8 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -131,6 +131,7 @@ struct MPS2TZMachineClass { uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */ + bool fpgaio_has_gpioalt2; /* Does FPGAIO have GPIOALT2 register? */ int numirq; /* Number of external interrupts */ int uart_overflow_irq; /* number of the combined UART overflow IRQ */ uint32_t init_svtor; /* init-svtor setting for SSE */ @@ -515,6 +516,7 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mm= s, void *opaque, qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_swit= ches); qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgct= rl); + qdev_prop_set_bit(DEVICE(fpgaio), "has-gpioalt2", mmc->fpgaio_has_gpio= alt2); sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); } @@ -1433,6 +1435,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, = const void *data) mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; mmc->fpgaio_has_dbgctrl =3D false; + mmc->fpgaio_has_gpioalt2 =3D false; mmc->numirq =3D 92; mmc->uart_overflow_irq =3D 47; mmc->init_svtor =3D 0x10000000; @@ -1467,6 +1470,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, = const void *data) mmc->fpgaio_num_leds =3D 2; mmc->fpgaio_has_switches =3D false; mmc->fpgaio_has_dbgctrl =3D false; + mmc->fpgaio_has_gpioalt2 =3D false; mmc->numirq =3D 92; mmc->uart_overflow_irq =3D 47; mmc->init_svtor =3D 0x10000000; @@ -1501,6 +1505,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, = const void *data) mmc->fpgaio_num_leds =3D 10; mmc->fpgaio_has_switches =3D true; mmc->fpgaio_has_dbgctrl =3D false; + mmc->fpgaio_has_gpioalt2 =3D false; mmc->numirq =3D 95; mmc->uart_overflow_irq =3D 47; mmc->init_svtor =3D 0x10000000; @@ -1540,6 +1545,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, = const void *data) mmc->fpgaio_num_leds =3D 10; mmc->fpgaio_has_switches =3D true; mmc->fpgaio_has_dbgctrl =3D true; + mmc->fpgaio_has_gpioalt2 =3D false; mmc->numirq =3D 96; mmc->uart_overflow_irq =3D 48; mmc->init_svtor =3D 0x00000000; @@ -1575,6 +1581,7 @@ static void mps3tz_an555_class_init(ObjectClass *oc, = const void *data) mmc->fpgaio_num_leds =3D 10; mmc->fpgaio_has_switches =3D true; mmc->fpgaio_has_dbgctrl =3D true; + mmc->fpgaio_has_gpioalt2 =3D true; mmc->numirq =3D 96; mmc->uart_overflow_irq =3D 48; mmc->init_svtor =3D 0x00000000; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index da78cb6070..6696384a25 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -31,6 +31,7 @@ REG32(LED0, 0) REG32(DBGCTRL, 4) REG32(BUTTON, 8) +REG32(GPIOALT2, 0xc) REG32(CLK1HZ, 0x10) REG32(CLK100HZ, 0x14) REG32(COUNTER, 0x18) @@ -142,6 +143,9 @@ static uint64_t mps2_fpgaio_read(void *opaque, hwaddr o= ffset, unsigned size) */ r =3D 0; break; + case A_GPIOALT2: + r =3D s->gpioalt2; + break; case A_PRESCALE: r =3D s->prescale; break; @@ -210,6 +214,14 @@ static void mps2_fpgaio_write(void *opaque, hwaddr off= set, uint64_t value, "MPS2 FPGAIO: DBGCTRL unimplemented\n"); s->dbgctrl =3D value; break; + case A_GPIOALT2: + if (!s->has_gpioalt2) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "MPS2 FPGAIO: GPIOALT2 unimplemented\n"); + s->gpioalt2 =3D value; + break; case A_PRESCALE: resync_counter(s); s->prescale =3D value; @@ -326,6 +338,7 @@ static const Property mps2_fpgaio_properties[] =3D { DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO, has_switches, false), DEFINE_PROP_BOOL("has-dbgctrl", MPS2FPGAIO, has_dbgctrl, false), + DEFINE_PROP_BOOL("has-gpioalt2", MPS2FPGAIO, has_gpioalt2, false), }; =20 static void mps2_fpgaio_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index edd9f23121..7512686616 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -40,11 +40,13 @@ struct MPS2FPGAIO { uint32_t num_leds; bool has_switches; bool has_dbgctrl; + bool has_gpioalt2; =20 uint32_t led0; uint32_t prescale; uint32_t misc; uint32_t dbgctrl; + uint32_t gpioalt2; =20 /* QEMU_CLOCK_VIRTUAL time at which counter and pscntr were last synce= d */ int64_t pscntr_sync_ticks; --=20 2.53.0