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Tue, 04 Aug 2026 01:15:09 -0700 (PDT) From: Wadim Mueller To: qemu-devel@nongnu.org Cc: philmd@linaro.org, bmeng.cn@gmail.com, qemu-block@nongnu.org, Wadim Mueller Subject: [PATCH] hw/sd/sdhci: complete non-interrupt ADMA descriptor chains in one pass Date: Tue, 4 Aug 2026 10:14:59 +0200 Message-ID: <20260804081459.8007-1-wafgo01@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=wafgo01@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785831338778158500 Content-Type: text/plain; charset="utf-8" sdhci_do_adma() processes at most SDHC_ADMA_DESCS_PER_DELAY descriptors per invocation and then reschedules itself SDHC_TRANSFER_DELAY ns later on QEMU_CLOCK_VIRTUAL. For a large bulk transfer this spreads the DMA across hundreds of virtual-clock round-trips, advancing the guest's virtual time between descriptor batches. A guest that bounds the transfer with its own data/status timeout (counted in guest time) can then see that timeout expire mid-transfer. Concretely, U-Boot on a TI AM64x reading a ~28 MiB image with a single CMD18 multi-block ADMA2 read intermittently aborts with "Timeout for status update" and falls back to (failing) distro boot. The transfer itself is correct; only the artificial per-batch pacing triggers the guest timeout. Run a descriptor chain that carries no SDHC_ADMA_ATTR_INT attribute to completion within a single call. Chains that do request a DMA-boundary interrupt still deliver it and reschedule exactly as before, so a guest relying on that pacing is unaffected. Now that the per-call bound is gone, cap the number of descriptors processed per call so that a malformed or circular descriptor list (a self-referencing link, or a persistently faulting non-END/non-INT descriptor) cannot spin the calling thread forever; on overflow, break to the existing reschedule path so the main loop stays responsive. Signed-off-by: Wadim Mueller --- hw/sd/sdhci-internal.h | 9 +++++++++ hw/sd/sdhci.c | 23 +++++++++++++++++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 9f768c418e..bb586a9666 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -278,6 +278,15 @@ FIELD(SDHC_MAXCURR, V18_VDD2, 32, 8); /* since= v4.20 */ #define SDHC_INSERTION_DELAY (NANOSECONDS_PER_SECOND) #define SDHC_TRANSFER_DELAY 100 #define SDHC_ADMA_DESCS_PER_DELAY 5 +/* + * Upper bound on ADMA2 descriptors handled in a single sdhci_do_adma() + * call, as a safety valve against a malformed or circular descriptor + * list. A well-formed transfer terminates far below this via END or + * blkcnt =3D=3D 0 (even a 4 GiB transfer built from 64 KiB TRAN descripto= rs + * is only ~64K descriptors); the bound merely guarantees the loop makes + * a decision instead of spinning forever. + */ +#define SDHC_ADMA_MAX_DESCRIPTORS (1 << 20) #define SDHC_CMD_RESPONSE (3 << 0) =20 enum { diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 89b595ce4a..e8e8928b4f 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -779,7 +779,6 @@ static void sdhci_do_adma(SDHCIState *s) const MemTxAttrs attrs =3D { .memory =3D true }; ADMADescr dscr =3D {}; MemTxResult res =3D MEMTX_ERROR; - int i; =20 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN && !s->blkcnt) { /* Stop Multiple Transfer */ @@ -787,7 +786,27 @@ static void sdhci_do_adma(SDHCIState *s) return; } =20 - for (i =3D 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { + /* + * Process the descriptor chain to completion (END or blkcnt =3D=3D 0), + * yielding to the guest only for a descriptor carrying the INT + * attribute (a DMA-boundary interrupt, handled at the end of the loop= ). + * + * Historically at most SDHC_ADMA_DESCS_PER_DELAY descriptors were + * handled per call before rescheduling SDHC_TRANSFER_DELAY ns later on + * QEMU_CLOCK_VIRTUAL. That pacing is only needed so a guest can obser= ve + * the intermediate DMA-interrupt state; a bulk transfer that requests + * no interrupt does not need slicing, and throttling it across many + * virtual-clock round-trips can make it race a guest-side transfer + * timeout. Run such chains to completion in one call instead. + * + * SDHC_ADMA_MAX_DESCRIPTORS bounds the loop so a malformed or circular + * chain cannot spin here forever; on overflow, break to the reschedule + * path so the main loop stays responsive. + */ + for (unsigned int adma_descs =3D 0; ; adma_descs++) { + if (adma_descs >=3D SDHC_ADMA_MAX_DESCRIPTORS) { + break; + } s->admaerr &=3D ~SDHC_ADMAERR_LENGTH_MISMATCH; =20 get_adma_description(s, &dscr); --=20 2.43.0