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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=nikhilks@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1785812146118158500 Content-Type: text/plain; charset="utf-8" Migrate load-and-reserve instructions (lbarx, lharx, lwarx, ldarx, lqarx) to decodetree using the X-form layout. A shared helper (do_load_locked) is introduced for standard-width variants, while LQARX is handled separately due to its 128-bit semantics and register pairing constraints. The implementation preserves legacy behavior, including: - Reservation granularity and overwrite semantics - Alignment requirements - Invalid instruction cases for LQARX Testing: - Verified TCG equivalence with legacy implementation Signed-off-by: Nikhil Kumar Singh Signed-off-by: Chinmay Rath [cr: ppc32 build fix, using @X_rc for decode] --- v1 -> v2: - Replaced verbose trans_XXX() handlers for lbarx, lharx, lwarx, and=20 ldarx with TRANS, TRANS64, and TRANS_FLAGS2 macros (per Chinmay). target/ppc/insn32.decode | 7 +++ target/ppc/translate.c | 124 +++++++++++++++++++-------------------- 2 files changed, 69 insertions(+), 62 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 342e65dadf..26948e08a7 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1309,6 +1309,13 @@ XVF64GERNN 111011 ... -- .... 0 ..... 11111010 = ..- @XX3_at xa=3D%xx_xa_pair ##Extend Sign Word and Shift Left Immediate XS-form EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 +## Load and Reserve Instructions +LBARX 011111 ..... ..... ..... 0000110100 . @X_rc +LHARX 011111 ..... ..... ..... 0001110100 . @X_rc +LWARX 011111 ..... ..... ..... 0000010100 . @X_rc +LDARX 011111 ..... ..... ..... 0001010100 . @X_rc +LQARX 011111 ..... ..... ..... 0100010100 . @X_rc + ## Vector Division Instructions =20 VDIVSW 000100 ..... ..... ..... 00110001011 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e627f48f9e..cc9287dcc5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2947,30 +2947,6 @@ static void gen_isync(DisasContext *ctx) ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } =20 -static void gen_load_locked(DisasContext *ctx, MemOp memop) -{ - TCGv gpr =3D cpu_gpr[rD(ctx->opcode)]; - TCGv t0 =3D tcg_temp_new(); - - gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); - tcg_gen_mov_tl(cpu_reserve, t0); - tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); - tcg_gen_mov_tl(cpu_reserve_val, gpr); -} - -#define LARX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - gen_load_locked(ctx, memop); \ -} - -/* lwarx */ -LARX(lbarx, MO_UB) -LARX(lharx, MO_UW) -LARX(lwarx, MO_UL) - static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, TCGv EA, TCGCond cond, int addend) { @@ -3219,42 +3195,9 @@ STCX(sthcx_, MO_UW) STCX(stwcx_, MO_UL) =20 #if defined(TARGET_PPC64) -/* ldarx */ -LARX(ldarx, MO_UQ) /* stdcx. */ STCX(stdcx_, MO_UQ) =20 -/* lqarx */ -static void gen_lqarx(DisasContext *ctx) -{ - int rd =3D rD(ctx->opcode); - TCGv EA, hi, lo; - TCGv_i128 t16; - - if (unlikely((rd & 1) || (rd =3D=3D rA(ctx->opcode)) || - (rd =3D=3D rB(ctx->opcode)))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - - gen_set_access_type(ctx, ACCESS_RES); - EA =3D tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - - /* Note that the low part is always in RD+1, even in LE mode. */ - lo =3D cpu_gpr[rd + 1]; - hi =3D cpu_gpr[rd]; - - t16 =3D tcg_temp_new_i128(); - tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIG= N)); - tcg_gen_extr_i128_i64(lo, hi, t16); - - tcg_gen_mov_tl(cpu_reserve, EA); - tcg_gen_movi_tl(cpu_reserve_length, 16); - tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val)); - tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2)); -} - /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { @@ -5741,6 +5684,68 @@ static bool trans_EXTSWSLI(DisasContext *ctx, arg_XS= *a) return true; } =20 +/* + * Load-and-reserve core + */ +static bool do_load_locked(DisasContext *ctx, arg_X_rc *a, MemOp memop) +{ + TCGv EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + TCGv gpr =3D cpu_gpr[a->rt]; + + gen_set_access_type(ctx, ACCESS_RES); + + tcg_gen_qemu_ld_tl(gpr, EA, ctx->mem_idx, memop | MO_ALIGN); + + tcg_gen_mov_tl(cpu_reserve, EA); + tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); + + tcg_gen_mov_tl(cpu_reserve_val, gpr); + + return true; +} + +TRANS_FLAGS2(ATOMIC_ISA206, LBARX, do_load_locked, DEF_MEMOP(MO_UB)) +TRANS_FLAGS2(ATOMIC_ISA206, LHARX, do_load_locked, DEF_MEMOP(MO_UW)) +TRANS(LWARX, do_load_locked, DEF_MEMOP(MO_UL)) +TRANS64(LDARX, do_load_locked, DEF_MEMOP(MO_UQ)) + +static bool trans_LQARX(DisasContext *ctx, arg_LQARX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); +#if defined(TARGET_PPC64) + TCGv EA; + TCGv_i128 t16; + /* Must use even register and avoid overlap */ + if (unlikely((a->rt & 1) || (a->rt =3D=3D a->ra) || (a->rt =3D=3D a->r= b))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + gen_set_access_type(ctx, ACCESS_RES); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + t16 =3D tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, + DEF_MEMOP(MO_128 | MO_ALIGN)); + + tcg_gen_extr_i128_i64(cpu_gpr[a->rt + 1], + cpu_gpr[a->rt], + t16); + + tcg_gen_mov_tl(cpu_reserve, EA); + tcg_gen_movi_tl(cpu_reserve_length, 16); + + tcg_gen_st_i64(cpu_gpr[a->rt], + tcg_env, offsetof(CPUPPCState, reserve_val)); + tcg_gen_st_i64(cpu_gpr[a->rt + 1], + tcg_env, offsetof(CPUPPCState, reserve_val2)); +#else + qemu_build_not_reached(); +#endif + return true; +} + #include "translate/fixedpoint-impl.c.inc" =20 #include "translate/fp-impl.c.inc" @@ -5853,9 +5858,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_S= TRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), -GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), @@ -5864,8 +5866,6 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00= 000000, PPC_RES), #if defined(TARGET_PPC64) GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), -GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), #endif --=20 2.54.0