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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1785442300487158500 Content-Type: text/plain; charset="utf-8" Prepare a common CFAM parent class for CFAM-S implementation. Add an abstract TYPE_FSI_CFAM_COMMON with an FSICFAMCommonClass holding what varies between types: the config table, the offsets of the FSI responder and the local bus within the register slot, and a realize_engines() hook for the engines on the local bus. Its realize is driven by those fields, so one realize serves every type. TYPE_FSI_CFAM keeps its name and becomes the first derived type, supplying the P9 config table, its slot offsets and the scratchpad engine. The config table becomes data, still written with the same CFAM_CONFIG_REG() expressions, which move to the header so a derived type can describe its own table the same way. No functional change: same memory map, same config words, same type and child names. aspeed_fsi-test verified. Signed-off-by: Mikail Sadic --- include/hw/fsi/cfam.h | 58 ++++++++++++++++++-- hw/fsi/cfam.c | 123 ++++++++++++++++++++++++------------------ hw/fsi/fsi-master.c | 2 +- 3 files changed, 127 insertions(+), 56 deletions(-) diff --git a/include/hw/fsi/cfam.h b/include/hw/fsi/cfam.h index cceb4bd6f1..0f5464b4a0 100644 --- a/include/hw/fsi/cfam.h +++ b/include/hw/fsi/cfam.h @@ -7,18 +7,44 @@ #ifndef FSI_CFAM_H #define FSI_CFAM_H =20 +#include "qemu/units.h" #include "system/memory.h" =20 #include "hw/fsi/fsi.h" #include "hw/fsi/lbus.h" =20 +/* + * All CFAM flavors present a register slot holding a config table, an FSI + * responder and a local bus carrying the engines the config table describ= es. + * That is the common model; each flavor supplies its own table, slot layo= ut + * and engines. + */ +#define TYPE_FSI_CFAM_COMMON "cfam-common" +OBJECT_DECLARE_TYPE(FSICFAMCommonState, FSICFAMCommonClass, FSI_CFAM_COMMO= N) + #define TYPE_FSI_CFAM "cfam" -#define FSI_CFAM(obj) OBJECT_CHECK(FSICFAMState, (obj), TYPE_FSI_CFAM) +OBJECT_DECLARE_SIMPLE_TYPE(FSICFAMState, FSI_CFAM) =20 /* P9-ism */ #define CFAM_CONFIG_NR_REGS 0x28 =20 -typedef struct FSICFAMState { +#define FSI_CFAM_SLOT_SIZE (2 * MiB) +#define FSI_CFAM_CONFIG_SIZE 0x400 + +#define ENGINE_CONFIG_NEXT BIT(31) +#define ENGINE_CONFIG_TYPE_PEEK (0x02 << 4) +#define ENGINE_CONFIG_TYPE_FSI (0x03 << 4) +#define ENGINE_CONFIG_TYPE_SCRATCHPAD (0x06 << 4) + +/* Valid, slots, version, type, crc */ +#define CFAM_CONFIG_REG(__VER, __TYPE, __CRC) \ + (ENGINE_CONFIG_NEXT | \ + 0x00010000 | \ + (__VER) | \ + (__TYPE) | \ + (__CRC)) + +struct FSICFAMCommonState { /* < private > */ FSISlaveState parent; =20 @@ -28,7 +54,33 @@ typedef struct FSICFAMState { MemoryRegion mr; =20 FSILBus lbus; +}; + +struct FSICFAMCommonClass { + /* < private > */ + DeviceClass parent_class; + + /* < public > */ + /* Config table served by the common ops, one word per 4-byte offset */ + const uint32_t *config; + unsigned config_nr; + + /* Layout of the register slot */ + hwaddr responder_offset; + hwaddr lbus_offset; + + /* Realize and map this flavor's local bus engines */ + bool (*realize_engines)(FSICFAMCommonState *cfam, Error **errp); +}; + +struct FSICFAMState { + /* < private > */ + FSICFAMCommonState parent; + FSIScratchPad scratchpad; -} FSICFAMState; +}; + +bool fsi_cfam_add_engine(FSICFAMCommonState *cfam, DeviceState *engine, + hwaddr offset, Error **errp); =20 #endif /* FSI_CFAM_H */ diff --git a/hw/fsi/cfam.c b/hw/fsi/cfam.c index 54c0b05769..361cb34808 100644 --- a/hw/fsi/cfam.c +++ b/hw/fsi/cfam.c @@ -16,19 +16,6 @@ =20 #include "hw/core/qdev-properties.h" =20 -#define ENGINE_CONFIG_NEXT BIT(31) -#define ENGINE_CONFIG_TYPE_PEEK (0x02 << 4) -#define ENGINE_CONFIG_TYPE_FSI (0x03 << 4) -#define ENGINE_CONFIG_TYPE_SCRATCHPAD (0x06 << 4) - -/* Valid, slots, version, type, crc */ -#define CFAM_CONFIG_REG(__VER, __TYPE, __CRC) \ - (ENGINE_CONFIG_NEXT | \ - 0x00010000 | \ - (__VER) | \ - (__TYPE) | \ - (__CRC)) - #define TO_REG(x) ((x) >> 2) =20 #define CFAM_CONFIG_CHIP_ID TO_REG(0x00) @@ -36,34 +23,33 @@ #define CFAM_CONFIG_CHIP_ID_P9 0xc0022d15 #define CFAM_CONFIG_CHIP_ID_BREAK 0xc0de0000 =20 +/* + * Config table of the P9 CFAM: the chip ID followed by one entry per engi= ne, + * entry n describing the engine at address n * 4. We need to add future + * engines from address 0x10 onwards. + */ +static const uint32_t cfam_p9_config[] =3D { + CFAM_CONFIG_CHIP_ID_P9, + CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_PEEK, 0xc), + CFAM_CONFIG_REG(0x5000, ENGINE_CONFIG_TYPE_FSI, 0xa), + CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_SCRATCHPAD, 0x7), +}; + static uint64_t fsi_cfam_config_read(void *opaque, hwaddr addr, unsigned s= ize) { + FSICFAMCommonClass *cc =3D FSI_CFAM_COMMON_GET_CLASS(opaque); + unsigned int reg =3D TO_REG(addr); + trace_fsi_cfam_config_read(addr, size); =20 - switch (addr) { - case 0x00: - return CFAM_CONFIG_CHIP_ID_P9; - case 0x04: - return CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_PEEK, 0xc); - case 0x08: - return CFAM_CONFIG_REG(0x5000, ENGINE_CONFIG_TYPE_FSI, 0xa); - case 0xc: - return CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_SCRATCHPAD, 0x7); - default: - /* - * The config table contains different engines from 0xc onwards. - * The scratch pad is already added at address 0xc. We need to add - * future engines from address 0x10 onwards. Returning 0 as engine - * is not implemented. - */ - return 0; - } + /* Engines past the end of the table are not implemented */ + return reg < cc->config_nr ? cc->config[reg] : 0; } =20 static void fsi_cfam_config_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { - FSICFAMState *cfam =3D FSI_CFAM(opaque); + FSICFAMCommonState *cfam =3D FSI_CFAM_COMMON(opaque); =20 trace_fsi_cfam_config_write(addr, size, data); =20 @@ -109,59 +95,92 @@ static const struct MemoryRegionOps fsi_cfam_unimpleme= nted_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void fsi_cfam_instance_init(Object *obj) +bool fsi_cfam_add_engine(FSICFAMCommonState *cfam, DeviceState *engine, + hwaddr offset, Error **errp) { - FSICFAMState *s =3D FSI_CFAM(obj); + if (!qdev_realize(engine, BUS(&cfam->lbus), errp)) { + return false; + } =20 - object_initialize_child(obj, "scratchpad", &s->scratchpad, - TYPE_FSI_SCRATCHPAD); + memory_region_add_subregion(&cfam->lbus.mr, offset, + &FSI_LBUS_DEVICE(engine)->iomem); + return true; } =20 -static void fsi_cfam_realize(DeviceState *dev, Error **errp) +static void fsi_cfam_common_realize(DeviceState *dev, Error **errp) { - FSICFAMState *cfam =3D FSI_CFAM(dev); + FSICFAMCommonState *cfam =3D FSI_CFAM_COMMON(dev); + FSICFAMCommonClass *cc =3D FSI_CFAM_COMMON_GET_CLASS(dev); FSISlaveState *slave =3D FSI_SLAVE(dev); + const char *type =3D object_get_typename(OBJECT(dev)); + g_autofree char *config_name =3D g_strdup_printf("%s.config", type); =20 /* Each slave has a 2MiB address space */ memory_region_init_io(&cfam->mr, OBJECT(cfam), &fsi_cfam_unimplemented= _ops, - cfam, TYPE_FSI_CFAM, 2 * MiB); + cfam, type, FSI_CFAM_SLOT_SIZE); =20 qbus_init(&cfam->lbus, sizeof(cfam->lbus), TYPE_FSI_LBUS, DEVICE(cfam), NULL); =20 memory_region_init_io(&cfam->config_iomem, OBJECT(cfam), &cfam_config_= ops, - cfam, TYPE_FSI_CFAM ".config", 0x400); + cfam, config_name, FSI_CFAM_CONFIG_SIZE); =20 memory_region_add_subregion(&cfam->mr, 0, &cfam->config_iomem); - memory_region_add_subregion(&cfam->mr, 0x800, &slave->iomem); - memory_region_add_subregion(&cfam->mr, 0xc00, &cfam->lbus.mr); + memory_region_add_subregion(&cfam->mr, cc->responder_offset, &slave->i= omem); + memory_region_add_subregion(&cfam->mr, cc->lbus_offset, &cfam->lbus.mr= ); + + cc->realize_engines(cfam, errp); +} + +static void fsi_cfam_common_class_init(ObjectClass *klass, const void *dat= a) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->bus_type =3D TYPE_FSI_BUS; + dc->realize =3D fsi_cfam_common_realize; +} + +static bool fsi_cfam_realize_engines(FSICFAMCommonState *cfam, Error **err= p) +{ + FSICFAMState *s =3D FSI_CFAM(cfam); =20 /* Add scratchpad engine */ - if (!qdev_realize(DEVICE(&cfam->scratchpad), BUS(&cfam->lbus), errp)) { - return; - } + object_initialize_child(OBJECT(s), "scratchpad", &s->scratchpad, + TYPE_FSI_SCRATCHPAD); =20 - FSILBusDevice *fsi_dev =3D FSI_LBUS_DEVICE(&cfam->scratchpad); - memory_region_add_subregion(&cfam->lbus.mr, 0, &fsi_dev->iomem); + return fsi_cfam_add_engine(cfam, DEVICE(&s->scratchpad), 0, errp); } =20 static void fsi_cfam_class_init(ObjectClass *klass, const void *data) { - DeviceClass *dc =3D DEVICE_CLASS(klass); - dc->bus_type =3D TYPE_FSI_BUS; - dc->realize =3D fsi_cfam_realize; + FSICFAMCommonClass *cc =3D FSI_CFAM_COMMON_CLASS(klass); + + cc->config =3D cfam_p9_config; + cc->config_nr =3D ARRAY_SIZE(cfam_p9_config); + cc->responder_offset =3D 0x800; + cc->lbus_offset =3D 0xc00; + cc->realize_engines =3D fsi_cfam_realize_engines; } =20 +static const TypeInfo fsi_cfam_common_info =3D { + .name =3D TYPE_FSI_CFAM_COMMON, + .parent =3D TYPE_FSI_SLAVE, + .instance_size =3D sizeof(FSICFAMCommonState), + .class_size =3D sizeof(FSICFAMCommonClass), + .class_init =3D fsi_cfam_common_class_init, + .abstract =3D true, +}; + static const TypeInfo fsi_cfam_info =3D { .name =3D TYPE_FSI_CFAM, - .parent =3D TYPE_FSI_SLAVE, - .instance_init =3D fsi_cfam_instance_init, + .parent =3D TYPE_FSI_CFAM_COMMON, .instance_size =3D sizeof(FSICFAMState), .class_init =3D fsi_cfam_class_init, }; =20 static void fsi_cfam_register_types(void) { + type_register_static(&fsi_cfam_common_info); type_register_static(&fsi_cfam_info); } =20 diff --git a/hw/fsi/fsi-master.c b/hw/fsi/fsi-master.c index 083a5507ab..d82df1c094 100644 --- a/hw/fsi/fsi-master.c +++ b/hw/fsi/fsi-master.c @@ -130,7 +130,7 @@ static void fsi_master_realize(DeviceState *dev, Error = **errp) } =20 /* address ? */ - memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.mr); + memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.parent.mr); } =20 static void fsi_master_reset(DeviceState *dev) --=20 2.53.0 From nobody Mon Sep 28 02:13:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1785442328; cv=none; d=zohomail.com; s=zohoarc; b=Ta4yuY1DaxXkdss/fICFTLpXCS0F2/eJrc7VkYOKr31IKH7XavsAbj53X3K9ZlzlzFKkE3eezROinglTXSzjz11ERsY93GvvUBTy1c8DovQUHUBITtxtqNyKnYL1xkJQJniCFWmJscxsUnYzn8Ct1l9nB7Q1fpmpnejh3btHeaY= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=Y0IOPq+csbNiZCdzz uIQcAE4iD6CSkfd7N8cKEWNwgg=; b=smpsq8CwOPya2QwRcrB09O3IcGPXt4tEz r18MC4uphZSEKieRaRngr4ToR8m640nGtA3vKSOIpF4DEtiTw87kdbgHdQp53RvT yJhC6sMa41tDpbSy4aG6V+lGSw3ZQdUMtKkrDpSsIwnUuBwQ2w94666XMeAD9ZXS NGvtEN8Zo5ov+wi6pZfM91UQ3/o4Xxir67ePcRARMt3FaOGEiAq/zGFIXy3bPyt8 E8UtwrJ8imv82+9/LoNzKbht0wn2JegUKUR/DUXuZaNg64EpFO6d7D90IN2s/lsh IYBrVkL/JWGKRkgnHnJhFfBjE6VtWtc3tVMHuvleeIaqYBrSAIlaQ== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 2/8] fsi/cfam: Add CFAM-S model Date: Thu, 30 Jul 2026 15:09:37 -0500 Message-ID: <20260730200945.1113936-3-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260730200945.1113936-1-mikail.sadic@ibm.com> References: <20260730200945.1113936-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-ORIG-GUID: mWwk015d5UXQgOd9TcvvPKspRn4i8_lq X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDE0NSBTYWx0ZWRfXzI6+vvnawTnC 1PjxaUZQPVlv9uyTiqpWzeoO+VvsvI0cePrk3LlwyEgcdqnrcsxfyFQJ1GmKmqd75Efamvzzmcp iTfqs6fbVcrTK8MID95OMT3tE8JElM8= X-Authority-Analysis: v=2.4 cv=E/z9Y6dl c=1 sm=1 tr=0 ts=6a6baf8e cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=NEAV23lmAAAA:8 a=VnNF1IyMAAAA:8 a=GLtLAL1jAtWljCBMQDYA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDE0NSBTYWx0ZWRfXyLWgJYRq7K1v xIULbAAwDWlqFkyLqTroq0+aVMQZCmmc5GuynMLhplCTfmhofhL+CFSuEItYXvDmj7e5I1MGE/7 3782oNsfU1bNDNBEF77DaLcvb/3ltCkqqaOXZNBO4yc3B6oakZQY9KRLw5/BIm3QNdq+LDlFeXf pgOZbXzZTebwoAETDkwiGfzUkU4XhppTSbBrlf1WaS/mhI5ZKaV6aBiJnGLauCPemlesKlRQ8cB BpRWbI1RHYBT2eBmhTATrIYE9Ls0i1sSB8bAov+YkLsFRC2gu8MG/EblaLB5GNFPp2OVF60jHv5 W5OU2Uwg88+Icuk1fD4kDV68Ib5BBMhuB7CzR4y8oldkw/mobK/1doCRWTHARVp0C7MS2HZj03/ uXWLjfd4o9MlxUTP6SD7yKoEpTJ+cgsZFa6N0Gl94vywVrHyzGGe+iXlmGvCgxbj7P1ebXdg+m8 eeXgFZk1eF3IowsvNIA== X-Proofpoint-GUID: k_-QzT2kljF6fNUxY6lmxOaHPF5oXazT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 spamscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300145 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=mikail.sadic@ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1785442330240158500 Content-Type: text/plain; charset="utf-8" Add TYPE_FSI_CFAM_S, derivative of CFAM, as a second type on the common CFAM base class. The base class builds the register slot, the config table region, the FSI responder and the local bus, so the CFAM-S supplies only its config table (chip ID with major 9, an FSI responder and a v1 mailbox), its slot offsets and the mailbox engine. Its realize chains the base one and adds the one thing that is new: the slot is aliased across the four slave-ID views, so enumeration and normal access reach the same registers. The v1 mailbox is a local bus engine added in lbus.c next to the scratchpad which the CFAM-S just instantiates. Sharing the base config table implementation means the CFAM-S also honors the SID_BREAK sequence and word-only config access. FSIMasterState gains a cfam_s field. fsi_master_init() creates both the cfam and cfam-s children, realize hooks them into the OPB-to-FSI aperture. Signed-off-by: Mikail Sadic --- docs/specs/fsi.rst | 15 ++++++ include/hw/fsi/cfam-s.h | 40 ++++++++++++++++ include/hw/fsi/cfam.h | 10 ++++ include/hw/fsi/fsi-master.h | 2 + include/hw/fsi/lbus.h | 11 +++++ hw/fsi/cfam-s.c | 91 +++++++++++++++++++++++++++++++++++++ hw/fsi/fsi-master.c | 7 +++ hw/fsi/lbus.c | 69 ++++++++++++++++++++++++++++ hw/fsi/meson.build | 2 +- hw/fsi/trace-events | 2 + 10 files changed, 248 insertions(+), 1 deletion(-) create mode 100644 include/hw/fsi/cfam-s.h create mode 100644 hw/fsi/cfam-s.c diff --git a/docs/specs/fsi.rst b/docs/specs/fsi.rst index f7d86d3e37..fb7a3669ef 100644 --- a/docs/specs/fsi.rst +++ b/docs/specs/fsi.rst @@ -120,3 +120,18 @@ from the BMC. (see the `pdbg source repository`_ for m= ore details) =20 .. _pdbg source repository: https://github.com/open-power/pdbg + +CFAM-S model +------------ + +The CFAM-S is a derivative of the CFAM. Both are modelled on a common CFAM +model that builds the register slot, the configuration table, the FSI +responder and the local bus; each supplies its own configuration table, sl= ot +layout and engines. The CFAM-S supports a limited set of engines: an FSI +responder and a version 1 mailbox. + +The configuration table advertises the responder and the mailbox engines. +The responder is backed by the FSI slave control registers; the mailbox +provides a small block of scratch registers. The register block is exposed +through each slave-ID view so that enumeration and normal access reach the +same registers. diff --git a/include/hw/fsi/cfam-s.h b/include/hw/fsi/cfam-s.h new file mode 100644 index 0000000000..daf72124c4 --- /dev/null +++ b/include/hw/fsi/cfam-s.h @@ -0,0 +1,40 @@ +/* + * IBM Common FRU Access Macro - S variant (CFAM-S) + * + * Copyright (C) 2026 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef FSI_CFAM_S_H +#define FSI_CFAM_S_H + +#include "system/memory.h" +#include "hw/fsi/cfam.h" +#include "hw/fsi/fsi.h" +#include "hw/fsi/lbus.h" + +#define TYPE_FSI_CFAM_S "cfam-s" +OBJECT_DECLARE_TYPE(FSICFAMSState, FSICFAMSClass, FSI_CFAM_S) + +/* The register slot is visible in each of the four slave-ID views */ +#define CFAM_S_WINDOW_SIZE (4 * FSI_CFAM_SLOT_SIZE) + +struct FSICFAMSState { + /* < private > */ + FSICFAMCommonState parent; + + /* parent.mr aliased across the slave-ID views */ + MemoryRegion window; + MemoryRegion slot_alias[3]; + + FSIMbox mbox; +}; + +struct FSICFAMSClass { + /* < private > */ + FSICFAMCommonClass parent_class; + + DeviceRealize parent_realize; +}; + +#endif /* FSI_CFAM_S_H */ diff --git a/include/hw/fsi/cfam.h b/include/hw/fsi/cfam.h index 0f5464b4a0..43f6be9d18 100644 --- a/include/hw/fsi/cfam.h +++ b/include/hw/fsi/cfam.h @@ -35,6 +35,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FSICFAMState, FSI_CFAM) #define ENGINE_CONFIG_TYPE_PEEK (0x02 << 4) #define ENGINE_CONFIG_TYPE_FSI (0x03 << 4) #define ENGINE_CONFIG_TYPE_SCRATCHPAD (0x06 << 4) +#define ENGINE_CONFIG_TYPE_MBOX_V1 (0x14 << 4) =20 /* Valid, slots, version, type, crc */ #define CFAM_CONFIG_REG(__VER, __TYPE, __CRC) \ @@ -44,6 +45,15 @@ OBJECT_DECLARE_SIMPLE_TYPE(FSICFAMState, FSI_CFAM) (__TYPE) | \ (__CRC)) =20 +/* As above, for the last entry in a table: NEXT is clear */ +#define CFAM_CONFIG_LAST(__VER, __TYPE, __CRC) \ + (0x00010000 | \ + (__VER) | \ + (__TYPE) | \ + (__CRC)) + +#define CFAM_CONFIG_CHIP_ID_MAJOR(__MAJOR) (((__MAJOR) & 0xf) << 8) + struct FSICFAMCommonState { /* < private > */ FSISlaveState parent; diff --git a/include/hw/fsi/fsi-master.h b/include/hw/fsi/fsi-master.h index 60ddaa994f..6a2782fdf2 100644 --- a/include/hw/fsi/fsi-master.h +++ b/include/hw/fsi/fsi-master.h @@ -11,6 +11,7 @@ #include "hw/core/qdev.h" #include "hw/fsi/fsi.h" #include "hw/fsi/cfam.h" +#include "hw/fsi/cfam-s.h" =20 #define TYPE_FSI_MASTER "fsi.master" OBJECT_DECLARE_SIMPLE_TYPE(FSIMasterState, FSI_MASTER) @@ -26,6 +27,7 @@ typedef struct FSIMasterState { =20 uint32_t regs[FSI_MASTER_NR_REGS]; FSICFAMState cfam; + FSICFAMSState cfam_s; } FSIMasterState; =20 =20 diff --git a/include/hw/fsi/lbus.h b/include/hw/fsi/lbus.h index 1b894509fe..582d7169d6 100644 --- a/include/hw/fsi/lbus.h +++ b/include/hw/fsi/lbus.h @@ -40,4 +40,15 @@ typedef struct FSIScratchPad { uint32_t regs[FSI_SCRATCHPAD_NR_REGS]; } FSIScratchPad; =20 +#define TYPE_FSI_MBOX "fsi.mbox" +OBJECT_DECLARE_SIMPLE_TYPE(FSIMbox, FSI_MBOX) + +#define FSI_MBOX_SCRATCH_NUM 5 + +struct FSIMbox { + FSILBusDevice parent; + + uint32_t scratch[FSI_MBOX_SCRATCH_NUM]; +}; + #endif /* FSI_LBUS_H */ diff --git a/hw/fsi/cfam-s.c b/hw/fsi/cfam-s.c new file mode 100644 index 0000000000..3df6da3788 --- /dev/null +++ b/hw/fsi/cfam-s.c @@ -0,0 +1,91 @@ +/* + * IBM Common FRU Access Macro - S variant (CFAM-S) + * + * A CFAM flavor built on the common CFAM model (see cfam.c). It supports = an + * FSI responder and a v1 mailbox, and exposes its register slot in each + * slave-ID view of the link. + * + * Copyright (C) 2026 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/units.h" +#include "hw/fsi/cfam-s.h" +#include "hw/fsi/fsi.h" + +/* Slot layout: 0x000 config table, 0x400 responder, 0x800 mailbox */ +#define CFAM_S_RESPONDER_BASE 0x400 +#define CFAM_S_MBOX_BASE 0x800 + +/* Config table: chip ID with major 9 (the CFAM-S), then the engines */ +static const uint32_t cfam_s_config[] =3D { + ENGINE_CONFIG_NEXT | CFAM_CONFIG_CHIP_ID_MAJOR(9) | 0xd, + CFAM_CONFIG_REG(0x1000, ENGINE_CONFIG_TYPE_FSI, 0xb), + CFAM_CONFIG_LAST(0x1000, ENGINE_CONFIG_TYPE_MBOX_V1, 0x3), +}; + +static bool fsi_cfam_s_realize_engines(FSICFAMCommonState *cfam, Error **e= rrp) +{ + FSICFAMSState *cfam_s =3D FSI_CFAM_S(cfam); + + object_initialize_child(OBJECT(cfam_s), "mbox", &cfam_s->mbox, + TYPE_FSI_MBOX); + return fsi_cfam_add_engine(cfam, DEVICE(&cfam_s->mbox), 0, errp); +} + +static void fsi_cfam_s_realize(DeviceState *dev, Error **errp) +{ + ERRP_GUARD(); + FSICFAMSState *cfam_s =3D FSI_CFAM_S(dev); + FSICFAMCommonState *cfam =3D FSI_CFAM_COMMON(dev); + FSICFAMSClass *sc =3D FSI_CFAM_S_GET_CLASS(dev); + + sc->parent_realize(dev, errp); + if (*errp) { + return; + } + + memory_region_init(&cfam_s->window, OBJECT(cfam_s), + TYPE_FSI_CFAM_S ".window", CFAM_S_WINDOW_SIZE); + memory_region_add_subregion(&cfam_s->window, 0, &cfam->mr); + + /* Alias the slot into the other three slave-ID views */ + for (int i =3D 0; i < ARRAY_SIZE(cfam_s->slot_alias); i++) { + memory_region_init_alias(&cfam_s->slot_alias[i], OBJECT(cfam_s), + TYPE_FSI_CFAM_S ".slot-alias", &cfam->mr,= 0, + FSI_CFAM_SLOT_SIZE); + memory_region_add_subregion(&cfam_s->window, + (i + 1) * FSI_CFAM_SLOT_SIZE, + &cfam_s->slot_alias[i]); + } +} + +static void fsi_cfam_s_class_init(ObjectClass *klass, const void *data) +{ + FSICFAMSClass *sc =3D FSI_CFAM_S_CLASS(klass); + FSICFAMCommonClass *cc =3D FSI_CFAM_COMMON_CLASS(klass); + + device_class_set_parent_realize(DEVICE_CLASS(klass), fsi_cfam_s_realiz= e, + &sc->parent_realize); + + cc->config =3D cfam_s_config; + cc->config_nr =3D ARRAY_SIZE(cfam_s_config); + cc->responder_offset =3D CFAM_S_RESPONDER_BASE; + cc->lbus_offset =3D CFAM_S_MBOX_BASE; + cc->realize_engines =3D fsi_cfam_s_realize_engines; +} + +static const TypeInfo cfam_s_types[] =3D { + { + .name =3D TYPE_FSI_CFAM_S, + .parent =3D TYPE_FSI_CFAM_COMMON, + .instance_size =3D sizeof(FSICFAMSState), + .class_size =3D sizeof(FSICFAMSClass), + .class_init =3D fsi_cfam_s_class_init, + }, +}; + +DEFINE_TYPES(cfam_s_types) diff --git a/hw/fsi/fsi-master.c b/hw/fsi/fsi-master.c index d82df1c094..82991b1005 100644 --- a/hw/fsi/fsi-master.c +++ b/hw/fsi/fsi-master.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/log.h" +#include "qemu/units.h" #include "trace.h" =20 #include "hw/fsi/fsi-master.h" @@ -113,6 +114,7 @@ static void fsi_master_init(Object *o) FSIMasterState *s =3D FSI_MASTER(o); =20 object_initialize_child(o, "cfam", &s->cfam, TYPE_FSI_CFAM); + object_initialize_child(o, "cfam-s", &s->cfam_s, TYPE_FSI_CFAM_S); =20 qbus_init(&s->bus, sizeof(s->bus), TYPE_FSI_BUS, DEVICE(s), NULL); =20 @@ -131,6 +133,11 @@ static void fsi_master_realize(DeviceState *dev, Error= **errp) =20 /* address ? */ memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.parent.mr); + + if (!qdev_realize(DEVICE(&s->cfam_s), BUS(&s->bus), errp)) { + return; + } + memory_region_add_subregion(&s->opb2fsi, 2 * MiB, &s->cfam_s.window); } =20 static void fsi_master_reset(DeviceState *dev) diff --git a/hw/fsi/lbus.c b/hw/fsi/lbus.c index cae29e0658..902f8d8a5e 100644 --- a/hw/fsi/lbus.c +++ b/hw/fsi/lbus.c @@ -107,11 +107,80 @@ static const TypeInfo fsi_scratchpad_info =3D { .class_init =3D fsi_scratchpad_class_init, }; =20 +/* The mailbox exposes its scratch registers at this offset */ +#define FSI_MBOX_SCRATCH_OFF 0xe0 +#define FSI_MBOX_SCRATCH_END (FSI_MBOX_SCRATCH_OFF + FSI_MBOX_SCRATCH_NUM = * 4) + +static uint64_t fsi_mbox_read(void *opaque, hwaddr addr, unsigned size) +{ + FSIMbox *mbox =3D FSI_MBOX(opaque); + + trace_fsi_mbox_read(addr, size); + + if (addr < FSI_MBOX_SCRATCH_OFF || addr >=3D FSI_MBOX_SCRATCH_END) { + return 0; + } + + return mbox->scratch[TO_REG(addr - FSI_MBOX_SCRATCH_OFF)]; +} + +static void fsi_mbox_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) +{ + FSIMbox *mbox =3D FSI_MBOX(opaque); + + trace_fsi_mbox_write(addr, size, data); + + if (addr < FSI_MBOX_SCRATCH_OFF || addr >=3D FSI_MBOX_SCRATCH_END) { + return; + } + + mbox->scratch[TO_REG(addr - FSI_MBOX_SCRATCH_OFF)] =3D data; +} + +static const struct MemoryRegionOps fsi_mbox_ops =3D { + .read =3D fsi_mbox_read, + .write =3D fsi_mbox_write, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void fsi_mbox_realize(DeviceState *dev, Error **errp) +{ + FSILBusDevice *ldev =3D FSI_LBUS_DEVICE(dev); + + memory_region_init_io(&ldev->iomem, OBJECT(ldev), &fsi_mbox_ops, + ldev, TYPE_FSI_MBOX, 0x400); +} + +static void fsi_mbox_reset(DeviceState *dev) +{ + FSIMbox *mbox =3D FSI_MBOX(dev); + + memset(mbox->scratch, 0, sizeof(mbox->scratch)); +} + +static void fsi_mbox_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->bus_type =3D TYPE_FSI_LBUS; + dc->realize =3D fsi_mbox_realize; + device_class_set_legacy_reset(dc, fsi_mbox_reset); +} + +static const TypeInfo fsi_mbox_info =3D { + .name =3D TYPE_FSI_MBOX, + .parent =3D TYPE_FSI_LBUS_DEVICE, + .instance_size =3D sizeof(FSIMbox), + .class_init =3D fsi_mbox_class_init, +}; + static void fsi_lbus_register_types(void) { type_register_static(&fsi_lbus_info); type_register_static(&fsi_lbus_device_type_info); type_register_static(&fsi_scratchpad_info); + type_register_static(&fsi_mbox_info); } =20 type_init(fsi_lbus_register_types); diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build index a18a076552..585d549405 100644 --- a/hw/fsi/meson.build +++ b/hw/fsi/meson.build @@ -1,2 +1,2 @@ -system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c'= ,'fsi-master.c')) +system_ss.add(when: 'CONFIG_FSI', if_true: files('lbus.c','fsi.c','cfam.c'= ,'cfam-s.c','fsi-master.c')) system_ss.add(when: 'CONFIG_FSI_APB2OPB_ASPEED', if_true: files('aspeed_ap= b2opb.c')) diff --git a/hw/fsi/trace-events b/hw/fsi/trace-events index 9e286d08d3..42edce6437 100644 --- a/hw/fsi/trace-events +++ b/hw/fsi/trace-events @@ -1,5 +1,7 @@ fsi_scratchpad_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=3D%= d" fsi_scratchpad_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" P= RIx64 " size=3D%d value=3D0x%"PRIx64 +fsi_mbox_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=3D%d" +fsi_mbox_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 = " size=3D%d value=3D0x%"PRIx64 fsi_slave_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=3D%d" fsi_slave_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64= " size=3D%d value=3D0x%"PRIx64 fsi_cfam_config_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size=3D= %d" --=20 2.53.0 From nobody Mon Sep 28 02:13:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 30 Jul 2026 20:09:48 +0000 (GMT) Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 24D1758055; Thu, 30 Jul 2026 20:09:48 +0000 (GMT) Received: from IBM-MFS.atx-us.ibm.com (unknown [9.16.49.87]) by smtpav06.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 30 Jul 2026 20:09:48 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=TR/zMuZQNfrB4LNiZ cJDwIVjsxAmSUCCo0C3kWPvJlw=; b=SfHpFSIbGj1NtcHLK1JFb1q9sK8rJOn9e y8PQOt9Y2WQzBxqk4VkoL1R43Fno29VrfjSzQLd8tBuXJet875bSWTMBIKtQ8r7j qIHnC8oMwW6s0vthbWBf8y70DPEdhXlILr6r5FYKIAqPCe/bkfpMJ6A5zqapYDlg 4MBuX8ZON+rqCzKuFbYtUJChbc75irkv4E64sRuWFeRNwPhuK27Qe8cIZf9Fd5a/ vUJwNu6ckN+Jt9CSCErmq5JO4POatjjg8mDaaey6a0heR1s4hVVl9uTHt+FCVOhZ 4k+clq/naTFlmqILWgFiL3L6jLntnWnWuEOvYAs9K2B1Z5KsTyELg== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 3/8] arm/aspeed: Wire AST2700 FSI controllers to APB-to-OPB bridges Date: Thu, 30 Jul 2026 15:09:38 -0500 Message-ID: <20260730200945.1113936-4-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260730200945.1113936-1-mikail.sadic@ibm.com> References: <20260730200945.1113936-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-ORIG-GUID: aXlHLMtTivrWextQ2yR7MwyTfWqUls1N X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDE0NSBTYWx0ZWRfX7nmPQ3u/Z7UM clZw9o6bu+P8Dh/04mMD9AMKIPfWA+MCHN6xncXFhq4Xqy6N6h1ZgHnL386599KLOx8fw6gseUK rlf5D2CZI84wicWzQ+/IhABIDexw7JZRJuLbxxBtJKahA6OGUq2J3pwnnR3088/htT8I+7w7th+ NbdVTiKZ/NPrfmr2oeo/ZnqdR8PX8jfL/NmJnBa2QtaK/E4GCuVD+ix4pPgVll3q8nPDG2QY2GT KFH9PJjz4zcpL9tlXNqEEinfP1pu6euD6frD39TMOTEc3s1+8ELP0gQgkbsNIviSrV9wbAKUuiR AV12go/N4EosKsC4Iw85TMtl/Uv/KiuTxxrlxSLTLWVoxiEK9LxACMAgn2yGUjbxpXz2pQKdrhS nWHAGbLryvJuVZT5mULvR6U37pA7qjQ12gF4mAwuGojWKwrC03PXboc7qQCYNKhk5PBf/Uert2j 3myOxnMp2ir+bJqv4yQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDE0NSBTYWx0ZWRfXzzJZXVcFJI40 QnztJ1jP0Iim84rGVna13mwAwZQ10wlt4C0TZ3L0+flfDXivWV8Y5Wpy9eJbaJXJ0uLvSc2MHXv ERi4XSl+guCLyfl5FZrdVTH4yQAsHbQ= X-Authority-Analysis: v=2.4 cv=AZeB2XXG c=1 sm=1 tr=0 ts=6a6baf8f cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=phIN1QjiwUTDb9KW1ZcA:9 X-Proofpoint-GUID: e06NPOStSOryLsiTMy1eqHDweHXpPIFC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 clxscore=1015 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300145 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1785442280631158500 Content-Type: text/plain; charset="utf-8" The AST2700 SoC exposes two FSI controllers behind APB-to-OPB bridges. Add the ASPEED_DEV_FSI1/FSI2 memory-map entries, instantiate both fsi[] APB-to-OPB bridges and map them during SoC realize, so the CFAM/CFAM-S devices on the FSI local buses become reachable from the SoC. Signed-off-by: Mikail Sadic --- hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index dddd7d2106..b908d7d4ff 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -17,6 +17,7 @@ #include "qemu/module.h" #include "qemu/error-report.h" #include "hw/i2c/aspeed_i2c.h" +#include "hw/fsi/aspeed_apb2opb.h" #include "net/net.h" #include "system/qtest.h" #include "system/system.h" @@ -98,6 +99,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, [ASPEED_DEV_PCIE_MMIO2] =3D 0xA0000000, + [ASPEED_DEV_FSI1] =3D 0x21800000, + [ASPEED_DEV_FSI2] =3D 0x23800000, [ASPEED_DEV_SPI_BOOT] =3D 0x100000000, [ASPEED_DEV_SDRAM] =3D 0x400000000, }; @@ -559,6 +562,11 @@ static void aspeed_soc_ast2700_init(Object *obj) sc->silicon_rev); } =20 + for (i =3D 0; i < ARRAY_SIZE(s->fsi); i++) { + object_initialize_child(obj, "fsi[*]", &s->fsi[i], + TYPE_ASPEED_APB2OPB); + } + object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem", &s->iomem, @@ -1132,6 +1140,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) } } =20 + /* FSI / OPB */ + for (i =3D 0; i < ARRAY_SIZE(s->fsi); i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fsi[i]), 0, + sc->memmap[ASPEED_DEV_FSI1 + i]); + } + + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], --=20 2.53.0 From nobody Mon Sep 28 02:13:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1785442277; cv=none; d=zohomail.com; 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Thu, 30 Jul 2026 20:09:48 +0000 (GMT) Received: from IBM-MFS.atx-us.ibm.com (unknown [9.16.49.87]) by smtpav06.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 30 Jul 2026 20:09:48 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=Q7oIuPCYo4p+RjfJB 3jCPNS97if4AWQut/dKB+3wAW8=; b=kdxnhdB4+rY//wFWSmzCSEUIkGnmrOiZO uHnucRR4HJenMVTsEYQ990U/pM8fFVzvlokQl3JZQS2pJZEIZqxnoKX/dKtYEraJ XHZzdojBmiXNj/g/tDg5Fm9yJ73ptDnb7u/3GPNWda/wgPrvzjfPVnQ7Exf0Z2fj pIRMn0L31NY+2SXIMOxPM515wn3I0pJYfHtKV/hvwjaP0QUvPxRIytuYNrRdum9v 3Wi0vwmnSa4WGP1l8QPwEfN9sZjBglhWEVGXCNXAj9cQ1m/cNSfgzNYrgA5r1bLa CTPx8Ki2+e50PhFq6bhRfoJpD8nMibgkAVHF4Qx6z7oD1TaN7FU1A== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 4/8] i2c/aspeed: Fix DMA receive first-byte handling for block reads Date: Thu, 30 Jul 2026 15:09:39 -0500 Message-ID: <20260730200945.1113936-5-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260730200945.1113936-1-mikail.sadic@ibm.com> References: <20260730200945.1113936-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDE0NSBTYWx0ZWRfX9Ib5WQIGA3va wx2IrXhUTpER0EnXQQqSHiw0nKuDCws+PM3sl70qwzzV3YfGfePXMLpPFCEvaq4zb8QKQWNTqtQ Uzxp6a1MbDh2Y+9DS6qdAkrZ1EM9wIU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDE0NSBTYWx0ZWRfX/UpgnRoE6ioX aJT7RqLwLhAs4V3E8yVw70E1YhxCR6O+NA6kmES4RnSwLU2km40KXGTeomIxYTgkyaGs9aDed6v pJMtN90KzJnx9l0rlpoiGcuxGzWPfWx9OiKbE7yJJW90XWGzAK9XJHo/Ohke4NMyVrxLn3g9Bbb gi5BqPCc+Og2heYIXA9frcyWm46Dunr56ugAVHZRdL1AQaHkgMOCwrqJllsDURnX7Spz/qUqBu7 WMj4g4SGu7orNh+c6Cr5QcEXQaaFzwbbJJE1KP/No59Re+b6FILK6D5du60mpdEViFsQrggymiG xNMqTQVcz+ix4tExjKfJBhPBtI3uGuSN2cLHg5XmRsQejScR1Vy/rKtTIeatchJZmubTpPCE49T s5v9GyGbS6Oy6DkiU3Br6YwxF4/c1JcRnzec2odf5ppXovXPVyzBLeCHdaR0GhfPAMUtnmfq0bQ cabOHqD3Kzkjmi0GtIA== X-Authority-Analysis: v=2.4 cv=b5WCJNGx c=1 sm=1 tr=0 ts=6a6baf90 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8 a=82TwdL3_f4vI9uiogJoA:9 X-Proofpoint-GUID: 15bHUHUO4BdO7DqZXfKyAbJetaJ-IBfd X-Proofpoint-ORIG-GUID: t7HXCBzbbRNUkpfalDDdzmwR-X-ZZ8fI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300145 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=mikail.sadic@ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1785442280619158500 Content-Type: text/plain; charset="utf-8" An SMBus block read (I2C_M_RECV_LEN) reads the block length from the first received byte. The Linux/U-Boot aspeed I2C driver obtains that first byte from the I2CC_STS_AND_BUFF register (modelled here as reg_byte_buf), even when the transfer uses DMA. The DMA receive path, however, only wrote received data to DRAM and never updated reg_byte_buf, so block reads read a stale/zero length. Mirror the first DMA-received byte into reg_byte_buf so that I2C_M_RECV_LEN transfers using DMA report the correct block length. This is required for the ucd9000 driver, which uses i2c_smbus_read_block_data(). Signed-off-by: Mikail Sadic --- hw/i2c/aspeed_i2c.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 27afcaecee..facb54d27e 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -365,6 +365,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) uint32_t reg_pool_ctrl =3D aspeed_i2c_bus_pool_ctrl_offset(bus); uint32_t reg_byte_buf =3D aspeed_i2c_bus_byte_buf_offset(bus); uint32_t reg_dma_len =3D aspeed_i2c_bus_dma_len_offset(bus); + bool first_dma_byte; int pool_rx_count =3D SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, RX_SIZE) + 1; =20 @@ -391,6 +392,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) } =20 aspeed_i2c_set_rx_dma_dram_offset(bus); + first_dma_byte =3D true; while (bus->regs[reg_dma_len]) { MemTxResult result; =20 @@ -407,6 +409,11 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) return; } =20 + /* Mirror first byte to reg_byte_buf for I2C_M_RECV_LEN. */ + if (first_dma_byte) { + SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, d= ata); + first_dma_byte =3D false; + } bus->dma_dram_offset++; bus->regs[reg_dma_len]--; /* In new mode, keep track of how many bytes we RXed */ --=20 2.53.0 From nobody Mon Sep 28 02:13:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1785442299; cv=none; d=zohomail.com; s=zohoarc; b=amr+RYa9Q84OLdhwg4MT11H+o7Z5N834h/W66/C7S7gGeRaeLNI8YcJP47OUqN3PNzW9zA63qNSVR4+YZcgJRC+8wlzNRlcb/0xWiAlzD4MnMYErAjx2icpjQqNLvy+0yugSAxC5UShcRoCTwqwabTqpigS3kDotC/I5fKKqRVQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785442299; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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b=eKU1QP189Hve0OkjCKq0TTpV94km0XP5W ozMfz/Z4X81qbdTg6DKT0Ofvqj8+jubkG47i0kpX1QspphScmdenblX0dBBzxW9U RpAx34l1VL8l+r6gS7T86LMnhMifipxt7UsFyKlx5L7eu9injFpB8jIJYBZJNwcT CPKP5yq+a7jmpmUWKY/zVQlR+rTfvni1wqsAUsJFSruLD0Uykft19wYsfC1+y6th jfZZRiG+vsJcqlscxlsLPHhv1VdDK2W1/J/cvEybCd5MiXHriAW6ez5oOuItmjBx tdtkso4nr32BO8SR3oZTQ5Wi3VlR4ipN2pJgG3LpzPOiC/shb5cDQ== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 5/8] hw/sensor: Add UCD90320 model Date: Thu, 30 Jul 2026 15:09:40 -0500 Message-ID: <20260730200945.1113936-6-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260730200945.1113936-1-mikail.sadic@ibm.com> References: <20260730200945.1113936-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: Gdo-mcPwe46Wa9Bj2ydwhVwMQWf-aEgn X-Proofpoint-ORIG-GUID: f-FEj2txod8zBAmV_phaVn5IrIpRRcV7 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDE0NSBTYWx0ZWRfXw5b/kJqe1rJT 8RMv5edOauWikFumpzUo1be2QkleyflCL71fuyUp+BzIIBPd4Mt9TF4mk9fmi56C9ZHDr2dUeoL 9Q1NlB1w3n5/BB1kY/QAd9ymCO/Z+iY= X-Authority-Analysis: v=2.4 cv=dYuwG3Xe c=1 sm=1 tr=0 ts=6a6baf90 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=YwPlQgHYUhtu6dumBzMA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDE0NSBTYWx0ZWRfXzvV6hLmdfO9h KWrWgKwXSwF1Z5qG0wZM6d914W+lFePYcuiQGnJB/FRVRhKn3aW94cvRaTavmmaSEGhHWiJG9qa clg+Fye2ZpGcFK+bUYWGI+44DIlVVaXnAF4y8XwsnDT3qWVg+S8j9ctnwXpqJ65V+U02LA/xjUN rnNf6G/UZRxZhbLdsfh7U8wl3T8oUgoS2uolTXEsF9JXijQr6Vx8kXUaqiXDA0x8B7y3wrMqYV+ GM0TIe0L3HPzINNztkCNrz8eX57hCaxezelCBQK/rGCFYkUj1y+FbxZ/tN4yrZNkil7YoWQmEq6 1vRfAf2rD90BL/iQp9D2qfgXOzKjyX0CptOQC5X1TkNonV4RFR0/JjIkR2+ARx9nvNt9bS2H9rg CoiV4xbTIRLJ+k2jiPCYa4sP0udVJhvVdcm39SM9KIiePkN/xl/gzjY7DGS4joU/+n7MaWb95FK gHoUNNg91ffOJw3WY0g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 clxscore=1015 phishscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300145 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1785442300500158500 Content-Type: text/plain; charset="utf-8" Add a PMBus device model for the TI-UCD90320 24-rail power sequencer. Configures 24 pages with linear vout mode and responds to the vendor-specific UCD9000_DEVICE_ID, NUM_PAGES, MONITOR_CONFIG, and MFR_STATUS commands, allowing the Linux ucd9000 driver to bind and create hwmon sysfs entries. Signed-off-by: Mikail Sadic --- MAINTAINERS | 1 + docs/specs/index.rst | 1 + docs/specs/ucd90320.rst | 36 +++++++++ hw/sensor/ucd90320.c | 169 ++++++++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/sensor/Kconfig | 4 + hw/sensor/meson.build | 1 + 7 files changed, 213 insertions(+) create mode 100644 docs/specs/ucd90320.rst create mode 100644 hw/sensor/ucd90320.c diff --git a/MAINTAINERS b/MAINTAINERS index 902db77218..ec415cb8e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4063,6 +4063,7 @@ F: hw/i2c/pmbus_device.c F: hw/sensor/adm1272.c F: hw/sensor/isl_pmbus_vr.c F: hw/sensor/max34451.c +F: hw/sensor/ucd90320.c F: include/hw/i2c/pmbus_device.h F: include/hw/sensor/isl_pmbus_vr.h F: tests/qtest/adm1272-test.c diff --git a/docs/specs/index.rst b/docs/specs/index.rst index b7909a108a..4de65e2fdf 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -39,4 +39,5 @@ guest hardware that is specific to QEMU. riscv-iommu riscv-aia aspeed-intc + ucd90320 iommu-testdev diff --git a/docs/specs/ucd90320.rst b/docs/specs/ucd90320.rst new file mode 100644 index 0000000000..fdc0878c75 --- /dev/null +++ b/docs/specs/ucd90320.rst @@ -0,0 +1,36 @@ +Texas Instruments UCD90320 Power Sequencer +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The UCD90320 is a 24-rail PMBus power sequencer. QEMU models it as a PMBus +device (``"ucd90320"``) so the Linux ``ucd9000`` driver can bind and create +``hwmon`` sysfs entries. + +The model configures 24 PMBus pages (one per rail) with ``VOUT_MODE =3D 0x= 00`` +(linear, exponent 0). ``READ_VOUT`` and ``MFR_STATUS`` return zero on all +pages. + +Vendor-specific commands handled: + ++------+---------------------------+--------------------------------------= ------+ +| Code | Name | Response = | ++=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D+ +| 0xD5 | ``UCD9000_MONITOR_CONFIG``| Block: one byte ``0x00`` = | ++------+---------------------------+--------------------------------------= ------+ +| 0xD6 | ``UCD9000_NUM_PAGES`` | Byte: ``24`` = | ++------+---------------------------+--------------------------------------= ------+ +| 0xF3 | ``UCD9000_MFR_STATUS`` | Block: four bytes ``0x00 0x00 0x00 0x= 00`` | ++------+---------------------------+--------------------------------------= ------+ +| 0xFD | ``UCD9000_DEVICE_ID`` | Block: ASCII string ``"UCD90320"`` = | ++------+---------------------------+--------------------------------------= ------+ + +``DEVICE_ID`` uses the vendor-specific code ``0xFD`` rather than the stand= ard +``PMBUS_IC_DEVICE_ID`` (``0xAD``), matching the Linux ``ucd9000`` probe +sequence. + +The UCD90320 is instantiated automatically in the ``huygens-bmc`` machine = on +I2C bus 5 at address ``0x11``. To instantiate on a different Aspeed machin= e: + +.. code-block:: c + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), + "ucd90320", 0x11); diff --git a/hw/sensor/ucd90320.c b/hw/sensor/ucd90320.c new file mode 100644 index 0000000000..6d4f828448 --- /dev/null +++ b/hw/sensor/ucd90320.c @@ -0,0 +1,169 @@ +/* + * Texas Instruments UCD90320 24-Rail PMBus Power Sequencer + * + * Copyright 2026 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/i2c/pmbus_device.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" + +#define TYPE_UCD90320 "ucd90320" + +/* UCD90320 has 24 sequenced power-rail pages */ +#define UCD90320_NUM_PAGES 24 + +/* Vendor-specific command codes (not in the standard PMBus register table= ) */ +#define UCD9000_MONITOR_CONFIG 0xd5 +#define UCD9000_NUM_PAGES 0xd6 +#define UCD9000_MFR_STATUS 0xf3 +#define UCD9000_DEVICE_ID 0xfd + +#define UCD90320_DEVICE_ID_LEN 8 +#define UCD90320_MFR_STATUS_LEN 4 + +typedef struct UCD90320State { + PMBusDevice parent; + + /* Reset values for the vendor-specific block-read commands. */ + uint8_t device_id[UCD90320_DEVICE_ID_LEN]; + uint8_t monitor_config; + uint8_t mfr_status[UCD90320_MFR_STATUS_LEN]; +} UCD90320State; + +#define UCD90320(obj) OBJECT_CHECK(UCD90320State, (obj), TYPE_UCD90320) + +static void ucd90320_send_block(PMBusDevice *pmdev, + const uint8_t *data, uint8_t len) +{ + int i; + + pmdev->out_buf[len + pmdev->out_buf_len] =3D len; + for (i =3D len - 1; i >=3D 0; i--) { + pmdev->out_buf[i + pmdev->out_buf_len] =3D data[len - 1 - i]; + } + pmdev->out_buf_len +=3D len + 1; +} + +static uint8_t ucd90320_read_byte(PMBusDevice *pmdev) +{ + UCD90320State *s =3D UCD90320(pmdev); + + switch (pmdev->code) { + case UCD9000_DEVICE_ID: + ucd90320_send_block(pmdev, s->device_id, sizeof(s->device_id)); + pmbus_idle(pmdev); + return 0; + case UCD9000_NUM_PAGES: + pmbus_send8(pmdev, UCD90320_NUM_PAGES); + pmbus_idle(pmdev); + return 0; + + case UCD9000_MONITOR_CONFIG: + ucd90320_send_block(pmdev, &s->monitor_config, + sizeof(s->monitor_config)); + pmbus_idle(pmdev); + return 0; + case UCD9000_MFR_STATUS: + ucd90320_send_block(pmdev, s->mfr_status, sizeof(s->mfr_status)); + pmbus_idle(pmdev); + return 0; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: reading from unsupported register: 0x%02x\n", + __func__, pmdev->code); + break; + } + return 0xFF; +} + +static int ucd90320_write_data(PMBusDevice *pmdev, const uint8_t *buf, + uint8_t len) +{ + if (len =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: writing empty data\n", __func_= _); + return -1; + } + + pmdev->code =3D buf[0]; + + if (len =3D=3D 1) { + return 0; + } + + return 0; +} + +static void ucd90320_exit_reset(Object *obj, ResetType type) +{ + PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); + UCD90320State *s =3D UCD90320(obj); + + pmdev->capability =3D 0x20; /* PEC supported */ + + for (int i =3D 0; i < UCD90320_NUM_PAGES; i++) { + pmdev->pages[i].operation =3D 0x80; /* on */ + pmdev->pages[i].on_off_config =3D 0x1a; + pmdev->pages[i].vout_mode =3D 0x00; /* linear mode, exponent= =3D0 */ + pmdev->pages[i].read_vout =3D 0; /* rails off, pgood=3D0 */ + } + + memcpy(s->device_id, "UCD90320", sizeof(s->device_id)); + s->monitor_config =3D 0x00; + memset(s->mfr_status, 0x00, sizeof(s->mfr_status)); +} + +static void ucd90320_init(Object *obj) +{ + PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); + uint64_t flags =3D PB_HAS_VOUT | PB_HAS_VOUT_MODE | + PB_HAS_STATUS_MFR_SPECIFIC; + + for (int i =3D 0; i < UCD90320_NUM_PAGES; i++) { + pmbus_page_config(pmdev, i, flags); + } +} + +static const VMStateDescription vmstate_ucd90320 =3D { + .name =3D TYPE_UCD90320, + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (const VMStateField[]) { + VMSTATE_PMBUS_DEVICE(parent, UCD90320State), + VMSTATE_UINT8_ARRAY(device_id, UCD90320State, UCD90320_DEVICE_ID_L= EN), + VMSTATE_UINT8(monitor_config, UCD90320State), + VMSTATE_UINT8_ARRAY(mfr_status, UCD90320State, + UCD90320_MFR_STATUS_LEN), + VMSTATE_END_OF_LIST() + } +}; + +static void ucd90320_class_init(ObjectClass *klass, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + PMBusDeviceClass *k =3D PMBUS_DEVICE_CLASS(klass); + + dc->desc =3D "Texas Instruments UCD90320 24-Rail Power Sequencer"; + dc->vmsd =3D &vmstate_ucd90320; + k->write_data =3D ucd90320_write_data; + k->receive_byte =3D ucd90320_read_byte; + k->device_num_pages =3D UCD90320_NUM_PAGES; + rc->phases.exit =3D ucd90320_exit_reset; +} + +static const TypeInfo ucd90320_types[] =3D { + { + .name =3D TYPE_UCD90320, + .parent =3D TYPE_PMBUS_DEVICE, + .instance_size =3D sizeof(UCD90320State), + .instance_init =3D ucd90320_init, + .class_init =3D ucd90320_class_init, + }, +}; + +DEFINE_TYPES(ucd90320_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 82e0bc2e70..ac44740547 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -555,6 +555,7 @@ config ASPEED_SOC select LED select PMBUS select MAX31785 + select UCD90320 select FSI_APB2OPB_ASPEED select AT24C select PCI_EXPRESS diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig index bc6331b4ab..135ffa7d5d 100644 --- a/hw/sensor/Kconfig +++ b/hw/sensor/Kconfig @@ -43,3 +43,7 @@ config ISL_PMBUS_VR config MAX31785 bool depends on PMBUS + +config UCD90320 + bool + depends on PMBUS diff --git a/hw/sensor/meson.build b/hw/sensor/meson.build index 420fdc3359..c0583161d3 100644 --- a/hw/sensor/meson.build +++ b/hw/sensor/meson.build @@ -8,3 +8,4 @@ system_ss.add(when: 'CONFIG_MAX34451', if_true: files('max3= 4451.c')) system_ss.add(when: 'CONFIG_LSM303DLHC_MAG', if_true: files('lsm303dlhc_ma= g.c')) system_ss.add(when: 'CONFIG_ISL_PMBUS_VR', if_true: files('isl_pmbus_vr.c'= )) system_ss.add(when: 'CONFIG_MAX31785', if_true: files('max31785.c')) +system_ss.add(when: 'CONFIG_UCD90320', if_true: files('ucd90320.c')) --=20 2.53.0 From nobody Mon Sep 28 02:13:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1785442300395158500 Content-Type: text/plain; charset="utf-8" In preparation for a sysbus UFS frontend (used by the Aspeed AST2700), separate the transport-independent UFS host-controller logic from the PCI-specific glue, following the pattern used by SDHCI and XHCI. UfsHc's PCIDevice parent is replaced by an anonymous union of a PCIDevice and a SysBusDevice, and the controller gains an explicit AddressSpace *dma_as used by ufs_addr_read()/ufs_addr_write() and the SG-list helpers instead of the PCI address space. Interrupt delivery goes through qemu_set_irq() in ufs_irq_check(). The realize path is split into a transport-agnostic ufs_realize_core() plus ufs_init_mmio(), and UfsBus gains an 'hc' back-pointer so ufs_lu_realize() no longer reaches through the PCI device. TYPE_UFS remains a PCI device, so '-device ufs' is unchanged and the PCI ufs-tests qtests still pass. Two small behaviour additions ride along on the core so that frontends with differing geometry and bus-scan behaviour can be modelled: - ufs-lu gains configurable 'logical-block-size' property. It defaults to UFS_BLOCK_SIZE, so the PCI device is unaffected. - an unmapped LUN now answers INQUIRY as "not connected" rather than failing the request, so that a host bus-scan does not observe controller errors for absent LUNs. Signed-off-by: Mikail Sadic --- hw/ufs/ufs.h | 18 ++++++++++++++++- hw/ufs/lu.c | 50 +++++++++++++++++++++++++++++++++++++++++---- hw/ufs/ufs.c | 57 ++++++++++++++++++++++++++++++++++++---------------- 3 files changed, 103 insertions(+), 22 deletions(-) diff --git a/hw/ufs/ufs.h b/hw/ufs/ufs.h index feb47f460d..3d4be8deb5 100644 --- a/hw/ufs/ufs.h +++ b/hw/ufs/ufs.h @@ -12,7 +12,9 @@ #define HW_UFS_UFS_H =20 #include "hw/pci/pci_device.h" +#include "hw/core/sysbus.h" #include "hw/scsi/scsi.h" +#include "scsi/constants.h" #include "block/ufs.h" =20 #define UFS_MAX_LUS 32 @@ -27,6 +29,7 @@ typedef struct UfsBusClass { =20 typedef struct UfsBus { BusState parent_bus; + struct UfsHc *hc; /* host controller owning this bus (frontend-agnosti= c) */ } UfsBus; =20 #define TYPE_UFS_BUS "ufs-bus" @@ -77,6 +80,7 @@ typedef UfsReqResult (*UfsScsiOp)(struct UfsLu *, UfsRequ= est *); typedef struct UfsLu { DeviceState qdev; uint8_t lun; + uint32_t logical_block_size; UnitDescriptor unit_desc; SCSIBus bus; SCSIDevice *scsi_dev; @@ -141,7 +145,15 @@ typedef struct UfsWb { } UfsWb; =20 typedef struct UfsHc { - PCIDevice parent_obj; + /* + * The controller can be instantiated either as a PCI function or as a + * sysbus device. Following the SDHCI model, both frontends share this + * state structure via a union of the possible parent objects. + */ + union { + PCIDevice pci_dev; + SysBusDevice sbdev; + }; UfsBus bus; MemoryRegion iomem; UfsReg reg; @@ -162,6 +174,7 @@ typedef struct UfsHc { Flags flags; =20 qemu_irq irq; + AddressSpace *dma_as; QEMUBH *doorbell_bh; QEMUBH *complete_bh; =20 @@ -302,4 +315,7 @@ void ufs_build_query_response(UfsRequest *req); void ufs_complete_req(UfsRequest *req, UfsReqResult req_result); void ufs_wb_update_avail_buffer(UfsHc *u); void ufs_init_wlu(UfsLu *wlu, uint8_t wlun); +UfsReqResult ufs_emulate_absent_lun(UfsRequest *req); +void ufs_init_mmio(UfsHc *u); +bool ufs_realize_core(UfsHc *u, Error **errp); #endif /* HW_UFS_UFS_H */ diff --git a/hw/ufs/lu.c b/hw/ufs/lu.c index 13f4a90145..a0b5574668 100644 --- a/hw/ufs/lu.c +++ b/hw/ufs/lu.c @@ -308,6 +308,44 @@ static int ufs_emulate_wlun_inquiry(UfsRequest *req, u= int8_t *outbuf, return SCSI_INQUIRY_LEN; } =20 +UfsReqResult ufs_emulate_absent_lun(UfsRequest *req) +{ + QEMU_UNINITIALIZED uint8_t outbuf[SCSI_INQUIRY_LEN]; + uint8_t sense_buf[UFS_SENSE_SIZE]; + uint8_t scsi_status; + int len =3D 0; + + if (req->req_upiu.sc.cdb[0] =3D=3D INQUIRY && + !(req->req_upiu.sc.cdb[1] & 0x1)) { + /* + * Standard INQUIRY to a logical unit that is not mapped: report it + * as "not connected" (peripheral qualifier 0x3, device type 0x1f) + * with GOOD status, like real hardware. Host-side bus scans then + * skip the unit quietly instead of flagging a controller error. + */ + memset(outbuf, 0, sizeof(outbuf)); + outbuf[0] =3D TYPE_NO_LUN; + outbuf[3] =3D 0x2; + outbuf[4] =3D SCSI_INQUIRY_LEN - 5; + len =3D SCSI_INQUIRY_LEN; + scsi_status =3D GOOD; + } else { + scsi_build_sense(sense_buf, SENSE_CODE(LUN_NOT_SUPPORTED)); + scsi_status =3D CHECK_CONDITION; + } + + len =3D MIN(len, (int)req->data_len); + if (scsi_status =3D=3D GOOD && len > 0 && + dma_buf_read(outbuf, len, NULL, req->sg, MEMTXATTRS_UNSPECIFIED) != =3D + MEMTX_OK) { + return UFS_REQUEST_FAIL; + } + + ufs_build_scsi_response_upiu(req, sense_buf, sizeof(sense_buf), len, + scsi_status); + return UFS_REQUEST_SUCCESS; +} + static UfsReqResult ufs_emulate_scsi_cmd(UfsLu *lu, UfsRequest *req) { uint8_t lun =3D lu->lun; @@ -394,6 +432,8 @@ static UfsReqResult ufs_process_scsi_cmd(UfsLu *lu, Ufs= Request *req) static const Property ufs_lu_props[] =3D { DEFINE_PROP_DRIVE("drive", UfsLu, conf.blk), DEFINE_PROP_UINT8("lun", UfsLu, lun, 0), + DEFINE_PROP_UINT32("logical-block-size", UfsLu, logical_block_size, + UFS_BLOCK_SIZE), }; =20 static bool ufs_add_lu(UfsHc *u, UfsLu *lu, Error **errp) @@ -435,7 +475,7 @@ static void ufs_init_lu(UfsLu *lu) lu->unit_desc.length =3D sizeof(UnitDescriptor); lu->unit_desc.descriptor_idn =3D UFS_QUERY_DESC_IDN_UNIT; lu->unit_desc.lu_enable =3D 0x01; - lu->unit_desc.logical_block_size =3D UFS_BLOCK_SIZE_SHIFT; + lu->unit_desc.logical_block_size =3D ctz32(lu->logical_block_size); lu->unit_desc.unit_index =3D lu->lun; lu->unit_desc.logical_block_count =3D cpu_to_be64(brdv_len / (1 << lu->unit_desc.logical_block_size)); @@ -475,8 +515,10 @@ static void ufs_init_scsi_device(UfsLu *lu, BlockBacke= nd *blk, Error **errp) scsi_dev =3D qdev_new("scsi-hd"); object_property_add_child(OBJECT(&lu->bus), "ufs-scsi", OBJECT(scsi_de= v)); =20 - qdev_prop_set_uint32(scsi_dev, "physical_block_size", UFS_BLOCK_SIZE); - qdev_prop_set_uint32(scsi_dev, "logical_block_size", UFS_BLOCK_SIZE); + qdev_prop_set_uint32(scsi_dev, "physical_block_size", + lu->logical_block_size); + qdev_prop_set_uint32(scsi_dev, "logical_block_size", + lu->logical_block_size); qdev_prop_set_uint32(scsi_dev, "scsi-id", 0); qdev_prop_set_uint32(scsi_dev, "lun", lu->lun); if (!qdev_prop_set_drive_err(scsi_dev, "drive", blk, errp)) { @@ -497,7 +539,7 @@ static void ufs_lu_realize(DeviceState *dev, Error **er= rp) { UfsLu *lu =3D DO_UPCAST(UfsLu, qdev, dev); BusState *s =3D qdev_get_parent_bus(dev); - UfsHc *u =3D UFS(s->parent); + UfsHc *u =3D UFS_BUS(s)->hc; BlockBackend *blk =3D lu->conf.blk; =20 if (!ufs_lu_check_constraints(lu, errp)) { diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index 464fd465b3..1489bd3321 100644 --- a/hw/ufs/ufs.c +++ b/hw/ufs/ufs.c @@ -102,7 +102,8 @@ static MemTxResult ufs_addr_read(UfsHc *u, hwaddr addr,= void *buf, int size) return MEMTX_DECODE_ERROR; } =20 - return pci_dma_read(PCI_DEVICE(u), addr, buf, size); + return dma_memory_read(u->dma_as, addr, buf, size, + MEMTXATTRS_UNSPECIFIED); } =20 static MemTxResult ufs_addr_write(UfsHc *u, hwaddr addr, const void *buf, @@ -117,7 +118,8 @@ static MemTxResult ufs_addr_write(UfsHc *u, hwaddr addr= , const void *buf, return MEMTX_DECODE_ERROR; } =20 - return pci_dma_write(PCI_DEVICE(u), addr, buf, size); + return dma_memory_write(u->dma_as, addr, buf, size, + MEMTXATTRS_UNSPECIFIED); } =20 static inline hwaddr ufs_get_utrd_addr(UfsHc *u, uint32_t slot) @@ -222,7 +224,7 @@ static MemTxResult ufs_dma_read_prdt(UfsRequest *req) } =20 req->sg =3D g_malloc0(sizeof(QEMUSGList)); - pci_dma_sglist_init(req->sg, PCI_DEVICE(u), prdt_len); + qemu_sglist_init(req->sg, DEVICE(u), prdt_len, u->dma_as); req->data_len =3D 0; =20 for (uint16_t i =3D 0; i < prdt_len; ++i) { @@ -317,14 +319,12 @@ static MemTxResult ufs_dma_write_upiu(UfsRequest *req) =20 static void ufs_irq_check(UfsHc *u) { - PCIDevice *pci =3D PCI_DEVICE(u); - if ((u->reg.is & UFS_INTR_MASK) & u->reg.ie) { trace_ufs_irq_raise(); - pci_irq_assert(pci); + qemu_set_irq(u->irq, 1); } else { trace_ufs_irq_lower(); - pci_irq_deassert(pci); + qemu_set_irq(u->irq, 0); } } =20 @@ -1092,7 +1092,7 @@ static UfsReqResult ufs_exec_scsi_cmd(UfsRequest *req) =20 if (!is_wlun(lun) && (lun >=3D UFS_MAX_LUS || u->lus[lun] =3D=3D NULL)= ) { trace_ufs_err_scsi_cmd_invalid_lun(lun); - return UFS_REQUEST_FAIL; + return ufs_emulate_absent_lun(req); } =20 switch (lun) { @@ -2488,6 +2488,12 @@ static bool ufs_check_constraints(UfsHc *u, Error **= errp) return true; } =20 +void ufs_init_mmio(UfsHc *u) +{ + memory_region_init_io(&u->iomem, OBJECT(u), &ufs_mmio_ops, u, "ufs", + u->reg_size); +} + static void ufs_init_pci(UfsHc *u, PCIDevice *pci_dev) { uint8_t *pci_conf =3D pci_dev->config; @@ -2495,8 +2501,7 @@ static void ufs_init_pci(UfsHc *u, PCIDevice *pci_dev) pci_conf[PCI_INTERRUPT_PIN] =3D 1; pci_config_set_prog_interface(pci_conf, 0x1); =20 - memory_region_init_io(&u->iomem, OBJECT(u), &ufs_mmio_ops, u, "ufs", - u->reg_size); + ufs_init_mmio(u); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &u->iomem); u->irq =3D pci_allocate_irq(pci_dev); } @@ -2689,25 +2694,43 @@ static void ufs_init_hc(UfsHc *u) timer_mod(&u->idle_timer, now + UFS_IDLE_TIMER_TICK); } =20 -static void ufs_realize(PCIDevice *pci_dev, Error **errp) +/* + * Frontend-agnostic realization: everything except the host-bus specific + * MMIO/IRQ/DMA plumbing, which the PCI or sysbus frontend sets up around + * this call. The frontend must assign u->dma_as before calling. + */ +bool ufs_realize_core(UfsHc *u, Error **errp) { - UfsHc *u =3D UFS(pci_dev); - if (!ufs_check_constraints(u, errp)) { - return; + return false; } =20 - qbus_init(&u->bus, sizeof(UfsBus), TYPE_UFS_BUS, &pci_dev->qdev, - u->parent_obj.qdev.id); + qbus_init(&u->bus, sizeof(UfsBus), TYPE_UFS_BUS, DEVICE(u), + DEVICE(u)->id); + u->bus.hc =3D u; =20 ufs_init_state(u); ufs_init_hc(u); - ufs_init_pci(u, pci_dev); =20 ufs_init_wlu(&u->report_wlu, UFS_UPIU_REPORT_LUNS_WLUN); ufs_init_wlu(&u->dev_wlu, UFS_UPIU_UFS_DEVICE_WLUN); ufs_init_wlu(&u->boot_wlu, UFS_UPIU_BOOT_WLUN); ufs_init_wlu(&u->rpmb_wlu, UFS_UPIU_RPMB_WLUN); + + return true; +} + +static void ufs_realize(PCIDevice *pci_dev, Error **errp) +{ + UfsHc *u =3D UFS(pci_dev); + + u->dma_as =3D pci_get_address_space(pci_dev); + + if (!ufs_realize_core(u, errp)) { + return; + } + + ufs_init_pci(u, pci_dev); } =20 static void ufs_exit(PCIDevice *pci_dev) --=20 2.53.0 From nobody Mon Sep 28 02:13:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 30 Jul 2026 20:09:50 +0000 (GMT) Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AE0BB58059; Thu, 30 Jul 2026 20:09:49 +0000 (GMT) Received: from IBM-MFS.atx-us.ibm.com (unknown [9.16.49.87]) by smtpav06.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 30 Jul 2026 20:09:49 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=FWH5fKEXgV1pyhFdq EV8/wNsqC10HjLI7+sxkBzqIC8=; b=LpH/8kojEHKnDEqZ3UDHpDV/hhbnEN0X2 zQ8znmDfXpIr8kK6PgnqDocfeyR9lu3cilXJ1aNlgZ2i1ROdlTRlGgekpNM/VwLK sR5D4fae7YHbfph1xcBTirjIF0Ee4vAAio9kldcqPekpkKHeqHUySurYEX5zglRf a9fY6pQgnJ1PfZ6ZYgWuY6uNfuP17oANrhQGZrdrTc8qDoc5Cl9e731bl07y5jXG ky59ZAAhTuP8WRXN1xDAICy2AOjAxiP7ZTXzBqqaPHkd8IXsjTofAwqez6MdQN/u fNG8eiqbjKae/eVOEoP2emVnVPPNkdW4KMTM9PIDmWfhS8f6Wn1iQ== From: Mikail Sadic To: clg@kaod.org, peter.maydell@linaro.org Cc: Mikail Sadic , pbonzini@redhat.com, ninad@linux.ibm.com, titusr@google.com, jeuk20.kim@samsung.com, philmd@mailo.com, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, kane_chen@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, calebs@linux.ibm.com, milesg@linux.ibm.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 7/8] ufs/aspeed: Add AST2700 sysbus UFS frontend Date: Thu, 30 Jul 2026 15:09:42 -0500 Message-ID: <20260730200945.1113936-8-mikail.sadic@ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260730200945.1113936-1-mikail.sadic@ibm.com> References: <20260730200945.1113936-1-mikail.sadic@ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-ORIG-GUID: YEVZtXDm-DSnWaz_85lEP0r0jnetkZSi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDE0NSBTYWx0ZWRfX0WxJXGdwxGl2 3LcIarXuILV4maGCeYZPYwLDYm8OQjRCOBm+AI+r8Sk+jnqIsLgh2Z9XybiK9QWayB23BJsq90F d0rTOsmAZyND2DSuQti2qsusDKBrjv6o2qiHA78GEj5ztieBijW0UC7vL0Wjxg21hFeyzHq2obF eSQ7l+gW9PdAb8jde2pPYiCVKqsyabtGklz7ZzCEL9fk9p813xUnbdmBC9rKYeAzUXRSQXWlxXD 3DaZxfyHrCZt02ibMIdCoursYHn6QYcNouTz7dwES0qMMjzZW3iU6993eqAY7HxNr5PyMBENUrq +Wicz0G8tpONw29M8kJqhu6xKFnx6AKUspJ1KrspmhpdZNy4fDwn/LA6Qlua9zb72ypJoPFIiqu vCXN04iFPKQI8lqgAp1dWWwTdrhXvyFSC1nndCyZJS+vbVPm5y1B7DHruko1iv/m7eV8WBnPD0P u5IvE94mY1zhHFGwwGA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDE0NSBTYWx0ZWRfXzwrId/mPb1pB 2CU8+116k4eY/OQw6IwcyJXBHbakk6IdqRJzOuc2qcRs+L0kwNHIy1fbczCe7ed23oG1k5QRHom iq9B3w9wiAyuWEZs1uDY4l8XQWabM3U= X-Authority-Analysis: v=2.4 cv=AZeB2XXG c=1 sm=1 tr=0 ts=6a6baf91 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=hD80L64hAAAA:8 a=3Ht_1UATksvqfbOLzXUA:9 X-Proofpoint-GUID: C8vwfhOB7860XLOsy7cT3YYkMREV46q5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 clxscore=1015 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300145 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1785442294514158500 Content-Type: text/plain; charset="utf-8" Add TYPE_ASPEED_UFS, a sysbus frontend around the common UFS core, and wire it into the AST2700 SoC. The frontend reuses UfsHc (instance_size =3D sizeof(UfsHc)), sets dma_as to address_space_memory, and calls ufs_realize_core() before exposing its MMIO region and IRQ via sysbus. It reports UFSHCI 2.0 (reg.ver =3D 0x0200) to match the AST2700 (aspeed,ufshc-m31-16nm). Signed-off-by: Mikail Sadic --- MAINTAINERS | 1 + docs/specs/aspeed-ufs.rst | 40 ++++++++++++++++++++ docs/specs/index.rst | 1 + include/hw/arm/aspeed.h | 1 + include/hw/arm/aspeed_soc.h | 3 ++ include/hw/ufs/aspeed_ufs.h | 16 ++++++++ hw/arm/aspeed.c | 25 +++++++++++++ hw/arm/aspeed_ast27x0.c | 13 +++++++ hw/ufs/aspeed_ufs.c | 75 +++++++++++++++++++++++++++++++++++++ hw/ufs/meson.build | 1 + 10 files changed, 176 insertions(+) create mode 100644 docs/specs/aspeed-ufs.rst create mode 100644 include/hw/ufs/aspeed_ufs.h create mode 100644 hw/ufs/aspeed_ufs.c diff --git a/MAINTAINERS b/MAINTAINERS index ec415cb8e4..abebae2ff9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2700,6 +2700,7 @@ M: Jeuk Kim S: Supported F: hw/ufs/* F: include/block/ufs.h +F: include/hw/ufs/aspeed_ufs.h F: tests/qtest/ufs-test.c =20 megasas diff --git a/docs/specs/aspeed-ufs.rst b/docs/specs/aspeed-ufs.rst new file mode 100644 index 0000000000..596b5d2756 --- /dev/null +++ b/docs/specs/aspeed-ufs.rst @@ -0,0 +1,40 @@ +ASPEED AST2700 UFS Host Controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The AST2700 SoC includes a UFS host controller identified in the device tr= ee +as ``aspeed,ufshc-m31-16nm``, mapped at ``0x12c08200`` (IRQ SPI 118). QEMU +models it as a sysbus frontend on top of the shared UFS core that also bac= ks +the PCI UFS device (``hw/ufs/ufs.c`` and ``hw/ufs/lu.c``). The frontend on= ly +provides the sysbus MMIO region, the interrupt line and the DMA address +space; all UFSHCI register behaviour, UTP transfer/task list processing, +UPIU and query handling and the SCSI logical-unit logic are implemented by +the core. + +The clock/reset wrapper at ``0x12c08000`` (``aspeed,ast2700-ufscnr``) is l= eft +as an ``UnimplementedDevice``. + +Logical units +------------- + +Storage is attached through ``ufs-lu`` devices on the controller's UFS bus +(``ufs-bus.0``), exactly as for the PCI UFS device. The Huygens OpenBMC im= age +is laid out for 512-byte sectors, so its logical unit is created with +``logical-block-size=3D512``. + +Usage +----- + +Attach a UFS image as logical unit 0 of the controller's UFS bus: + +.. code-block:: console + + qemu-system-aarch64 -M huygens-bmc \ + -nodefaults \ + -blockdev node-name=3Dfmc0,driver=3Dfile,filename=3Dimage-bmc \ + -device w25q01jvq,bus=3Dssi.0,cs=3D0,drive=3Dfmc0 \ + -blockdev node-name=3Dufs0,driver=3Dfile,filename=3Dufs.img \ + -device ufs-lu,bus=3Dufs-bus.0,drive=3Dufs0,lun=3D0,logical-block-size= =3D512 \ + -display none -serial mon:stdio + +Please check :doc:`../../system/arm/aspeed` for more details on the +``huygens-bmc`` machine. diff --git a/docs/specs/index.rst b/docs/specs/index.rst index 4de65e2fdf..dd0cdec8d4 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -40,4 +40,5 @@ guest hardware that is specific to QEMU. riscv-aia aspeed-intc ucd90320 + aspeed-ufs iommu-testdev diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index a00238ed74..dedc784926 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -62,6 +62,7 @@ struct AspeedMachineClass { uint32_t uart_default; bool sdhci_wp_inverted; bool vbootrom; + uint32_t ufs_block_size; }; =20 /* diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 41dc04e293..56fab0a350 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -35,6 +35,7 @@ #include "hw/gpio/aspeed_gpio.h" #include "hw/gpio/aspeed_sgpio.h" #include "hw/sd/aspeed_sdhci.h" +#include "hw/ufs/aspeed_ufs.h" #include "hw/usb/hcd-ehci.h" #include "qom/object.h" #include "hw/misc/aspeed_lpc.h" @@ -118,6 +119,7 @@ struct AspeedSoCState { AspeedAPB2OPBState fsi[2]; AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM]; + UfsHc ufs; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" @@ -298,6 +300,7 @@ enum { ASPEED_DEV_PRIC0, ASPEED_DEV_PRIC1, ASPEED_DEV_OTP, + ASPEED_DEV_UFS, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/include/hw/ufs/aspeed_ufs.h b/include/hw/ufs/aspeed_ufs.h new file mode 100644 index 0000000000..1ccd0b51c0 --- /dev/null +++ b/include/hw/ufs/aspeed_ufs.h @@ -0,0 +1,16 @@ +/* + * ASPEED AST2700 UFS Host Controller + * + * Copyright 2026 IBM Corp. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ASPEED_UFS_H +#define ASPEED_UFS_H + +#include "hw/ufs/ufs.h" + +#define TYPE_ASPEED_UFS "aspeed-ufs" +#define ASPEED_UFS(obj) OBJECT_CHECK(UfsHc, (obj), TYPE_ASPEED_UFS) + +#endif /* ASPEED_UFS_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a48c442058..5b9943a0e0 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -187,6 +187,31 @@ static void aspeed_machine_init(MachineState *machine) aspeed_connect_serial_hds_to_uarts(bmc); qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); =20 + /* + * If the SoC instantiated a UFS host controller (AST2700), attach the + * first backend drive to it as logical unit 0. The controller and its + * UFS bus only exist once the SoC has been realized, so the ufs-lu is + * created here rather than through a controller drive property. + */ + if (object_resolve_path_component(OBJECT(bmc->soc), "ufs")) { + DriveInfo *ufs_dinfo =3D drive_get(IF_NONE, 0, 0); + + if (ufs_dinfo) { + DeviceState *ufs_lu =3D qdev_new(TYPE_UFS_LU); + + qdev_prop_set_uint8(ufs_lu, "lun", 0); + if (amc->ufs_block_size) { + qdev_prop_set_uint32(ufs_lu, "logical-block-size", + amc->ufs_block_size); + } + qdev_prop_set_drive_err(ufs_lu, "drive", + blk_by_legacy_dinfo(ufs_dinfo), + &error_fatal); + qdev_realize_and_unref(ufs_lu, BUS(&bmc->soc->ufs.bus), + &error_fatal); + } + } + if (defaults_enabled()) { aspeed_board_init_flashes(&bmc->soc->fmc, bmc->fmc_model ? bmc->fmc_model : amc->fmc_m= odel, diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index b908d7d4ff..1ee8f3a210 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -46,6 +46,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_GIC_REDIST] =3D 0x12280000, [ASPEED_DEV_SDMC] =3D 0x12C00000, [ASPEED_DEV_SCU] =3D 0x12C02000, + [ASPEED_DEV_UFS] =3D 0x12c08200, [ASPEED_DEV_RTC] =3D 0x12C0F000, [ASPEED_DEV_TIMER1] =3D 0x12C10000, [ASPEED_DEV_PCIE_PHY0] =3D 0x12C15000, @@ -129,6 +130,7 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_EHCI2] =3D 37, [ASPEED_DEV_PCIE0] =3D 56, [ASPEED_DEV_PCIE1] =3D 57, + [ASPEED_DEV_UFS] =3D 118, [ASPEED_DEV_LPC] =3D 192, [ASPEED_DEV_IBT] =3D 192, [ASPEED_DEV_KCS] =3D 192, @@ -533,6 +535,8 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0= ], TYPE_SYSBUS_SDHCI); =20 + object_initialize_child(obj, "ufs", &s->ufs, TYPE_ASPEED_UFS); + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); =20 @@ -1039,6 +1043,15 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_EMMC)); =20 + /* UFS */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ufs), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ufs), 0, + sc->memmap[ASPEED_DEV_UFS]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ufs), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_UFS)); + /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), &error_abort); diff --git a/hw/ufs/aspeed_ufs.c b/hw/ufs/aspeed_ufs.c new file mode 100644 index 0000000000..d3e1a9a736 --- /dev/null +++ b/hw/ufs/aspeed_ufs.c @@ -0,0 +1,75 @@ +/* + * ASPEED AST2700 UFS Host Controller + * + * Sysbus frontend for the AST2700 UFS host controller + * (aspeed,ufshc-m31-16nm). The UFSHCI register interface, UTRL/UTMRL + * processing, UPIU/query handling and the SCSI/logical-unit logic are all + * provided by the shared UFS core (hw/ufs/ufs.c, hw/ufs/lu.c); this file + * only supplies the sysbus-specific MMIO, IRQ and DMA plumbing. + * + * The ASPEED clock/reset wrapper at 0x12c08000 (aspeed,ast2700-ufscnr) is + * modelled elsewhere as an UnimplementedDevice. + * + * Copyright 2026 IBM Corp. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/core/qdev-properties.h" +#include "system/address-spaces.h" +#include "hw/ufs/aspeed_ufs.h" + +static void aspeed_ufs_realize(DeviceState *dev, Error **errp) +{ + UfsHc *u =3D ASPEED_UFS(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + /* AST2700 UFS masters DMA into system memory. */ + u->dma_as =3D &address_space_memory; + + if (!ufs_realize_core(u, errp)) { + return; + } + + /* + * The AST2700 host controller (aspeed,ufshc-m31-16nm) reports UFSHCI + * version 2.0. The shared core defaults to 4.1, which makes the U-Boot + * and Linux aspeed-ufs drivers run 4.x-only probe steps that this mod= el + * does not implement. Pin the controller version register to 2.0. + */ + u->reg.ver =3D 0x00000200; + + ufs_init_mmio(u); + sysbus_init_mmio(sbd, &u->iomem); + sysbus_init_irq(sbd, &u->irq); +} + +static const Property aspeed_ufs_props[] =3D { + DEFINE_PROP_STRING("serial", UfsHc, params.serial), + DEFINE_PROP_UINT8("nutrs", UfsHc, params.nutrs, 32), + DEFINE_PROP_UINT8("nutmrs", UfsHc, params.nutmrs, 8), + DEFINE_PROP_UINT32("wb-max-size", UfsHc, params.wb_max_size, 0x400), + DEFINE_PROP_UINT32("wb-min-size", UfsHc, params.wb_min_size, 0x100), +}; + +static void aspeed_ufs_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D aspeed_ufs_realize; + dc->desc =3D "ASPEED UFS Host Controller"; + device_class_set_props(dc, aspeed_ufs_props); + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); +} + +static const TypeInfo aspeed_ufs_types[] =3D { + { + .name =3D TYPE_ASPEED_UFS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(UfsHc), + .class_init =3D aspeed_ufs_class_init, + }, +}; + +DEFINE_TYPES(aspeed_ufs_types) diff --git a/hw/ufs/meson.build b/hw/ufs/meson.build index 6e68328b93..86052e6fd2 100644 --- a/hw/ufs/meson.build +++ b/hw/ufs/meson.build @@ -1 +1,2 @@ system_ss.add(when: 'CONFIG_UFS_PCI', if_true: files('ufs.c', 'lu.c')) +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_ufs.c')) --=20 2.53.0 From nobody Mon Sep 28 02:13:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1785442316; cv=none; d=zohomail.com; s=zohoarc; b=iA8ldySWpZ5CKn/Yg+ycxPvi9GaYR9gIykctyrExYWqrN9u3A91qpfLkJx9o00AIbG+vsRYitjpvIq/flKX4BJgPWfi8kh9nm+VQgbNnPig3GVsv25DqUq74ufgDmko+BL6yRFSnHBcuVdP3sCzFiodR9lCXzbzo/8/X/sz5lUo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=mikail.sadic@ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1785442318406158500 Content-Type: text/plain; charset="utf-8" Huygens is the BMC of the IBM POWER12 server platform. The BMC handles power sequencing, thermal management, VPD access and host firmware boot for the POWER host processors. It is built around the Aspeed AST2700 A2 SoC. Add a 'huygens-bmc' machine that instantiates the AST2700 SoC with the board-specific configuration needed to boot the OpenBMC Linux image: the FMC/SPI flash models, the I2C topology (BMC, system and chassis VPD EEPROMs, the UCD90320 power sequencer and temperature sensors) and the network controllers. Signed-off-by: Mikail Sadic --- docs/system/arm/aspeed.rst | 50 ++++++- hw/arm/aspeed_ast27x0_huygens.c | 241 ++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 290 insertions(+), 2 deletions(-) create mode 100644 hw/arm/aspeed_ast27x0_huygens.c diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 2d51ceeb84..4e42b1edee 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -271,8 +271,8 @@ configuration file for OTP memory: done > otpmem.img fi =20 -Aspeed 2700 family boards (``ast2700-evb``, ``ast2700fc``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D +Aspeed 2700 family boards (``ast2700-evb``, ``ast2700fc``, ``huygens-bmc``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D =20 The QEMU Aspeed machines model BMCs of Aspeed evaluation boards. They are based on different releases of the Aspeed SoC : @@ -285,6 +285,7 @@ AST2700 SoC based machines : =20 - ``ast2700-evb`` Aspeed AST2700 Evaluation board (Cortex-A35) - ``ast2700fc`` Aspeed AST2700 Evaluation board (Cortex-A35 + C= ortex-M4) +- ``huygens-bmc`` Aspeed AST2700 IBM Huygens POWER12 BMC =20 Supported devices ----------------- @@ -312,6 +313,8 @@ Supported devices * PECI Controller (minimal) * I3C Controller * Internal Bridge Controller (SLI dummy) + * UFS Host Controller (aspeed,ufshc-m31-16nm) - ``huygens-bmc`` only + * FSI APB-to-OPB bridge with CFAM-S mailbox =20 Missing devices --------------- @@ -440,6 +443,49 @@ Use ``tio`` or another terminal emulator to connect to= the consoles: $ tio /dev/pts/56 $ tio /dev/pts/57 =20 +Booting the huygens-bmc machine +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The IBM Huygens BMC is based on the AST2700 A2 SoC. Its storage is +split across two images: + +* the FMC (SPI NOR) flash image (``image-bmc``) holds U-Boot, the Linux + kernel and the FIT image; +* the UFS image (``ufs.img``) holds the root filesystem. + +Both images can be built from the OpenBMC project tree. + +To boot the machine, attach the flash image to the FMC device and the +root filesystem image to a UFS logical unit. ``-nodefaults`` is used so the +board does not also create a default flash at chip-select 0, and the conso= le +is wired explicitly since ``-nodefaults`` disables the implicit one: + +.. code-block:: bash + + $ qemu-system-aarch64 -M huygens-bmc \ + -nodefaults \ + -blockdev node-name=3Dfmc0,driver=3Dfile,filename=3Dimage-bmc \ + -device w25q01jvq,bus=3Dssi.0,cs=3D0,drive=3Dfmc0 \ + -blockdev node-name=3Dufs0,driver=3Dfile,filename=3Dufs.img \ + -device ufs-lu,bus=3Dufs-bus.0,drive=3Dufs0,lun=3D0,logical-block-= size=3D512 \ + -display none -serial mon:stdio + +The FMC flash sits on chip-select 0 of the ``ssi.0`` bus and the UFS logic= al +unit on ``ufs-bus.0``. The Huygens image is laid out for 512-byte sectors, +hence ``logical-block-size=3D512``. + +The machine instantiates three ``ftgmac100`` Ethernet controllers, which +are wired up by the board. To expose them with user networking, add three +``-nic user`` options to the command above: + +.. code-block:: bash + + -nic user \ + -nic user \ + -nic user + +The default BMC console is ``uart12``. + =20 Aspeed Bridge IC and Platform Root of Trust processor family boards (``ast= 1030-evb``, ``ast1040-evb``, ``ast1060-evb``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/hw/arm/aspeed_ast27x0_huygens.c b/hw/arm/aspeed_ast27x0_huygen= s.c new file mode 100644 index 0000000000..bed91ce042 --- /dev/null +++ b/hw/arm/aspeed_ast27x0_huygens.c @@ -0,0 +1,241 @@ +/* + * IBM Huygens + * + * Copyright 2026 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/machines-qom.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/nvram/eeprom_at24c.h" +#include "hw/i2c/i2c_mux_pca954x.h" +#include "hw/sensor/tmp105.h" + +/* SCU HW Strap1 */ +#define HUYGENS_BMC_HW_STRAP1 0x00000800 +/* SCUIO HW Strap1 */ +#define HUYGENS_BMC_HW_STRAP2 0x00000700 + +/* + * 2048-byte IPZ VPD image: + * VHDR, VTOC, VINI, VMPU, VSBP, VSYS, UTIL, DINF, VCEN + ECC + */ +static const uint8_t huygens_bmc_fruid[] =3D { + 0x00, 0x0f, 0x17, 0xba, 0x3a, 0xc9, 0x32, 0x31, 0x49, 0xb2, 0xde, 0x84, + 0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02, + 0x30, 0x31, 0x50, 0x54, 0x0e, 0x56, 0x54, 0x4f, 0x43, 0xd5, 0x00, 0x37, + 0x00, 0x74, 0x00, 0xa6, 0x05, 0x1d, 0x00, 0x50, 0x46, 0x08, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x84, 0x70, 0x00, 0x52, 0x54, + 0x04, 0x56, 0x54, 0x4f, 0x43, 0x50, 0x54, 0x62, 0x56, 0x49, 0x4e, 0x49, + 0xd5, 0x00, 0xab, 0x00, 0x84, 0x00, 0x85, 0x05, 0x21, 0x00, 0x56, 0x4d, + 0x50, 0x55, 0xff, 0x00, 0x2f, 0x01, 0xa4, 0x00, 0x5c, 0x05, 0x29, 0x00, + 0x56, 0x53, 0x42, 0x50, 0xff, 0x00, 0xd3, 0x01, 0x30, 0x00, 0x50, 0x05, + 0x0c, 0x00, 0x56, 0x53, 0x59, 0x53, 0xff, 0x00, 0x03, 0x02, 0x44, 0x01, + 0xff, 0x04, 0x51, 0x00, 0x55, 0x54, 0x49, 0x4c, 0xff, 0x00, 0x47, 0x03, + 0xe8, 0x00, 0xc5, 0x04, 0x3a, 0x00, 0x44, 0x49, 0x4e, 0x46, 0xff, 0x00, + 0x2f, 0x04, 0x30, 0x00, 0xb9, 0x04, 0x0c, 0x00, 0x56, 0x43, 0x45, 0x4e, + 0xff, 0x00, 0x5f, 0x04, 0x48, 0x00, 0xa7, 0x04, 0x12, 0x00, 0x50, 0x46, + 0x01, 0x00, 0x78, 0x84, 0x80, 0x00, 0x52, 0x54, 0x04, 0x56, 0x49, 0x4e, + 0x49, 0x44, 0x52, 0x10, 0x51, 0x45, 0x4d, 0x55, 0x20, 0x48, 0x55, 0x59, + 0x47, 0x45, 0x4e, 0x53, 0x20, 0x42, 0x4d, 0x43, 0x43, 0x45, 0x01, 0x20, + 0x56, 0x5a, 0x02, 0x20, 0x20, 0x46, 0x4e, 0x07, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x50, 0x4e, 0x07, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x53, 0x4e, 0x0c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x43, 0x43, 0x04, 0x20, 0x20, 0x20, 0x20, 0x48, + 0x45, 0x04, 0x20, 0x20, 0x20, 0x20, 0x43, 0x54, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x48, 0x57, 0x02, 0x00, 0x01, 0x42, 0x33, 0x06, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x42, 0x34, 0x01, 0x20, 0x42, 0x37, 0x0c, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x46, + 0x01, 0x00, 0x78, 0x84, 0xa0, 0x00, 0x52, 0x54, 0x04, 0x56, 0x4d, 0x50, + 0x55, 0x56, 0x5a, 0x02, 0x30, 0x31, 0x53, 0x4f, 0x02, 0x00, 0x00, 0x44, + 0x49, 0x04, 0x00, 0x00, 0x00, 0x00, 0x49, 0x4e, 0x80, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x02, 0x00, 0x00, 0x78, 0x84, + 0x2c, 0x00, 0x52, 0x54, 0x04, 0x56, 0x53, 0x42, 0x50, 0x44, 0x52, 0x10, + 0x56, 0x50, 0x44, 0x20, 0x52, 0x4f, 0x4f, 0x54, 0x20, 0x4e, 0x4f, 0x44, + 0x45, 0x20, 0x20, 0x20, 0x50, 0x41, 0x01, 0x59, 0x49, 0x4d, 0x04, 0x70, + 0x00, 0x10, 0x00, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x78, 0x84, + 0x40, 0x01, 0x52, 0x54, 0x04, 0x56, 0x53, 0x59, 0x53, 0x44, 0x52, 0x06, + 0x53, 0x59, 0x53, 0x54, 0x45, 0x4d, 0x42, 0x52, 0x02, 0x20, 0x20, 0x53, + 0x45, 0x07, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x53, 0x47, 0x07, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x54, 0x4d, 0x08, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x54, 0x4e, 0x08, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x4d, 0x4e, 0x07, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x49, 0x44, 0x02, 0x20, 0x20, 0x53, 0x55, 0x06, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x4e, 0x4e, 0x10, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x52, 0x47, 0x04, 0x20, 0x20, 0x20, 0x20, 0x52, 0x42, 0x04, 0x20, 0x20, + 0x20, 0x20, 0x57, 0x4e, 0x0c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x46, 0x56, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x41, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x41, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x41, 0x4b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x41, 0x54, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x42, 0x4e, 0x40, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x42, 0x41, 0x01, 0x20, 0x4d, + 0x4d, 0x01, 0x20, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x78, 0x84, + 0xe4, 0x00, 0x52, 0x54, 0x04, 0x55, 0x54, 0x49, 0x4c, 0x44, 0x30, 0x01, + 0x00, 0x44, 0x31, 0x01, 0x00, 0x44, 0x32, 0x01, 0x00, 0x44, 0x33, 0x01, + 0x00, 0x44, 0x34, 0x04, 0x00, 0x00, 0x00, 0x00, 0x44, 0x35, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x44, 0x36, 0x04, 0x00, 0x00, 0x00, 0x00, 0x44, 0x37, + 0x04, 0x00, 0x00, 0x00, 0x00, 0x44, 0x38, 0x08, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x44, 0x39, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x46, 0x30, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x46, 0x31, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x46, 0x32, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x33, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, + 0x34, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x35, + 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x36, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x37, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x38, 0x10, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x46, 0x39, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x02, + 0x00, 0x00, 0x78, 0x84, 0x2c, 0x00, 0x52, 0x54, 0x04, 0x44, 0x49, 0x4e, + 0x46, 0x52, 0x49, 0x04, 0x00, 0x00, 0x00, 0x00, 0x46, 0x4c, 0x14, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x46, 0x04, 0x00, 0x00, + 0x00, 0x00, 0x78, 0x84, 0x44, 0x00, 0x52, 0x54, 0x04, 0x56, 0x43, 0x45, + 0x4e, 0x44, 0x52, 0x06, 0x43, 0x45, 0x43, 0x20, 0x20, 0x20, 0x53, 0x45, + 0x07, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x54, 0x4d, 0x08, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x46, 0x43, 0x08, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x52, 0x47, 0x04, 0x20, 0x20, 0x20, + 0x20, 0x52, 0x42, 0x04, 0x20, 0x20, 0x20, 0x20, 0x50, 0x46, 0x03, 0x00, + /* ECC area */ + 0x00, 0x00, 0x78, 0x4d, 0x5d, 0x84, 0x8c, 0x0a, 0xf9, 0xed, 0x3d, 0x96, + 0x11, 0x4a, 0x45, 0x9a, 0xb6, 0xb2, 0xd9, 0x19, 0x43, 0x05, 0x0f, 0xdd, + 0xb5, 0xf9, 0x3d, 0x5b, 0x81, 0xb3, 0x79, 0xcb, 0x19, 0x48, 0xbb, 0xa2, + 0x57, 0x10, 0x6e, 0x39, 0x38, 0x85, 0x5e, 0xa3, 0x24, 0xbc, 0x02, 0x63, + 0x6b, 0x79, 0xa3, 0x6b, 0xed, 0xcd, 0x27, 0x4e, 0x79, 0x9f, 0x76, 0x4e, + 0x7b, 0x93, 0x2d, 0xf4, 0x4c, 0x51, 0x0e, 0x28, 0x46, 0x43, 0x2b, 0xd9, + 0x1b, 0x21, 0x21, 0xc8, 0xe4, 0x6e, 0x9b, 0x4e, 0x34, 0x7e, 0x6e, 0x82, + 0x1b, 0x09, 0x13, 0xf1, 0x40, 0x7b, 0x9f, 0x6d, 0x50, 0x3e, 0x65, 0x31, + 0x1f, 0x19, 0x6f, 0x61, 0x78, 0x27, 0x72, 0x7c, 0x59, 0x34, 0x7c, 0x05, + 0x58, 0x13, 0x6f, 0x78, 0x13, 0x56, 0x33, 0x19, 0x1e, 0x79, 0x17, 0x41, + 0x28, 0x58, 0x6d, 0x26, 0x01, 0x34, 0x7d, 0x68, 0x1d, 0x7e, 0x1c, 0x42, + 0x49, 0x2a, 0x11, 0x7c, 0x70, 0x1a, 0x66, 0x47, 0x68, 0x6e, 0x3f, 0x5e, + 0x6b, 0x6d, 0x25, 0x7e, 0x3e, 0x24, 0x39, 0x07, 0x3c, 0x6e, 0x5b, 0x5d, + 0x4e, 0x59, 0x79, 0x7d, 0x6f, 0x5f, 0x7f, 0x5f, 0x4b, 0x5f, 0x6d, 0x3e, + 0x58, 0x57, 0x1b, 0x19, 0x5d, 0x14, 0x43, 0x83, 0xfc, 0xe6, 0x49, 0x84, + 0x41, 0x28, 0x0b, 0x0a, 0x00, 0x5b, 0xec, 0x46, 0x13, 0x4d, 0x00, 0xdc, + 0x89, 0xab, 0xbb, 0x77, 0x77, 0x7e, 0xee, 0xff, 0xfd, 0xdf, 0xff, 0xbb, + 0xbf, 0xff, 0x77, 0x7f, 0xfe, 0xee, 0xff, 0xfd, 0xdf, 0xff, 0xbb, 0xbf, + 0xfe, 0x76, 0x7e, 0xca, 0xc8, 0x99, 0x51, 0xd7, 0x70, 0x00, 0x03, 0x26, + 0x9e, 0x4e, 0x7f, 0x13, 0x38, 0xbb, 0x3c, 0xbb, 0x00, 0x02, 0xa0, 0x0a, + 0xcb, 0x70, 0xb7, 0x9f, 0x2b, 0x79, 0xa4, 0x00, 0x07, 0x71, 0xad, 0x17, + 0x41, 0xd7, 0xb9, 0x8c, 0x6d, 0x08, 0x2c, 0x80, 0x04, 0x56, 0x6b, 0x9f, + 0x00, 0x9f, 0xbe, 0xdb, 0x71, 0x63, 0x01, 0xb8, 0xf0, 0x41, 0xc0, 0xe1, + 0x8d, 0x3a, 0x6f, 0xc0, 0x66, 0x5f, 0xb6, 0x4c, 0x2a, 0x5f, 0x06, 0x00, + /* Rest is 0x00 */ +}; +static const size_t huygens_bmc_fruid_len =3D sizeof(huygens_bmc_fruid); + +/* chassis1 VPD: huygens_bmc_fruid with VCEN.FC patched to "2E4C-001" */ +#define HUYGENS_CHASSIS1_FC_OFFSET 0x048a +static const uint8_t huygens_chassis1_fc[] =3D { + 0x32, 0x45, 0x34, 0x43, 0x2d, 0x30, 0x30, 0x31 +}; + +static void huygens_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D bmc->soc; + + /* I2C0: BMC EEPROM */ + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 8 * KiB); + + /* I2C5: UCD90320 power sequencer */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ucd90320", = 0x11); + + /* I2C6: chassis1 backplane VPD EEPROM */ + { + g_autofree uint8_t *ch1 =3D g_malloc(huygens_bmc_fruid_len); + memcpy(ch1, huygens_bmc_fruid, huygens_bmc_fruid_len); + memcpy(ch1 + HUYGENS_CHASSIS1_FC_OFFSET, + huygens_chassis1_fc, sizeof(huygens_chassis1_fc)); + at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x50, + 8 * KiB, ch1, huygens_bmc_fruid_len); + } + + /* I2C8: System VPD at 0x53 */ + at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x53, + 4 * KiB, huygens_bmc_fruid, huygens_bmc_fruid_le= n); + /* LCD EEPROM */ + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 8 * KiB); + + /* I2C9: System VPD redundant and op-panel devices */ + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), + 0x53, 8 * KiB); /* SYSVPD-redundant */ + + /* TMP275 temperature sensor (compatible with TMP105) */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), + TYPE_TMP105, 0x48); + + /* Op-panel EEPROM */ + at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x51, 8 * KiB); + + /* PCA9552 LED controllers on bus 9 */ + aspeed_create_pca9552(soc, 9, 0x62); + aspeed_create_pca9552(soc, 9, 0x64); + aspeed_create_pca9552(soc, 9, 0x66); + + /* DPS310 pressure sensor */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "dps310", 0x= 76); +} + +static void aspeed_machine_huygens_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->alias =3D "ast2700-huygens"; + mc->desc =3D "Aspeed AST2700 A2 [IBM Huygens]"; + amc->soc_name =3D "ast2700-a2"; + amc->hw_strap1 =3D HUYGENS_BMC_HW_STRAP1; + amc->hw_strap2 =3D HUYGENS_BMC_HW_STRAP2; + amc->fmc_model =3D "w25q01jvq"; + amc->spi_model =3D "w25q512jv"; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; + amc->uart_default =3D ASPEED_DEV_UART12; + amc->i2c_init =3D huygens_bmc_i2c_init; + amc->vbootrom =3D true; + /* UFS LUN block size to match the OpenBMC image layout */ + amc->ufs_block_size =3D 512; + mc->default_ram_size =3D 2 * GiB; + aspeed_machine_class_init_cpus_defaults(mc); +} + +static const TypeInfo aspeed_ast27x0_huygens_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("huygens-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_huygens_class_init, + .interfaces =3D aarch64_machine_interfaces, + } +}; + +DEFINE_TYPES(aspeed_ast27x0_huygens_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 4233a800be..a237f1d04f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -75,6 +75,7 @@ arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: fil= es( 'aspeed_ast27x0-fc.c', 'aspeed_ast27x0-ssp.c', 'aspeed_ast27x0-tsp.c', + 'aspeed_ast27x0_huygens.c', 'aspeed_coprocessor_common.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) --=20 2.53.0