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Swap a1 and a2 at the four variable shift emitters. This covers the I32 and I64 forms of SHL, SHR, SAR, and ROTR. Cc: qemu-stable@nongnu.org Fixes: 03568c0d5395 ("tcg: Convert rotl, rotr to TCGOutOpBinary") Fixes: b5aafbaa8346 ("tcg: Convert sar to TCGOutOpBinary") Fixes: 27d21ee7c791 ("tcg: Convert shl to TCGOutOpBinary") Fixes: edd6ba8a6bc8 ("tcg: Convert shr to TCGOutOpBinary") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4103 Signed-off-by: Quintin Kong Signed-off-by: Richard Henderson Message-ID: --- tcg/mips/tcg-target.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 400eafbab4..29cf7fa0ab 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2049,7 +2049,7 @@ static void tgen_rotr(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { MIPSInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_ROTRV : OPC_DROTRV; - tcg_out_opc_reg(s, insn, a0, a1, a2); + tcg_out_opc_reg(s, insn, a0, a2, a1); } =20 static void tgen_rotri(TCGContext *s, TCGType type, @@ -2073,7 +2073,7 @@ static void tgen_sar(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { MIPSInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV; - tcg_out_opc_reg(s, insn, a0, a1, a2); + tcg_out_opc_reg(s, insn, a0, a2, a1); } =20 static void tgen_sari(TCGContext *s, TCGType type, @@ -2096,7 +2096,7 @@ static void tgen_shl(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { MIPSInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV; - tcg_out_opc_reg(s, insn, a0, a1, a2); + tcg_out_opc_reg(s, insn, a0, a2, a1); } =20 static void tgen_shli(TCGContext *s, TCGType type, @@ -2119,7 +2119,7 @@ static void tgen_shr(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) { MIPSInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV; - tcg_out_opc_reg(s, insn, a0, a1, a2); + tcg_out_opc_reg(s, insn, a0, a2, a1); } =20 static void tgen_shri(TCGContext *s, TCGType type, --=20 2.43.0 From nobody Mon Sep 28 02:08:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1785364105; cv=none; d=zohomail.com; s=zohoarc; b=F68zGF39vK/nDvTrquwvIdrd0W74F8Ns3KTDeN6MV2EYRiNauW2K6IDdvAWliLeHERLYqnETX9scT3Q+l+mit7y9ClRMpeB37MJa7b88MyXFBY/kUKgZpTZhnVJEHBRgbU3e6AsQLdoqxssrvf21SzOkctEup6yH3Yp0RIHV95I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785364105; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=x7llLYb5SiO/txOcB5U0TYVAXKt2eTpfMujF/WHT6VM=; b=mkeif+OiM/Rnh/hmgbFJxwkezmKLmPQ98nQ+CeBVgfVm4/k69d+Sko1xbokjTx2omWSHsx1PXT6+eRCDhh7+DDeV8szzxHpAh5mEX4fkQyorwLym3K3ytjOt+886RWZpj5Y/7uO4oET8pA3IsSCnQBKZX11njHC0h4u4A1z5KvE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1785364105568638.7985211950125; Wed, 29 Jul 2026 15:28:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wpCkb-0007ef-PS; Wed, 29 Jul 2026 18:27:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wpCka-0007eP-KC for qemu-devel@nongnu.org; Wed, 29 Jul 2026 18:27:44 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wpCkS-0008Mr-Fk for qemu-devel@nongnu.org; Wed, 29 Jul 2026 18:27:44 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2d01663d816so13709995ad.1 for ; Wed, 29 Jul 2026 15:27:36 -0700 (PDT) Received: from stoup.. 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That is valid for a direct load, but a pre-R6 MIPS host implements an unaligned 32-bit or 64-bit load with an LWR/LWL or LDR/LDL pair. Both instructions require the original base address. If lo and base overlap, the first instruction replaces the base with part of the loaded value. The second instruction then accesses an unrelated address. Prior to eb664d0c527, the address register was always a temporary, so this problem never occured. Copy an overlapping base to TCG_TMP0. Fixes: eb664d0c527 ("tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4102 Signed-off-by: Quintin Kong [rth: Move fixup into tcg_out_qemu_ld_unalign for qemu 10 series] Signed-off-by: Richard Henderson Message-ID: --- tcg/mips/tcg-target.c.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 29cf7fa0ab..a683bff625 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1338,9 +1338,9 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TC= GReg lo, TCGReg hi, const MIPSInsn ld1 =3D HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; const MIPSInsn ld2 =3D HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; bool sgn =3D opc & MO_SIGN; + MemOp size =3D opc & MO_SIZE; =20 - switch (opc & MO_SIZE) { - case MO_16: + if (size =3D=3D MO_16) { if (HOST_BIG_ENDIAN) { tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); @@ -1360,8 +1360,16 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, T= CGReg lo, TCGReg hi, tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); } - break; + return; + } =20 + /* Both loads in the unaligned pair require the original base. */ + if (lo =3D=3D base) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_TMP0, base); + base =3D TCG_TMP0; + } + + switch (size) { case MO_32: tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); --=20 2.43.0