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Mon, 27 Jul 2026 00:23:19 -0700 (PDT) From: Flavien Solt Date: Mon, 27 Jul 2026 15:22:57 +0800 Subject: [PATCH v4 1/3] hw/misc/iommu-testdev: support PCI MSI test writes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260727-qemu-mrif-v4-v4-1-73e0890ad395@gmail.com> References: <20260727-qemu-mrif-v4-v4-0-73e0890ad395@gmail.com> In-Reply-To: <20260727-qemu-mrif-v4-v4-0-73e0890ad395@gmail.com> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Andrew Jones , Tao Tang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Nutty Liu , Flavien Solt X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785136991; l=4023; i=flavien.solt97@gmail.com; s=qemu-mrif-v4-gmail; h=from:subject:message-id; bh=yIX+yizbuFr6xs+s2GSP1Z8I3zE1QKm9lbVXzs9EUOM=; b=qTtW8ZHvdx4oCwNTcaIg8WOdf+aUjrep/4ZeMYDANYsNFc3Qc5aJFh+ss8fDrDBQKOwckE/3x R/GXZoxUuTuChgnW52ut/S2caOsECkU3m+odM3cQUp/e103JA6UgozX X-Developer-Key: i=flavien.solt97@gmail.com; a=ed25519; pk=wEVvqF5SMWVnTyKNb8WAo78S30Q6giJmU/VisghJRtI= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=flavien.solt97@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785137067946158500 iommu-testdev writes ITD_DMA_WRITE_VAL with unspecified requester attributes. RISC-V MSI remapping tests need to select an interrupt identity in the payload. The MSI trap also identifies the device through MemTxAttrs.requester_id. Add a write-value register with the existing constant as its reset default. Populate the requester ID from the PCI function. Existing translation tests retain their payload while interrupt-remapping tests can issue a valid MSI for the test device. Signed-off-by: Flavien Solt Reviewed-by: Tao Tang Reviewed-by: Nutty Liu Acked-by: Alistair Francis --- hw/misc/iommu-testdev.c | 14 ++++++++++++-- include/hw/misc/iommu-testdev.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/hw/misc/iommu-testdev.c b/hw/misc/iommu-testdev.c index 15eb6de..6428a57 100644 --- a/hw/misc/iommu-testdev.c +++ b/hw/misc/iommu-testdev.c @@ -28,6 +28,7 @@ struct IOMMUTestDevState { uint64_t dma_paddr; uint32_t dma_len; uint32_t dma_result; + uint32_t dma_write_val; bool dma_armed; /* armed until a trigger consumes the request */ =20 AddressSpace *dma_as; /* IOMMU-mediated DMA AS for this device */ @@ -80,6 +81,7 @@ static void iommu_testdev_maybe_run_dma(IOMMUTestDevState= *s) =20 /* Initialize MemTxAttrs from generic register. */ attrs.secure =3D ITD_ATTRS_GET_SECURE(s->dma_attrs_cfg); + attrs.requester_id =3D pci_requester_id(&s->parent_obj); =20 space_valid =3D ITD_ATTRS_GET_SPACE_VALID(s->dma_attrs_cfg); if (space_valid) { @@ -97,12 +99,12 @@ static void iommu_testdev_maybe_run_dma(IOMMUTestDevSta= te *s) =20 as =3D s->dma_as; =20 - /* Step 1: Write ITD_DMA_WRITE_VAL to DMA address */ + /* Step 1: Write the configured test value to DMA address */ trace_iommu_testdev_dma_write(s->dma_vaddr, s->dma_len); =20 for (int i =3D 0; i < s->dma_len; i++) { /* Data is written in little-endian order */ - write_buf[i] =3D (ITD_DMA_WRITE_VAL >> ((i % 4) * 8)) & 0xff; + write_buf[i] =3D (s->dma_write_val >> ((i % 4) * 8)) & 0xff; } write_res =3D dma_memory_write(as, s->dma_vaddr, write_buf, s->dma_len, attrs); @@ -186,6 +188,9 @@ static uint64_t iommu_testdev_mmio_read(void *opaque, h= waddr addr, case ITD_REG_DMA_ATTRS: value =3D s->dma_attrs_cfg; break; + case ITD_REG_DMA_WRITE_VAL: + value =3D s->dma_write_val; + break; default: value =3D 0; break; @@ -240,6 +245,9 @@ static void iommu_testdev_mmio_write(void *opaque, hwad= dr addr, uint64_t val, case ITD_REG_DMA_ATTRS: s->dma_attrs_cfg =3D data; break; + case ITD_REG_DMA_WRITE_VAL: + s->dma_write_val =3D data; + break; default: break; } @@ -263,6 +271,7 @@ static void iommu_testdev_realize(PCIDevice *pdev, Erro= r **errp) s->dma_paddr =3D 0; s->dma_len =3D 0; s->dma_result =3D ITD_DMA_RESULT_IDLE; + s->dma_write_val =3D ITD_DMA_WRITE_VAL; s->dma_armed =3D false; s->dma_attrs_cfg =3D ITD_ATTRS_SET_SPACE(0, ITD_ATTRS_SPACE_NONSECURE); s->dma_as =3D pci_device_iommu_address_space(pdev); @@ -280,6 +289,7 @@ static void iommu_testdev_reset(DeviceState *dev) s->dma_paddr =3D 0; s->dma_len =3D 0; s->dma_result =3D ITD_DMA_RESULT_IDLE; + s->dma_write_val =3D ITD_DMA_WRITE_VAL; s->dma_armed =3D false; s->dma_attrs_cfg =3D ITD_ATTRS_SET_SPACE(0, ITD_ATTRS_SPACE_NONSECURE); } diff --git a/include/hw/misc/iommu-testdev.h b/include/hw/misc/iommu-testde= v.h index 3383659..2f4e931 100644 --- a/include/hw/misc/iommu-testdev.h +++ b/include/hw/misc/iommu-testdev.h @@ -81,6 +81,7 @@ enum { ITD_REG_DMA_ATTRS =3D 0x18, ITD_REG_DMA_GPA_LO =3D 0x1c, ITD_REG_DMA_GPA_HI =3D 0x20, + ITD_REG_DMA_WRITE_VAL =3D 0x24, BAR0_SIZE =3D 0x1000, }; =20 --=20 2.54.0 From nobody Mon Sep 28 02:07:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 27 Jul 2026 00:23:23 -0700 (PDT) From: Flavien Solt Date: Mon, 27 Jul 2026 15:22:58 +0800 Subject: [PATCH v4 2/3] hw/riscv/riscv-iommu.c: always send MRIF notice MSI MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260727-qemu-mrif-v4-v4-2-73e0890ad395@gmail.com> References: <20260727-qemu-mrif-v4-v4-0-73e0890ad395@gmail.com> In-Reply-To: <20260727-qemu-mrif-v4-v4-0-73e0890ad395@gmail.com> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Andrew Jones , Tao Tang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Nutty Liu , Flavien Solt , qemu-stable@nongnu.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785136991; l=1860; i=flavien.solt97@gmail.com; s=qemu-mrif-v4-gmail; h=from:subject:message-id; bh=AyhDitwqEMTLhlxlyQPXe6ylATgJ9+x3GdqYluglOUU=; b=4Ok61yc4C5AdfW6amsyCzxZweTU7B+B3UNZTbZYBxs2/L/yAQ8ctCgjRRgrQu6KHSvo8SN9bo EuVmKzjdZRTC30+dLE8x6Vkxp+dEYaiv1EcKIFw2uRX34SvvC5LxZOv X-Developer-Key: i=flavien.solt97@gmail.com; a=ed25519; pk=wEVvqF5SMWVnTyKNb8WAo78S30Q6giJmU/VisghJRtI= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=flavien.solt97@gmail.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785137082070158500 The AIA specification requires an IOMMU to send the configured notice MSI after storing an MSI to an MRIF, even when the corresponding interrupt-enable bit is clear. riscv_iommu_msi_write() currently reads the MRIF interrupt-enable doubleword and suppresses the notice MSI when the matching bit is zero. This makes notice delivery depend on a bit that AIA requires the IOMMU to ignore. Remove the enable-word read and send the notice MSI unconditionally after updating the MRIF pending bit. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Cc: qemu-stable@nongnu.org Reviewed-by: Andrew Jones Signed-off-by: Flavien Solt Reviewed-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Chao Liu Tested-by: Chao Liu --- hw/riscv/riscv-iommu.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index f6865d1..2bbac30 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -788,19 +788,6 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUSta= te *s, goto err; } =20 - /* Get MRIF enable bits */ - addr =3D addr + sizeof(intn); - res =3D dma_memory_read(s->target_as, addr, &intn, sizeof(intn), attrs= ); - if (res !=3D MEMTX_OK) { - cause =3D RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT; - goto err; - } - - if (!(intn & data)) { - /* notification disabled, MRIF update completed. */ - return MEMTX_OK; - } - /* Send notification message */ addr =3D PPN_PHYS(get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NPPN)); 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Mon, 27 Jul 2026 00:23:27 -0700 (PDT) From: Flavien Solt Date: Mon, 27 Jul 2026 15:22:59 +0800 Subject: [PATCH v4 3/3] tests/qtest: add RISC-V IOMMU MRIF notice tests MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260727-qemu-mrif-v4-v4-3-73e0890ad395@gmail.com> References: <20260727-qemu-mrif-v4-v4-0-73e0890ad395@gmail.com> In-Reply-To: <20260727-qemu-mrif-v4-v4-0-73e0890ad395@gmail.com> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Andrew Jones , Tao Tang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Nutty Liu , Flavien Solt X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785136991; l=5610; i=flavien.solt97@gmail.com; s=qemu-mrif-v4-gmail; h=from:subject:message-id; bh=4t7hBi12kQx0si3QEEq84Twv7XWE8/6T8sOjpFerZr0=; b=wzoZ0OFvX/7Vog8nEJRorFelzPdlMMrBL/w2dJX6yd+snee10vYgveoeDDoZyFnddoEx9irc8 vRRmXyb7ZXFCskMCjL4+W5pry8Jf4PNOA2KuenvUxX+1UdCfwXlTXW0 X-Developer-Key: i=flavien.solt97@gmail.com; a=ed25519; pk=wEVvqF5SMWVnTyKNb8WAo78S30Q6giJmU/VisghJRtI= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=flavien.solt97@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785137066355158500 Exercise MRIF-mode MSI writes through iommu-testdev with the destination interrupt-enable bit both clear and set. Each case requires the pending bit to be stored plus the configured notice ID to reach guest memory. The enable-clear case regresses the notice suppression fixed by the previous patch. The enable-set case provides a control for the existing path. Signed-off-by: Flavien Solt Reviewed-by: Chao Liu --- tests/qtest/iommu-riscv-test.c | 102 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 102 insertions(+) diff --git a/tests/qtest/iommu-riscv-test.c b/tests/qtest/iommu-riscv-test.c index 2638024..85f79ea 100644 --- a/tests/qtest/iommu-riscv-test.c +++ b/tests/qtest/iommu-riscv-test.c @@ -14,6 +14,7 @@ #include "hw/pci/pci_regs.h" #include "hw/misc/iommu-testdev.h" #include "hw/riscv/riscv-iommu-bits.h" +#include "libqos/qos-iommu-testdev.h" #include "libqos/qos-riscv-iommu.h" #include "libqos/riscv-iommu.h" =20 @@ -26,6 +27,13 @@ #define RISCV_BUS_MMIO_LIMIT 0x80000000 #define RISCV_ECAM_ALLOC_PTR 0x30000000 =20 +#define RISCV_MRIF_MSI_IOVA 0x00000000fee00000ull +#define RISCV_MRIF_MSI_PT_GPA (QRIOMMU_SPACE_OFFS + 0x00030000ull) +#define RISCV_MRIF_BASE_GPA (QRIOMMU_SPACE_OFFS + 0x00031000ull) +#define RISCV_MRIF_NOTICE_GPA (QRIOMMU_SPACE_OFFS + 0x00032000ull) +#define RISCV_MRIF_INTID 5u +#define RISCV_MRIF_NOTICE_ID 0x12du + typedef struct RiscvIommuTestState { QTestState *qts; QGenericPCIBus gbus; @@ -264,6 +272,96 @@ static void test_riscv_iommu_nested(void) run_riscv_iommu_translation(&cfg); } =20 +static void riscv_iommu_setup_mrif_context(RiscvIommuTestState *state) +{ + uint64_t dc_addr; + uint64_t msiptp; + uint64_t pte0; + uint64_t pte1; + + qtest_memset(state->qts, QRIOMMU_SPACE_OFFS + QRIOMMU_DDT_BASE, 0, + 0x1000); + qtest_memset(state->qts, RISCV_MRIF_MSI_PT_GPA, 0, 0x1000); + qtest_memset(state->qts, RISCV_MRIF_BASE_GPA, 0, 0x1000); + qtest_memset(state->qts, RISCV_MRIF_NOTICE_GPA, 0, 4); + + dc_addr =3D QRIOMMU_SPACE_OFFS + QRIOMMU_DDT_BASE + + state->testdev->devfn * sizeof(struct riscv_iommu_dc); + + msiptp =3D (RISCV_MRIF_MSI_PT_GPA >> 12) | + ((uint64_t)RISCV_IOMMU_DC_MSIPTP_MODE_FLAT << 60); + + qtest_writeq(state->qts, dc_addr + 0, RISCV_IOMMU_DC_TC_V); + qtest_writeq(state->qts, dc_addr + 8, 0); + qtest_writeq(state->qts, dc_addr + 16, 0); + qtest_writeq(state->qts, dc_addr + 24, 0); + qtest_writeq(state->qts, dc_addr + 32, msiptp); + qtest_writeq(state->qts, dc_addr + 40, 0); + qtest_writeq(state->qts, dc_addr + 48, RISCV_MRIF_MSI_IOVA >> 12); + qtest_writeq(state->qts, dc_addr + 56, 0); + + pte0 =3D RISCV_IOMMU_MSI_PTE_V | + ((uint64_t)RISCV_IOMMU_MSI_PTE_M_MRIF << 1) | + ((RISCV_MRIF_BASE_GPA >> 9) << 7); + pte1 =3D ((RISCV_MRIF_NOTICE_GPA >> 12) << 10) | RISCV_MRIF_NOTICE_ID; + + qtest_writeq(state->qts, RISCV_MRIF_MSI_PT_GPA, pte0); + qtest_writeq(state->qts, RISCV_MRIF_MSI_PT_GPA + 8, pte1); + + qriommu_program_regs(state->qts, state->iommu_base); +} + +static void run_riscv_iommu_mrif_notice(bool enable_bit) +{ + RiscvIommuTestState state =3D { 0 }; + uint64_t pending; + uint64_t enabled; + uint32_t notice; + uint32_t dma_result; + + if (!riscv_iommu_test_setup(&state)) { + return; + } + + riscv_iommu_check(state.qts, state.iommu_base, QRIOMMU_TM_BARE); + riscv_iommu_setup_mrif_context(&state); + + enabled =3D enable_bit ? (1ull << RISCV_MRIF_INTID) : 0; + qtest_writeq(state.qts, RISCV_MRIF_BASE_GPA + 8, enabled); + qpci_io_writel(state.testdev, state.testdev_bar, ITD_REG_DMA_WRITE_VAL, + RISCV_MRIF_INTID); + + dma_result =3D qos_iommu_testdev_trigger_dma( + state.testdev, state.testdev_bar, RISCV_MRIF_MSI_IOVA, + RISCV_MRIF_NOTICE_GPA, DMA_LEN, qriommu_build_dma_attrs()); + + pending =3D qtest_readq(state.qts, RISCV_MRIF_BASE_GPA); + notice =3D qtest_readl(state.qts, RISCV_MRIF_NOTICE_GPA); + + g_test_message("MRIF notice: enable=3D%u pending=3D0x%" PRIx64 + " notice=3D0x%x", enable_bit, pending, notice); + + /* + * Interrupt remapping consumes the original DMA write; the generic + * test device cannot read it back from the supplied physical address. + */ + g_assert_cmpuint(dma_result, =3D=3D, ITD_DMA_ERR_MISMATCH); + g_assert_cmpuint(pending & (1ull << RISCV_MRIF_INTID), !=3D, 0); + g_assert_cmpuint(notice, =3D=3D, RISCV_MRIF_NOTICE_ID); + + riscv_iommu_test_teardown(&state); +} + +static void test_riscv_iommu_mrif_notice_enable_clear(void) +{ + run_riscv_iommu_mrif_notice(false); +} + +static void test_riscv_iommu_mrif_notice_enable_set(void) +{ + run_riscv_iommu_mrif_notice(true); +} + int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); @@ -275,5 +373,9 @@ int main(int argc, char **argv) test_riscv_iommu_g_stage_only); qtest_add_func("/iommu-testdev/translation/ns-nested", test_riscv_iommu_nested); + qtest_add_func("/iommu-testdev/mrif-notice/enable-clear", + test_riscv_iommu_mrif_notice_enable_clear); + qtest_add_func("/iommu-testdev/mrif-notice/enable-set", + test_riscv_iommu_mrif_notice_enable_set); return g_test_run(); } --=20 2.54.0