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Thu, 23 Jul 2026 09:43:59 -0700 (PDT) From: Simon Xu To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Simon Xu Subject: [PATCH] hw/misc/mps2-scc.c: fix scc_partno() and cfg7 write Date: Thu, 23 Jul 2026 11:43:57 -0500 Message-Id: <20260723164357.1462-1-simonxhy0404@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=simonxhy0404@gmail.com; helo=mail-oo1-xc29.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1784825079029158500 Content-Type: text/plain; charset="utf-8" Increase the extract32 length from 8 to 12. The Primary part number is defined as bits[15:4] by the "SSE-310 with M85 and U55 FPGA" documentation. For example for the mps3-an547, 0x547 is 12 bits but we only return 8 bits right now. Change the CFG7 write function to modify the correct variable. Signed-off-by: Simon Xu --- hw/misc/mps2-scc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 7877b31479..554b504c72 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -57,7 +57,7 @@ REG32(ID, 0xFFC) static int scc_partno(MPS2SCC *s) { /* Return the partno field of the SCC_ID (0x524, 0x511, etc) */ - return extract32(s->id, 4, 8); + return extract32(s->id, 4, 12); } =20 /* Is CFG_REG2 present? */ @@ -299,7 +299,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset,= uint64_t value, goto bad_offset; } /* AN536: Core 1 vector table base address */ - s->cfg6 =3D value; + s->cfg7 =3D value; break; case A_CFGDATA_OUT: s->cfgdata_out =3D value; --=20 2.34.1