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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1784721910; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=AXzOszz6KSfOvpcQSu0jqwTTH5w9E3i3/Q0a4AONinE=; b=cGGbt49tbTe3DGGKSdoTZRt2AbwN4rtWIAXsp4UXVqWDiSqQsCoxckaxKTE52U3RhsZEbG mgzse+vmFw5vD9ZtkMdiqnCJ14gUoYcp2Ak174weOPvAM1ALM376TUFeirXNTSHga+vmR9 0Ous/slruwL6BkMpMdjT5M3lSu+1oD4= X-MC-Unique: Kl2729egNIOkuj4obT80aw-1 X-Mimecast-MFC-AGG-ID: Kl2729egNIOkuj4obT80aw_1784721908 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Marcelo Tosatti , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH] target/i386/kvm: Fix UBSAN shift error in MTRR mask computation Date: Wed, 22 Jul 2026 14:04:37 +0200 Message-ID: <20260722120437.697986-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: permerror client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1784721989081158501 On AMD EPYC processors, raw CPUID leaf 0x80000008 reports 52 physical address bits. When a machine type such as microvm forces host_phys_bits=3Dtrue, the CPU ends up with phys_bits=3D52, causing MAKE_64BIT_MASK(52, 0) to shift by 64 =E2=80=94 which is undefined behavior. Fix by only computing the mask when phys_bits < 52. Fixes: fcc35e7ccaed ("target-i386: Fill high bits of mtrr mask") Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/kvm/kvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 4272b6770c7c9e3907a8f4de2c3234378f16482e..6dd314c90748e49b1ff27933b20= 8dc552dd58906 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -5064,8 +5064,7 @@ static int kvm_get_msrs(X86CPU *cpu) * we're migrating to. */ =20 - if (cpu->fill_mtrr_mask) { - assert(cpu->phys_bits <=3D 52); + if (cpu->fill_mtrr_mask && cpu->phys_bits < 52) { mtrr_top_bits =3D MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_b= its); } else { mtrr_top_bits =3D 0; --=20 2.55.0