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b=InDrFhhdkwsFUv/hFxhLrw31nhI3czpy9vRHcjlI6N2KW7O5GNrYFQvd95I0Am3+q4J2xxvUrXFI5NTpXHVysaoRWZbignVxM2gyDrxNQE2Vz/SYlx0H0z17KA2SSDaet8URWesAJJnOnX5WU40ItmkFd1p+m/raMxT9/FmFpmtecXrta6PsEVogatoSS2Q5kU8Biz7WhYRM7tcbTMWdtEDHSLpKVY6KoxgJnmh+CsXcpmm8EL8SuXDq9ChTU+i97A9ZvnybN1Bp+gmHnBK4+2Ii+Fs9fFHq+BmWJYu4Y1en0Gx7umLpQwQ0u3sEiQi2SQVPDhxsPYMgow/Yj6uHeA== From: Joel Bueno To: "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" CC: "richard.henderson@linaro.org" , "pbonzini@redhat.com" , "palmer@dabbelt.com" , "alistair.francis@wdc.com" , "liwei1518@gmail.com" , "daniel.barboza@oss.qualcomm.com" , "zhiwei_liu@linux.alibaba.com" , "chao.liu.zevorn@gmail.com" , Joel Bueno Subject: [PATCH v2] tcg/riscv: raise VLEN limit to the specification's maximum Thread-Topic: [PATCH v2] tcg/riscv: raise VLEN limit to the specification's maximum Thread-Index: AQHdFdBbI/5EsFyGHUubwwFAkANbPA== Date: Fri, 17 Jul 2026 09:40:53 +0000 Message-ID: <20260717094046.1600827-1-joel.bueno@openchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=openchip.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c207::3; envelope-from=joel.bueno@openchip.com; helo=MRWPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @openchip.com) X-ZM-MESSAGEID: 1784281295674158500 Content-Type: text/plain; charset="utf-8" The RISC-V V(ector) extension specification allows VLEN up to 65536 bits (vlenb =3D 8192 bytes). 3 changes are needed to support this: 1. Widen simd_desc SIMD_MAXSZ_BITS from 8 to 10, raising the maxsz encoding limit from 2048 to 8200 bytes. This costs 2 data bits (22 to 20). 2. Raise RV_VLEN_MAX from 1024 to 65536. This increases the static per-CPU vector register file from 4 KB to 256 KB. 3. Widen the vlen CPU property from uint16 to uint32 so that vlen=3D65536 can be specified on the command line. To ensure TCG emits instructions correctly, we, clamp the vl_eq_vlmax TB fl= ag so it is never set when the total register group size (vlmax << vsew) exceeds the simd_desc maxsz limit. This forces the helper-based path for very large register groups (e.g., VLEN=3D32768 with LMUL=3D4), preventing t= he GVEC fast path from silently truncating the operation and zeroing tail registers. We also need to fix probe_pages() so that vector ld/st works due to larger vector register sizes in regards of how many memory pages they span. This enables larger memory operations to succeed since address calculations can now properly span more than 2 pages. To finish off, we add an additional check on trans_rvv.c.inc to properly decide when to use the helper function or not; this ensures that we never hit: ./build/qemu-riscv64: ../accel/tcg/translate-all.c:356: tb_gen_code: Assert= ion `max_insns > 1' failed; On high VLEN configurations due to the amount of ld/st it generates (Where = TCG tries to halve the amount of emitted instructions so the generated machine = code fits on the buffer but fails to do so when a single vector load/store opcod= e fills the entire buffer (Or overruns it...!). Signed-off-by: joel.bueno --- * Fix vext_ldst_us emitter. Wasn't able to trigger the wrong functionality = from within qemu-user but qemu-system with 16k VLEN crashed when context switchi= ng. include/tcg/tcg-gvec-desc.h | 7 ++++-- target/riscv/cpu.c | 12 +++++----- target/riscv/cpu.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/tcg/tcg-cpu.c | 4 +++- target/riscv/vector_helper.c | 30 ++++++++++++++++--------- 6 files changed, 36 insertions(+), 22 deletions(-) diff --git a/include/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h index 704bd86454..6c277fedad 100644 --- a/include/tcg/tcg-gvec-desc.h +++ b/include/tcg/tcg-gvec-desc.h @@ -21,7 +21,7 @@ #define TCG_TCG_GVEC_DESC_H =20 /* - * This configuration allows MAXSZ to represent 2048 bytes, and + * This configuration allows MAXSZ to represent up to 8200 bytes, and * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32. * * Encode this with: @@ -29,9 +29,12 @@ * 2 -> maxsz * * This steals the input that would otherwise map to 24 to match maxsz. + * + * MAXSZ uses 10 bits to support RISC-V VLEN up to 65536 bits + * (vlenb =3D 8192 bytes). This leaves 20 DATA bits (was 22). */ #define SIMD_MAXSZ_SHIFT 0 -#define SIMD_MAXSZ_BITS 8 +#define SIMD_MAXSZ_BITS 10 =20 #define SIMD_OPRSZ_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS) #define SIMD_OPRSZ_BITS 2 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fa497e5e8a..b5c2139810 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1637,10 +1637,10 @@ static void prop_vlen_set(Object *obj, Visitor *v, = const char *name, void *opaque, Error **errp) { RISCVCPU *cpu =3D RISCV_CPU(obj); - uint16_t cpu_vlen =3D cpu->cfg.vlenb << 3; - uint16_t value; + uint32_t cpu_vlen =3D cpu->cfg.vlenb << 3; + uint32_t value; =20 - if (!visit_type_uint16(v, name, &value, errp)) { + if (!visit_type_uint32(v, name, &value, errp)) { return; } =20 @@ -1663,13 +1663,13 @@ static void prop_vlen_set(Object *obj, Visitor *v, = const char *name, static void prop_vlen_get(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - uint16_t value =3D RISCV_CPU(obj)->cfg.vlenb << 3; + uint32_t value =3D RISCV_CPU(obj)->cfg.vlenb << 3; =20 - visit_type_uint16(v, name, &value, errp); + visit_type_uint32(v, name, &value, errp); } =20 static const PropertyInfo prop_vlen =3D { - .type =3D "uint16", + .type =3D "uint32", .description =3D "vlen", .get =3D prop_vlen_get, .set =3D prop_vlen_set, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7582874c35..5796aaf04b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -186,7 +186,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied= _rules[]; #include "pmp.h" #endif =20 -#define RV_VLEN_MAX 1024 +#define RV_VLEN_MAX 65536 #define RV_MAX_MHPMEVENTS 32 #define RV_MAX_MHPMCOUNTERS 32 #define RV_MAX_TRIGGERS 2 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 23262b1d03..f34fea3407 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1190,9 +1190,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t r= s1, uint32_t nf, * Update vstart with the number of processed elements. * Use the helper function if either: * - vstart is not 0. + * - total transfer size potentially exceeding emittable buffer length. */ =20 - bool use_helper_fn =3D !s->vstart_eq_zero; + bool use_helper_fn =3D !s->vstart_eq_zero || ((s->cfg_ptr->vlenb * nf)= > 512); =20 if (!use_helper_fn) { uint32_t size =3D s->cfg_ptr->vlenb * nf; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b73e3e9dd4..021f9c60bd 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -33,6 +33,7 @@ #include "accel/accel-cpu-target.h" #include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" +#include "tcg/tcg-gvec-desc.h" #ifndef CONFIG_USER_ONLY #include "hw/core/boards.h" #include "system/tcg.h" @@ -125,7 +126,8 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); uint32_t maxsz =3D vlmax << vsew; bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && - (maxsz >=3D 8); + (maxsz >=3D 8) && + (maxsz <=3D (8 << SIMD_MAXSZ_BITS)); flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vsew); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e321ca2616..1254a7b9c4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -176,13 +176,15 @@ static void probe_pages(CPURISCVState *env, target_ul= ong addr, target_ulong len, mmu_index, ra); } =20 - if (len > curlen) { + while (len > curlen) { addr +=3D curlen; - curlen =3D len - curlen; + len -=3D curlen; + curlen =3D MIN(-(addr | TARGET_PAGE_MASK), len); if (flags !=3D NULL) { + void *page_host; *flags |=3D probe_access_flags(env, adjust_addr(env, addr), cu= rlen, access_type, mmu_index, nonfault, - host, ra); + &page_host, ra); } else { probe_access(env, adjust_addr(env, addr), curlen, access_type, mmu_index, ra); @@ -480,8 +482,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, } =20 /* Load/store elements in the second page */ - if (unlikely(env->vstart < evl)) { - /* Cross page element */ + while (unlikely(env->vstart < evl)) { + /* Element crossing the page boundary */ if (unlikely(page_split % msize)) { for (k =3D 0; k < nf; k++) { addr =3D base + ((env->vstart * nf + k) << log2_esz); @@ -489,15 +491,21 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVSta= te *env, uint32_t desc, env->vstart + k * max_elems, vd, ra); } env->vstart++; + if (env->vstart >=3D evl) { + break; + } } =20 addr =3D base + ((env->vstart * nf) << log2_esz); - /* Get number of elements of second page */ - elems =3D evl - env->vstart; - - /* Load/store elements in the second page */ - vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, log2_esz, - is_load, mmu_index, ldst_tlb, ldst_host, ra); + page_split =3D -(addr | TARGET_PAGE_MASK); + elems =3D page_split / msize; + if (env->vstart + elems >=3D evl) { + elems =3D evl - env->vstart; + } + if (likely(elems)) { + vext_page_ldst_us(env, vd, addr, elems, nf, max_elems, log2_es= z, + is_load, mmu_index, ldst_tlb, ldst_host, ra); + } } =20 env->vstart =3D 0; --=20 2.43.0