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Thu, 16 Jul 2026 12:15:59 -0700 (PDT) X-Received: by 2002:a05:6a21:a393:b0:3b2:8674:9830 with SMTP id adf61e73a8af0-3c38d90d347mr4729447637.14.1784229359099; Thu, 16 Jul 2026 12:15:59 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Brian Cain , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Pierrick Bouvier Subject: [PATCH v2 1/3] target/hexagon: initialize deferred sreg-write temps to current value Date: Thu, 16 Jul 2026 12:15:53 -0700 Message-Id: <20260716191555.3397687-2-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260716191555.3397687-1-brian.cain@oss.qualcomm.com> References: <20260716191555.3397687-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=IMIyzAvG c=1 sm=1 tr=0 ts=6a592df0 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=IlOZXNdbeIrMSDKviAkA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE2MDE5NyBTYWx0ZWRfX/PmmGGwHBHDd IBt4Z5JugCuHZEJqjKafzmWpry18NQ5OJh69zzr5/xyw/UKKaEM+VmSd1MuFiHyuROlHS7ZdBmj Nr5XLKb6hAEMGS1Fy0A81RPM7gQRuVdoNyRQ3vU3RPBReNEOFpurJZAPusTecNCfRyEW/h5K1u3 zpRt31YFhsrxy6YyRXwZdH706mJif3y367Q5sWL+ggx8yRU3IYNnYcBpJDhqKelXIW/bH198vtP surhHMWCAajkQ4LLb7hudifPX+EA80YSZiTFxll4GqFLjpvz1Rs+5e2xkLGmhhFWwrCurn0UzEE 6+MS++uwifOrWhvEC6/+nRyRGhSDfbdUzLHorsYigBuSreEkGDftphEPGEBWuhKB4r7WMNb4Ryu BS7HjommkAILVLQDR+VrCaH3rl3rnXfvlc0c7/DYUa/XeujBecw0367jMmAAbwWbbk08gHGjj2M 2P75kW89BI/a5RYyQPQ== X-Proofpoint-GUID: BcX6O23lCedpOww_2UNwFnr_BNOCl2bF X-Proofpoint-ORIG-GUID: BcX6O23lCedpOww_2UNwFnr_BNOCl2bF X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE2MDE5NyBTYWx0ZWRfX/A+4bCKzZ4v8 6UrRD2kjpks/ziYS02ZjQTfOTe7cTQLbb1GylDJe3CRQ9pN2tM8dZ65nD0VkJoA65DghAalkAWJ IVRl+TD7xEl+OvC1p4VpwLU02kI49H0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-16_06,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607160197 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784229413056158500 Unconditionally allocate and initialize the temp to the sreg's current value for every logged sreg write, rather than only allocating when need_commit is set or the register is SSR. Without this, reading a deferred sreg write within the same packet before it is committed can observe an uninitialized temp instead of the register's pre-packet value. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 77235916f4b..28a171bf623 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -615,9 +615,10 @@ static void gen_start_packet(DisasContext *ctx) } for (i =3D 0; i < ctx->sreg_log_idx; i++) { int reg_num =3D ctx->sreg_log[i]; - if (reg_num < HEX_SREG_GLB_START && - (ctx->need_commit || reg_num =3D=3D HEX_SREG_SSR)) { + if (reg_num < HEX_SREG_GLB_START) { ctx->t_sreg_new_value[reg_num] =3D tcg_temp_new(); + tcg_gen_mov_tl(ctx->t_sreg_new_value[reg_num], + hex_t_sreg[reg_num]); } } for (i =3D 0; i < NUM_GREGS; i++) { --=20 2.34.1 From nobody Mon Jul 27 20:02:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784229398; cv=none; d=zohomail.com; s=zohoarc; b=DK+B3uQ5qRQLKHeI4uV2G0HqIrLMMJaTgesKyX7Kq7T4Y7Bb2FGCBlU92fsp1A8smxxF7mrNlec2chg09TSJKeIz7JTlUB6jefQ6ujENXfCjn4xnFnRwRcnaLqh7qVvsaOSdaJzaXBWbSGdiyJqrl2/dM4y4jEQ2TlcabGtJ5rE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784229398; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=v9TEZ/r+WdyXkCh0jPLt6TPCbm8hNKa/SZ+tY3PO/BU=; b=TMq44OZc3QOehtPu0hJWoutH9X1fX+qFYf5kmXE4Ue1yxXTJMgkIU9GYFqcb3kcOXB7f9FY0jkS7d3WVBYgqSzBkoqdVMHzdBxIa7GeNONePP9/GXo+G8qSGYoGsu/AlMO359SDinPD06OMSvBQ4sgbmHy0LwPT1WdhiqW0y1MI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784229398479983.2196858052629; Thu, 16 Jul 2026 12:16:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wkRZ2-0008Cg-RM; Thu, 16 Jul 2026 15:16:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wkRZ0-0008Ak-Tw for qemu-devel@nongnu.org; Thu, 16 Jul 2026 15:16:06 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wkRYz-0002xn-1S for qemu-devel@nongnu.org; Thu, 16 Jul 2026 15:16:06 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66GHZfpB3544468 for ; Thu, 16 Jul 2026 19:16:03 GMT Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ff3u80cn2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 16 Jul 2026 19:16:03 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-c9d5a5b63c5so10495269a12.1 for ; Thu, 16 Jul 2026 12:16:03 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784229399238158500 Add hex_next_PC, a global mirroring CPUHexagonState::next_PC, and ctx->need_next_pc, so that gen_write_new_pc_addr() can write the branch target through hex_next_PC instead of hex_gpr[HEX_REG_PC] when a later unconditional write of PC is expected. gen_end_tb() then commits hex_next_PC into hex_gpr[HEX_REG_PC] at the end of the packet. Previously, non-COF instructions that still end a TB did not advance the PC, since next_PC's value was never written back into the PC register. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/translate.h | 3 +++ target/hexagon/genptr.c | 14 ++++++++--- target/hexagon/translate.c | 51 ++++++++++++++++++++++++++------------ 3 files changed, 49 insertions(+), 19 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 0a7f37d5842..2fca157553b 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -40,6 +40,7 @@ typedef struct DisasContext { int reg_log_idx; DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS); + bool pkt_ends_tb; bool implicit_usr_write; #ifndef CONFIG_USER_ONLY int greg_log[GREG_WRITES_MAX]; @@ -75,6 +76,7 @@ typedef struct DisasContext { DECLARE_BITMAP(insn_qregs_read, NUM_QREGS); bool pre_commit; bool need_commit; + bool need_next_pc; TCGCond branch_cond; target_ulong branch_dest; bool is_tight_loop; @@ -310,6 +312,7 @@ extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; extern TCGv hex_pred[NUM_PREGS]; extern TCGv hex_slot_cancelled; extern TCGv hex_new_value_usr; +extern TCGv hex_next_PC; extern TCGv hex_store_addr[STORES_MAX]; extern TCGv_i32 hex_store_width[STORES_MAX]; extern TCGv hex_store_val32[STORES_MAX]; diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 1ebc7471409..dc9ba8a0060 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -613,14 +613,22 @@ static void gen_write_new_pc_addr(DisasContext *ctx, = TCGv addr, tcg_gen_brcondi_tl(cond, pred, 1, pred_false); } =20 + /* + * If gen_end_tb() will unconditionally overwrite PC with hex_next_PC + * (because this packet has a predicated COF that may not execute), + * write the branch target there instead of directly into the PC + * global, or the overwrite in gen_end_tb() would clobber it. + */ + TCGv pc_wr =3D ctx->need_next_pc ? hex_next_PC : hex_gpr[HEX_REG_PC]; + if (ctx->pkt.pkt_has_multi_cof) { /* If there are multiple branches in a packet, ignore the second o= ne */ - tcg_gen_movcond_tl(TCG_COND_NE, hex_gpr[HEX_REG_PC], + tcg_gen_movcond_tl(TCG_COND_NE, pc_wr, ctx->branch_taken, tcg_constant_tl(0), - hex_gpr[HEX_REG_PC], addr); + pc_wr, addr); tcg_gen_movi_tl(ctx->branch_taken, 1); } else { - tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], addr); + tcg_gen_mov_tl(pc_wr, addr); } =20 if (cond !=3D TCG_COND_ALWAYS) { diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 28a171bf623..22f0ff5b891 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -54,6 +54,7 @@ static const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] = =3D { TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; TCGv hex_pred[NUM_PREGS]; TCGv hex_slot_cancelled; +TCGv hex_next_PC; TCGv hex_new_value_usr; TCGv hex_store_addr[STORES_MAX]; TCGv_i32 hex_store_width[STORES_MAX]; @@ -184,10 +185,16 @@ static void gen_goto_tb(DisasContext *ctx, unsigned t= b_slot_idx, } } =20 +static bool need_next_PC(DisasContext *ctx); + static void gen_end_tb(DisasContext *ctx) { gen_exec_counters(ctx); =20 + if (ctx->need_next_pc) { + tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); + } + if (ctx->branch_cond !=3D TCG_COND_NEVER) { if (ctx->branch_cond !=3D TCG_COND_ALWAYS) { TCGLabel *skip =3D gen_new_label(); @@ -391,17 +398,25 @@ static bool pkt_ends_tb(Packet *pkt) =20 static bool need_next_PC(DisasContext *ctx) { - /* Check for conditional control flow or HW loop end */ - for (int i =3D 0; i < ctx->pkt.num_insns; i++) { - uint16_t opcode =3D ctx->pkt.insn[i].opcode; - if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) { - return true; - } - if (GET_ATTRIB(opcode, A_HWLOOP0_END) || - GET_ATTRIB(opcode, A_HWLOOP1_END)) { - return true; + Packet *pkt =3D &ctx->pkt; + if (pkt->pkt_has_cof || ctx->pkt_ends_tb) { + for (int i =3D 0; i < pkt->num_insns; i++) { + uint16_t opcode =3D pkt->insn[i].opcode; + if ((GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_CO= F)) || + GET_ATTRIB(opcode, A_HWLOOP0_END) || + GET_ATTRIB(opcode, A_HWLOOP1_END)) { + return true; + } } } + /* + * We end the TB on some instructions that do not change the flow (for + * other reasons). In these cases, we must set pc too, as the insn won= 't + * do it themselves. + */ + if (ctx->pkt_ends_tb && !check_for_attrib(pkt, A_COF)) { + return true; + } return false; } =20 @@ -637,12 +652,14 @@ static void gen_start_packet(DisasContext *ctx) ctx->branch_taken =3D NULL; if (ctx->pkt.pkt_has_cof) { ctx->branch_taken =3D tcg_temp_new(); - if (ctx->pkt.pkt_has_multi_cof) { - tcg_gen_movi_tl(ctx->branch_taken, 0); - } - if (need_next_PC(ctx)) { - tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC); - } + } + if (ctx->pkt.pkt_has_multi_cof) { + tcg_gen_movi_tl(ctx->branch_taken, 0); + } + ctx->pkt_ends_tb =3D pkt_ends_tb(&ctx->pkt); + ctx->need_next_pc =3D need_next_PC(ctx); + if (ctx->need_next_pc) { + tcg_gen_movi_tl(hex_next_PC, next_PC); } =20 /* Preload the predicated registers into get_result_gpr(ctx, i) */ @@ -1142,7 +1159,7 @@ static void gen_commit_packet(DisasContext *ctx) ctx->pkt.vhist_insn->generate(ctx); } =20 - if (pkt_ends_tb(&ctx->pkt) || ctx->base.is_jmp =3D=3D DISAS_NORETURN) { + if (ctx->pkt_ends_tb || ctx->base.is_jmp =3D=3D DISAS_NORETURN) { gen_end_tb(ctx); } } @@ -1327,6 +1344,8 @@ void hexagon_translate_init(void) } hex_new_value_usr =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); + hex_next_PC =3D tcg_global_mem_new(tcg_env, + offsetof(CPUHexagonState, next_PC), "next_PC"); =20 for (i =3D 0; i < NUM_PREGS; i++) { hex_pred[i] =3D tcg_global_mem_new(tcg_env, --=20 2.34.1 From nobody Mon Jul 27 20:02:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784229406; cv=none; d=zohomail.com; s=zohoarc; b=e6lAfrUJnYHGf8fnN45cLAqRX/MXozi0uSgkXCJmn9uvIcIMqBWltxWifhs50grDFMD8Sj15ugKS8MUTXFMDpNXxFaRQQYX4eXmj6ZW8Gq3iow+ziGZx8dOgZbVABl8vz/8C3uG3GaTMyb2Ynq+/PmguhwzLgKGUXf88eFaGRP0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784229406; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FuJtJ2k3T/KZLw+xH9iOVSqK+1drjPQNHXrhqEQohJE=; b=BtyDqQZqUyhLFS66vNST6+4UMGuIw9Dw6JcUcqTFvfG1ZPu10q9nen4Ux+74WQmwMst5U3xrQzufxUXYGcut/MQWeJ5qM+ugMeRu9D1cFzRlg4vUswqnaC6Y9ASNPbQlxNZ4EqmZYGs7rMmObjZxh/J8dB3m516aqipWH/eO+oQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784229406194251.28647424551139; Thu, 16 Jul 2026 12:16:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wkRZ4-0008Ek-Kz; Thu, 16 Jul 2026 15:16:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wkRZ2-0008Cd-P9 for qemu-devel@nongnu.org; Thu, 16 Jul 2026 15:16:08 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wkRZ0-0002y5-Sz for qemu-devel@nongnu.org; Thu, 16 Jul 2026 15:16:08 -0400 Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66GGSgOI3481375 for ; Thu, 16 Jul 2026 19:16:05 GMT Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fetcf33t9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 16 Jul 2026 19:16:05 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c88da04b719so3389669a12.2 for ; Thu, 16 Jul 2026 12:16:05 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784229407169158500 Add new test cases from hexagon-arch-tests to exercise exceptions, guest mode. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 1 + tests/functional/hexagon/meson.build | 5 ++ tests/functional/hexagon/test_arch_tests.py | 57 +++++++++++++++++++++ tests/functional/meson.build | 1 + 4 files changed, 64 insertions(+) create mode 100644 tests/functional/hexagon/meson.build create mode 100755 tests/functional/hexagon/test_arch_tests.py diff --git a/MAINTAINERS b/MAINTAINERS index 6171cc74940..a87c5ed23d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1357,6 +1357,7 @@ F: hw/hexagon/ F: include/hw/hexagon/ F: configs/devices/hexagon-softmmu/default.mak F: docs/system/hexagon/ +F: tests/functional/hexagon/ F: docs/devel/hexagon-sys.rst =20 LoongArch Machines diff --git a/tests/functional/hexagon/meson.build b/tests/functional/hexago= n/meson.build new file mode 100644 index 00000000000..2b5a1a8f264 --- /dev/null +++ b/tests/functional/hexagon/meson.build @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +tests_hexagon_system_thorough =3D [ + 'arch_tests', +] diff --git a/tests/functional/hexagon/test_arch_tests.py b/tests/functional= /hexagon/test_arch_tests.py new file mode 100755 index 00000000000..54a1412c597 --- /dev/null +++ b/tests/functional/hexagon/test_arch_tests.py @@ -0,0 +1,57 @@ +#!/usr/bin/env python3 +# +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import QemuSystemTest, Asset +from qemu_test.cmd import wait_for_console_pattern + + +class ArchTestsUart(QemuSystemTest): + """ + Hexagon architecture verification tests + + These are bare-metal tests from hexagon-arch-tests that exercise + system functionality. + + Tests output results via UART. + """ + timeout =3D 60 + + ASSET_TARBALL =3D Asset( + "https://github.com/qualcomm/qemu-hexagon-testing/releases/" + "download/v0.2.5/arch_tests_uart.tar.gz", + "edb4f37b877a3a72a0e10920477458a43b40045d34398fee8cb763fefd342f4f", + ) + + def run_uart_test(self, test_name: str, + machine: str =3D "virt") -> None: + """ + Run an arch test binary and verify PASS via UART console output. + """ + self.set_machine(machine) + self.archive_extract(self.ASSET_TARBALL) + target_bin =3D self.scratch_file('arch_tests_uart_package', + 'bin', test_name) + self.vm.set_console() + self.set_vm_arg("-display", "none") + self.set_vm_arg("-kernel", target_bin) + self.vm.launch() + wait_for_console_pattern(self, "PASS") + + def test_exceptions(self) -> None: + """Tests exception delivery for trap instructions, privilege + violations, and verifies SSR cause codes and ELR values. + """ + self.run_uart_test("test_exceptions") + + def test_guest_mode(self) -> None: + """Tests guest mode entry/exit via CCR configuration, verifying + GSR fields, GELR, and guest event vector table dispatch. + """ + self.run_uart_test("test_guest_mode") + + +if __name__ =3D=3D "__main__": + QemuSystemTest.main() diff --git a/tests/functional/meson.build b/tests/functional/meson.build index c158197c4b7..c7362dd00ef 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -14,6 +14,7 @@ subdir('aarch64') subdir('alpha') subdir('arm') subdir('avr') +subdir('hexagon') subdir('hppa') subdir('i386') subdir('loongarch64') --=20 2.34.1