From nobody Wed Sep 23 02:50:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784141868; cv=none; d=zohomail.com; s=zohoarc; b=ApICzWrA2xvEEdEPq2uw2pgzCxPHz7yHkNGr6BtjTRTMhaaCL5/XwoZKhmE8kotqsgdcy93rn+fwu1oVQDNPGRFmIrS/q9H6p01/qUlEaOQhz8QCtZIEsk1Keg5h01sDlUqHddPHDwb4WHqQX+a5JUTXa53jQO7tXjcLdloNs50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784141868; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QAGLj1XrqN2CD9OUPfE+JAmfbes2UCSMYiRAQ6NeIBw=; b=Q2anTcMbD32ePZUs07SLbefUuiRpbUBmzU16dIN4ZtxnNee2SwNfPnBdnxsA4VDnsUu9O2OMIhlI+EdosVpd4Al5d/1MBLnrT3Cr+GBR9WpsY0mIuf8GF8w9Iug+kNnzplbLrW44XkpR8wuQo+/io9XQfg3++hqOzx/yr4Txdjg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784141868522301.9222814859901; Wed, 15 Jul 2026 11:57:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wk4nb-0002us-FT; Wed, 15 Jul 2026 14:57:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wk4nS-0002tA-UQ for qemu-devel@nongnu.org; Wed, 15 Jul 2026 14:57:32 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wk4nI-00060s-Fe for qemu-devel@nongnu.org; Wed, 15 Jul 2026 14:57:30 -0400 Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66FHB8nP342918 for ; Wed, 15 Jul 2026 18:57:15 GMT Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fe855aak8-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 15 Jul 2026 18:57:15 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2cc8bde6318so106195405ad.3 for ; Wed, 15 Jul 2026 11:57:15 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3140e6c2b17sm5469546eec.25.2026.07.15.11.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 11:57:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= QAGLj1XrqN2CD9OUPfE+JAmfbes2UCSMYiRAQ6NeIBw=; b=QHhWzOBMCYIjj0LG 3/XUeaNk2mWDMCYRpAKJq5znvCTv9X3wsI+Y8j6XdLiReEfPUnmTlzuHmX4VZAeO 0iSY6QTCyC9hwhJ3pP85KIxB9RkYjv1GXisU1YKc6ZMuBQHI45IJwXDjUIVa0h10 0vZKQPqi1Hr+oDZEU5HlGk+I3+lHIpRkfuh3gV+5v3JCIy/6MDnUZaaxFz1QYPSA oAzsCtfO7dC36rJzTd7cyXTcsbN9ZaSKqU6YXEX8Fm28/73UVkkk6KZQ/RHreFMo zh5o+omVPrD2r77OuRGIX2sfeG7Wfz/sC51UGbX7IA5JCLSVq0pGaoQ1anWCNjjS fbR3VQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784141835; x=1784746635; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=QAGLj1XrqN2CD9OUPfE+JAmfbes2UCSMYiRAQ6NeIBw=; b=DtMj5uHWPlSQalTAXaoFNj1wTt0HP4GMtIcb3bna7wAGhloRG4FOvriyJLpIBLzTBC 9eLxEi0Fw1BcmcSR3IX4miP2CGGTNW/zrRjKiTeEfHzym95H7Rgrd8ddbYR47zhwfYM0 sEeb8P8+nppQwuAIkOVgj05qUJZEZPEJ2cv4xQ2jPCVSL9gfusLwX+cPVxv8E/t4L7Ul tVEjmcN4KVCiESr57ZVgJvKLItnnj0ZOVf3O9R3ttIUjVowMkIewTncQk6+WALorbAkF PwedMnsWZWAiWDePiS5v3oUBUPhU2zlieQ2GzKmM3oOQ920XDcsP/xx7GbGjAz5feQFt sZHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784141835; x=1784746635; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=QAGLj1XrqN2CD9OUPfE+JAmfbes2UCSMYiRAQ6NeIBw=; b=R4aMBO3BJWVgGAY1ljAASU8p8lsX51fTLW33b27/zNicd/rpVIpJxqfrkPYK/dDB/J HDQT189ffkEmSMGOYssuadK55Yw6Lbq8KB3lP6ifd5Fa1cF7pYZhoM7g8uKFkrdxwYjh I/P5xwR8yBmEFHSkCHObkehWbieEeAGO3hi1qFJ9mWRr36F/BHyRJVSEi0PpLzTINCRT YnuNMyKqF/cSbDS9Dqt6QG6JfxV30uh8rOjDqtevSMUw730SQXvrkbYabIKNxqOaEzxe suuTZKy5Fo5Amt5PV66t0LJc9v++V2s36KbnkrRNnG8ToiaPqtdPMMMFy58nqtZeqTpD mvbw== X-Gm-Message-State: AOJu0YzT3vIemL+BPmVxwieol0VsluCftsYB6E0Mq34+Qr6M1GIYjNOe 4782iFOg8iHMdN3MTStBUtFUP5jT2P+APvOIG45rUY0MdHqnZGCZg+CrGzDRpd90PCHh2VwdnwC I4+Fn0arUsw0hCRsgseH+raRrekSV/cIhCXbpHs+br1+j8EDgVC/meC4ZGOXUxBRuNw== X-Gm-Gg: AfdE7cnPADIO8ZXCEIcJRR10FT9G/9m7RUFv9o2KhI9Av5C2tSpasH0Jiq4U22LdQ4y i44Z06Jm+ZRcky7fwUtKULrUQujez1uak1cKaMdbTkWUmCXQKCOmY6JQcr1+wydcW/ZwCAvgfgS pWML810f1L3xaMucTYvsU6buTFs5uhNif+XryxAMTEIlb+iX+3HxMIpdRmLj585c+tZvPKpDuRQ r+FKDlIRdIK0Ay4BrJ3KAleUAi+QeaTMLvY8iPqfmT0JE0K7pFeJPuyBGLZ6pGMPR9xHKV6/bTO 3T9asA3gT2yVQf+FVCFu5qIxbBVl7qfA5tujY9RrpqHPZ+Ss/x7VeUbb/OJyBcC+3WZXoZxl8Be hGrJFGxp4QWj/WlHTYNul+24SXZSLXhgiCWiPCA5EgWI5s+I3rO8/ogchHVw= X-Received: by 2002:a17:90a:d887:b0:38e:a74:dfe4 with SMTP id 98e67ed59e1d1-38e1afbf3bdmr7092186a91.25.1784141834505; Wed, 15 Jul 2026 11:57:14 -0700 (PDT) X-Received: by 2002:a17:90a:d887:b0:38e:a74:dfe4 with SMTP id 98e67ed59e1d1-38e1afbf3bdmr7092159a91.25.1784141833903; Wed, 15 Jul 2026 11:57:13 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , peter.maydell@linaro.org, matheus.bernardino@oss.qualcomm.com, ltaylorsimpson@gmail.com, Thomas Huth , Brian Cain , Laurent Vivier , Fabiano Rosas , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 6/7] tests/qtest: add L2VIC qtest Date: Wed, 15 Jul 2026 11:57:00 -0700 Message-Id: <20260715185701.1287176-7-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260715185701.1287176-1-brian.cain@oss.qualcomm.com> References: <20260715185701.1287176-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 4FQ3oi5D4JIwjiWyN-GJtjQstdphrG60 X-Authority-Analysis: v=2.4 cv=KOlqylFo c=1 sm=1 tr=0 ts=6a57d80b cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=1LxsVcIvEUuLhGiP2wwA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE1MDE4OCBTYWx0ZWRfXzlehuxiqzPpg 5kLyb9QDlfiLBuADkB4+/dB7bBJiONOapLuJzfWPbQwDHP2Nx8DF258EO5UwZ8X8zNCilhNHQxk V3CYfMfz4hQNDDTVVEBHd6pAVQTQKaw1PbfaDryI0U42+eb2iPdJ09ZCfQy7u4aLT1jL6ySY5bh XVyFCW4lnKjWemCJeskciuUdmDOeRzJTZtjkH7yCJBm+FWBZ2KZIXXZn3RiEdjX063oohBbWhBU FMIATeQKpR1WdlW6PVauXl9S8lOI20pzExR1yX0NxvMaNWtWYi3wwgnYrMUo9SonRLElz7QG/Or Tf5ANgXw5TiBNf1ohfwyILysi2ZxXwDblpEVyLDdPdSVlvlYjCnt6IC7ULnKZiCgwrFuqsDNxsa 3KdVj3WLxeC6409UvBTMshZcLGCYM1Bmbk+xoGHZUqEYiwRFpIGOygRORiP5E9RKOKTtDv4h1IE lpJpHdZ2NVSxkfxMD/w== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE1MDE4OCBTYWx0ZWRfXxozkoLhHRZx6 iX9jY55edREY+wydzsL+xkbVY+xqN17T1ckAEDO+v6yQfG3i2oj/EbbS53LfEuzP0nf32UE5UK1 HU4FidN1B6TMUBE61n6c1rAvtPaJH3c= X-Proofpoint-ORIG-GUID: 4FQ3oi5D4JIwjiWyN-GJtjQstdphrG60 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-15_04,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607150188 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784141870501158500 Add a qtest exercising the L2VIC interrupt controller's basic register access and interrupt enable/disable behavior. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- MAINTAINERS | 1 + tests/qtest/l2vic-test.c | 242 +++++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 2 +- 3 files changed, 244 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/l2vic-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 7281a281632..b7012e945e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -252,6 +252,7 @@ S: Supported F: target/hexagon/ F: hw/intc/hex-l2vic.c F: include/hw/intc/hex-l2vic.h +F: tests/qtest/l2vic-test.c X: target/hexagon/idef-parser/ X: target/hexagon/gen_idef_parser_funcs.py F: linux-user/hexagon/ diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c new file mode 100644 index 00000000000..9887e458a6f --- /dev/null +++ b/tests/qtest/l2vic-test.c @@ -0,0 +1,242 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + * + * QTest testcase for the L2VIC Interrupt Controller + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" +#include "hw/intc/hex-l2vic.h" + +/* Base addresses for L2VIC */ +#define L2VIC_BASE 0xfc910000 +#define L2VIC_FAST_BASE 0xfc920000 + +/* Helper functions */ +static uint32_t l2vic_read32(uint64_t base, uint32_t offset) +{ + return readl(base + offset); +} + +static void l2vic_write32(uint64_t base, uint32_t offset, uint32_t value) +{ + writel(base + offset, value); +} + +/* Test basic register access */ +static void test_l2vic_register_access(void) +{ + uint32_t val; + + /* Test that basic registers can be read/written */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + /* Should have enabled interrupt 0 */ + g_assert_cmpuint(val & 0x1, =3D=3D, 0x1); + + /* Clear it */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + /* Should be cleared now */ + g_assert_cmpuint(val & 0x1, =3D=3D, 0x0); +} + +/* Test interrupt enable/disable */ +static void test_l2vic_interrupt_enable(void) +{ + uint32_t val; + + /* Initially all interrupts should be disabled */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + g_assert_cmpuint(val, =3D=3D, 0); + + /* Enable some interrupts */ + /* Enable IRQ 0 and 2 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x5); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + g_assert_cmpuint(val & 0x5, =3D=3D, 0x5); + + /* Disable one */ + /* Disable IRQ 0 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + g_assert_cmpuint(val & 0x1, =3D=3D, 0x0); /* IRQ 0 should be disabled= */ + g_assert_cmpuint(val & 0x4, =3D=3D, 0x4); /* IRQ 2 should still be en= abled */ +} + +/* Test register read/write without triggering interrupts */ +static void test_l2vic_basic_functionality(void) +{ + l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + l2vic_read32(L2VIC_BASE, L2VIC_INT_PENDINGn); + l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + l2vic_read32(L2VIC_BASE, L2VIC_INT_TYPEn); + + /* Exercise write-only registers */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0); +} + +/* + * Test L2VIC IRQ outputs + */ +static void test_l2vic_irq_outputs(void) +{ + uint32_t val; + + /* Clear any previous configuration */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0xFFFFFFFF); + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0xFFFFFFFF); + /* Reset all to level-triggered */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0); + + /* Test Group 0 interrupts (default group: IRQ2) */ + /* Configure interrupt 0 as edge-triggered (required for soft interrup= ts) */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x1); + /* Enable interrupt 0 and generate software interrupt */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x1); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x1); + + /* Verify interrupt is active (would assert IRQ2 in real hardware) */ + /* In L2VIC: pending interrupts become active and clear from pending */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x1, =3D=3D, 0x1); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x1, =3D=3D, 0x0); + + /* Test Group 1 interrupts: IRQ3 */ + /* Configure interrupt 1 as edge-triggered and to group 1 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x2); + /* Set bit 1 for interrupt 1 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_1, 0x2); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x2); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x2); + + /* Verify interrupt is active in group 1 (would assert IRQ3) */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x2, =3D=3D, 0x2); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_GRPn_1); + g_assert_cmpuint(val & 0x2, =3D=3D, 0x2); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x2); + + /* Test Group 2 interrupts: IRQ4 */ + /* Configure interrupt 2 as edge-triggered and to group 2 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x4); + /* Set bit 2 for interrupt 2 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_2, 0x4); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x4); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x4); + + /* Verify interrupt is active in group 2 (would assert IRQ4) */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x4, =3D=3D, 0x4); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_GRPn_2); + g_assert_cmpuint(val & 0x4, =3D=3D, 0x4); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x4); + + /* Test Group 3 interrupts: IRQ5 */ + /* Configure interrupt 3 as edge-triggered and to group 3 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x8); + /* Set bit 3 for interrupt 3 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_3, 0x8); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x8); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x8); + + /* Verify interrupt is active in group 3 (would assert IRQ5) */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x8, =3D=3D, 0x8); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_GRPn_3); + g_assert_cmpuint(val & 0x8, =3D=3D, 0x8); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x8); + + /* Test multiple pending interrupts (only one can be active at a time)= */ + /* Configure all interrupts 0-3 as edge-triggered */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0xF); + /* Enable interrupts 0-3 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0xF); + /* Generate all 4 interrupts */ + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0xF); + + /* Verify that highest prio interrupt becomes active */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + /* At least one bit should be set, but not necessarily all */ + g_assert_cmpuint(val & 0xF, !=3D, 0x0); + + /* Clear all active interrupts */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, val & 0xF); + + /* After clearing, check if more interrupts become active */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + /* Could be 0 if all processed, or have more if pending */ + + /* Test that software interrupts require edge-triggered configuration = */ + /* Configure interrupt 5 as level-triggered (default) */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x0); + /* Enable interrupt 5 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x20); + /* Try to generate level interrupt */ + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x20); + + /* Should not work - no interrupt should be active */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + /* No interrupt because level-triggered */ + g_assert_cmpuint(val & 0x20, =3D=3D, 0x0); + + /* Now configure as edge-triggered and try again */ + /* Set edge-triggered */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x20); + /* Generate interrupt */ + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x20); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x20, =3D=3D, 0x20); + + /* Clean up - clear all configuration */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0xFFFFFFFF); + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0xFFFFFFFF); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_0, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_1, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_2, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_3, 0); +} + +static void test_l2vic_on_machine(gconstpointer data) +{ + const char *machine =3D (const char *)data; + g_autofree char *args =3D g_strdup_printf("-machine %s", machine); + + qtest_start(args); + + /* Run all the L2VIC tests */ + test_l2vic_register_access(); + test_l2vic_interrupt_enable(); + test_l2vic_basic_functionality(); + test_l2vic_irq_outputs(); + + qtest_end(); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + /* Test on virt machine */ + qtest_add_data_func("/l2vic/virt/all-tests", "virt", + test_l2vic_on_machine); + + /* Test on V66G_1024 machine */ + qtest_add_data_func("/l2vic/V66G_1024/all-tests", "V66G_1024", + test_l2vic_on_machine); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 56ff860e216..a76863c7dd6 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -299,7 +299,7 @@ qtests_riscv64 =3D ['riscv-csr-test'] + \ ['iommu-riscv-test'] : []) + \ (config_all_devices.has_key('CONFIG_K230') ? ['k230-wdt-test'] : []) =20 -qtests_hexagon =3D ['boot-serial-test'] +qtests_hexagon =3D ['boot-serial-test', 'l2vic-test'] =20 qos_test_ss =3D ss.source_set() qos_test_ss.add( --=20 2.34.1