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Wed, 15 Jul 2026 11:57:04 -0700 (PDT) X-Received: by 2002:a17:90b:3d81:b0:387:df8f:1406 with SMTP id 98e67ed59e1d1-38e2a0eacc3mr3301303a91.39.1784141824200; Wed, 15 Jul 2026 11:57:04 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , peter.maydell@linaro.org, matheus.bernardino@oss.qualcomm.com, ltaylorsimpson@gmail.com, Thomas Huth , Brian Cain , Laurent Vivier , Fabiano Rosas , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/7] target/hexagon: initialize deferred sreg-write temps to current value Date: Wed, 15 Jul 2026 11:56:55 -0700 Message-Id: <20260715185701.1287176-2-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260715185701.1287176-1-brian.cain@oss.qualcomm.com> References: <20260715185701.1287176-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=APNfGQ4N c=1 sm=1 tr=0 ts=6a57d801 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=IlOZXNdbeIrMSDKviAkA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE1MDE4OCBTYWx0ZWRfXyTpS3/A6GQ7e EKukGx778EE4wugPO7JGAF4JyBgj+eIms4HB11yDPuOKvzl+eGmUI3mJgp/Xsj4dr1QPu4jzktF NwG9LU4lFaAReTT7J5pwqcDK+eX/VjY= X-Proofpoint-ORIG-GUID: Oz8rXBfmjjHJ2N8veiYUUTGOP7bdFNlb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE1MDE4OCBTYWx0ZWRfX1Xv49QVGfUEv Mc27HiqKZWXeoPmJYiyCNowhznYau3KW1GdeM6Qh4esTIMYzK625YG2uKqlhVSwweLMc9l0DWGw 1FodAFEmjS32Z/FC62kCNF8UjIhu6ns5a3krG5Nwk3kXYdaHnKacPsHzXhgdzLrbMDSlkWCi216 bMrGCLWlfjx5OJrOxbIJZVh5URE7hHbEmYSaXjDPSEs4I4vfOVGtaanwRaYfZIbP9n9KNgboa0o b9oWxY+6+a5BjPuv1PMnfN1Hi4F+7kl9POGCLkS94iF42xAs0Z8wKVU5wFLnNRV1xRF9lRSQ7sV Y2cUG+v8l3fcTlO0ZJSDuJdAuUi/OmbFCHPQukhUgMHMyW/gbUP44odw9qYWlhPaOoXWqzR0pOi SXW4u2KNN+s7yFrKPRL4jf8+DGdVubGU7mtRvMqqNyqjoqn4+OrSJ44ZMRZrglV9WyWCkB1gGrf YzCg6LlqmOYhfgMXKTA== X-Proofpoint-GUID: Oz8rXBfmjjHJ2N8veiYUUTGOP7bdFNlb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-15_04,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607150188 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784141926781158500 Unconditionally allocate and initialize the temp to the sreg's current value for every logged sreg write, rather than only allocating when need_commit is set or the register is SSR. Without this, reading a deferred sreg write within the same packet before it is committed can observe an uninitialized temp instead of the register's pre-packet value. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 77235916f4b..28a171bf623 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -615,9 +615,10 @@ static void gen_start_packet(DisasContext *ctx) } for (i =3D 0; i < ctx->sreg_log_idx; i++) { int reg_num =3D ctx->sreg_log[i]; - if (reg_num < HEX_SREG_GLB_START && - (ctx->need_commit || reg_num =3D=3D HEX_SREG_SSR)) { + if (reg_num < HEX_SREG_GLB_START) { ctx->t_sreg_new_value[reg_num] =3D tcg_temp_new(); + tcg_gen_mov_tl(ctx->t_sreg_new_value[reg_num], + hex_t_sreg[reg_num]); } } for (i =3D 0; i < NUM_GREGS; i++) { --=20 2.34.1 From nobody Sat Jul 25 16:49:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784141859; cv=none; d=zohomail.com; s=zohoarc; b=XyYSmj2sQQJ1lCJtsJsvb3Zjw19xijZjCcuvcBxInj7OzFASM1nfWfEX/fZj8mGx4Bh6KDh9NcKoPnyeUeLBLUwIss4PBy3Nb49RSBX5DEBk/lU1dmwhKnJrDMBUdNlCXpKleJd3ht/THWDXdf2NEoZlnwZ5HTewVBGV/OIIwjI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784141859; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=v9TEZ/r+WdyXkCh0jPLt6TPCbm8hNKa/SZ+tY3PO/BU=; b=eJ6A1B8nSxIUAgQD1qiy33CKxT+0pEs/7+Nk0Pm9PgACCJ6nYUkIRn6rNB5sAEAz2KkRgB3sfxdxYrrjZtqAPRk+f8+Y38wM/hMFc98Q3nhSgFCpGC/V1d2E2EjymKYWNe4+Rm3GPjlwVJllDXqcGDayXQomi2//zmV95n5ttCw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784141859055176.65080485614646; Wed, 15 Jul 2026 11:57:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wk4nC-0002ka-0e; Wed, 15 Jul 2026 14:57:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wk4nA-0002k3-Hz for qemu-devel@nongnu.org; Wed, 15 Jul 2026 14:57:12 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wk4n7-0005xs-5P for qemu-devel@nongnu.org; Wed, 15 Jul 2026 14:57:12 -0400 Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66FHBHiG204399 for ; Wed, 15 Jul 2026 18:57:08 GMT Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4feayfhgju-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 15 Jul 2026 18:57:08 +0000 (GMT) Received: by mail-pg1-f199.google.com with SMTP id 41be03b00d2f7-cab041eced3so6491895a12.1 for ; Wed, 15 Jul 2026 11:57:08 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784141860573158500 Add hex_next_PC, a global mirroring CPUHexagonState::next_PC, and ctx->need_next_pc, so that gen_write_new_pc_addr() can write the branch target through hex_next_PC instead of hex_gpr[HEX_REG_PC] when a later unconditional write of PC is expected. gen_end_tb() then commits hex_next_PC into hex_gpr[HEX_REG_PC] at the end of the packet. Previously, non-COF instructions that still end a TB did not advance the PC, since next_PC's value was never written back into the PC register. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/translate.h | 3 +++ target/hexagon/genptr.c | 14 ++++++++--- target/hexagon/translate.c | 51 ++++++++++++++++++++++++++------------ 3 files changed, 49 insertions(+), 19 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 0a7f37d5842..2fca157553b 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -40,6 +40,7 @@ typedef struct DisasContext { int reg_log_idx; DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS); + bool pkt_ends_tb; bool implicit_usr_write; #ifndef CONFIG_USER_ONLY int greg_log[GREG_WRITES_MAX]; @@ -75,6 +76,7 @@ typedef struct DisasContext { DECLARE_BITMAP(insn_qregs_read, NUM_QREGS); bool pre_commit; bool need_commit; + bool need_next_pc; TCGCond branch_cond; target_ulong branch_dest; bool is_tight_loop; @@ -310,6 +312,7 @@ extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; extern TCGv hex_pred[NUM_PREGS]; extern TCGv hex_slot_cancelled; extern TCGv hex_new_value_usr; +extern TCGv hex_next_PC; extern TCGv hex_store_addr[STORES_MAX]; extern TCGv_i32 hex_store_width[STORES_MAX]; extern TCGv hex_store_val32[STORES_MAX]; diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 1ebc7471409..dc9ba8a0060 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -613,14 +613,22 @@ static void gen_write_new_pc_addr(DisasContext *ctx, = TCGv addr, tcg_gen_brcondi_tl(cond, pred, 1, pred_false); } =20 + /* + * If gen_end_tb() will unconditionally overwrite PC with hex_next_PC + * (because this packet has a predicated COF that may not execute), + * write the branch target there instead of directly into the PC + * global, or the overwrite in gen_end_tb() would clobber it. + */ + TCGv pc_wr =3D ctx->need_next_pc ? hex_next_PC : hex_gpr[HEX_REG_PC]; + if (ctx->pkt.pkt_has_multi_cof) { /* If there are multiple branches in a packet, ignore the second o= ne */ - tcg_gen_movcond_tl(TCG_COND_NE, hex_gpr[HEX_REG_PC], + tcg_gen_movcond_tl(TCG_COND_NE, pc_wr, ctx->branch_taken, tcg_constant_tl(0), - hex_gpr[HEX_REG_PC], addr); + pc_wr, addr); tcg_gen_movi_tl(ctx->branch_taken, 1); } else { - tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], addr); + tcg_gen_mov_tl(pc_wr, addr); } =20 if (cond !=3D TCG_COND_ALWAYS) { diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 28a171bf623..22f0ff5b891 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -54,6 +54,7 @@ static const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] = =3D { TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; TCGv hex_pred[NUM_PREGS]; TCGv hex_slot_cancelled; +TCGv hex_next_PC; TCGv hex_new_value_usr; TCGv hex_store_addr[STORES_MAX]; TCGv_i32 hex_store_width[STORES_MAX]; @@ -184,10 +185,16 @@ static void gen_goto_tb(DisasContext *ctx, unsigned t= b_slot_idx, } } =20 +static bool need_next_PC(DisasContext *ctx); + static void gen_end_tb(DisasContext *ctx) { gen_exec_counters(ctx); =20 + if (ctx->need_next_pc) { + tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); + } + if (ctx->branch_cond !=3D TCG_COND_NEVER) { if (ctx->branch_cond !=3D TCG_COND_ALWAYS) { TCGLabel *skip =3D gen_new_label(); @@ -391,17 +398,25 @@ static bool pkt_ends_tb(Packet *pkt) =20 static bool need_next_PC(DisasContext *ctx) { - /* Check for conditional control flow or HW loop end */ - for (int i =3D 0; i < ctx->pkt.num_insns; i++) { - uint16_t opcode =3D ctx->pkt.insn[i].opcode; - if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) { - return true; - } - if (GET_ATTRIB(opcode, A_HWLOOP0_END) || - GET_ATTRIB(opcode, A_HWLOOP1_END)) { - return true; + Packet *pkt =3D &ctx->pkt; + if (pkt->pkt_has_cof || ctx->pkt_ends_tb) { + for (int i =3D 0; i < pkt->num_insns; i++) { + uint16_t opcode =3D pkt->insn[i].opcode; + if ((GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_CO= F)) || + GET_ATTRIB(opcode, A_HWLOOP0_END) || + GET_ATTRIB(opcode, A_HWLOOP1_END)) { + return true; + } } } + /* + * We end the TB on some instructions that do not change the flow (for + * other reasons). In these cases, we must set pc too, as the insn won= 't + * do it themselves. + */ + if (ctx->pkt_ends_tb && !check_for_attrib(pkt, A_COF)) { + return true; + } return false; } =20 @@ -637,12 +652,14 @@ static void gen_start_packet(DisasContext *ctx) ctx->branch_taken =3D NULL; if (ctx->pkt.pkt_has_cof) { ctx->branch_taken =3D tcg_temp_new(); - if (ctx->pkt.pkt_has_multi_cof) { - tcg_gen_movi_tl(ctx->branch_taken, 0); - } - if (need_next_PC(ctx)) { - tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC); - } + } + if (ctx->pkt.pkt_has_multi_cof) { + tcg_gen_movi_tl(ctx->branch_taken, 0); + } + ctx->pkt_ends_tb =3D pkt_ends_tb(&ctx->pkt); + ctx->need_next_pc =3D need_next_PC(ctx); + if (ctx->need_next_pc) { + tcg_gen_movi_tl(hex_next_PC, next_PC); } =20 /* Preload the predicated registers into get_result_gpr(ctx, i) */ @@ -1142,7 +1159,7 @@ static void gen_commit_packet(DisasContext *ctx) ctx->pkt.vhist_insn->generate(ctx); } =20 - if (pkt_ends_tb(&ctx->pkt) || ctx->base.is_jmp =3D=3D DISAS_NORETURN) { + if (ctx->pkt_ends_tb || ctx->base.is_jmp =3D=3D DISAS_NORETURN) { gen_end_tb(ctx); } } @@ -1327,6 +1344,8 @@ void hexagon_translate_init(void) } hex_new_value_usr =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); + hex_next_PC =3D tcg_global_mem_new(tcg_env, + offsetof(CPUHexagonState, next_PC), "next_PC"); =20 for (i =3D 0; i < NUM_PREGS; i++) { hex_pred[i] =3D tcg_global_mem_new(tcg_env, --=20 2.34.1 From nobody Sat Jul 25 16:49:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784141845; cv=none; d=zohomail.com; s=zohoarc; b=lzQBQFxyi+BHebKE1lJoDZUTLB/ITTpwPsn6p+qo+KPdYTVPT+m7z3ujVtGsU9DWcXh+wnlXA3jZyz/xV2tps8EEsKYlOHTpz7uAPcqHfozuQxIGREmuf5cF7bp19R6u/uEH98uHxkqMgQ7JPl1gD7ynKkActIh+YNcB9pW+SOE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784141845; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=A1dKhWmVEpScQ2nw0jysc1Wm3J7x83ChWxRAi/X43Y0=; b=foUvHUfHxFUWR6yD7B+kRJnatE3lvO155apbr0RZabAQffy3j9Ook+0sxGXkipf+vu0L0MrJGLqgGb3Tm18PK0WvRm9H5Y3RS2OBDag8T0osk5QmWAekl3w0SZhoBvMOK6NQv5CtBcu1f7fv7gSa7C9SN03MFTpo9hfvT7xsgTU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784141845658785.1109244882994; Wed, 15 Jul 2026 11:57:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wk4nC-0002kb-1D; Wed, 15 Jul 2026 14:57:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wk4nA-0002k2-He for qemu-devel@nongnu.org; Wed, 15 Jul 2026 14:57:12 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wk4n8-0005yV-LY for qemu-devel@nongnu.org; Wed, 15 Jul 2026 14:57:12 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66FHBX3x051127 for ; Wed, 15 Jul 2026 18:57:09 GMT Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fecny8yfr-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 15 Jul 2026 18:57:09 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-38d7fcd1f66so8516520a91.2 for ; Wed, 15 Jul 2026 11:57:09 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784141846777158500 set_bit32()/test_bit32()/etc already let devices operate on guest-visible uint32_t register arrays without depending on the host's 'unsigned long' size. find_first_bit() has no such equivalent, which pushes callers towards casting a uint32_t array to 'unsigned long *'. Add find_first_bit32(), implemented the same way as find_first_bit(). Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- include/qemu/bitops.h | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index c7b838a6283..f7363a5479f 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -43,10 +43,9 @@ * be some guest-visible register view of the bit array. * * We do not currently implement uint32_t versions of find_last_bit(), - * find_next_bit(), find_next_zero_bit(), find_first_bit() or - * find_first_zero_bit(), because we haven't yet needed them. If you - * need them you should implement them similarly to the 'unsigned long' - * versions. + * find_next_bit(), find_next_zero_bit() or find_first_zero_bit(), + * because we haven't yet needed them. If you need them you should + * implement them similarly to the 'unsigned long' versions. * * You can declare a bitmap to be used with these functions via the * DECLARE_BITMAP and DECLARE_BITMAP32 macros in bitmap.h. @@ -382,6 +381,29 @@ static inline int test_bit32(long nr, const uint32_t *= addr) return 1U & (addr[BIT32_WORD(nr)] >> (nr & 31)); } =20 +/** + * find_first_bit32 - find the first set bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit number of the first set bit, + * or @size if there is no set bit in the bitmap. + */ +static inline uint32_t find_first_bit32(const uint32_t *addr, uint32_t siz= e) +{ + uint32_t result; + + for (result =3D 0; result < size; result +=3D 32) { + uint32_t tmp =3D *addr++; + if (tmp) { + result +=3D ctz32(tmp); + return result < size ? result : size; + } + } + /* Not found */ + return size; +} + /** * DOC: Miscellaneous bit operations on single values * --=20 2.34.1 From nobody Sat Jul 25 16:49:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784141859; cv=none; d=zohomail.com; s=zohoarc; b=gcHujFdlfcvzYTgfqgok1ceyUPGOSb+gniK7ad2pXLuDdDS/00nsH+HV2goktHIiVlVYAv6DOo8RYzgKD3erSKNSJMNIkCdNzW19hifFbag2NNjRFT28PlH3EOnB/3foagUbKwK6NdLmEQMTjmdnta5lIr4WG3zEl+jw7JjNbK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784141859; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=p6z0s61vbbQhGDm1mT3xGTL7beG4pyzV7k9B6Xqjv28=; b=PrdndEJIbxX5BDc/8fWBF/VIQR5v5jDvqe0BlqvEOoucx5rngfHZ6itvt9XbClZluSg5LTdi/5kethsLOfDTkvNI8cSQaidMbjJwJBw+s+bLXHvvkHQqPpIuT88eviYHnTcUyoBQgHZLHf0DFFBtokw7PKrEjIwf1FvNcVQycHo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784141859206358.7757590791721; Wed, 15 Jul 2026 11:57:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wk4nJ-0002mB-U1; Wed, 15 Jul 2026 14:57:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wk4nI-0002li-Fe for qemu-devel@nongnu.org; Wed, 15 Jul 2026 14:57:20 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wk4nB-0005zC-4T for qemu-devel@nongnu.org; Wed, 15 Jul 2026 14:57:17 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66FHIACU281095 for ; Wed, 15 Jul 2026 18:57:12 GMT Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4feeg1gc1h-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 15 Jul 2026 18:57:11 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c9fe4c5eb39so4207676a12.1 for ; Wed, 15 Jul 2026 11:57:11 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784141860605158500 From: Sid Manning The Hexagon DSP requires an L2VIC to route up to 1024 external interrupt sources through 4 VID output groups into the core's 8 interrupt inputs. This device model implements the register interface, interrupt steering, and edge/level type handling needed by the sysemu machine models. Co-authored-by: Matheus Tavares Bernardino Co-authored-by: Damien Hedde Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 3 + docs/devel/hexagon-l2vic.rst | 55 ++++ docs/devel/index-internals.rst | 1 + include/hw/intc/hex-l2vic.h | 87 ++++++ target/hexagon/cpu.h | 2 + hw/intc/hex-l2vic.c | 532 +++++++++++++++++++++++++++++++++ target/hexagon/cpu.c | 2 + target/hexagon/op_helper.c | 21 +- hw/hexagon/Kconfig | 1 + hw/intc/Kconfig | 3 + hw/intc/meson.build | 2 + hw/intc/trace-events | 4 + 12 files changed, 712 insertions(+), 1 deletion(-) create mode 100644 docs/devel/hexagon-l2vic.rst create mode 100644 include/hw/intc/hex-l2vic.h create mode 100644 hw/intc/hex-l2vic.c diff --git a/MAINTAINERS b/MAINTAINERS index ecb8cfdc41e..7281a281632 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -250,6 +250,8 @@ M: Brian Cain R: Pierrick Bouvier S: Supported F: target/hexagon/ +F: hw/intc/hex-l2vic.c +F: include/hw/intc/hex-l2vic.h X: target/hexagon/idef-parser/ X: target/hexagon/gen_idef_parser_funcs.py F: linux-user/hexagon/ @@ -262,6 +264,7 @@ F: gdbstub/gdb-xml/hexagon*.xml F: docs/system/target-hexagon.rst F: docs/system/hexagon/ F: docs/devel/hexagon-sys.rst +F: docs/devel/hexagon-l2vic.rst T: git https://github.com/qualcomm/qemu.git hex-next =20 Hexagon idef-parser diff --git a/docs/devel/hexagon-l2vic.rst b/docs/devel/hexagon-l2vic.rst new file mode 100644 index 00000000000..9cb2a86871e --- /dev/null +++ b/docs/devel/hexagon-l2vic.rst @@ -0,0 +1,55 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Hexagon L2 Vectored Interrupt Controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + +.. code-block:: none + + +-------------+ +----------------------+ + | l2vic | | hexagon core | + | | | | + IRQ in ---->| | | | + IRQ in ---->| VID0 -|----------------->| irq2 | + ... ---->| | | | | + IRQ in ---->| | | v | + | ... | | | + | | | / | | \ | + IRQ in ---->| | | t0 t1 t2 t3 ...| + IRQ in ---->| VIDN -| | | + ... ---->| | | | + IRQ in ---->| | | Global SREG File | + | | | | + | State | | | + | [ ] <--|=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D|=3D=3D> [ VID ] | + | [ ] <--|=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D|=3D=3D> [ VID1 ] | + | | | | + +-------------+ +----------------------+ + +L2VIC/Core Integration +---------------------- + +* hexagon core supports 8 external interrupt sources +* l2vic supports 1024 input interrupts mapped among 4 output interrupts +* l2vic has four output signals: { VID0, VID1, VID2, VID3 } +* l2vic device has a bank of registers per-VID that can be used to query + the status or assert new interrupts. +* Interrupts are 'steered' to threads based on { thread priority, 'EX' sta= te, + thread interrupt mask, thread interrupt enable, global interrupt enable, + etc. }. +* Any hardware thread could conceivably handle any input interrupt, depend= ent + on state. +* The system register transfer instruction can read the VID0-VID3 values f= rom + the l2vic when reading from hexagon core system registers "VID" and "VID= 1". +* When l2vic VID0 has multiple active interrupts, it pulses the VID0 output + IRQ and stores the IRQ number for the VID0 register field. Only after t= his + interrupt is cleared can the l2vic pulse the VID0 output IRQ again and p= rovide + the next interrupt number on the VID0 register. +* The ``ciad`` instruction clears the l2vic input interrupt and un-disable= s the + core interrupt. If some/an l2vic VID0 interrupt is pending when this oc= curs, + the next interrupt should fire and any subsequent reads of the VID regis= ter + should reflect the newly raised interrupt. +* In QEMU, on an external interrupt or an unmasked-pending interrupt, + all vCPUs are triggered (has_work=3D=3Dtrue) and each will grab the IO l= ock + while considering the steering logic to determine whether they're the th= read + that must handle the interrupt. diff --git a/docs/devel/index-internals.rst b/docs/devel/index-internals.rst index b89bab9b306..84985973490 100644 --- a/docs/devel/index-internals.rst +++ b/docs/devel/index-internals.rst @@ -15,6 +15,7 @@ Details about QEMU's various subsystems including how to = add features to them. clocks ebpf_rss hexagon-sys + hexagon-l2vic migration/index multi-process reset diff --git a/include/hw/intc/hex-l2vic.h b/include/hw/intc/hex-l2vic.h new file mode 100644 index 00000000000..f6519bcd6c2 --- /dev/null +++ b/include/hw/intc/hex-l2vic.h @@ -0,0 +1,87 @@ +/* + * QEMU L2VIC Interrupt Controller + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_INTC_HEX_L2VIC_H +#define HW_INTC_HEX_L2VIC_H + +#include "qom/object.h" + +#define L2VIC_VID_GRP_0 0x0 /* Read */ +#define L2VIC_VID_GRP_1 0x4 /* Read */ +#define L2VIC_VID_GRP_2 0x8 /* Read */ +#define L2VIC_VID_GRP_3 0xC /* Read */ +#define L2VIC_INT_ENABLEn 0x100 /* Read/Write */ +#define L2VIC_INT_ENABLE_CLEARn 0x180 /* Write */ +#define L2VIC_INT_ENABLE_SETn 0x200 /* Write */ +#define L2VIC_INT_TYPEn 0x280 /* Read/Write */ +#define L2VIC_INT_STATUSn 0x380 /* Read */ +#define L2VIC_INT_CLEARn 0x400 /* Write */ +#define L2VIC_SOFT_INTn 0x480 /* Write */ +#define L2VIC_INT_PENDINGn 0x500 /* Read */ +#define L2VIC_INT_GRPn_0 0x600 /* Read/Write */ +#define L2VIC_INT_GRPn_1 0x680 /* Read/Write */ +#define L2VIC_INT_GRPn_2 0x700 /* Read/Write */ +#define L2VIC_INT_GRPn_3 0x780 /* Read/Write */ + +#define L2VIC_INTERRUPT_MAX 1024 +/* + * Note about l2vic groups: + * Each interrupt to L2VIC can be configured to associate with one of + * four groups. + * Group 0 interrupts go to IRQ2 via VID 0 (SSR: 0xC2, the default) + * Group 1 interrupts go to IRQ3 via VID 1 (SSR: 0xC3) + * Group 2 interrupts go to IRQ4 via VID 2 (SSR: 0xC4) + * Group 3 interrupts go to IRQ5 via VID 3 (SSR: 0xC5) + */ + +#define TYPE_HEX_L2VIC "hex-l2vic" +/* + * L2VIC Interface for CPU/GlobalReg interaction + */ +#define TYPE_HEX_L2VIC_INTERFACE "hex-l2vic-if" + +typedef struct HexL2VicInterface HexL2VicInterface; + +typedef struct HexL2VicInterfaceClass { + InterfaceClass parent_class; + + /* Read VID register for given group */ + uint32_t (*read_vid)(HexL2VicInterface *l2vic, uint32_t group); + + /* Update VID register value */ + void (*update_vid)(HexL2VicInterface *l2vic, uint32_t group, + uint32_t value); + + /* Clear interrupt using CIAD instruction */ + void (*clear_interrupt)(HexL2VicInterface *l2vic); +} HexL2VicInterfaceClass; + +DECLARE_OBJ_CHECKERS(HexL2VicInterface, HexL2VicInterfaceClass, + HEX_L2VIC_INTERFACE, TYPE_HEX_L2VIC_INTERFACE); + +/* Convenience functions for interface users */ +static inline uint32_t l2vic_read_vid(HexL2VicInterface *l2vic, + uint32_t group) +{ + HexL2VicInterfaceClass *k =3D HEX_L2VIC_INTERFACE_GET_CLASS(l2vic); + return k->read_vid(l2vic, group); +} + +static inline void l2vic_update_vid(HexL2VicInterface *l2vic, uint32_t gro= up, + uint32_t value) +{ + HexL2VicInterfaceClass *k =3D HEX_L2VIC_INTERFACE_GET_CLASS(l2vic); + k->update_vid(l2vic, group, value); +} + +static inline void l2vic_clear_interrupt(HexL2VicInterface *l2vic) +{ + HexL2VicInterfaceClass *k =3D HEX_L2VIC_INTERFACE_GET_CLASS(l2vic); + k->clear_interrupt(l2vic); +} + +#endif /* HW_INTC_HEX_L2VIC_H */ diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 7694fd91fa8..f6c3c639325 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -39,6 +39,7 @@ typedef struct HexagonGlobalRegState HexagonGlobalRegStat= e; #include "qemu/bitmap.h" =20 #include "target/hexagon/reg_fields.h" +#include "hw/intc/hex-l2vic.h" =20 #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 @@ -198,6 +199,7 @@ struct ArchCPU { uint32_t boot_addr; HexagonGlobalRegState *globalregs; uint32_t htid; + HexL2VicInterface *l2vic; #endif }; =20 diff --git a/hw/intc/hex-l2vic.c b/hw/intc/hex-l2vic.c new file mode 100644 index 00000000000..6b2dc6bb091 --- /dev/null +++ b/hw/intc/hex-l2vic.c @@ -0,0 +1,532 @@ +/* + * QEMU L2VIC Interrupt Controller + * + * Arm PrimeCell PL190 Vector Interrupt Controller was used as a reference. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/irq.h" +#include "hw/core/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/lockable.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/bitmap.h" +#include "qemu/bitops.h" +#include "hw/intc/hex-l2vic.h" +#include "trace.h" + +static void bitmap32_write_word(uint32_t *bitmap, int word_offset, uint32_= t val) +{ + bitmap[word_offset] =3D val; +} + +static void bitmap32_clear_word(uint32_t *bitmap, int word_offset, + uint32_t mask) +{ + bitmap[word_offset] &=3D ~mask; +} + +static void bitmap32_set_word(uint32_t *bitmap, int word_offset, uint32_t = mask) +{ + bitmap[word_offset] |=3D mask; +} + +static uint32_t bitmap32_read_word(uint32_t *bitmap, int word_offset) +{ + return bitmap[word_offset]; +} + +OBJECT_DECLARE_SIMPLE_TYPE(HexL2VICState, HEX_L2VIC) + +#define SLICE_MAX (L2VIC_INTERRUPT_MAX / 32) +#define L2VIC_REG_RANGE_SIZE 0x80 + +typedef struct HexL2VICState { + SysBusDevice parent_obj; + + QemuMutex active; + MemoryRegion iomem; + MemoryRegion fast_iomem; + /* + * offset 0:vid group 0 etc, 10 bits in each group + * are used: + */ + uint32_t vid_group[4]; + uint32_t vid0; + /* Enable interrupt source */ + DECLARE_BITMAP32(int_enable, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + /* Present for debugging, not used */ + DECLARE_BITMAP32(int_pending, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + /* Which enabled interrupt is active */ + DECLARE_BITMAP32(int_status, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + /* Edge or Level interrupt */ + DECLARE_BITMAP32(int_type, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + /* L2 interrupt group 0-3 0x600-0x7FF */ + DECLARE_BITMAP32(int_group_n0, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + DECLARE_BITMAP32(int_group_n1, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + DECLARE_BITMAP32(int_group_n2, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + DECLARE_BITMAP32(int_group_n3, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + qemu_irq irq[8]; +} HexL2VICState; + +typedef enum { + L2VIC_OP_WRITE, + L2VIC_OP_CLEAR, + L2VIC_OP_SET, +} L2VicWriteOp; + +typedef struct { + hwaddr base; + size_t state_offset; + L2VicWriteOp write_op; + bool write_only; +} L2VicRegRange; + +static const L2VicRegRange l2vic_reg_ranges[] =3D { + { L2VIC_INT_ENABLEn, offsetof(HexL2VICState, int_enable), + L2VIC_OP_WRITE, false }, + { L2VIC_INT_ENABLE_CLEARn, offsetof(HexL2VICState, int_enable), + L2VIC_OP_CLEAR, true }, + { L2VIC_INT_ENABLE_SETn, offsetof(HexL2VICState, int_enable), + L2VIC_OP_SET, true }, + { L2VIC_INT_TYPEn, offsetof(HexL2VICState, int_type), + L2VIC_OP_WRITE, false }, + { L2VIC_INT_STATUSn, offsetof(HexL2VICState, int_status), + L2VIC_OP_WRITE, false }, + { L2VIC_INT_CLEARn, offsetof(HexL2VICState, int_status), + L2VIC_OP_CLEAR, true }, + { L2VIC_SOFT_INTn, offsetof(HexL2VICState, int_enable), + L2VIC_OP_SET, true }, + { L2VIC_INT_PENDINGn, offsetof(HexL2VICState, int_pending), + L2VIC_OP_WRITE, false }, + { L2VIC_INT_GRPn_0, offsetof(HexL2VICState, int_group_n0), + L2VIC_OP_WRITE, false }, + { L2VIC_INT_GRPn_1, offsetof(HexL2VICState, int_group_n1), + L2VIC_OP_WRITE, false }, + { L2VIC_INT_GRPn_2, offsetof(HexL2VICState, int_group_n2), + L2VIC_OP_WRITE, false }, + { L2VIC_INT_GRPn_3, offsetof(HexL2VICState, int_group_n3), + L2VIC_OP_WRITE, false }, +}; + +static uint32_t *l2vic_state_bitmap(HexL2VICState *s, size_t state_offset) +{ + return (uint32_t *)((char *)s + state_offset); +} + +static bool l2vic_reg_read_range(HexL2VICState *s, hwaddr offset, + uint64_t *value) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(l2vic_reg_ranges); i++) { + const L2VicRegRange *r =3D &l2vic_reg_ranges[i]; + + if (offset >=3D r->base && + offset < r->base + L2VIC_REG_RANGE_SIZE) { + if (r->write_only) { + *value =3D 0; + } else { + uint32_t *bitmap =3D l2vic_state_bitmap(s, r->state_offset= ); + *value =3D bitmap32_read_word(bitmap, + (offset - r->base) >> 2); + } + return true; + } + } + return false; +} + +static bool l2vic_reg_write_range(HexL2VICState *s, hwaddr offset, + uint32_t val) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(l2vic_reg_ranges); i++) { + const L2VicRegRange *r =3D &l2vic_reg_ranges[i]; + + if (offset >=3D r->base && + offset < r->base + L2VIC_REG_RANGE_SIZE) { + uint32_t *bitmap =3D l2vic_state_bitmap(s, r->state_offset); + int word =3D (offset - r->base) >> 2; + + switch (r->write_op) { + case L2VIC_OP_WRITE: + bitmap32_write_word(bitmap, word, val); + break; + case L2VIC_OP_CLEAR: + bitmap32_clear_word(bitmap, word, val); + break; + case L2VIC_OP_SET: + bitmap32_set_word(bitmap, word, val); + break; + default: + g_assert_not_reached(); + } + return true; + } + } + return false; +} + +/* + * Find out if this irq is associated with a group other than + * the default group + */ +static uint32_t *get_int_group(HexL2VICState *s, int irq) +{ + int n =3D irq & 0x1f; + if (n < 8) { + return s->int_group_n0; + } + if (n < 16) { + return s->int_group_n1; + } + if (n < 24) { + return s->int_group_n2; + } + return s->int_group_n3; +} + +static int find_slice(int irq) +{ + return irq / 32; +} + +static int get_vid(HexL2VICState *s, int irq) +{ + uint32_t *group =3D get_int_group(s, irq); + uint32_t slice =3D group[find_slice(irq)]; + /* Mask with 0x7 to remove the GRP:EN bit */ + uint32_t val =3D slice >> ((irq & 0x7) * 4); + if (val & 0x8) { + return val & 0x7; + } else { + return 0; + } +} + +static inline bool vid_active(HexL2VICState *s) +{ + /* scan all 1024 bits in int_status array */ + const uint32_t size =3D L2VIC_INTERRUPT_MAX; + const uint32_t active_irq =3D find_first_bit32(s->int_status, size); + return active_irq !=3D size; +} + +static bool l2vic_update(HexL2VICState *s, int irq) +{ + bool pending; + bool enable; + + if (vid_active(s)) { + return true; + } + + pending =3D test_bit32(irq, s->int_pending); + enable =3D test_bit32(irq, s->int_enable); + if (pending && enable) { + int vid =3D get_vid(s, irq); + set_bit32(irq, s->int_status); + clear_bit32(irq, s->int_pending); + /* + * Only auto-disable for edge-triggered interrupts (type=3D1). + * Level-triggered interrupts (type=3D0, the default) keep their + * enable bit set across deliveries -- the firmware enables once + * and expects the interrupt to remain enabled. + */ + if (test_bit32(irq, s->int_type)) { + clear_bit32(irq, s->int_enable); + } + s->vid0 =3D irq; + s->vid_group[vid] =3D irq; + + qemu_irq_pulse(s->irq[vid + 2]); + trace_hex_l2vic_delivered(irq, vid); + return true; + } + return false; +} + +static void l2vic_update_all(HexL2VICState *s) +{ + for (int i =3D 0; i < L2VIC_INTERRUPT_MAX; i++) { + if (l2vic_update(s, i)) { + /* once vid is active, no-one else can set it until ciad */ + return; + } + } +} + +static void l2vic_set_irq(void *opaque, int irq, int level) +{ + HexL2VICState *s =3D (HexL2VICState *)opaque; + + QEMU_LOCK_GUARD(&s->active); + if (level) { + set_bit32(irq, s->int_pending); + } + l2vic_update(s, irq); +} + +static void l2vic_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + HexL2VICState *s =3D (HexL2VICState *)opaque; + + QEMU_LOCK_GUARD(&s->active); + trace_hex_l2vic_reg_write((unsigned)offset, (uint32_t)val); + + if (!l2vic_reg_write_range(s, offset, val)) { + qemu_log_mask(LOG_UNIMP, + "%s: offset 0x%" HWADDR_PRIx " unimplemented\n", + __func__, offset); + } + + /* SOFT_INT also sets pending for edge-triggered interrupts */ + if (offset >=3D L2VIC_SOFT_INTn && + offset < L2VIC_SOFT_INTn + L2VIC_REG_RANGE_SIZE && val) { + int irq =3D ctz32((uint32_t)val); + irq +=3D ((offset - L2VIC_SOFT_INTn) >> 2) * 32; + + if (test_bit32(irq, s->int_type)) { + set_bit32(irq, s->int_pending); + } + } + + l2vic_update_all(s); +} + +static uint64_t l2vic_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t value; + HexL2VICState *s =3D (HexL2VICState *)opaque; + + QEMU_LOCK_GUARD(&s->active); + + if (offset <=3D L2VIC_VID_GRP_3) { + value =3D s->vid_group[offset >> 2]; + } else if (!l2vic_reg_read_range(s, offset, &value)) { + value =3D 0; + qemu_log_mask(LOG_GUEST_ERROR, + "L2VIC: %s: offset 0x%" HWADDR_PRIx "\n", __func__, + offset); + } + + trace_hex_l2vic_reg_read((unsigned)offset, (uint32_t)value); + return value; +} + +static const MemoryRegionOps l2vic_ops =3D { + .read =3D l2vic_read, + .write =3D l2vic_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +#define FASTL2VIC_ENABLE 0x0 +#define FASTL2VIC_DISABLE 0x1 +#define FASTL2VIC_INT 0x2 + +static void fastl2vic_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + if (offset =3D=3D 0) { + uint32_t cmd =3D (val >> 16) & 0x3; + uint32_t irq =3D val & 0x3ff; + uint32_t slice =3D (irq / 32) * 4; + val =3D 1 << (irq % 32); + + if (cmd =3D=3D FASTL2VIC_ENABLE) { + l2vic_write(opaque, L2VIC_INT_ENABLE_SETn + slice, val, size); + } else if (cmd =3D=3D FASTL2VIC_DISABLE) { + l2vic_write(opaque, L2VIC_INT_ENABLE_CLEARn + slice, val, size= ); + } else if (cmd =3D=3D FASTL2VIC_INT) { + l2vic_write(opaque, L2VIC_SOFT_INTn + slice, val, size); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid write cmd %" PRId32 "\n", + __func__, cmd); + } + return; + } + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid write offset 0x%08" HWADDR= _PRIx + "\n", __func__, offset); +} + +static const MemoryRegionOps fastl2vic_ops =3D { + .write =3D fastl2vic_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +/* L2VIC Interface Implementation */ +static uint32_t l2vic_interface_read_vid_impl(HexL2VicInterface *iface, + uint32_t group) +{ + HexL2VICState *s =3D HEX_L2VIC(iface); + uint32_t result =3D 0; + + QEMU_LOCK_GUARD(&s->active); + if (group =3D=3D 0) { + /* VID register: VID1 (bits 16-31), VID0 (bits 0-15) */ + result =3D deposit32(result, 0, 16, s->vid_group[0]); + result =3D deposit32(result, 16, 16, s->vid_group[1]); + } else if (group =3D=3D 1) { + /* VID1 register: VID3 (bits 16-31), VID2 (bits 0-15) */ + result =3D deposit32(result, 0, 16, s->vid_group[2]); + result =3D deposit32(result, 16, 16, s->vid_group[3]); + } + return result; +} + +static void l2vic_interface_update_vid_impl(HexL2VicInterface *iface, + uint32_t group, uint32_t value) +{ + HexL2VICState *s =3D HEX_L2VIC(iface); + + QEMU_LOCK_GUARD(&s->active); + + if (group =3D=3D 0) { + /* VID register: unpack VID0 and VID1 */ + s->vid_group[0] =3D extract32(value, 0, 16); + s->vid_group[1] =3D extract32(value, 16, 16); + } else if (group =3D=3D 1) { + /* VID1 register: unpack VID2 and VID3 */ + s->vid_group[2] =3D extract32(value, 0, 16); + s->vid_group[3] =3D extract32(value, 16, 16); + } + + l2vic_update_all(s); +} + +static void l2vic_interface_clear_interrupt_impl(HexL2VicInterface *iface) +{ + HexL2VICState *s =3D HEX_L2VIC(iface); + + QEMU_LOCK_GUARD(&s->active); + if (s->vid0 < L2VIC_INTERRUPT_MAX) { + clear_bit32(s->vid0, s->int_status); + } + l2vic_update_all(s); +} + +static void l2vic_reset_hold(Object *obj, ResetType type G_GNUC_UNUSED) +{ + HexL2VICState *s =3D HEX_L2VIC(obj); + + QEMU_LOCK_GUARD(&s->active); + memset(s->int_enable, 0, sizeof(s->int_enable)); + memset(s->int_pending, 0, sizeof(s->int_pending)); + memset(s->int_status, 0, sizeof(s->int_status)); + memset(s->int_type, 0, sizeof(s->int_type)); + memset(s->int_group_n0, 0, sizeof(s->int_group_n0)); + memset(s->int_group_n1, 0, sizeof(s->int_group_n1)); + memset(s->int_group_n2, 0, sizeof(s->int_group_n2)); + memset(s->int_group_n3, 0, sizeof(s->int_group_n3)); + memset(s->vid_group, 0, sizeof(s->vid_group)); + s->vid0 =3D 0; + + l2vic_update_all(s); +} + +static void reset_irq_handler(void *opaque, int irq, int level) +{ + Object *obj =3D OBJECT(opaque); + + if (level) { + l2vic_reset_hold(obj, RESET_TYPE_COLD); + } +} + +static void l2vic_init(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + HexL2VICState *s =3D HEX_L2VIC(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + int i; + + memory_region_init_io(&s->iomem, obj, &l2vic_ops, s, "l2vic", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); + memory_region_init_io(&s->fast_iomem, obj, &fastl2vic_ops, s, "fast", + 0x10000); + sysbus_init_mmio(sbd, &s->fast_iomem); + + qdev_init_gpio_in(dev, l2vic_set_irq, L2VIC_INTERRUPT_MAX); + qdev_init_gpio_in_named(dev, reset_irq_handler, "reset", 1); + for (i =3D 0; i < 8; i++) { + sysbus_init_irq(sbd, &s->irq[i]); + } + qemu_mutex_init(&s->active); +} + +static const VMStateDescription vmstate_l2vic =3D { + .name =3D "l2vic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D + (VMStateField[]){ + VMSTATE_UINT32_ARRAY(vid_group, HexL2VICState, 4), + VMSTATE_UINT32(vid0, HexL2VICState), + VMSTATE_UINT32_ARRAY(int_enable, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_type, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_status, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_pending, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n0, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n1, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n2, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n3, HexL2VICState, SLICE_MAX), + VMSTATE_END_OF_LIST() } +}; + +static void l2vic_interface_class_init(ObjectClass *klass, const void *dat= a) +{ + HexL2VicInterfaceClass *k =3D HEX_L2VIC_INTERFACE_CLASS(klass); + + k->read_vid =3D l2vic_interface_read_vid_impl; + k->update_vid =3D l2vic_interface_update_vid_impl; + k->clear_interrupt =3D l2vic_interface_clear_interrupt_impl; +} + +static void l2vic_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->vmsd =3D &vmstate_l2vic; + rc->phases.hold =3D l2vic_reset_hold; +} + +static const TypeInfo l2vic_interface_info =3D { + .name =3D TYPE_HEX_L2VIC_INTERFACE, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(HexL2VicInterfaceClass), + .class_init =3D l2vic_interface_class_init, +}; + +static const TypeInfo l2vic_info =3D { + .name =3D TYPE_HEX_L2VIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(HexL2VICState), + .instance_init =3D l2vic_init, + .class_init =3D l2vic_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HEX_L2VIC_INTERFACE }, + { } + }, +}; + +static void l2vic_register_types(void) +{ + type_register_static(&l2vic_interface_info); + type_register_static(&l2vic_info); +} + +type_init(l2vic_register_types) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 42d93e5da47..be56ac0419f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -65,6 +65,8 @@ static const Property hexagon_cpu_properties[] =3D { DEFINE_PROP_LINK("tlb", HexagonCPU, tlb, TYPE_HEXAGON_TLB, HexagonTLBState *), DEFINE_PROP_UINT32("exec-start-addr", HexagonCPU, boot_addr, 0xfffffff= f), + DEFINE_PROP_LINK("l2vic", HexagonCPU, l2vic, + TYPE_HEX_L2VIC_INTERFACE, HexL2VicInterface *), DEFINE_PROP_LINK("global-regs", HexagonCPU, globalregs, TYPE_HEXAGON_GLOBALREG, HexagonGlobalRegState *), DEFINE_PROP_UINT32("htid", HexagonCPU, htid, 0), diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 125952aee59..0d88ae65e75 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -40,6 +40,7 @@ #include "hw/hexagon/hexagon_globalreg.h" #include "hex_mmu.h" #include "hw/hexagon/hexagon_tlb.h" +#include "hw/intc/hex-l2vic.h" #include "hex_interrupts.h" #include "hexswi.h" #endif @@ -1557,7 +1558,25 @@ void HELPER(raise_stack_overflow)(CPUHexagonState *e= nv, uint32_t slot, =20 void HELPER(ciad)(CPUHexagonState *env, uint32_t mask) { - g_assert_not_reached(); + uint32_t ipendad; + uint32_t iad; + HexagonCPU *cpu; + + BQL_LOCK_GUARD(); + cpu =3D env_archcpu(env); + ipendad =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId) : 0; + iad =3D fGET_FIELD(ipendad, IPENDAD_IAD); + fSET_FIELD(ipendad, IPENDAD_IAD, iad & ~(mask)); + if (cpu->globalregs) { + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); + } + if (cpu->l2vic) { + l2vic_clear_interrupt(cpu->l2vic); + } + hex_interrupt_update(env); } =20 void HELPER(siad)(CPUHexagonState *env, uint32_t mask) diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index 52065ab3b22..191c6c5d65c 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -2,6 +2,7 @@ config HEX_DSP bool default y depends on HEXAGON + select HEX_L2VIC =20 config HEX_VIRT bool diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 636d00b7e88..097de4efc5d 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -8,6 +8,9 @@ config I8259 config PL190 bool =20 +config HEX_L2VIC + bool + config IOAPIC bool select I8259 diff --git a/hw/intc/meson.build b/hw/intc/meson.build index fac2d228f9b..9077a3f3297 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -74,6 +74,8 @@ specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('x= ics_spapr.c', 'spapr_xi specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) + +specific_ss.add(when: 'CONFIG_HEX_L2VIC', if_true: files('hex-l2vic.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongs= on_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.= c')) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index e7d6c304487..7512c6e6004 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -337,6 +337,10 @@ sh_intc_register(const char *s, int id, unsigned short= v, int c, int m) "%s %u - sh_intc_read(unsigned size, uint64_t offset, unsigned long val) "size %u 0= x%" PRIx64 " -> 0x%lx" sh_intc_write(unsigned size, uint64_t offset, unsigned long val) "size %u = 0x%" PRIx64 " <- 0x%lx" sh_intc_set(int id, int enable) "setting interrupt group %d to %d" +# hex-l2vic.c +hex_l2vic_reg_write(unsigned int addr, uint32_t value) "addr: 0x%03x value= : 0x%08"PRIx32 +hex_l2vic_reg_read(unsigned int addr, uint32_t value) "addr: 0x%03x value:= 0x%08"PRIx32 +hex_l2vic_delivered(int irq, int vid) "l2vic: delivered %d (vid %d)" =20 # loongson_ipi.c loongson_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u ad= dr: 0x%"PRIx64 "val: 0x%"PRIx64 --=20 2.34.1 From nobody Sat Jul 25 16:49:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784141969059158500 Instantiate the L2VIC device in both machine models, map its slow and MMIO regions, and link it to each CPU via the "l2vic" property. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon.h | 1 + include/hw/hexagon/hexagon_globalreg.h | 4 +++ hw/hexagon/hexagon_dsp.c | 20 +++++++++++++ hw/hexagon/hexagon_globalreg.c | 41 ++++++++++++++++++++++---- hw/hexagon/virt.c | 22 ++++++++++++++ 5 files changed, 83 insertions(+), 5 deletions(-) diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 1034b09c2ac..6753ae32cde 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -156,6 +156,7 @@ struct HexagonCommonMachineState { =20 MemoryRegion ram; MemoryRegion cfgtable_rom; + DeviceState *l2vic_dev; }; =20 #endif diff --git a/include/hw/hexagon/hexagon_globalreg.h b/include/hw/hexagon/he= xagon_globalreg.h index 950099808fd..397dc6854c9 100644 --- a/include/hw/hexagon/hexagon_globalreg.h +++ b/include/hw/hexagon/hexagon_globalreg.h @@ -10,6 +10,7 @@ =20 #include "hw/core/qdev.h" #include "hw/core/sysbus.h" +#include "hw/intc/hex-l2vic.h" #include "qom/object.h" #include "target/hexagon/cpu.h" =20 @@ -22,6 +23,9 @@ struct HexagonGlobalRegState { /* Array of system registers */ uint32_t regs[NUM_SREGS]; =20 + /* L2VIC interface used to back the VID/VID1 registers */ + HexL2VicInterface *l2vic; + /* Global performance cycle counter base */ uint64_t g_pcycle_base; =20 diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c index aa493993229..4cf88627c8f 100644 --- a/hw/hexagon/hexagon_dsp.c +++ b/hw/hexagon/hexagon_dsp.c @@ -16,6 +16,7 @@ #include "hw/hexagon/hexagon.h" #include "hw/hexagon/hexagon_globalreg.h" #include "hw/hexagon/hexagon_tlb.h" +#include "hw/intc/hex-l2vic.h" #include "hw/core/loader.h" #include "qapi/error.h" #include "qemu/error-report.h" @@ -111,6 +112,7 @@ static void hexagon_common_init(MachineState *machine, = Rev_t rev, MemoryRegion *address_space; DeviceState *glob_regs_dev; DeviceState *tlb_dev; + DeviceState *cpu0 =3D NULL; =20 memset(&hexagon_binfo, 0, sizeof(hexagon_binfo)); if (machine->kernel_filename) { @@ -131,11 +133,21 @@ static void hexagon_common_init(MachineState *machine= , Rev_t rev, machine->ram_size, &error_fatal); memory_region_add_subregion(address_space, 0x0, &hms->ram); =20 + hms->l2vic_dev =3D qdev_new(TYPE_HEX_L2VIC); + object_property_add_child(OBJECT(machine), "l2vic", + OBJECT(hms->l2vic_dev)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(hms->l2vic_dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(hms->l2vic_dev), 0, m_cfg->l2vic_base); + sysbus_mmio_map(SYS_BUS_DEVICE(hms->l2vic_dev), 1, + m_cfg->cfgtable.fastl2vic_base << 16); + glob_regs_dev =3D qdev_new(TYPE_HEXAGON_GLOBALREG); object_property_add_child(OBJECT(machine), "global-regs", OBJECT(glob_regs_dev)); qdev_prop_set_uint64(glob_regs_dev, "config-table-addr", m_cfg->cfgbas= e); qdev_prop_set_uint32(glob_regs_dev, "dsp-rev", rev); + object_property_set_link(OBJECT(glob_regs_dev), "l2vic", + OBJECT(hms->l2vic_dev), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(glob_regs_dev), &error_fatal); =20 tlb_dev =3D qdev_new(TYPE_HEXAGON_TLB); @@ -154,15 +166,23 @@ static void hexagon_common_init(MachineState *machine= , Rev_t rev, */ qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", (i !=3D 0)); if (i =3D=3D 0) { + cpu0 =3D DEVICE(cpu); hexagon_init_bootstrap(dms, cpu); } object_property_set_link(OBJECT(cpu), "global-regs", OBJECT(glob_regs_dev), &error_fatal); object_property_set_link(OBJECT(cpu), "tlb", OBJECT(tlb_dev), &error_fatal); + object_property_set_link(OBJECT(cpu), "l2vic", + OBJECT(hms->l2vic_dev), &error_fatal); qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); } =20 + for (int i =3D 0; i < 8; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(hms->l2vic_dev), i, + qdev_get_gpio_in(cpu0, i)); + } + rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable, sizeof(m_cfg->cfgtable), m_cfg->cfgbase, &address_space_memory); diff --git a/hw/hexagon/hexagon_globalreg.c b/hw/hexagon/hexagon_globalreg.c index b5e5913507e..3d0d6f9516c 100644 --- a/hw/hexagon/hexagon_globalreg.c +++ b/hw/hexagon/hexagon_globalreg.c @@ -11,6 +11,7 @@ #include "hw/core/qdev-properties.h" #include "hw/core/sysbus.h" #include "hw/core/resettable.h" +#include "hw/intc/hex-l2vic.h" #include "migration/vmstate.h" #include "qom/object.h" #include "target/hexagon/cpu.h" @@ -135,6 +136,32 @@ static inline uint32_t apply_write_mask(uint32_t new_v= al, uint32_t cur_val, return new_val; } =20 +static inline bool is_vid_reg(uint32_t reg) +{ + return reg =3D=3D HEX_SREG_VID || reg =3D=3D HEX_SREG_VID1; +} + +/* + * HEX_SREG_VID/VID1 are backed by the L2VIC's VID group registers + * rather than the plain regs[] array, when an L2VIC is wired up. + */ +static uint32_t get_reg_value(HexagonGlobalRegState *s, uint32_t reg) +{ + if (is_vid_reg(reg) && s->l2vic) { + return l2vic_read_vid(s->l2vic, reg =3D=3D HEX_SREG_VID ? 0 : 1); + } + return s->regs[reg]; +} + +static void set_reg_value(HexagonGlobalRegState *s, uint32_t reg, + uint32_t value) +{ + s->regs[reg] =3D value; + if (is_vid_reg(reg) && s->l2vic) { + l2vic_update_vid(s->l2vic, reg =3D=3D HEX_SREG_VID ? 0 : 1, value); + } +} + uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg, uint32_t htid) { @@ -146,7 +173,7 @@ uint32_t hexagon_globalreg_read(HexagonGlobalRegState *= s, uint32_t reg, g_assert(reg < NUM_SREGS); g_assert(reg >=3D HEX_SREG_GLB_START); =20 - value =3D s->regs[reg]; + value =3D get_reg_value(s, reg); =20 trace_hexagon_globalreg_read(htid, get_sreg_name(reg), value); return value; @@ -160,7 +187,7 @@ void hexagon_globalreg_write(HexagonGlobalRegState *s, = uint32_t reg, } g_assert(reg < NUM_SREGS); g_assert(reg >=3D HEX_SREG_GLB_START); - s->regs[reg] =3D value; + set_reg_value(s, reg, value); trace_hexagon_globalreg_write(htid, get_sreg_name(reg), value); } =20 @@ -168,6 +195,7 @@ uint32_t hexagon_globalreg_masked_value(HexagonGlobalRe= gState *s, uint32_t reg, uint32_t value) { uint32_t reg_mask; + uint32_t cur_val; =20 if (!s) { return value; @@ -175,9 +203,10 @@ uint32_t hexagon_globalreg_masked_value(HexagonGlobalR= egState *s, uint32_t reg, g_assert(reg < NUM_SREGS); g_assert(reg >=3D HEX_SREG_GLB_START); reg_mask =3D global_sreg_immut_masks[reg]; + cur_val =3D get_reg_value(s, reg); return reg_mask =3D=3D IMMUTABLE ? - s->regs[reg] : - apply_write_mask(value, s->regs[reg], reg_mask); + cur_val : + apply_write_mask(value, cur_val, reg_mask); } =20 void hexagon_globalreg_write_masked(HexagonGlobalRegState *s, uint32_t reg, @@ -186,7 +215,7 @@ void hexagon_globalreg_write_masked(HexagonGlobalRegSta= te *s, uint32_t reg, if (!s) { return; } - s->regs[reg] =3D hexagon_globalreg_masked_value(s, reg, value); + set_reg_value(s, reg, hexagon_globalreg_masked_value(s, reg, value)); } =20 uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s) @@ -275,6 +304,8 @@ static const VMStateDescription vmstate_hexagon_globalr= eg =3D { }; =20 static const Property hexagon_globalreg_properties[] =3D { + DEFINE_PROP_LINK("l2vic", HexagonGlobalRegState, l2vic, + TYPE_HEX_L2VIC_INTERFACE, HexL2VicInterface *), DEFINE_PROP_UINT32("boot-evb", HexagonGlobalRegState, boot_evb, 0x0), DEFINE_PROP_UINT64("config-table-addr", HexagonGlobalRegState, config_table_addr, 0xffffffffULL), diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c index a3638998b87..2256d3d53a5 100644 --- a/hw/hexagon/virt.c +++ b/hw/hexagon/virt.c @@ -15,6 +15,7 @@ #include "hw/hexagon/hexagon.h" #include "hw/hexagon/hexagon_globalreg.h" #include "hw/hexagon/hexagon_tlb.h" +#include "hw/intc/hex-l2vic.h" #include "hw/core/loader.h" #include "hw/core/qdev-properties.h" #include "hw/core/qdev-clock.h" @@ -268,10 +269,22 @@ static void virt_init(MachineState *ms) &vms->parent_obj.cfgtable_rom); fdt_add_hvx(vms, m_cfg); =20 + vms->parent_obj.l2vic_dev =3D qdev_new(TYPE_HEX_L2VIC); + object_property_add_child(OBJECT(ms), "l2vic", + OBJECT(vms->parent_obj.l2vic_dev)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(vms->parent_obj.l2vic_dev), + &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(vms->parent_obj.l2vic_dev), 0, + m_cfg->l2vic_base); + sysbus_mmio_map(SYS_BUS_DEVICE(vms->parent_obj.l2vic_dev), 1, + m_cfg->cfgtable.fastl2vic_base << 16); + gsregs_dev =3D qdev_new(TYPE_HEXAGON_GLOBALREG); object_property_add_child(OBJECT(ms), "global-regs", OBJECT(gsregs_dev= )); qdev_prop_set_uint64(gsregs_dev, "config-table-addr", m_cfg->cfgbase); qdev_prop_set_uint32(gsregs_dev, "dsp-rev", v68_rev); + object_property_set_link(OBJECT(gsregs_dev), "l2vic", + OBJECT(vms->parent_obj.l2vic_dev), &error_fat= al); sysbus_realize_and_unref(SYS_BUS_DEVICE(gsregs_dev), &error_fatal); =20 tlb_dev =3D qdev_new(TYPE_HEXAGON_TLB); @@ -301,9 +314,18 @@ static void virt_init(MachineState *ms) OBJECT(gsregs_dev), &error_fatal); object_property_set_link(OBJECT(cpu), "tlb", OBJECT(tlb_dev), &error_fatal); + object_property_set_link(OBJECT(cpu), "l2vic", + OBJECT(vms->parent_obj.l2vic_dev), + &error_fatal); =20 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); } + + for (int i =3D 0; i < 8; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(vms->parent_obj.l2vic_dev), i, + qdev_get_gpio_in(cpu0, i)); + } + fdt_add_cpu_nodes(vms); clk_phandle =3D fdt_add_clocks(vms); fdt_add_uart(vms, VIRT_UART0, clk_phandle); --=20 2.34.1 From nobody Sat Jul 25 16:49:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784141868; cv=none; d=zohomail.com; s=zohoarc; b=ApICzWrA2xvEEdEPq2uw2pgzCxPHz7yHkNGr6BtjTRTMhaaCL5/XwoZKhmE8kotqsgdcy93rn+fwu1oVQDNPGRFmIrS/q9H6p01/qUlEaOQhz8QCtZIEsk1Keg5h01sDlUqHddPHDwb4WHqQX+a5JUTXa53jQO7tXjcLdloNs50= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784141870501158500 Add a qtest exercising the L2VIC interrupt controller's basic register access and interrupt enable/disable behavior. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- MAINTAINERS | 1 + tests/qtest/l2vic-test.c | 242 +++++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 2 +- 3 files changed, 244 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/l2vic-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 7281a281632..b7012e945e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -252,6 +252,7 @@ S: Supported F: target/hexagon/ F: hw/intc/hex-l2vic.c F: include/hw/intc/hex-l2vic.h +F: tests/qtest/l2vic-test.c X: target/hexagon/idef-parser/ X: target/hexagon/gen_idef_parser_funcs.py F: linux-user/hexagon/ diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c new file mode 100644 index 00000000000..9887e458a6f --- /dev/null +++ b/tests/qtest/l2vic-test.c @@ -0,0 +1,242 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + * + * QTest testcase for the L2VIC Interrupt Controller + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" +#include "hw/intc/hex-l2vic.h" + +/* Base addresses for L2VIC */ +#define L2VIC_BASE 0xfc910000 +#define L2VIC_FAST_BASE 0xfc920000 + +/* Helper functions */ +static uint32_t l2vic_read32(uint64_t base, uint32_t offset) +{ + return readl(base + offset); +} + +static void l2vic_write32(uint64_t base, uint32_t offset, uint32_t value) +{ + writel(base + offset, value); +} + +/* Test basic register access */ +static void test_l2vic_register_access(void) +{ + uint32_t val; + + /* Test that basic registers can be read/written */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + /* Should have enabled interrupt 0 */ + g_assert_cmpuint(val & 0x1, =3D=3D, 0x1); + + /* Clear it */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + /* Should be cleared now */ + g_assert_cmpuint(val & 0x1, =3D=3D, 0x0); +} + +/* Test interrupt enable/disable */ +static void test_l2vic_interrupt_enable(void) +{ + uint32_t val; + + /* Initially all interrupts should be disabled */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + g_assert_cmpuint(val, =3D=3D, 0); + + /* Enable some interrupts */ + /* Enable IRQ 0 and 2 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x5); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + g_assert_cmpuint(val & 0x5, =3D=3D, 0x5); + + /* Disable one */ + /* Disable IRQ 0 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + g_assert_cmpuint(val & 0x1, =3D=3D, 0x0); /* IRQ 0 should be disabled= */ + g_assert_cmpuint(val & 0x4, =3D=3D, 0x4); /* IRQ 2 should still be en= abled */ +} + +/* Test register read/write without triggering interrupts */ +static void test_l2vic_basic_functionality(void) +{ + l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + l2vic_read32(L2VIC_BASE, L2VIC_INT_PENDINGn); + l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + l2vic_read32(L2VIC_BASE, L2VIC_INT_TYPEn); + + /* Exercise write-only registers */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0); +} + +/* + * Test L2VIC IRQ outputs + */ +static void test_l2vic_irq_outputs(void) +{ + uint32_t val; + + /* Clear any previous configuration */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0xFFFFFFFF); + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0xFFFFFFFF); + /* Reset all to level-triggered */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0); + + /* Test Group 0 interrupts (default group: IRQ2) */ + /* Configure interrupt 0 as edge-triggered (required for soft interrup= ts) */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x1); + /* Enable interrupt 0 and generate software interrupt */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x1); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x1); + + /* Verify interrupt is active (would assert IRQ2 in real hardware) */ + /* In L2VIC: pending interrupts become active and clear from pending */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x1, =3D=3D, 0x1); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x1, =3D=3D, 0x0); + + /* Test Group 1 interrupts: IRQ3 */ + /* Configure interrupt 1 as edge-triggered and to group 1 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x2); + /* Set bit 1 for interrupt 1 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_1, 0x2); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x2); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x2); + + /* Verify interrupt is active in group 1 (would assert IRQ3) */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x2, =3D=3D, 0x2); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_GRPn_1); + g_assert_cmpuint(val & 0x2, =3D=3D, 0x2); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x2); + + /* Test Group 2 interrupts: IRQ4 */ + /* Configure interrupt 2 as edge-triggered and to group 2 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x4); + /* Set bit 2 for interrupt 2 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_2, 0x4); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x4); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x4); + + /* Verify interrupt is active in group 2 (would assert IRQ4) */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x4, =3D=3D, 0x4); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_GRPn_2); + g_assert_cmpuint(val & 0x4, =3D=3D, 0x4); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x4); + + /* Test Group 3 interrupts: IRQ5 */ + /* Configure interrupt 3 as edge-triggered and to group 3 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x8); + /* Set bit 3 for interrupt 3 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_3, 0x8); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x8); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x8); + + /* Verify interrupt is active in group 3 (would assert IRQ5) */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x8, =3D=3D, 0x8); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_GRPn_3); + g_assert_cmpuint(val & 0x8, =3D=3D, 0x8); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x8); + + /* Test multiple pending interrupts (only one can be active at a time)= */ + /* Configure all interrupts 0-3 as edge-triggered */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0xF); + /* Enable interrupts 0-3 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0xF); + /* Generate all 4 interrupts */ + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0xF); + + /* Verify that highest prio interrupt becomes active */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + /* At least one bit should be set, but not necessarily all */ + g_assert_cmpuint(val & 0xF, !=3D, 0x0); + + /* Clear all active interrupts */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, val & 0xF); + + /* After clearing, check if more interrupts become active */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + /* Could be 0 if all processed, or have more if pending */ + + /* Test that software interrupts require edge-triggered configuration = */ + /* Configure interrupt 5 as level-triggered (default) */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x0); + /* Enable interrupt 5 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x20); + /* Try to generate level interrupt */ + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x20); + + /* Should not work - no interrupt should be active */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + /* No interrupt because level-triggered */ + g_assert_cmpuint(val & 0x20, =3D=3D, 0x0); + + /* Now configure as edge-triggered and try again */ + /* Set edge-triggered */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x20); + /* Generate interrupt */ + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x20); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x20, =3D=3D, 0x20); + + /* Clean up - clear all configuration */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0xFFFFFFFF); + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0xFFFFFFFF); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_0, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_1, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_2, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_3, 0); +} + +static void test_l2vic_on_machine(gconstpointer data) +{ + const char *machine =3D (const char *)data; + g_autofree char *args =3D g_strdup_printf("-machine %s", machine); + + qtest_start(args); + + /* Run all the L2VIC tests */ + test_l2vic_register_access(); + test_l2vic_interrupt_enable(); + test_l2vic_basic_functionality(); + test_l2vic_irq_outputs(); + + qtest_end(); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + /* Test on virt machine */ + qtest_add_data_func("/l2vic/virt/all-tests", "virt", + test_l2vic_on_machine); + + /* Test on V66G_1024 machine */ + qtest_add_data_func("/l2vic/V66G_1024/all-tests", "V66G_1024", + test_l2vic_on_machine); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 56ff860e216..a76863c7dd6 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -299,7 +299,7 @@ qtests_riscv64 =3D ['riscv-csr-test'] + \ ['iommu-riscv-test'] : []) + \ (config_all_devices.has_key('CONFIG_K230') ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784141880620158500 Add new test cases from hexagon-arch-tests to exercise exceptions, guest mode, interrupt steering, etc. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- MAINTAINERS | 1 + tests/functional/hexagon/meson.build | 5 ++ tests/functional/hexagon/test_arch_tests.py | 63 +++++++++++++++++++++ tests/functional/meson.build | 1 + 4 files changed, 70 insertions(+) create mode 100644 tests/functional/hexagon/meson.build create mode 100755 tests/functional/hexagon/test_arch_tests.py diff --git a/MAINTAINERS b/MAINTAINERS index b7012e945e2..b96d8f43fff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1361,6 +1361,7 @@ F: hw/hexagon/ F: include/hw/hexagon/ F: configs/devices/hexagon-softmmu/default.mak F: docs/system/hexagon/ +F: tests/functional/hexagon/ F: docs/devel/hexagon-sys.rst =20 LoongArch Machines diff --git a/tests/functional/hexagon/meson.build b/tests/functional/hexago= n/meson.build new file mode 100644 index 00000000000..2b5a1a8f264 --- /dev/null +++ b/tests/functional/hexagon/meson.build @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +tests_hexagon_system_thorough =3D [ + 'arch_tests', +] diff --git a/tests/functional/hexagon/test_arch_tests.py b/tests/functional= /hexagon/test_arch_tests.py new file mode 100755 index 00000000000..2bb34f9b8dc --- /dev/null +++ b/tests/functional/hexagon/test_arch_tests.py @@ -0,0 +1,63 @@ +#!/usr/bin/env python3 +# +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import QemuSystemTest, Asset +from qemu_test.cmd import wait_for_console_pattern + + +class ArchTestsUart(QemuSystemTest): + """ + Hexagon architecture verification tests + + These are bare-metal tests from hexagon-arch-tests that exercise + system functionality. + + Tests output results via UART. + """ + timeout =3D 60 + + ASSET_TARBALL =3D Asset( + "https://github.com/qualcomm/qemu-hexagon-testing/releases/" + "download/v0.2.5/arch_tests_uart.tar.gz", + "edb4f37b877a3a72a0e10920477458a43b40045d34398fee8cb763fefd342f4f", + ) + + def run_uart_test(self, test_name: str, + machine: str =3D "virt") -> None: + """ + Run an arch test binary and verify PASS via UART console output. + """ + self.set_machine(machine) + self.archive_extract(self.ASSET_TARBALL) + target_bin =3D self.scratch_file('arch_tests_uart_package', + 'bin', test_name) + self.vm.set_console() + self.set_vm_arg("-display", "none") + self.set_vm_arg("-kernel", target_bin) + self.vm.launch() + wait_for_console_pattern(self, "PASS") + + def test_exceptions(self) -> None: + """Tests exception delivery for trap instructions, privilege + violations, and verifies SSR cause codes and ELR values. + """ + self.run_uart_test("test_exceptions") + + def test_guest_mode(self) -> None: + """Tests guest mode entry/exit via CCR configuration, verifying + GSR fields, GELR, and guest event vector table dispatch. + """ + self.run_uart_test("test_guest_mode") + + def test_int_steering(self) -> None: + """Tests interrupt steering via priority-based routing to + specific threads using STID priority and iassignw. + """ + self.run_uart_test("test_int_steering") + + +if __name__ =3D=3D "__main__": + QemuSystemTest.main() diff --git a/tests/functional/meson.build b/tests/functional/meson.build index c158197c4b7..c7362dd00ef 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -14,6 +14,7 @@ subdir('aarch64') subdir('alpha') subdir('arm') subdir('avr') +subdir('hexagon') subdir('hppa') subdir('i386') subdir('loongarch64') --=20 2.34.1