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bh=R5roSOjIvXkZzxUg80HnEUwbsRLnFkDsyeHT0J+U5BY=; b=JM7KtcJ6Hewq51nHIXwv2A89X019wInT9qt/IIS/Lu0SDDIVqtgSE8DWizifuso002LSUsOiiN7OCjsxD1xHz9LKUDhSjlPIxCQJ8Ume2BYMcPAoLfYc3wZVLviCNNmYpEmAxbfse5QyCMWeJ50qcfbegQ2U/vis7kRZwbes2dT5M8cn0FRtJiRBMJGf7+Ujv958QrCi2vKLDScuCLI2a0G+surnouGg6378O4YUC6jlGpaVlir5hh2zL9GlnNvVuFDyMWM4ZMCRGgv/PmupCpji7Uc+Xd1zq8gfqYghTspF802hTiV7W0/ajt7uNxGoNiOUZq9uXJUJ4zDHrqWxhg== From: Jamin Lin To: =?iso-8859-1?Q?Daniel_P=2E_Berrang=E9?= , =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Eric Blake , Markus Armbruster , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: Jamin Lin , Troy Lee Subject: [PATCH v2 03/17] hw/misc/aspeed_hace: Support scatter-gather mode for the crypto command Thread-Topic: [PATCH v2 03/17] hw/misc/aspeed_hace: Support scatter-gather mode for the crypto command Thread-Index: AQHdFAqtgjMZaWWo4kmP72LwW7wHfg== Date: Wed, 15 Jul 2026 03:33:17 +0000 Message-ID: <20260715033311.1648424-4-jamin_lin@aspeedtech.com> References: <20260715033311.1648424-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260715033311.1648424-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=jamin_lin@aspeedtech.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @aspeedtech.com) X-ZM-MESSAGEID: 1784086578554158500 Content-Type: text/plain; charset="utf-8" The AST2600 and later crypto engines drive the source and destination through scatter-gather lists (HACE10[18]/[19]) rather than the single contiguous buffers used by the AST2500 direct access mode. Each SG list entry is a length word (SG_LIST_LEN_LAST marks the final entry) followed by a DRAM address, matching the hash engine layout. Add a crypt_prepare_sg() helper that gathers the source into / scatters the destination out of the bounce buffer by walking the SG list, and select it or the existing crypt_prepare_direct() from do_crypt_operation based on HACE10[18], mirroring the hash engine's direct/scatter-gather dispatch. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 70 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 64 insertions(+), 6 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index de4399f322..3d3f1fc8dd 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -610,13 +610,58 @@ static bool crypt_prepare_direct(AspeedHACEState *s, = uint64_t addr, } =20 /* - * Perform an AES/DES/3DES ECB/CBC operation in direct access mode: the so= urce - * and destination are single contiguous buffers (HACE00/HACE04) and the I= V/key - * come from the context buffer (HACE08). For CBC the resulting chaining I= V is - * written back to the context buffer so the driver can continue the chain. + * Scatter-gather mode: the source/destination register points at an SG li= st + * whose entries are a length word (SG_LIST_LEN_LAST flags the final entry) + * followed by a DRAM address, matching the hash engine layout. Gather @len + * bytes into @buf, or scatter @buf back out when @to_dram is true. + * Returns true on success. + */ +static bool crypt_prepare_sg(AspeedHACEState *s, uint64_t addr, + uint8_t *buf, uint32_t len, bool to_dram) +{ + uint32_t copied =3D 0; + uint32_t sg_addr; + uint32_t sg_len; + uint32_t entry; + int i; + + for (i =3D 0; i < ASPEED_HACE_MAX_SG && copied < len; i++) { + entry =3D address_space_ldl_le(&s->dram_as, addr, + MEMTXATTRS_UNSPECIFIED, NULL); + sg_addr =3D address_space_ldl_le(&s->dram_as, addr + SG_LIST_LEN_S= IZE, + MEMTXATTRS_UNSPECIFIED, NULL); + sg_len =3D entry & SG_LIST_LEN_MASK; + + sg_addr &=3D SG_LIST_ADDR_MASK; + addr +=3D SG_LIST_ENTRY_SIZE; + + if (sg_len > len - copied) { + sg_len =3D len - copied; + } + if (address_space_rw(&s->dram_as, sg_addr, MEMTXATTRS_UNSPECIFIED, + buf + copied, sg_len, to_dram)) { + return false; + } + copied +=3D sg_len; + + if (entry & SG_LIST_LEN_LAST) { + break; + } + } + + return copied =3D=3D len; +} + +/* + * Perform an AES/DES/3DES ECB/CBC operation. The source and destination a= re + * either single contiguous buffers (direct access mode) or scatter-gather + * lists (HACE10[18]/[19]), addressed by HACE00/HACE04; the IV/key come fr= om + * the context buffer (HACE08). For CBC the resulting chaining IV is writt= en + * back to the context buffer so the driver can continue the chain. */ static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd) { + bool sg_mode =3D cmd & CRYPT_CMD_SRC_SG_CTRL; uint32_t len =3D s->regs[R_CRYPT_DATA_LEN]; bool encrypt =3D cmd & CRYPT_CMD_ENCRYPT; g_autoptr(QCryptoCipher) cipher =3D NULL; @@ -633,6 +678,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint= 32_t cmd) size_t iv_offset; size_t blocklen; size_t keylen; + bool status; =20 if (len =3D=3D 0) { return; @@ -686,8 +732,14 @@ static void do_crypt_operation(AspeedHACEState *s, uin= t32_t cmd) src_buf =3D g_malloc0(len); dst_buf =3D g_malloc0(len); =20 + /* Gather the source into the bounce buffer, per the selected mode. */ src_addr =3D s->regs[R_CRYPT_SRC]; - if (!crypt_prepare_direct(s, src_addr, src_buf, len, false)) { + if (sg_mode) { + status =3D crypt_prepare_sg(s, src_addr, src_buf, len, false); + } else { + status =3D crypt_prepare_direct(s, src_addr, src_buf, len, false); + } + if (!status) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read src, addr=3D0x%" HWADDR_PRIx "\n= ", __func__, src_addr); @@ -716,8 +768,14 @@ static void do_crypt_operation(AspeedHACEState *s, uin= t32_t cmd) } } =20 + /* Scatter the result back out, per the selected mode. */ dst_addr =3D s->regs[R_CRYPT_DEST]; - if (!crypt_prepare_direct(s, dst_addr, dst_buf, len, true)) { + if (sg_mode) { + status =3D crypt_prepare_sg(s, dst_addr, dst_buf, len, true); + } else { + status =3D crypt_prepare_direct(s, dst_addr, dst_buf, len, true); + } + if (!status) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write dst, addr=3D0x%" HWADDR_PRIx "\= n", __func__, dst_addr); --=20 2.43.0