From nobody Sat Jul 25 18:54:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784044321; cv=none; d=zohomail.com; s=zohoarc; b=LSK5iLQAOxOaC/odFZmquaUC2lEmCNZMoGYkw1jC9UBCyBIPponGSJuISQTv5BlDCUCrtjOTG1QoUOKG9Ar5/fmYcYCBVfaie+QkbdzdSM+VfjTrAKNPGtBZDnA9jUlhGj6+DnmvzEGy1vYx4QqR1WGh8o52pG3BBvAbM+eVuME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784044321; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cMDDgULMPaXVsCQN/OjK/Qlh+8CwP1mRe2DYbS8FB9M=; b=T35tTEOrszPXJ1ITLIYCjlZjrdS5cINqAXR1nlfSnqgPcL1BQ7fd9YcIUDVMERplJy1XR3XBDq2RfvWWC/3p7R1YwEe9TWwluq9J/T/CO61Ym1jLny9kTjNlqTr3+mymmpF/yZ9ju7FaNmDW9xydycCs1d30JbE/maiTK1A27+4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784044321396144.99645769910467; Tue, 14 Jul 2026 08:52:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wjfPz-0000xL-4D; Tue, 14 Jul 2026 11:51:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfPy-0000x2-Au for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:34 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfPw-00013o-ME for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:34 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66EEcNCX800181 for ; Tue, 14 Jul 2026 15:51:30 GMT Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fdnnr0r02-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 14 Jul 2026 15:51:30 +0000 (GMT) Received: by mail-pg1-f199.google.com with SMTP id 41be03b00d2f7-ca7c1e22995so5230307a12.3 for ; Tue, 14 Jul 2026 08:51:30 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b987fc629sm41343581c88.0.2026.07.14.08.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 08:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= cMDDgULMPaXVsCQN/OjK/Qlh+8CwP1mRe2DYbS8FB9M=; b=VYyouABV2y39JRG7 9e+NH1yvmqgbeBtoz0lWtU4+bUtt5JQi7XFYiwbEVYXPwP2e/j9kU+Pqsp4phudj ErCQZ8bSyEBi9pBhhWli7gKQ7jfV7nQfGFJLdx1vy7aEP+PSkZciRe1N+0Gy8HN2 cG4lv07mjCwnrSo+1CzMaRkw13jxDhhrzhfJuiQCo1y7J9O3NaiWRN1ur5k6gsvW fnya3RobxxrfyxF+wLaUugb0O3VH0raT31pkNu5gL5qrro7LdLXRKbJI6s/J8nof hzcohtYcmdyWzTmpva2OO/d7LNJw1iGpggT/7uv5MQhuFXepK501GingUYt+V2G9 6YEt5A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784044289; x=1784649089; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=cMDDgULMPaXVsCQN/OjK/Qlh+8CwP1mRe2DYbS8FB9M=; b=M/8y+yLbqzGvWKM6TEnjmF0lj7IQdSJUrc4FBCJjbzhCbmhG8lzhz4QOBJhVOvHgL5 WWBRiRkSkBb6PcsSzQnnZE+6shomuakmWwHeUZiNgHQWKle0bgjEe7k53JkVy7V8aJ2J zmlmjvoLarcqppMgv2uFpQCo9Q+DndLae1jHg3kVZ0K1+ONKmJH152ls4xJ/qea5yRX4 D6ms+uSOMEG2IOJghGwDhzaAgQ6pu4684jqJ0DYatVKYwvtlYAo+NMwns0KQgdFH92Kf Z9XgnRbcjsmDQjoOyNTl55J8dFCM9MZ1v5Zq56R0KEnUc9yzRicbjzEmRG8tQji7p1aU tmog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784044289; x=1784649089; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=cMDDgULMPaXVsCQN/OjK/Qlh+8CwP1mRe2DYbS8FB9M=; b=CITOMh0gIvu8Xd1CgTwjleQQZR/xerPp2XiKag+bO1mVJp4/is0O1EBJTmGu0uioPX oh27eqZM/Iv0+k19lwvU/ROX+dlUqd8vpTR2s/WiWLfA0Za4gFGbu52dxiOOs8+vLRyp WKvv6qMTKJBz4xQ2CaAN7H6ke9XOaITV4PdliYpmO7IHkc2Mcoro8he0jzyNFVz07YNC QYdjZSmmR6WXGV/Cd2xrYAwPa7X3jBFWiM+ODnJUUJweFw9Th6zm4xlBW3/6toDe43jX d99ZUSQ90UBqqmZlPNP1TanMxNq4mBqfjE3eAMxNLWlbn9ke1Qk47/fciDkeLwhoGZn8 a7yA== X-Gm-Message-State: AOJu0YxU78sw7taKpMdSjhG4TWE7TJz18ULuKZf5S+TDa08Ldz+QIQ83 zVhBchfwfQPb/k0w3o2WchW1TfJ7z3bhBMvYRd0k9TnbHuZdtta9osNg4i3vfeOmmAShH5sslWI gMCrddNc4y8is8OYLQR6ksxZoy5PrloLCR1q94xYybHEPcZA1SJMwVDZw80uYNBpKEQ== X-Gm-Gg: AfdE7ckCUcxN5wtc0aweptTRW+EGmxXm7Y5Fy3nKlWHuHTfq9VkhTvleMTA2oXOjpaG zriXwOZwZPVY9CZ3D2nmRDLGTrRx6FgX86sfm54Vaii1duNX0QGRqqqNehOTSa/clJBrj5rc1ou YnpX+Iu3EC3SyzUpunnfH1arq8Hn/FyOLvopfwFTT4O2fUj1miguDyeOzy4gbLiPgHcI7PUtr45 VKaIkz20gPxg7Dlee6Zn5ErpKFrQJXQsAqDE8b/ml1rhbyrpzvs4T8pRzpmKn8P0S76+pnTPhyR UX+Id5QYhLF3Uxe1u+n9mVoq58qup92lqQmpv5SdKfDuttpnOb8rBcLDUe7ZL5B9yqd31RAS5i+ g6JwGFgZj2D6JC85UhuBuo8h5I1HQW4SQUtCd+3AAono/IdfZfSNpbyXgcS0= X-Received: by 2002:a05:6a21:6d8a:b0:3b4:3ef0:9132 with SMTP id adf61e73a8af0-3c110009b1emr16839341637.11.1784044289427; Tue, 14 Jul 2026 08:51:29 -0700 (PDT) X-Received: by 2002:a05:6a21:6d8a:b0:3b4:3ef0:9132 with SMTP id adf61e73a8af0-3c110009b1emr16839303637.11.1784044288972; Tue, 14 Jul 2026 08:51:28 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: ltaylorsimpson@gmail.com, Laurent Vivier , Thomas Huth , Paolo Bonzini , matheus.bernardino@oss.qualcomm.com, Fabiano Rosas , Brian Cain , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/7] target/hexagon: initialize deferred sreg-write temps to current value Date: Tue, 14 Jul 2026 08:51:20 -0700 Message-Id: <20260714155126.3509544-2-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> References: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfX3sU7TuoLfSE5 se1wg3L7XpdMlisT3ASqhzVkzZDjTkvIz5N77myUHjQLsyLJMs17DK1qyUpHYNxtc00Gx+qRuPi FQpSHkSf7gz5ww70LGWa5FEW9yYN40U= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfXw5sgclBjLW17 ZuJ6kMKRqU37IKWw1/QTta35z/VtlbNxu1cubAhPdFdxshbe55hi6tNi9rCUwmXXZeYKU82fX4C w7CkdorTtsgtmeqAAar8CzZDklAN0jBBVoTD+OQVN6ufuQwhhDujX/LUNkDKFdpbuc4Q5lujz6u AFp9tCbke0CbiMIKVoJBR+rcKw4JoDcBTbEZ594wucM2K4ICx5LNpIJGLvholKOHAAhgfD41Qea vHrD+wScoK+471vSVsvo3eJ1ZWeLwnii/tWh/8yiAavMcIE255H2FsHtiLxh+q7/qMcVw6ZkBdc xr72dem6qTZjxuDRm1kN082WadblO2eAYeSCfakhfTQ71TMajTRT4v8znElndnXihwd47P+QXBF CTVdJhoGmWVqfwYqboySTkgGFrhTpL/u2PSmJxu/xbyImqB8KE/pFimqnEoUdU0cqm9nm+cj8Yi bvcI+dTZbUjFFDpzXeg== X-Proofpoint-ORIG-GUID: 2xzp8DkrGq10va4If9j4s4E2r0JkwDhJ X-Authority-Analysis: v=2.4 cv=NfPWEWD4 c=1 sm=1 tr=0 ts=6a565b02 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=IlOZXNdbeIrMSDKviAkA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: 2xzp8DkrGq10va4If9j4s4E2r0JkwDhJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_03,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1015 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140164 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784044323255158500 Unconditionally allocate and initialize the temp to the sreg's current value for every logged sreg write, rather than only allocating when need_commit is set or the register is SSR. Without this, reading a deferred sreg write within the same packet before it is committed can observe an uninitialized temp instead of the register's pre-packet value. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 77235916f4b..28a171bf623 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -615,9 +615,10 @@ static void gen_start_packet(DisasContext *ctx) } for (i =3D 0; i < ctx->sreg_log_idx; i++) { int reg_num =3D ctx->sreg_log[i]; - if (reg_num < HEX_SREG_GLB_START && - (ctx->need_commit || reg_num =3D=3D HEX_SREG_SSR)) { + if (reg_num < HEX_SREG_GLB_START) { ctx->t_sreg_new_value[reg_num] =3D tcg_temp_new(); + tcg_gen_mov_tl(ctx->t_sreg_new_value[reg_num], + hex_t_sreg[reg_num]); } } for (i =3D 0; i < NUM_GREGS; i++) { --=20 2.34.1 From nobody Sat Jul 25 18:54:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784044346; cv=none; d=zohomail.com; s=zohoarc; b=Q8nfCuvZLRNbtU55AuKbhjnu6SJ1Mst/wnDFWaMgojXa6dG9gxki8yzDMsGIRTaD2fN+juOvOTb7ailqKUBwvJkSF+NixqVo0Sbyoie5rpGHooEpw8iDWS68TnjamcxYF2cql24wN3KZyrV55yLszaeDjjZsTt/TK+OwjaEiyzw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784044346; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=v9TEZ/r+WdyXkCh0jPLt6TPCbm8hNKa/SZ+tY3PO/BU=; b=YaWyeEjeuwPTNx3wSFcLqrY96sBMQ/QnfbZHHAHphoyCG8ThDeAzjqkv0bhHhqYrjIQV3OcleiUOaFYeeUFIsqQcY20KtAkuMieSHs8bm8zsu6kzjAh3y2tYVkcvXCdLlz39cml1pRN40pMknw6pe+/YLp30tl3J4BAm1qR+LG4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784044346392388.36153997972474; Tue, 14 Jul 2026 08:52:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wjfQ0-0000y5-Ir; Tue, 14 Jul 2026 11:51:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfPz-0000xk-Oh for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:35 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfPx-00013y-Rb for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:35 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66EEdKwf889069 for ; Tue, 14 Jul 2026 15:51:32 GMT Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fdgudhyb2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 14 Jul 2026 15:51:32 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-c894391f000so2490157a12.1 for ; Tue, 14 Jul 2026 08:51:32 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b987fc629sm41343581c88.0.2026.07.14.08.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 08:51:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= v9TEZ/r+WdyXkCh0jPLt6TPCbm8hNKa/SZ+tY3PO/BU=; b=cfwxzWM8MHWz6/Nd rA3cTaXo8HeSBNIcibnh2OtDXj0D6OEPmpQsHqZokYlBpyTy7YbdN2hhqWzcb+HA dnLHgS+PSgRdbAKeRBgM+VPO5U/swLuqeOPycXhP1DlVrb/J9RvtPosTAnwSrzac CrY3vXD81byB7tivs5i8k/9mDRtTfq7eDCykQQulY0UslN40MruuMTue75K4w9ya AevFwCvOoMzzNdOi1/Ntitx26v97htuuNl7x/PeyuOPkwumCqru+6l+wCtqV6lz4 MqraLGVWnixDNO9AHVkt2pwQn5QAscQQw0j96GE0bt87IEIuS71geQt2ivz+zfQW Q44q2A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784044291; x=1784649091; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=v9TEZ/r+WdyXkCh0jPLt6TPCbm8hNKa/SZ+tY3PO/BU=; b=c9/rRSGV0OOH+z2UlBQCTPmns1tdvhNEC5VemCMgu7vOwA+gb+5QT4vX2P8akM4bk8 BCoQUilcmU4yo0k91AsIeGOfchTvNattGJA/zFS3rhzU6rrxzJBvt1AEGXZvZ/aeDZZI WEtgUjiSVcvzfnLM0k4jvsvX7v2CYhfU1uTyomGwE3hH0yCU/8400J4mGzdJXamAlS+8 pG5jvg5vPDG1UDeV68JFqW8NllYVkQAymJ5314AkGs+FSv6MRQhOCDbC5mBWaMlDIM94 3m1ttR5fMo+9+vAWL4uty+42BVcDpmI75ToBM/mW06HlpT91e2AAdEFHZY3fZH03dd1J ueaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784044291; x=1784649091; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=v9TEZ/r+WdyXkCh0jPLt6TPCbm8hNKa/SZ+tY3PO/BU=; b=alm4VcKIv/dRUUTmfrZLmtFTXMwHgDkmgjNPdicmKzUHB4rRibt5//AaA4ZZMdOhfn oH6naO1bOi+SCY0Ho7y9rqn76y95GG0BhiH8x8pBDmOiB4WAu+6jZ6fFjPaomFY7sAxq 2grvxPAuO7nTPj77ekJB/XZw0xgN/RuMgjZgd9H2OIlYAiEEXZDATyrOAEnmCEX644HE bDF+chLhi5a/fAJqN+H/GZ4Tml9z0SkdSUfW5xDF+FnJxAOCU1OSjaoKCLQIkKvsDHIU NzBzKVTfNxq53FUVFmegbcItOS3CMsKYPpeh7cPiwsznMutH0xM+8dv5ywvipmVc+V9d YZYQ== X-Gm-Message-State: AOJu0YzR+2jGGq1jDA9HfYWoNwzurwMzylBeedAsSas8o1eHLnX2RnzM J49duBK8ibSWbHE0FMz4NHpTioXEweuKB1TDdTBYrDPIhQJ8FK3ldVlIPjY1Qmrn/3/ZEX6fn1d g9J3j96Htey8MGef7e71yyo2BfoiMnzM/ttkWpJ1dfyX+2z167lRF7PsGAzAph7jGAg== X-Gm-Gg: AfdE7cnmxjNlJ/DbLc2ClNUWj4rs5TgCoB9phV3jzp+Svblq8bhxuIaHVnWLsYXVqAT MoKW7DsqAcm0EPbct7jBMB/6FailWjNcdT3eiEqUwrQhSlHw+CzWxUDhUf66pZfWH4VCc3G3DOI H4X291bx3BocoeZx/oRVWCVPKSZOdtrb1L9E7PhWMs3SWezmc7t0J86NlsBTyipfz/IG0v/WtD6 vllxB6jzfGNFEUk2QL8ImJD0+0EoxRFXB2OkKSBJUl1skqYkR3zvG//PYZV7QmXAGvtjlqmcKgv ZF1NJfDkOa0jpbgO+GiqEBdg4zabrynMSN+Xy67oNEfz/ANwuC/VkhjjgY8fuSiDwHRntPcD9Gs nRjyVLY5ytZAl7TNiWX1MnijfoYaiunbJ9vgJUT16wQ8Yz7rYDPe1wH9HTFk= X-Received: by 2002:a05:6a20:430f:b0:3b4:7758:e397 with SMTP id adf61e73a8af0-3c110157a16mr15358173637.16.1784044291519; Tue, 14 Jul 2026 08:51:31 -0700 (PDT) X-Received: by 2002:a05:6a20:430f:b0:3b4:7758:e397 with SMTP id adf61e73a8af0-3c110157a16mr15358127637.16.1784044291004; Tue, 14 Jul 2026 08:51:31 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: ltaylorsimpson@gmail.com, Laurent Vivier , Thomas Huth , Paolo Bonzini , matheus.bernardino@oss.qualcomm.com, Fabiano Rosas , Brian Cain , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/7] target/hexagon: fix PC not advancing for non-COF TB-ending packets Date: Tue, 14 Jul 2026 08:51:21 -0700 Message-Id: <20260714155126.3509544-3-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> References: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 2Yz7ulqKmOfaNGm30k5nPYOvTUQr1npL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfX0nbFDspqYvYn RawjQx/Mq71XkWTOs+8gMgehrOFcMB5z95BK11bYnrVLBydoa2xkHU5mNsTSHKKjC5Roc4h/v3W J6xLDg9vhQQ5/YrQaKmBqsyVM8wXq2PloZoZt3UqrYCMe9ZqnLPmv4XEcj5kN0AmOYIeLof+KhX oVdYQuz6CwUjbkd4XaNlIQHmVa/zAshtOrMOJJDG0BtrRHXR4YjPl+i8bCoyXfm1elxLhEUXAMD 677LelucDfMYG76sAJEO8ucltepre8o3OJWQqpj4aTWFzICGBslFlISTmqLsDPaSbAKqI5X8kvH CT5YHUiwwnUCH5tbbUDyu1DSNsqvbHrSWe8ivrWw5iWAdE1vDr8jcuDZfNXCDOrBBgzTPKbbKVX hHuyX4fPMrZlhfPz+CjjXCJytymRoE9Y/LXYX5xzbzQT6Q2BzRpPnVIKg6vB81d4H1b+iS2GddM CPiE3tlg3vGws8yfrIA== X-Authority-Analysis: v=2.4 cv=T/O8ifKQ c=1 sm=1 tr=0 ts=6a565b04 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=j_Ogrd1p5-rMj9Zg3YEA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfXy5iIS9H2Gmvb YVMIGG5qE372gd2BXyn5XWHW6HBVAd/gs/5kowI92C398WLY9H3R5Wb4GrYsgWw+0gDVzj3nyCX CvcVEKpqi74spPGFbdMEA/MDtxS1bRE= X-Proofpoint-ORIG-GUID: 2Yz7ulqKmOfaNGm30k5nPYOvTUQr1npL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_03,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 adultscore=0 spamscore=0 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140164 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784044347458158500 Add hex_next_PC, a global mirroring CPUHexagonState::next_PC, and ctx->need_next_pc, so that gen_write_new_pc_addr() can write the branch target through hex_next_PC instead of hex_gpr[HEX_REG_PC] when a later unconditional write of PC is expected. gen_end_tb() then commits hex_next_PC into hex_gpr[HEX_REG_PC] at the end of the packet. Previously, non-COF instructions that still end a TB did not advance the PC, since next_PC's value was never written back into the PC register. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/translate.h | 3 +++ target/hexagon/genptr.c | 14 ++++++++--- target/hexagon/translate.c | 51 ++++++++++++++++++++++++++------------ 3 files changed, 49 insertions(+), 19 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 0a7f37d5842..2fca157553b 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -40,6 +40,7 @@ typedef struct DisasContext { int reg_log_idx; DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS); + bool pkt_ends_tb; bool implicit_usr_write; #ifndef CONFIG_USER_ONLY int greg_log[GREG_WRITES_MAX]; @@ -75,6 +76,7 @@ typedef struct DisasContext { DECLARE_BITMAP(insn_qregs_read, NUM_QREGS); bool pre_commit; bool need_commit; + bool need_next_pc; TCGCond branch_cond; target_ulong branch_dest; bool is_tight_loop; @@ -310,6 +312,7 @@ extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; extern TCGv hex_pred[NUM_PREGS]; extern TCGv hex_slot_cancelled; extern TCGv hex_new_value_usr; +extern TCGv hex_next_PC; extern TCGv hex_store_addr[STORES_MAX]; extern TCGv_i32 hex_store_width[STORES_MAX]; extern TCGv hex_store_val32[STORES_MAX]; diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 1ebc7471409..dc9ba8a0060 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -613,14 +613,22 @@ static void gen_write_new_pc_addr(DisasContext *ctx, = TCGv addr, tcg_gen_brcondi_tl(cond, pred, 1, pred_false); } =20 + /* + * If gen_end_tb() will unconditionally overwrite PC with hex_next_PC + * (because this packet has a predicated COF that may not execute), + * write the branch target there instead of directly into the PC + * global, or the overwrite in gen_end_tb() would clobber it. + */ + TCGv pc_wr =3D ctx->need_next_pc ? hex_next_PC : hex_gpr[HEX_REG_PC]; + if (ctx->pkt.pkt_has_multi_cof) { /* If there are multiple branches in a packet, ignore the second o= ne */ - tcg_gen_movcond_tl(TCG_COND_NE, hex_gpr[HEX_REG_PC], + tcg_gen_movcond_tl(TCG_COND_NE, pc_wr, ctx->branch_taken, tcg_constant_tl(0), - hex_gpr[HEX_REG_PC], addr); + pc_wr, addr); tcg_gen_movi_tl(ctx->branch_taken, 1); } else { - tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], addr); + tcg_gen_mov_tl(pc_wr, addr); } =20 if (cond !=3D TCG_COND_ALWAYS) { diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 28a171bf623..22f0ff5b891 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -54,6 +54,7 @@ static const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] = =3D { TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; TCGv hex_pred[NUM_PREGS]; TCGv hex_slot_cancelled; +TCGv hex_next_PC; TCGv hex_new_value_usr; TCGv hex_store_addr[STORES_MAX]; TCGv_i32 hex_store_width[STORES_MAX]; @@ -184,10 +185,16 @@ static void gen_goto_tb(DisasContext *ctx, unsigned t= b_slot_idx, } } =20 +static bool need_next_PC(DisasContext *ctx); + static void gen_end_tb(DisasContext *ctx) { gen_exec_counters(ctx); =20 + if (ctx->need_next_pc) { + tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); + } + if (ctx->branch_cond !=3D TCG_COND_NEVER) { if (ctx->branch_cond !=3D TCG_COND_ALWAYS) { TCGLabel *skip =3D gen_new_label(); @@ -391,17 +398,25 @@ static bool pkt_ends_tb(Packet *pkt) =20 static bool need_next_PC(DisasContext *ctx) { - /* Check for conditional control flow or HW loop end */ - for (int i =3D 0; i < ctx->pkt.num_insns; i++) { - uint16_t opcode =3D ctx->pkt.insn[i].opcode; - if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) { - return true; - } - if (GET_ATTRIB(opcode, A_HWLOOP0_END) || - GET_ATTRIB(opcode, A_HWLOOP1_END)) { - return true; + Packet *pkt =3D &ctx->pkt; + if (pkt->pkt_has_cof || ctx->pkt_ends_tb) { + for (int i =3D 0; i < pkt->num_insns; i++) { + uint16_t opcode =3D pkt->insn[i].opcode; + if ((GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_CO= F)) || + GET_ATTRIB(opcode, A_HWLOOP0_END) || + GET_ATTRIB(opcode, A_HWLOOP1_END)) { + return true; + } } } + /* + * We end the TB on some instructions that do not change the flow (for + * other reasons). In these cases, we must set pc too, as the insn won= 't + * do it themselves. + */ + if (ctx->pkt_ends_tb && !check_for_attrib(pkt, A_COF)) { + return true; + } return false; } =20 @@ -637,12 +652,14 @@ static void gen_start_packet(DisasContext *ctx) ctx->branch_taken =3D NULL; if (ctx->pkt.pkt_has_cof) { ctx->branch_taken =3D tcg_temp_new(); - if (ctx->pkt.pkt_has_multi_cof) { - tcg_gen_movi_tl(ctx->branch_taken, 0); - } - if (need_next_PC(ctx)) { - tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC); - } + } + if (ctx->pkt.pkt_has_multi_cof) { + tcg_gen_movi_tl(ctx->branch_taken, 0); + } + ctx->pkt_ends_tb =3D pkt_ends_tb(&ctx->pkt); + ctx->need_next_pc =3D need_next_PC(ctx); + if (ctx->need_next_pc) { + tcg_gen_movi_tl(hex_next_PC, next_PC); } =20 /* Preload the predicated registers into get_result_gpr(ctx, i) */ @@ -1142,7 +1159,7 @@ static void gen_commit_packet(DisasContext *ctx) ctx->pkt.vhist_insn->generate(ctx); } =20 - if (pkt_ends_tb(&ctx->pkt) || ctx->base.is_jmp =3D=3D DISAS_NORETURN) { + if (ctx->pkt_ends_tb || ctx->base.is_jmp =3D=3D DISAS_NORETURN) { gen_end_tb(ctx); } } @@ -1327,6 +1344,8 @@ void hexagon_translate_init(void) } hex_new_value_usr =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); + hex_next_PC =3D tcg_global_mem_new(tcg_env, + offsetof(CPUHexagonState, next_PC), "next_PC"); =20 for (i =3D 0; i < NUM_PREGS; i++) { hex_pred[i] =3D tcg_global_mem_new(tcg_env, --=20 2.34.1 From nobody Sat Jul 25 18:54:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784044345; cv=none; d=zohomail.com; s=zohoarc; b=UjX4ecjw/72lNwnwy4mfzeMbIaQnlq4y6fgstgWSBSHKWjDwmx20mYwppm0LljT+DYBx4buDRLyu4eB4X9ODQPkdgBH9fVPSTbkx3uyc7O74SIKkOk+r9FWsx1vXTIUMhRz2y8qpixMakqdRLRRoK8QkWEGsGhHENalGi+96VsY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784044345; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ar6lVTR4o40Y8mAt9MPiR+MLeALHdR24ouRtrSRI3B4=; b=V/ipwKnuhkCke8SRhFqSm9NOZ7v/paKONu9b3Z6z63z+2gyLolSZsLJDw7mmmx/vFjq17O5E391aoqQDqrV58q7FS68hHapr9cB6gBKPy+b5YOmPConUs08xFqBfA2RFduANRSOQ1qetI1Ag1sjD8hyWY481I//5UMCM4GyvxR0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784044345078860.5148123313661; Tue, 14 Jul 2026 08:52:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wjfQ2-0000yd-3x; Tue, 14 Jul 2026 11:51:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfQ0-0000y6-IQ for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:36 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfPz-00014E-16 for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:36 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66EEcP9V893288 for ; Tue, 14 Jul 2026 15:51:34 GMT Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fdnnqrr5d-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 14 Jul 2026 15:51:33 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c88aab7c1fcso10349565a12.3 for ; Tue, 14 Jul 2026 08:51:33 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b987fc629sm41343581c88.0.2026.07.14.08.51.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 08:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ar6lVTR4o40Y8mAt9MPiR+MLeALHdR24ouRtrSRI3B4=; b=W0prmCqFYdgN7hvf Ngz5QIM5o4mQx4ZP3figoClumhz+mnEvhOHDpRfl6m8PHgGsWDKyT3S9Fi7ELOR6 OAuiV7PdYj2AWf4sBkG1KHxVqFd09LiKCtRQ0Cb9B5v4svwoDZNUGgKSnB0Upc25 k1aGgmM1mYLDFNrJ+q+F6zTQlRxwgOdeLAKkjtugq1p7USb3RzE5tJ9h75Z2JEq4 eEhELl5ug+tCoztFOVJzHzWXcQ3JnMEBYVuJ51eVf6RoMqrDZ36NxqRc5s2R4kzH 5wCeuldXgcq8u6kytAdzgHyBw0xw5AEZyyItM0RHsM30IL4rrjPxWOctR3oxX9Wn yj6wnQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784044293; x=1784649093; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=ar6lVTR4o40Y8mAt9MPiR+MLeALHdR24ouRtrSRI3B4=; b=csGYI9fQfLoWMcfFdl+m9fJfpti6sTq0GwdsNyDKG/tdPMvaXjTtQmpFJYtv/s/wzR EiwdSRq3fOCL0DvtN/cm2hG91xQeE9mapWe5AFEQMxmtFC7dwOmRLczLC6IkZeYZNgIx NJ3wt8GW3Ojk0LmyXnTrCX8vOn5ha+oZzJHzlJubKnhZD0Nqrg7Qxe8NqEam+4QRQx/N i4DyB5hfeR+qoOTX5Y9CqgRctoOZRe6BCyFq4DqDEGqaPqOdpZaVCdAnKjvy7OPLeDii fqYkCXNEyKchijq2K18U0EeP5TrA6hfYbsXNK1LXKrMk94lq4AicoMRlJgr31Cx1U4i0 FRTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784044293; x=1784649093; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=ar6lVTR4o40Y8mAt9MPiR+MLeALHdR24ouRtrSRI3B4=; b=SlNsSw3ECEHs/LDQZhk6S1yxbfzQvQQ9IX7X9G/QbfqP4haUhDggqySjZPAMnaPpNM LH05URgM+0ZPOgXehFz/a9Nmno47e+U08pAlDF64KqJrvenO78yvWHgyuKBb2ui2+eqP Xnoz1QgIYEbbPUXalwaFESbMopKOw57ODSSFVerw5sRapHQkkzD+0r7ENlIcLjOiu9d/ iIuTpIinoJUMuqDFGrV8xm5ImsZYpGuywr2OTsyY4E1qct3leZ1UdyHMZ9ty5tj52RTU nZGsKDBlf+eNgCLDgv7I2fcqZj8QByaQQXamSZfwHFuUXQ3ZmwYerBs0zJmUfebFcvxj 7ZoA== X-Gm-Message-State: AOJu0YyTFq3DBc1ZSflPyM9wLMMtau9U13LWZMdmNFEn5sjm+sKZ3i8o JzAWVtQuiUTRSM/uyNDVNb/PNK19dcEwrXFw8zg3PgGIEUAW/ngjMprmpK4Nt7sPJq8bXVdBljH aUUMpeSVl44FOU3iHohhlzeEDxXG4PEwN/eNK97rbitlqU2a+snxKIVNEkSAJlnQLfQ== X-Gm-Gg: AfdE7cke59KGtCOgkqJ+NJZYqhyDt+le1OyPrL9NHC/M3WL2Y9x+/hSr0LU4jrXN4jA Pdt5PdKKiQaXpyiteqPLzLWi75EsWyo1sHaVgPIFYRmueQIq7I8GEPvptRP3RKuJx9CUMi/ExrA 1vKH+FUn7URsvFrNVJMT+5Jvt2PmPoMkOF6QnqmEI8tOt29SV5bV77t1Y3ctq0F0owJS3cwFjX/ 6xs7w72uLTwuPBY8nfphMdMPbv1Bg7epUhCNcC/umAbqArGYRmjuxqV2ocGJ3LzlM40lYisbylu QFBLzccYbXz9by7vA1/XYyZfJJbRg0thJwMr3nggM23H8qXabP6+S4vQCt6ff6d8GWj5Y1wMWrZ rxh5qwPntHchQGN2Z8NKwgx79okIzFgHCnWZQrZGMavQEgqSJISz3nlR6gTU= X-Received: by 2002:a05:6a20:c6c9:b0:3bd:3800:7538 with SMTP id adf61e73a8af0-3c35707e50dmr3251909637.33.1784044292825; Tue, 14 Jul 2026 08:51:32 -0700 (PDT) X-Received: by 2002:a05:6a20:c6c9:b0:3bd:3800:7538 with SMTP id adf61e73a8af0-3c35707e50dmr3251861637.33.1784044292239; Tue, 14 Jul 2026 08:51:32 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: ltaylorsimpson@gmail.com, Laurent Vivier , Thomas Huth , Paolo Bonzini , matheus.bernardino@oss.qualcomm.com, Fabiano Rosas , Brian Cain , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/7] bitops.h: Add find_first_bit32() Date: Tue, 14 Jul 2026 08:51:22 -0700 Message-Id: <20260714155126.3509544-4-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> References: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfX1Th+tlUXJZoR f2rhtgc2BomT9nz7VWdi5xbyJG0dlCqJhOuARrnkb4NtTbGpFJwfuJSvQrF1MmOhIKib4KzSoWs BwIKhFwsu8Cbgb3HGWZ879dYxCZOue3zHLRKtFfPZm7BnmAT4T0/92fUhOYwxBiPOT6/B4TvYxG sZLiufBjWy43maARIEl18YfqAFwM4rgJ1Udl6OCBIBi6v3fDHbDg7uKs2kTO1rmURGcaqqIMgFX E8ZrE1qQRUPnQLyKX+1exeyCQEClZYuL+z1/bVieMzfGNe9Fnpmrho2cjfJm2ZnyGkX1lwz4uX0 Kfd+NvYeTQgCxwKAXtxi0tK9bZ9hdN9zXQOLTWBjOqn3Y5f2L5jXHb0WNd0DTtQe7Jf/BMkraJi Gd/8BwArxseKP1iLxUftS+CkNh4FfHAikzdaLXvsEta44xRZZ9mYxlih8xCG9pMslRcdjrAxrCu Z2d+5quOPJmm3c+MeMg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfX7LoTa7mMWgzL dHw7QuekeStm42S+vY22+/kCEobE0L8Ya/fvfF/3IRi4vPfJl91RFMaVeT2bbxLvLaMiHIWEOZ0 6py9IcwYDRpfTj9hLgjkj5pZYNyKjK8= X-Authority-Analysis: v=2.4 cv=U+Oiy+ru c=1 sm=1 tr=0 ts=6a565b05 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=w2bVgGKsJa40EddZz84A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: -fxkjmO-py6ghDaIx1IQ5-DEZc6LE4dy X-Proofpoint-ORIG-GUID: -fxkjmO-py6ghDaIx1IQ5-DEZc6LE4dy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_03,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140164 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784044345345158500 set_bit32()/test_bit32()/etc already let devices operate on guest-visible uint32_t register arrays without depending on the host's 'unsigned long' size. find_first_bit() has no such equivalent, which pushes callers towards casting a uint32_t array to 'unsigned long *'. Add find_first_bit32(), implemented the same way as find_first_bit(). Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- include/qemu/bitops.h | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index c7b838a6283..f7363a5479f 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -43,10 +43,9 @@ * be some guest-visible register view of the bit array. * * We do not currently implement uint32_t versions of find_last_bit(), - * find_next_bit(), find_next_zero_bit(), find_first_bit() or - * find_first_zero_bit(), because we haven't yet needed them. If you - * need them you should implement them similarly to the 'unsigned long' - * versions. + * find_next_bit(), find_next_zero_bit() or find_first_zero_bit(), + * because we haven't yet needed them. If you need them you should + * implement them similarly to the 'unsigned long' versions. * * You can declare a bitmap to be used with these functions via the * DECLARE_BITMAP and DECLARE_BITMAP32 macros in bitmap.h. @@ -382,6 +381,29 @@ static inline int test_bit32(long nr, const uint32_t *= addr) return 1U & (addr[BIT32_WORD(nr)] >> (nr & 31)); } =20 +/** + * find_first_bit32 - find the first set bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit number of the first set bit, + * or @size if there is no set bit in the bitmap. + */ +static inline uint32_t find_first_bit32(const uint32_t *addr, uint32_t siz= e) +{ + uint32_t result; + + for (result =3D 0; result < size; result +=3D 32) { + uint32_t tmp =3D *addr++; + if (tmp) { + result +=3D ctz32(tmp); + return result < size ? result : size; + } + } + /* Not found */ + return size; +} + /** * DOC: Miscellaneous bit operations on single values * --=20 2.34.1 From nobody Sat Jul 25 18:54:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784044344; cv=none; d=zohomail.com; s=zohoarc; b=oIXdrsS1YLRGCIB+lP+mTYMgVS19Ow7Fm8kgYHc9V5kAlRlVw6ADKh2FbC1UVYRN3cLgjQcpamhCz/f01vG6Mu3xJVn/97TwdH5K/cPtfzYJjiQKRxW0xk4SEVgNg6V1guBUJ4SGvilU8qes8e0J5OuYPvaci1rTTlI/mVcq9QI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784044344; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fyJkzO5j4TgyiaTMhEsNKoqg2aFZ6z7LN49qqrz0Mm8=; b=lMjtna2gWcJ+dXmg/Z3YSP0Ut3G3+B7aqzZrn4Ckjnqje5bpWE7rLeejclMuo9CNAtQUBzcpYhqSB2RfmEsmSfHhetuaS6FN+LTOUuZVsI1JopzCR9iJgDDzNnsfG6Ptru1myYlgA0MAixGeR0gmyjDShJz+ZH0CapciChEtJNo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784044344967962.7005984897381; Tue, 14 Jul 2026 08:52:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wjfQ6-0000zy-Ug; Tue, 14 Jul 2026 11:51:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfQ5-0000z3-5p for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:41 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfQ1-00014U-IE for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:40 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66EEcn8g677312 for ; Tue, 14 Jul 2026 15:51:36 GMT Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fdde0at1h-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 14 Jul 2026 15:51:36 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-38e2237bc43so711179a91.1 for ; Tue, 14 Jul 2026 08:51:36 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b987fc629sm41343581c88.0.2026.07.14.08.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 08:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= fyJkzO5j4TgyiaTMhEsNKoqg2aFZ6z7LN49qqrz0Mm8=; b=E6b4h5EQFxbHUSyZ 8qosS1hXoWzCUmTN886+unOGsr26TRFADX6AlR9pISL3J41NMwMa+FCIRondWsZc kTDWap6wLYIU9+o6ffFIyjiRWXfvQ3rKOelGIKgvQVDf6E8xN1ZP+khibpZKGowp ZhHpORSGkKsbv3gqdpXDYcJJT8YOyS9qkJ79RdQKbI9v5fMr15o8Ir12oCL7iVmz D5OftUHNTC44ZjHJY0v4SPfsn1BblkSkna4/3lZ+m8bhuKm7eqHaeHiflQ/ogHDX A7fKgB3cvn4FtMQK5Hd8pDiGGLqpAv+eSyknnu5gp4VGgp25teUuN60I3TwbKMcy gKaV+Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784044295; x=1784649095; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=fyJkzO5j4TgyiaTMhEsNKoqg2aFZ6z7LN49qqrz0Mm8=; b=iqQf5OMMm+ViHeAx8UYRDHM4Nbi1zwa6GYMtUIuYW6nOugTExxHFzTzg/VMyAdkv80 eCF6pSt3dHtptlqn8JvDS2YAipOeLeS9ze+JioxkNK2wW3XNHbU6d7Oj1hHAyMSxbjFT xtGDY80ZlaobOkWzuRPjHsh+nK5oIHiMreV8/YwFYofcRBCjknCzhuLViX9BN7G5ekVV UN+LU6h4sPpjv8BjR3uvXDKj+HrvyJxRZ0wWSg4prspbhs4oxZvssq+4cCXejL42xTYk 0FHturFTUXsGu9W0PuYiJJPOEW0as5GibxRkcG/rt6NAWsQmMYOP5mhKFZTh9/qLVyeJ KP/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784044295; x=1784649095; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=fyJkzO5j4TgyiaTMhEsNKoqg2aFZ6z7LN49qqrz0Mm8=; b=o+/ajEtMavAFzu+k4EGECgiQ/rH06enFO5wMHLbztk2f9/8cpomxzy8hsazMdJk0xT igENU/uKnesYioIwLp+VZUDwnx25T5tXphbTM7z2r924RT3K9n1tZCxJ2HrEn/ScipVY RStAiLxL3SGFgFdw23qy07z8ODdlJW4tiEK2/jS+teHg3GvRo5jowx252VkoVSGlSjMB csl7fbZrq9+1QM3rW++oGo+tMk/n+nfLeEFBsJYnZrxqWGXMj8b3188+/mH7n233zZ1y 22R7XYWYlMObzLUhaNSLR2g2Nu8AF+sahhQqzG9RtzTXHhTMqo8/hV7CBnIdySBODhTA izdA== X-Gm-Message-State: AOJu0YwSeYKfMG+UEa1rnAMP1UcHmsGt61NVke5kMmztMBeLILm9O0U7 HbCRIyxNIxO8NBgz85tuKlHvTPwY+SdjeoEj/u5T9dMpJ03oyxoTfUzxaAQgmCQvNrrHcx3e5uY dV8NmFkcmh1xX61c46gdtIFkm4yQbU3y1rcp1XL9+DRHrCsntEpsJUUAIQo50cZV05w== X-Gm-Gg: AfdE7clIOQ8aD4z7Jm3/7DqwCUehq8drCMgYcXAokDzy+5NHLtaJtnfwVgOPnHiMmZ+ /7JSwLtjPoGg69qKPF9pPO6O7Za4M3htjE5EGIjn4Pn5We9oqSObHHWx158BNUjQK4FhYnxmrjq er6FXJbkacXa8OuoD2NMKo3g0O8tgirm0JkInJNDn+U8zvUvAlI1uD/48YSXduXTYYns8/uYgn5 60rRxKGLfSMfHiySF1UBrvVAtr2AoEj9N/Cm1eYuEGaObWy5UGDdGjawCUbJOV7kVBCxC8O1f7B P7gI9CSPXqLMA5k+pN9ktljRBI7ItdNHthxDk/NlJjL3/2BxTqJzL7tRXqNG6pR9g9/W7G6LMbb sl4f8IVoB/dtkkXdqIXH9yQcVvhaHHmOIIVs6S/k3AX5y/57lKx7usq8fgWg= X-Received: by 2002:a05:6a20:7484:b0:3c0:9c1a:8935 with SMTP id adf61e73a8af0-3c34d893c43mr5287375637.61.1784044294957; Tue, 14 Jul 2026 08:51:34 -0700 (PDT) X-Received: by 2002:a05:6a20:7484:b0:3c0:9c1a:8935 with SMTP id adf61e73a8af0-3c34d893c43mr5287319637.61.1784044294280; Tue, 14 Jul 2026 08:51:34 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: ltaylorsimpson@gmail.com, Laurent Vivier , Thomas Huth , Paolo Bonzini , matheus.bernardino@oss.qualcomm.com, Fabiano Rosas , Brian Cain , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sid Manning , Matheus Tavares Bernardino , Damien Hedde Subject: [PATCH 4/7] hw/intc: Add l2vic interrupt controller Date: Tue, 14 Jul 2026 08:51:23 -0700 Message-Id: <20260714155126.3509544-5-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> References: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfXybPPYsMwSRI9 8UsZiwfXxcXKrKlGhFdUBLr0h+H5DFhC5Gu5JXFu4PEjtUzKLy3nB0bNEhPunWTek4G/0zz9j0T ponorAib7PoV8abVJwViKi59GqtgDQY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfXwg3O1gjOS4+Y d24gkXhyWoHzXV2iLrzXDaPwvvmZE8CRu3NagQoGENY+wHgO9xcVNzWLSf3EJMUe7FMdSaZLDxn i+i+cMKBeLhXXYTUbyqkMHz/TRwAQ5/grGQUxjyQj93tqGv7WSe4b+VqFX2X4iHL9A1TdVfA94U 1kACcTLSOHWfCvACsSrgcu4MhxlxHJQdkWElsCAWTH0ZS/UqPfzyHqdgPih1eAjAcqKisqR+7yq vOTp9sKm6BbstF/ufGnC2w9oSA+1ZnYha77YEedmk+W8HqGn1tQ3Z9WM+aNAHJwIQ739RK4i/vR e74Bv/RN6JFy8mqFykTLXz5oomypVt0I1tz9MVaAOYGIcsEMHRte2Qr7aumq0pJpGm76okJ/VQF ERWsEIdG+WI9q+u7SrNah3XDGqFveVndccUmGasr4SUQPCLM3YNc6+u+b/SC06NC2vkwCQ7Bjit 5XpFC1z7fPQUPfaOZIQ== X-Proofpoint-ORIG-GUID: 0wNfHgfDjcLabYe7yQ_uzPcv060IVMFd X-Proofpoint-GUID: 0wNfHgfDjcLabYe7yQ_uzPcv060IVMFd X-Authority-Analysis: v=2.4 cv=F/FnsKhN c=1 sm=1 tr=0 ts=6a565b08 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=NEAV23lmAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=bj4OHAFAiDXEHoaV4fEA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_03,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140164 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784044345432158500 From: Sid Manning The Hexagon DSP requires an L2VIC to route up to 1024 external interrupt sources through 4 VID output groups into the core's 8 interrupt inputs. This device model implements the register interface, interrupt steering, and edge/level type handling needed by the sysemu machine models. Co-authored-by: Matheus Tavares Bernardino Co-authored-by: Damien Hedde Signed-off-by: Brian Cain --- MAINTAINERS | 3 + docs/devel/hexagon-l2vic.rst | 55 ++++ docs/devel/index-internals.rst | 1 + include/hw/intc/hex-l2vic.h | 87 ++++++ target/hexagon/cpu.h | 2 + hw/intc/hex-l2vic.c | 511 +++++++++++++++++++++++++++++++++ target/hexagon/cpu.c | 2 + target/hexagon/op_helper.c | 21 +- hw/hexagon/Kconfig | 1 + hw/intc/Kconfig | 3 + hw/intc/meson.build | 2 + hw/intc/trace-events | 4 + 12 files changed, 691 insertions(+), 1 deletion(-) create mode 100644 docs/devel/hexagon-l2vic.rst create mode 100644 include/hw/intc/hex-l2vic.h create mode 100644 hw/intc/hex-l2vic.c diff --git a/MAINTAINERS b/MAINTAINERS index e25df9493c5..1240d180b85 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -250,6 +250,8 @@ M: Brian Cain R: Pierrick Bouvier S: Supported F: target/hexagon/ +F: hw/intc/hex-l2vic.c +F: include/hw/intc/hex-l2vic.h X: target/hexagon/idef-parser/ X: target/hexagon/gen_idef_parser_funcs.py F: linux-user/hexagon/ @@ -262,6 +264,7 @@ F: gdbstub/gdb-xml/hexagon*.xml F: docs/system/target-hexagon.rst F: docs/system/hexagon/ F: docs/devel/hexagon-sys.rst +F: docs/devel/hexagon-l2vic.rst T: git https://github.com/qualcomm/qemu.git hex-next =20 Hexagon idef-parser diff --git a/docs/devel/hexagon-l2vic.rst b/docs/devel/hexagon-l2vic.rst new file mode 100644 index 00000000000..9cb2a86871e --- /dev/null +++ b/docs/devel/hexagon-l2vic.rst @@ -0,0 +1,55 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Hexagon L2 Vectored Interrupt Controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + +.. code-block:: none + + +-------------+ +----------------------+ + | l2vic | | hexagon core | + | | | | + IRQ in ---->| | | | + IRQ in ---->| VID0 -|----------------->| irq2 | + ... ---->| | | | | + IRQ in ---->| | | v | + | ... | | | + | | | / | | \ | + IRQ in ---->| | | t0 t1 t2 t3 ...| + IRQ in ---->| VIDN -| | | + ... ---->| | | | + IRQ in ---->| | | Global SREG File | + | | | | + | State | | | + | [ ] <--|=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D|=3D=3D> [ VID ] | + | [ ] <--|=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D|=3D=3D> [ VID1 ] | + | | | | + +-------------+ +----------------------+ + +L2VIC/Core Integration +---------------------- + +* hexagon core supports 8 external interrupt sources +* l2vic supports 1024 input interrupts mapped among 4 output interrupts +* l2vic has four output signals: { VID0, VID1, VID2, VID3 } +* l2vic device has a bank of registers per-VID that can be used to query + the status or assert new interrupts. +* Interrupts are 'steered' to threads based on { thread priority, 'EX' sta= te, + thread interrupt mask, thread interrupt enable, global interrupt enable, + etc. }. +* Any hardware thread could conceivably handle any input interrupt, depend= ent + on state. +* The system register transfer instruction can read the VID0-VID3 values f= rom + the l2vic when reading from hexagon core system registers "VID" and "VID= 1". +* When l2vic VID0 has multiple active interrupts, it pulses the VID0 output + IRQ and stores the IRQ number for the VID0 register field. Only after t= his + interrupt is cleared can the l2vic pulse the VID0 output IRQ again and p= rovide + the next interrupt number on the VID0 register. +* The ``ciad`` instruction clears the l2vic input interrupt and un-disable= s the + core interrupt. If some/an l2vic VID0 interrupt is pending when this oc= curs, + the next interrupt should fire and any subsequent reads of the VID regis= ter + should reflect the newly raised interrupt. +* In QEMU, on an external interrupt or an unmasked-pending interrupt, + all vCPUs are triggered (has_work=3D=3Dtrue) and each will grab the IO l= ock + while considering the steering logic to determine whether they're the th= read + that must handle the interrupt. diff --git a/docs/devel/index-internals.rst b/docs/devel/index-internals.rst index b89bab9b306..84985973490 100644 --- a/docs/devel/index-internals.rst +++ b/docs/devel/index-internals.rst @@ -15,6 +15,7 @@ Details about QEMU's various subsystems including how to = add features to them. clocks ebpf_rss hexagon-sys + hexagon-l2vic migration/index multi-process reset diff --git a/include/hw/intc/hex-l2vic.h b/include/hw/intc/hex-l2vic.h new file mode 100644 index 00000000000..f6519bcd6c2 --- /dev/null +++ b/include/hw/intc/hex-l2vic.h @@ -0,0 +1,87 @@ +/* + * QEMU L2VIC Interrupt Controller + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_INTC_HEX_L2VIC_H +#define HW_INTC_HEX_L2VIC_H + +#include "qom/object.h" + +#define L2VIC_VID_GRP_0 0x0 /* Read */ +#define L2VIC_VID_GRP_1 0x4 /* Read */ +#define L2VIC_VID_GRP_2 0x8 /* Read */ +#define L2VIC_VID_GRP_3 0xC /* Read */ +#define L2VIC_INT_ENABLEn 0x100 /* Read/Write */ +#define L2VIC_INT_ENABLE_CLEARn 0x180 /* Write */ +#define L2VIC_INT_ENABLE_SETn 0x200 /* Write */ +#define L2VIC_INT_TYPEn 0x280 /* Read/Write */ +#define L2VIC_INT_STATUSn 0x380 /* Read */ +#define L2VIC_INT_CLEARn 0x400 /* Write */ +#define L2VIC_SOFT_INTn 0x480 /* Write */ +#define L2VIC_INT_PENDINGn 0x500 /* Read */ +#define L2VIC_INT_GRPn_0 0x600 /* Read/Write */ +#define L2VIC_INT_GRPn_1 0x680 /* Read/Write */ +#define L2VIC_INT_GRPn_2 0x700 /* Read/Write */ +#define L2VIC_INT_GRPn_3 0x780 /* Read/Write */ + +#define L2VIC_INTERRUPT_MAX 1024 +/* + * Note about l2vic groups: + * Each interrupt to L2VIC can be configured to associate with one of + * four groups. + * Group 0 interrupts go to IRQ2 via VID 0 (SSR: 0xC2, the default) + * Group 1 interrupts go to IRQ3 via VID 1 (SSR: 0xC3) + * Group 2 interrupts go to IRQ4 via VID 2 (SSR: 0xC4) + * Group 3 interrupts go to IRQ5 via VID 3 (SSR: 0xC5) + */ + +#define TYPE_HEX_L2VIC "hex-l2vic" +/* + * L2VIC Interface for CPU/GlobalReg interaction + */ +#define TYPE_HEX_L2VIC_INTERFACE "hex-l2vic-if" + +typedef struct HexL2VicInterface HexL2VicInterface; + +typedef struct HexL2VicInterfaceClass { + InterfaceClass parent_class; + + /* Read VID register for given group */ + uint32_t (*read_vid)(HexL2VicInterface *l2vic, uint32_t group); + + /* Update VID register value */ + void (*update_vid)(HexL2VicInterface *l2vic, uint32_t group, + uint32_t value); + + /* Clear interrupt using CIAD instruction */ + void (*clear_interrupt)(HexL2VicInterface *l2vic); +} HexL2VicInterfaceClass; + +DECLARE_OBJ_CHECKERS(HexL2VicInterface, HexL2VicInterfaceClass, + HEX_L2VIC_INTERFACE, TYPE_HEX_L2VIC_INTERFACE); + +/* Convenience functions for interface users */ +static inline uint32_t l2vic_read_vid(HexL2VicInterface *l2vic, + uint32_t group) +{ + HexL2VicInterfaceClass *k =3D HEX_L2VIC_INTERFACE_GET_CLASS(l2vic); + return k->read_vid(l2vic, group); +} + +static inline void l2vic_update_vid(HexL2VicInterface *l2vic, uint32_t gro= up, + uint32_t value) +{ + HexL2VicInterfaceClass *k =3D HEX_L2VIC_INTERFACE_GET_CLASS(l2vic); + k->update_vid(l2vic, group, value); +} + +static inline void l2vic_clear_interrupt(HexL2VicInterface *l2vic) +{ + HexL2VicInterfaceClass *k =3D HEX_L2VIC_INTERFACE_GET_CLASS(l2vic); + k->clear_interrupt(l2vic); +} + +#endif /* HW_INTC_HEX_L2VIC_H */ diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 7694fd91fa8..f6c3c639325 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -39,6 +39,7 @@ typedef struct HexagonGlobalRegState HexagonGlobalRegStat= e; #include "qemu/bitmap.h" =20 #include "target/hexagon/reg_fields.h" +#include "hw/intc/hex-l2vic.h" =20 #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 @@ -198,6 +199,7 @@ struct ArchCPU { uint32_t boot_addr; HexagonGlobalRegState *globalregs; uint32_t htid; + HexL2VicInterface *l2vic; #endif }; =20 diff --git a/hw/intc/hex-l2vic.c b/hw/intc/hex-l2vic.c new file mode 100644 index 00000000000..a284ae8a567 --- /dev/null +++ b/hw/intc/hex-l2vic.c @@ -0,0 +1,511 @@ +/* + * QEMU L2VIC Interrupt Controller + * + * Arm PrimeCell PL190 Vector Interrupt Controller was used as a reference. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/irq.h" +#include "hw/core/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/lockable.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/bitmap.h" +#include "qemu/bitops.h" +#include "hw/intc/hex-l2vic.h" +#include "trace.h" + +static void bitmap32_write_word(uint32_t *bitmap, int word_offset, uint32_= t val) +{ + bitmap[word_offset] =3D val; +} + +static void bitmap32_clear_word(uint32_t *bitmap, int word_offset, + uint32_t mask) +{ + bitmap[word_offset] &=3D ~mask; +} + +static void bitmap32_set_word(uint32_t *bitmap, int word_offset, uint32_t = mask) +{ + bitmap[word_offset] |=3D mask; +} + +static uint32_t bitmap32_read_word(uint32_t *bitmap, int word_offset) +{ + return bitmap[word_offset]; +} + +OBJECT_DECLARE_SIMPLE_TYPE(HexL2VICState, HEX_L2VIC) + +#define SLICE_MAX (L2VIC_INTERRUPT_MAX / 32) + +typedef struct HexL2VICState { + SysBusDevice parent_obj; + + QemuMutex active; + MemoryRegion iomem; + MemoryRegion fast_iomem; + /* + * offset 0:vid group 0 etc, 10 bits in each group + * are used: + */ + uint32_t vid_group[4]; + uint32_t vid0; + /* Enable interrupt source */ + DECLARE_BITMAP32(int_enable, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + /* Present for debugging, not used */ + DECLARE_BITMAP32(int_pending, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + /* Which enabled interrupt is active */ + DECLARE_BITMAP32(int_status, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + /* Edge or Level interrupt */ + DECLARE_BITMAP32(int_type, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + /* L2 interrupt group 0-3 0x600-0x7FF */ + DECLARE_BITMAP32(int_group_n0, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + DECLARE_BITMAP32(int_group_n1, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + DECLARE_BITMAP32(int_group_n2, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + DECLARE_BITMAP32(int_group_n3, L2VIC_INTERRUPT_MAX) QEMU_ALIGNED(16); + qemu_irq irq[8]; +} HexL2VICState; + +/* + * Find out if this irq is associated with a group other than + * the default group + */ +static uint32_t *get_int_group(HexL2VICState *s, int irq) +{ + int n =3D irq & 0x1f; + if (n < 8) { + return s->int_group_n0; + } + if (n < 16) { + return s->int_group_n1; + } + if (n < 24) { + return s->int_group_n2; + } + return s->int_group_n3; +} + +static int find_slice(int irq) +{ + return irq / 32; +} + +static int get_vid(HexL2VICState *s, int irq) +{ + uint32_t *group =3D get_int_group(s, irq); + uint32_t slice =3D group[find_slice(irq)]; + /* Mask with 0x7 to remove the GRP:EN bit */ + uint32_t val =3D slice >> ((irq & 0x7) * 4); + if (val & 0x8) { + return val & 0x7; + } else { + return 0; + } +} + +static inline bool vid_active(HexL2VICState *s) +{ + /* scan all 1024 bits in int_status array */ + const uint32_t size =3D L2VIC_INTERRUPT_MAX; + const uint32_t active_irq =3D find_first_bit32(s->int_status, size); + return active_irq !=3D size; +} + +static bool l2vic_update(HexL2VICState *s, int irq) +{ + bool pending; + bool enable; + + if (vid_active(s)) { + return true; + } + + pending =3D test_bit32(irq, s->int_pending); + enable =3D test_bit32(irq, s->int_enable); + if (pending && enable) { + int vid =3D get_vid(s, irq); + set_bit32(irq, s->int_status); + clear_bit32(irq, s->int_pending); + /* + * Only auto-disable for edge-triggered interrupts (type=3D1). + * Level-triggered interrupts (type=3D0, the default) keep their + * enable bit set across deliveries -- the firmware enables once + * and expects the interrupt to remain enabled. + */ + if (test_bit32(irq, s->int_type)) { + clear_bit32(irq, s->int_enable); + } + s->vid0 =3D irq; + s->vid_group[vid] =3D irq; + + qemu_irq_pulse(s->irq[vid + 2]); + trace_hex_l2vic_delivered(irq, vid); + return true; + } + return false; +} + +static void l2vic_update_all(HexL2VICState *s) +{ + for (int i =3D 0; i < L2VIC_INTERRUPT_MAX; i++) { + if (l2vic_update(s, i)) { + /* once vid is active, no-one else can set it until ciad */ + return; + } + } +} + +static void l2vic_set_irq(void *opaque, int irq, int level) +{ + HexL2VICState *s =3D (HexL2VICState *)opaque; + + QEMU_LOCK_GUARD(&s->active); + if (level) { + set_bit32(irq, s->int_pending); + } + l2vic_update(s, irq); +} + +static void l2vic_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + HexL2VICState *s =3D (HexL2VICState *)opaque; + + QEMU_LOCK_GUARD(&s->active); + trace_hex_l2vic_reg_write((unsigned)offset, (uint32_t)val); + + if (offset >=3D L2VIC_INT_ENABLEn && + offset < (L2VIC_INT_ENABLE_CLEARn)) { + bitmap32_write_word(s->int_enable, + (offset - L2VIC_INT_ENABLEn) >> 2, val); + } else if (offset >=3D L2VIC_INT_ENABLE_CLEARn && + offset < L2VIC_INT_ENABLE_SETn) { + bitmap32_clear_word(s->int_enable, + (offset - L2VIC_INT_ENABLE_CLEARn) >> 2, val); + } else if (offset >=3D L2VIC_INT_ENABLE_SETn && offset < L2VIC_INT_TYP= En) { + bitmap32_set_word(s->int_enable, + (offset - L2VIC_INT_ENABLE_SETn) >> 2, val); + } else if (offset >=3D L2VIC_INT_TYPEn && offset < L2VIC_INT_TYPEn + 0= x80) { + bitmap32_write_word(s->int_type, + (offset - L2VIC_INT_TYPEn) >> 2, val); + } else if (offset >=3D L2VIC_INT_STATUSn && offset < L2VIC_INT_CLEARn)= { + bitmap32_write_word(s->int_status, + (offset - L2VIC_INT_STATUSn) >> 2, val); + } else if (offset >=3D L2VIC_INT_CLEARn && offset < L2VIC_SOFT_INTn) { + bitmap32_clear_word(s->int_status, + (offset - L2VIC_INT_CLEARn) >> 2, val); + } else if (offset >=3D L2VIC_INT_PENDINGn && + offset < L2VIC_INT_PENDINGn + 0x80) { + bitmap32_write_word(s->int_pending, + (offset - L2VIC_INT_PENDINGn) >> 2, val); + } else if (offset >=3D L2VIC_SOFT_INTn && offset < L2VIC_INT_PENDINGn)= { + int irq; + hwaddr byteoffset =3D offset - L2VIC_SOFT_INTn; + + bitmap32_set_word(s->int_enable, (offset - L2VIC_SOFT_INTn) >> 2, = val); + if (val) { + irq =3D ctz32((uint32_t)val); + irq +=3D byteoffset * 8; + + if (test_bit32(irq, s->int_type)) { + set_bit32(irq, s->int_pending); + } + } + } else if (offset >=3D L2VIC_INT_GRPn_0 && offset < L2VIC_INT_GRPn_1) { + bitmap32_write_word(s->int_group_n0, + (offset - L2VIC_INT_GRPn_0) >> 2, val); + } else if (offset >=3D L2VIC_INT_GRPn_1 && offset < L2VIC_INT_GRPn_2) { + bitmap32_write_word(s->int_group_n1, + (offset - L2VIC_INT_GRPn_1) >> 2, val); + } else if (offset >=3D L2VIC_INT_GRPn_2 && offset < L2VIC_INT_GRPn_3) { + bitmap32_write_word(s->int_group_n2, + (offset - L2VIC_INT_GRPn_2) >> 2, val); + } else if (offset >=3D L2VIC_INT_GRPn_3 && offset < L2VIC_INT_GRPn_3 += 0x80) { + bitmap32_write_word(s->int_group_n3, + (offset - L2VIC_INT_GRPn_3) >> 2, val); + } else { + qemu_log_mask(LOG_UNIMP, + "%s: offset 0x%" HWADDR_PRIx " unimplemented\n", + __func__, offset); + } + + l2vic_update_all(s); +} + +static uint64_t l2vic_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t value; + HexL2VICState *s =3D (HexL2VICState *)opaque; + + QEMU_LOCK_GUARD(&s->active); + + if (offset =3D=3D L2VIC_VID_GRP_0) { + value =3D s->vid_group[0]; + } else if (offset =3D=3D L2VIC_VID_GRP_1) { + value =3D s->vid_group[1]; + } else if (offset =3D=3D L2VIC_VID_GRP_2) { + value =3D s->vid_group[2]; + } else if (offset =3D=3D L2VIC_VID_GRP_3) { + value =3D s->vid_group[3]; + } else if (offset >=3D L2VIC_INT_ENABLEn && + offset < L2VIC_INT_ENABLE_CLEARn) { + value =3D bitmap32_read_word(s->int_enable, + (offset - L2VIC_INT_ENABLEn) >> 2); + } else if (offset >=3D L2VIC_INT_ENABLE_CLEARn && + offset < L2VIC_INT_ENABLE_SETn) { + value =3D 0; + } else if (offset >=3D L2VIC_INT_ENABLE_SETn && offset < L2VIC_INT_TYP= En) { + value =3D 0; + } else if (offset >=3D L2VIC_INT_TYPEn && offset < L2VIC_INT_TYPEn + 0= x80) { + value =3D bitmap32_read_word(s->int_type, + (offset - L2VIC_INT_TYPEn) >> 2); + } else if (offset >=3D L2VIC_INT_STATUSn && offset < L2VIC_INT_CLEARn)= { + value =3D bitmap32_read_word(s->int_status, + (offset - L2VIC_INT_STATUSn) >> 2); + } else if (offset >=3D L2VIC_INT_CLEARn && offset < L2VIC_SOFT_INTn) { + /* INT_CLEARn is write-only, return 0 on read */ + value =3D 0; + } else if (offset >=3D L2VIC_SOFT_INTn && offset < L2VIC_INT_PENDINGn)= { + value =3D 0; + } else if (offset >=3D L2VIC_INT_PENDINGn && + offset < L2VIC_INT_PENDINGn + 0x80) { + value =3D bitmap32_read_word(s->int_pending, + (offset - L2VIC_INT_PENDINGn) >> 2); + } else if (offset >=3D L2VIC_INT_GRPn_0 && offset < L2VIC_INT_GRPn_1) { + value =3D bitmap32_read_word(s->int_group_n0, + (offset - L2VIC_INT_GRPn_0) >> 2); + } else if (offset >=3D L2VIC_INT_GRPn_1 && offset < L2VIC_INT_GRPn_2) { + value =3D bitmap32_read_word(s->int_group_n1, + (offset - L2VIC_INT_GRPn_1) >> 2); + } else if (offset >=3D L2VIC_INT_GRPn_2 && offset < L2VIC_INT_GRPn_3) { + value =3D bitmap32_read_word(s->int_group_n2, + (offset - L2VIC_INT_GRPn_2) >> 2); + } else if (offset >=3D L2VIC_INT_GRPn_3 && offset < L2VIC_INT_GRPn_3 += 0x80) { + value =3D bitmap32_read_word(s->int_group_n3, + (offset - L2VIC_INT_GRPn_3) >> 2); + } else { + value =3D 0; + qemu_log_mask(LOG_GUEST_ERROR, + "L2VIC: %s: offset 0x%" HWADDR_PRIx "\n", __func__, + offset); + } + + trace_hex_l2vic_reg_read((unsigned)offset, (uint32_t)value); + return value; +} + +static const MemoryRegionOps l2vic_ops =3D { + .read =3D l2vic_read, + .write =3D l2vic_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +#define FASTL2VIC_ENABLE 0x0 +#define FASTL2VIC_DISABLE 0x1 +#define FASTL2VIC_INT 0x2 + +static void fastl2vic_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + if (offset =3D=3D 0) { + uint32_t cmd =3D (val >> 16) & 0x3; + uint32_t irq =3D val & 0x3ff; + uint32_t slice =3D (irq / 32) * 4; + val =3D 1 << (irq % 32); + + if (cmd =3D=3D FASTL2VIC_ENABLE) { + l2vic_write(opaque, L2VIC_INT_ENABLE_SETn + slice, val, size); + } else if (cmd =3D=3D FASTL2VIC_DISABLE) { + l2vic_write(opaque, L2VIC_INT_ENABLE_CLEARn + slice, val, size= ); + } else if (cmd =3D=3D FASTL2VIC_INT) { + l2vic_write(opaque, L2VIC_SOFT_INTn + slice, val, size); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid write cmd %" PRId32 "\n", + __func__, cmd); + } + return; + } + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid write offset 0x%08" HWADDR= _PRIx + "\n", __func__, offset); +} + +static const MemoryRegionOps fastl2vic_ops =3D { + .write =3D fastl2vic_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +/* L2VIC Interface Implementation */ +static uint32_t l2vic_interface_read_vid_impl(HexL2VicInterface *iface, + uint32_t group) +{ + HexL2VICState *s =3D HEX_L2VIC(iface); + uint32_t result =3D 0; + + QEMU_LOCK_GUARD(&s->active); + if (group =3D=3D 0) { + /* VID register: VID1 (bits 16-31), VID0 (bits 0-15) */ + result =3D deposit32(result, 0, 16, s->vid_group[0]); + result =3D deposit32(result, 16, 16, s->vid_group[1]); + } else if (group =3D=3D 1) { + /* VID1 register: VID3 (bits 16-31), VID2 (bits 0-15) */ + result =3D deposit32(result, 0, 16, s->vid_group[2]); + result =3D deposit32(result, 16, 16, s->vid_group[3]); + } + return result; +} + +static void l2vic_interface_update_vid_impl(HexL2VicInterface *iface, + uint32_t group, uint32_t value) +{ + HexL2VICState *s =3D HEX_L2VIC(iface); + + QEMU_LOCK_GUARD(&s->active); + + if (group =3D=3D 0) { + /* VID register: unpack VID0 and VID1 */ + s->vid_group[0] =3D extract32(value, 0, 16); + s->vid_group[1] =3D extract32(value, 16, 16); + } else if (group =3D=3D 1) { + /* VID1 register: unpack VID2 and VID3 */ + s->vid_group[2] =3D extract32(value, 0, 16); + s->vid_group[3] =3D extract32(value, 16, 16); + } + + l2vic_update_all(s); +} + +static void l2vic_interface_clear_interrupt_impl(HexL2VicInterface *iface) +{ + HexL2VICState *s =3D HEX_L2VIC(iface); + + QEMU_LOCK_GUARD(&s->active); + if (s->vid0 < L2VIC_INTERRUPT_MAX) { + clear_bit32(s->vid0, s->int_status); + } + l2vic_update_all(s); +} + +static void l2vic_reset_hold(Object *obj, ResetType type G_GNUC_UNUSED) +{ + HexL2VICState *s =3D HEX_L2VIC(obj); + + QEMU_LOCK_GUARD(&s->active); + memset(s->int_enable, 0, sizeof(s->int_enable)); + memset(s->int_pending, 0, sizeof(s->int_pending)); + memset(s->int_status, 0, sizeof(s->int_status)); + memset(s->int_type, 0, sizeof(s->int_type)); + memset(s->int_group_n0, 0, sizeof(s->int_group_n0)); + memset(s->int_group_n1, 0, sizeof(s->int_group_n1)); + memset(s->int_group_n2, 0, sizeof(s->int_group_n2)); + memset(s->int_group_n3, 0, sizeof(s->int_group_n3)); + memset(s->vid_group, 0, sizeof(s->vid_group)); + s->vid0 =3D 0; + + l2vic_update_all(s); +} + +static void reset_irq_handler(void *opaque, int irq, int level) +{ + Object *obj =3D OBJECT(opaque); + + if (level) { + l2vic_reset_hold(obj, RESET_TYPE_COLD); + } +} + +static void l2vic_init(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + HexL2VICState *s =3D HEX_L2VIC(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + int i; + + memory_region_init_io(&s->iomem, obj, &l2vic_ops, s, "l2vic", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); + memory_region_init_io(&s->fast_iomem, obj, &fastl2vic_ops, s, "fast", + 0x10000); + sysbus_init_mmio(sbd, &s->fast_iomem); + + qdev_init_gpio_in(dev, l2vic_set_irq, L2VIC_INTERRUPT_MAX); + qdev_init_gpio_in_named(dev, reset_irq_handler, "reset", 1); + for (i =3D 0; i < 8; i++) { + sysbus_init_irq(sbd, &s->irq[i]); + } + qemu_mutex_init(&s->active); +} + +static const VMStateDescription vmstate_l2vic =3D { + .name =3D "l2vic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D + (VMStateField[]){ + VMSTATE_UINT32_ARRAY(vid_group, HexL2VICState, 4), + VMSTATE_UINT32(vid0, HexL2VICState), + VMSTATE_UINT32_ARRAY(int_enable, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_type, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_status, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_pending, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n0, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n1, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n2, HexL2VICState, SLICE_MAX), + VMSTATE_UINT32_ARRAY(int_group_n3, HexL2VICState, SLICE_MAX), + VMSTATE_END_OF_LIST() } +}; + +static void l2vic_interface_class_init(ObjectClass *klass, const void *dat= a) +{ + HexL2VicInterfaceClass *k =3D HEX_L2VIC_INTERFACE_CLASS(klass); + + k->read_vid =3D l2vic_interface_read_vid_impl; + k->update_vid =3D l2vic_interface_update_vid_impl; + k->clear_interrupt =3D l2vic_interface_clear_interrupt_impl; +} + +static void l2vic_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->vmsd =3D &vmstate_l2vic; + rc->phases.hold =3D l2vic_reset_hold; +} + +static const TypeInfo l2vic_interface_info =3D { + .name =3D TYPE_HEX_L2VIC_INTERFACE, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(HexL2VicInterfaceClass), + .class_init =3D l2vic_interface_class_init, +}; + +static const TypeInfo l2vic_info =3D { + .name =3D TYPE_HEX_L2VIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(HexL2VICState), + .instance_init =3D l2vic_init, + .class_init =3D l2vic_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HEX_L2VIC_INTERFACE }, + { } + }, +}; + +static void l2vic_register_types(void) +{ + type_register_static(&l2vic_interface_info); + type_register_static(&l2vic_info); +} + +type_init(l2vic_register_types) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 42d93e5da47..be56ac0419f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -65,6 +65,8 @@ static const Property hexagon_cpu_properties[] =3D { DEFINE_PROP_LINK("tlb", HexagonCPU, tlb, TYPE_HEXAGON_TLB, HexagonTLBState *), DEFINE_PROP_UINT32("exec-start-addr", HexagonCPU, boot_addr, 0xfffffff= f), + DEFINE_PROP_LINK("l2vic", HexagonCPU, l2vic, + TYPE_HEX_L2VIC_INTERFACE, HexL2VicInterface *), DEFINE_PROP_LINK("global-regs", HexagonCPU, globalregs, TYPE_HEXAGON_GLOBALREG, HexagonGlobalRegState *), DEFINE_PROP_UINT32("htid", HexagonCPU, htid, 0), diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 125952aee59..0d88ae65e75 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -40,6 +40,7 @@ #include "hw/hexagon/hexagon_globalreg.h" #include "hex_mmu.h" #include "hw/hexagon/hexagon_tlb.h" +#include "hw/intc/hex-l2vic.h" #include "hex_interrupts.h" #include "hexswi.h" #endif @@ -1557,7 +1558,25 @@ void HELPER(raise_stack_overflow)(CPUHexagonState *e= nv, uint32_t slot, =20 void HELPER(ciad)(CPUHexagonState *env, uint32_t mask) { - g_assert_not_reached(); + uint32_t ipendad; + uint32_t iad; + HexagonCPU *cpu; + + BQL_LOCK_GUARD(); + cpu =3D env_archcpu(env); + ipendad =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId) : 0; + iad =3D fGET_FIELD(ipendad, IPENDAD_IAD); + fSET_FIELD(ipendad, IPENDAD_IAD, iad & ~(mask)); + if (cpu->globalregs) { + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); + } + if (cpu->l2vic) { + l2vic_clear_interrupt(cpu->l2vic); + } + hex_interrupt_update(env); } =20 void HELPER(siad)(CPUHexagonState *env, uint32_t mask) diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index 52065ab3b22..191c6c5d65c 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -2,6 +2,7 @@ config HEX_DSP bool default y depends on HEXAGON + select HEX_L2VIC =20 config HEX_VIRT bool diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 636d00b7e88..097de4efc5d 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -8,6 +8,9 @@ config I8259 config PL190 bool =20 +config HEX_L2VIC + bool + config IOAPIC bool select I8259 diff --git a/hw/intc/meson.build b/hw/intc/meson.build index fac2d228f9b..9077a3f3297 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -74,6 +74,8 @@ specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('x= ics_spapr.c', 'spapr_xi specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) + +specific_ss.add(when: 'CONFIG_HEX_L2VIC', if_true: files('hex-l2vic.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongs= on_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.= c')) diff --git a/hw/intc/trace-events b/hw/intc/trace-events index e7d6c304487..7512c6e6004 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -337,6 +337,10 @@ sh_intc_register(const char *s, int id, unsigned short= v, int c, int m) "%s %u - sh_intc_read(unsigned size, uint64_t offset, unsigned long val) "size %u 0= x%" PRIx64 " -> 0x%lx" sh_intc_write(unsigned size, uint64_t offset, unsigned long val) "size %u = 0x%" PRIx64 " <- 0x%lx" sh_intc_set(int id, int enable) "setting interrupt group %d to %d" +# hex-l2vic.c +hex_l2vic_reg_write(unsigned int addr, uint32_t value) "addr: 0x%03x value= : 0x%08"PRIx32 +hex_l2vic_reg_read(unsigned int addr, uint32_t value) "addr: 0x%03x value:= 0x%08"PRIx32 +hex_l2vic_delivered(int irq, int vid) "l2vic: delivered %d (vid %d)" =20 # loongson_ipi.c loongson_ipi_read(unsigned size, uint64_t addr, uint64_t val) "size: %u ad= dr: 0x%"PRIx64 "val: 0x%"PRIx64 --=20 2.34.1 From nobody Sat Jul 25 18:54:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784044339; cv=none; d=zohomail.com; s=zohoarc; b=RSXIig32gV+Sa843k585Y2s6V8QkGtUxcf6zVqj3Q9E4sw0qlbdtuvAyVm2FZz8L6//2rJZvquLe5V3kYX111NHnNun9HzMDUBZXLBUW9E3fUWTndybFNgF7peDHvARr0hrC7UafnPgLUUwW2BFrUlu7eS/ZrXwWw+rJfvgIe/8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784044339; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RvDTigIKJjsKosJ3emR2R076QugkRC4yRGucJVActXs=; b=fQaVwYIEUSQK3HlCuoBKLL0ypy1wm91Hx3h2jNk++Pnjgt6jUHUXm9odaUsaH0za1wLYfnGwSaZSsWMsi6AVakJHLTM0PLxykeCGq/HgnfEc/0EXPIn+L4QHQlI/DwkiDfJybZ8LxbJbu3LE8WaM/YwIyqbgBEKpqkqQCIyC104= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784044339903349.19405517209066; Tue, 14 Jul 2026 08:52:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wjfQ6-0000zO-GV; Tue, 14 Jul 2026 11:51:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfQ4-0000yu-K6 for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:40 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfQ2-00014Z-LD for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:40 -0400 Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66EEchAx824377 for ; Tue, 14 Jul 2026 15:51:37 GMT Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fdbr4b43m-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 14 Jul 2026 15:51:37 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c9d5a5b63c5so6642835a12.1 for ; Tue, 14 Jul 2026 08:51:37 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b987fc629sm41343581c88.0.2026.07.14.08.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 08:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= RvDTigIKJjsKosJ3emR2R076QugkRC4yRGucJVActXs=; b=BW9UaLkdNnj7ZKEy XEKMmuMPNrwrz3TYkCGaXJuDyC4izHF4RFNLsr88gf9P9q46SesQxhbETFVo8Gnc 7zh4Nor67T5CD5Q1+UKjfi3rigoV5qkFEuF2BxjzOnO1AkKdP6PgQ4sV46ZxTBWv ry7tmHB3VqQp8fOxyVlzUT4MLLBLXdNznPtOysM3fGLP9kkVg0YEOCuYTLrAmw2r 5xLMnPYEBhQ6rx/rRHzSEMgW0HaMBCvTYO//wZ0Qm/FuJSVebum2ct5J99iY8wiV sMH7MN/xer5c9266goTZ1Xqh6Ne7yWz35b9vZgRtsgpnn88sTd1Df5uwsAGmG2qr V32VVg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784044297; x=1784649097; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=RvDTigIKJjsKosJ3emR2R076QugkRC4yRGucJVActXs=; b=h4QphwVTx2DzmRzIDYQE6+XXdJRPlt9AaIyUsvJJJEd3Wq4g26KzrVN+QKRYCxs8xG f4ma8A4cBi4cz9heE0SobrgAY5sDmX8Cy7MdXW/Hhoka4tRpsT8NrmZjvkEzVPgt6wRY y4/xNlS79GO87OhrcJeZ0x5W201p3cnQgu0RZaUSpGikKrNzW+3k7xhYULhyUh9X9QEt ppTvbfqn9pTCZNtnEKsBniS0SSWRtrg3sf104AI9qTiX2IafmfHbzIw9/Eh1TVdx8MHW wYfmy8nzjhQK934T5ODPzQXli+ALwbvEtLmCY6GjMAkbO/FdyUPsETZQ4E1w6AUul2uD wiFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784044297; x=1784649097; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=RvDTigIKJjsKosJ3emR2R076QugkRC4yRGucJVActXs=; b=Jjn5095evE/QMYbDE6py9U67s2MpbLNJ+pBbwSdd2MYIuwt4YjgJOs76rGislO7fus Po9LqvTNN3EqtbXkVhVhaGBIF5DgAR847qbMGWP7/URo9f3wiOfyruHyr/+hIXRvLGdQ VTEF3isugHGslgMp94fdI8q12ZLn3mtVko5Nu1gTdofb2TPOSuy/j4lll4Ypta6q26uR pPK6BrX+YRH5Kp6o3yVPDxKyX6ob9P+SOk/HKm3ByJg+p/oe2sRA4AYnf8R0rXF7Ri4D 5QcaGkDOE+yi645vAay8QbxKcLE8CWMFRV7U61Ke39GY5nTDnuEM7hrGOZzSeMm/+tVB lbmA== X-Gm-Message-State: AOJu0Yxpbfn71qLu3hQfSRrZ6cKoOmuNMTZbYMngje1b634mR7NsNJgH H77zGdPRmrT9c7H8DuPWrud5iTOaO6wBQFQMM1VWZbCsmhgZDM1Ikz8oL0bscvqXLHxce978bYC cZg5gx49CKklVSyZ4rF9B3iTuVYoUfXoTRkGRkhPqdkjd+u737xPfN4A8H59pDSkoOA== X-Gm-Gg: AfdE7cmo+gq2P+baYl3TkZg0OoEv4Swk93n7U18kwJ5Jq2Jvvm4G9XDgB0RrBSnXV6X gK7V7GhfVryLOae3Y21yTot3SyN3shOax9cv7pUHzaqrTIWY5dz9cxd9vVfG5z/E+oANCxDn9lI ZRHSbdnng28nlihSoSiD93Ri4JrcWTL5VT6/S3CjXRH+RL2Ou8Yazqinfp8051ksoOqCF7nZApr MWI8tNt2BjF+VIRmpQ1YPUx9J8Gf0TSf29Ylr8hDoLpEISYckHwpMnaVVtvBp001iamUFxX2DS2 pRg1SB0866vLrwGQ8arDw27ZQ+SkKJ2eP+Jg+s98dU7IWvnhO+4nWHw6NqJPMORr/hGuryM2bQA Hnu/PX7FnBLx4sS2UH4QGq6Wz/z8sao1ZZvUZJyHVXIrysIdoG/idukYziB8= X-Received: by 2002:a05:6a20:d818:b0:3b4:e4f0:94e1 with SMTP id adf61e73a8af0-3c3571d0443mr3857580637.39.1784044296495; Tue, 14 Jul 2026 08:51:36 -0700 (PDT) X-Received: by 2002:a05:6a20:d818:b0:3b4:e4f0:94e1 with SMTP id adf61e73a8af0-3c3571d0443mr3857551637.39.1784044296012; Tue, 14 Jul 2026 08:51:36 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: ltaylorsimpson@gmail.com, Laurent Vivier , Thomas Huth , Paolo Bonzini , matheus.bernardino@oss.qualcomm.com, Fabiano Rosas , Brian Cain , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/7] hw/hexagon: connect l2vic device Date: Tue, 14 Jul 2026 08:51:24 -0700 Message-Id: <20260714155126.3509544-6-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> References: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: LjbopdRuKRYxHZqFI2wDCd9QOYkWMPbv X-Proofpoint-ORIG-GUID: LjbopdRuKRYxHZqFI2wDCd9QOYkWMPbv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfX0VXXt7v54x2d vd4uxF+f43Nh86/20qu2dh22myrSUnrSOq6XUiSWh5LCxjIF8HRZGMoVASMHV4Z0xsHc2tuqPZk 8sHtXrKzAGZ11cYGYaSc46EN06rvS8R6YbD+BG8G1Cv2rQMqrmjoDs9ibe4k3i5QocbIKEvxD1t iayxG5hHr26wN7nVScPH52DXdTRqOmgzQsY+qYDu9K81eQ09d5Ixp8hbz0Oi7XwkRqITkPcBRa5 d6y+892yuP/P1iDNSs7km5nizHNknk01GJMqKBLB1ruo3rL3l3xyAn8We/dp+2iTdqhqk+dBKRn u8LTKfvKBeh9NjIGu7rVyYXVb+QnVYo5JiTWhxqO9mOkFb8ab5HJXOnI/RM6TkcI0JjD06Ndefp 405E4gYzthCaDF1Bv2d7BvufT1JF84Hmbz1RZq96nQB1qCMBgLumaJwYW+yazlyG7tYStLUPqYM T4umEfPscYmVKxVB0iw== X-Authority-Analysis: v=2.4 cv=F5hnsKhN c=1 sm=1 tr=0 ts=6a565b09 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=ch7oxrfPrZXSMDqqmA0A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfX1XCF3BWj2V8j FtxDd654BO7SVBjDa6lhMoUCpxkAQKJHroUuryuq4bd8gUvtGuhvS76HXxaBGw3ciPENYGZnIRW JnTzdET6VgQR3m4i7f7yIXt01YTrT5w= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_03,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 clxscore=1015 adultscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140164 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784044341482158500 Instantiate the L2VIC device in both machine models, map its slow and MMIO regions, and link it to each CPU via the "l2vic" property. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- include/hw/hexagon/hexagon.h | 1 + include/hw/hexagon/hexagon_globalreg.h | 4 +++ hw/hexagon/hexagon_dsp.c | 20 +++++++++++++ hw/hexagon/hexagon_globalreg.c | 41 ++++++++++++++++++++++---- hw/hexagon/virt.c | 22 ++++++++++++++ 5 files changed, 83 insertions(+), 5 deletions(-) diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 1034b09c2ac..6753ae32cde 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -156,6 +156,7 @@ struct HexagonCommonMachineState { =20 MemoryRegion ram; MemoryRegion cfgtable_rom; + DeviceState *l2vic_dev; }; =20 #endif diff --git a/include/hw/hexagon/hexagon_globalreg.h b/include/hw/hexagon/he= xagon_globalreg.h index 950099808fd..397dc6854c9 100644 --- a/include/hw/hexagon/hexagon_globalreg.h +++ b/include/hw/hexagon/hexagon_globalreg.h @@ -10,6 +10,7 @@ =20 #include "hw/core/qdev.h" #include "hw/core/sysbus.h" +#include "hw/intc/hex-l2vic.h" #include "qom/object.h" #include "target/hexagon/cpu.h" =20 @@ -22,6 +23,9 @@ struct HexagonGlobalRegState { /* Array of system registers */ uint32_t regs[NUM_SREGS]; =20 + /* L2VIC interface used to back the VID/VID1 registers */ + HexL2VicInterface *l2vic; + /* Global performance cycle counter base */ uint64_t g_pcycle_base; =20 diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c index aa493993229..4cf88627c8f 100644 --- a/hw/hexagon/hexagon_dsp.c +++ b/hw/hexagon/hexagon_dsp.c @@ -16,6 +16,7 @@ #include "hw/hexagon/hexagon.h" #include "hw/hexagon/hexagon_globalreg.h" #include "hw/hexagon/hexagon_tlb.h" +#include "hw/intc/hex-l2vic.h" #include "hw/core/loader.h" #include "qapi/error.h" #include "qemu/error-report.h" @@ -111,6 +112,7 @@ static void hexagon_common_init(MachineState *machine, = Rev_t rev, MemoryRegion *address_space; DeviceState *glob_regs_dev; DeviceState *tlb_dev; + DeviceState *cpu0 =3D NULL; =20 memset(&hexagon_binfo, 0, sizeof(hexagon_binfo)); if (machine->kernel_filename) { @@ -131,11 +133,21 @@ static void hexagon_common_init(MachineState *machine= , Rev_t rev, machine->ram_size, &error_fatal); memory_region_add_subregion(address_space, 0x0, &hms->ram); =20 + hms->l2vic_dev =3D qdev_new(TYPE_HEX_L2VIC); + object_property_add_child(OBJECT(machine), "l2vic", + OBJECT(hms->l2vic_dev)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(hms->l2vic_dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(hms->l2vic_dev), 0, m_cfg->l2vic_base); + sysbus_mmio_map(SYS_BUS_DEVICE(hms->l2vic_dev), 1, + m_cfg->cfgtable.fastl2vic_base << 16); + glob_regs_dev =3D qdev_new(TYPE_HEXAGON_GLOBALREG); object_property_add_child(OBJECT(machine), "global-regs", OBJECT(glob_regs_dev)); qdev_prop_set_uint64(glob_regs_dev, "config-table-addr", m_cfg->cfgbas= e); qdev_prop_set_uint32(glob_regs_dev, "dsp-rev", rev); + object_property_set_link(OBJECT(glob_regs_dev), "l2vic", + OBJECT(hms->l2vic_dev), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(glob_regs_dev), &error_fatal); =20 tlb_dev =3D qdev_new(TYPE_HEXAGON_TLB); @@ -154,15 +166,23 @@ static void hexagon_common_init(MachineState *machine= , Rev_t rev, */ qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", (i !=3D 0)); if (i =3D=3D 0) { + cpu0 =3D DEVICE(cpu); hexagon_init_bootstrap(dms, cpu); } object_property_set_link(OBJECT(cpu), "global-regs", OBJECT(glob_regs_dev), &error_fatal); object_property_set_link(OBJECT(cpu), "tlb", OBJECT(tlb_dev), &error_fatal); + object_property_set_link(OBJECT(cpu), "l2vic", + OBJECT(hms->l2vic_dev), &error_fatal); qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); } =20 + for (int i =3D 0; i < 8; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(hms->l2vic_dev), i, + qdev_get_gpio_in(cpu0, i)); + } + rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable, sizeof(m_cfg->cfgtable), m_cfg->cfgbase, &address_space_memory); diff --git a/hw/hexagon/hexagon_globalreg.c b/hw/hexagon/hexagon_globalreg.c index b5e5913507e..3d0d6f9516c 100644 --- a/hw/hexagon/hexagon_globalreg.c +++ b/hw/hexagon/hexagon_globalreg.c @@ -11,6 +11,7 @@ #include "hw/core/qdev-properties.h" #include "hw/core/sysbus.h" #include "hw/core/resettable.h" +#include "hw/intc/hex-l2vic.h" #include "migration/vmstate.h" #include "qom/object.h" #include "target/hexagon/cpu.h" @@ -135,6 +136,32 @@ static inline uint32_t apply_write_mask(uint32_t new_v= al, uint32_t cur_val, return new_val; } =20 +static inline bool is_vid_reg(uint32_t reg) +{ + return reg =3D=3D HEX_SREG_VID || reg =3D=3D HEX_SREG_VID1; +} + +/* + * HEX_SREG_VID/VID1 are backed by the L2VIC's VID group registers + * rather than the plain regs[] array, when an L2VIC is wired up. + */ +static uint32_t get_reg_value(HexagonGlobalRegState *s, uint32_t reg) +{ + if (is_vid_reg(reg) && s->l2vic) { + return l2vic_read_vid(s->l2vic, reg =3D=3D HEX_SREG_VID ? 0 : 1); + } + return s->regs[reg]; +} + +static void set_reg_value(HexagonGlobalRegState *s, uint32_t reg, + uint32_t value) +{ + s->regs[reg] =3D value; + if (is_vid_reg(reg) && s->l2vic) { + l2vic_update_vid(s->l2vic, reg =3D=3D HEX_SREG_VID ? 0 : 1, value); + } +} + uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg, uint32_t htid) { @@ -146,7 +173,7 @@ uint32_t hexagon_globalreg_read(HexagonGlobalRegState *= s, uint32_t reg, g_assert(reg < NUM_SREGS); g_assert(reg >=3D HEX_SREG_GLB_START); =20 - value =3D s->regs[reg]; + value =3D get_reg_value(s, reg); =20 trace_hexagon_globalreg_read(htid, get_sreg_name(reg), value); return value; @@ -160,7 +187,7 @@ void hexagon_globalreg_write(HexagonGlobalRegState *s, = uint32_t reg, } g_assert(reg < NUM_SREGS); g_assert(reg >=3D HEX_SREG_GLB_START); - s->regs[reg] =3D value; + set_reg_value(s, reg, value); trace_hexagon_globalreg_write(htid, get_sreg_name(reg), value); } =20 @@ -168,6 +195,7 @@ uint32_t hexagon_globalreg_masked_value(HexagonGlobalRe= gState *s, uint32_t reg, uint32_t value) { uint32_t reg_mask; + uint32_t cur_val; =20 if (!s) { return value; @@ -175,9 +203,10 @@ uint32_t hexagon_globalreg_masked_value(HexagonGlobalR= egState *s, uint32_t reg, g_assert(reg < NUM_SREGS); g_assert(reg >=3D HEX_SREG_GLB_START); reg_mask =3D global_sreg_immut_masks[reg]; + cur_val =3D get_reg_value(s, reg); return reg_mask =3D=3D IMMUTABLE ? - s->regs[reg] : - apply_write_mask(value, s->regs[reg], reg_mask); + cur_val : + apply_write_mask(value, cur_val, reg_mask); } =20 void hexagon_globalreg_write_masked(HexagonGlobalRegState *s, uint32_t reg, @@ -186,7 +215,7 @@ void hexagon_globalreg_write_masked(HexagonGlobalRegSta= te *s, uint32_t reg, if (!s) { return; } - s->regs[reg] =3D hexagon_globalreg_masked_value(s, reg, value); + set_reg_value(s, reg, hexagon_globalreg_masked_value(s, reg, value)); } =20 uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s) @@ -275,6 +304,8 @@ static const VMStateDescription vmstate_hexagon_globalr= eg =3D { }; =20 static const Property hexagon_globalreg_properties[] =3D { + DEFINE_PROP_LINK("l2vic", HexagonGlobalRegState, l2vic, + TYPE_HEX_L2VIC_INTERFACE, HexL2VicInterface *), DEFINE_PROP_UINT32("boot-evb", HexagonGlobalRegState, boot_evb, 0x0), DEFINE_PROP_UINT64("config-table-addr", HexagonGlobalRegState, config_table_addr, 0xffffffffULL), diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c index a3638998b87..2256d3d53a5 100644 --- a/hw/hexagon/virt.c +++ b/hw/hexagon/virt.c @@ -15,6 +15,7 @@ #include "hw/hexagon/hexagon.h" #include "hw/hexagon/hexagon_globalreg.h" #include "hw/hexagon/hexagon_tlb.h" +#include "hw/intc/hex-l2vic.h" #include "hw/core/loader.h" #include "hw/core/qdev-properties.h" #include "hw/core/qdev-clock.h" @@ -268,10 +269,22 @@ static void virt_init(MachineState *ms) &vms->parent_obj.cfgtable_rom); fdt_add_hvx(vms, m_cfg); =20 + vms->parent_obj.l2vic_dev =3D qdev_new(TYPE_HEX_L2VIC); + object_property_add_child(OBJECT(ms), "l2vic", + OBJECT(vms->parent_obj.l2vic_dev)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(vms->parent_obj.l2vic_dev), + &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(vms->parent_obj.l2vic_dev), 0, + m_cfg->l2vic_base); + sysbus_mmio_map(SYS_BUS_DEVICE(vms->parent_obj.l2vic_dev), 1, + m_cfg->cfgtable.fastl2vic_base << 16); + gsregs_dev =3D qdev_new(TYPE_HEXAGON_GLOBALREG); object_property_add_child(OBJECT(ms), "global-regs", OBJECT(gsregs_dev= )); qdev_prop_set_uint64(gsregs_dev, "config-table-addr", m_cfg->cfgbase); qdev_prop_set_uint32(gsregs_dev, "dsp-rev", v68_rev); + object_property_set_link(OBJECT(gsregs_dev), "l2vic", + OBJECT(vms->parent_obj.l2vic_dev), &error_fat= al); sysbus_realize_and_unref(SYS_BUS_DEVICE(gsregs_dev), &error_fatal); =20 tlb_dev =3D qdev_new(TYPE_HEXAGON_TLB); @@ -301,9 +314,18 @@ static void virt_init(MachineState *ms) OBJECT(gsregs_dev), &error_fatal); object_property_set_link(OBJECT(cpu), "tlb", OBJECT(tlb_dev), &error_fatal); + object_property_set_link(OBJECT(cpu), "l2vic", + OBJECT(vms->parent_obj.l2vic_dev), + &error_fatal); =20 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); } + + for (int i =3D 0; i < 8; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(vms->parent_obj.l2vic_dev), i, + qdev_get_gpio_in(cpu0, i)); + } + fdt_add_cpu_nodes(vms); clk_phandle =3D fdt_add_clocks(vms); fdt_add_uart(vms, VIRT_UART0, clk_phandle); --=20 2.34.1 From nobody Sat Jul 25 18:54:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784044350; cv=none; d=zohomail.com; s=zohoarc; b=WzxTc7HtNePCZpYu3YSPwXjIKsixDQ22X4s3/W125z+smUFis8nHflCa8B3FB4tMw+YwLrfijOg4I3vY2EhfIIJ1TpS+AigkJONUSrqG0pW2Njyjpf/RAN7SjsGLVRSgO2FIESOJy/59IVDleHLuUHN1xx+M6B0MzuM1XPWjIp4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784044350; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UjCW2KnZukssLQmuAHY3Tg9UeCyWnt5eIH8EmF45Ai8=; b=iqmmIUsyP/gimLec6e1/thJNcM85NtgCMtR0mQwN7LlgnR3+gZbGFe7hdmR6ItZXCMkiGTjagLeV/MnCUuR8pB1oksBCDsojbg3SdAQ4Kg6RXBBJbgx+s6EG7w6omMXhT+HBnq8rjae+vxHMSiq7r8o5rDReCI/a3O8fRAMejkM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784044350198442.32982202802737; Tue, 14 Jul 2026 08:52:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wjfQ7-000105-Dn; Tue, 14 Jul 2026 11:51:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfQ6-0000zI-ED for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:42 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfQ4-00014d-9V for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:42 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66EEcW4m800390 for ; Tue, 14 Jul 2026 15:51:39 GMT Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fdnnr0r0m-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 14 Jul 2026 15:51:39 +0000 (GMT) Received: by mail-pg1-f199.google.com with SMTP id 41be03b00d2f7-c856470fe9fso1054315a12.2 for ; Tue, 14 Jul 2026 08:51:39 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b987fc629sm41343581c88.0.2026.07.14.08.51.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 08:51:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UjCW2KnZukssLQmuAHY3Tg9UeCyWnt5eIH8EmF45Ai8=; b=LvGef/Zehk7AGYyR 3XF8ilp9sI1GUGNp8swTqvOSVmzofq00xZou58Og6+fZjHubeCA9bG+3CaAyDqUI xSvoHgvy1vezBcmVhTQE2Yzk11MV2vQxbwliWz4mvKpITkxDH/peQOBN+z0xHOOe 7WH3xxS47oALbzcaLbtsgl5jyhxXapOYV5NwYdoynI9YE5WWVjiyg5ljvwKwSGeF FpeCgpPwqyksa60/Ob9FaKu4vXwFA4r2yFAvyelwPe8VVmBjfVITmE/06Aa9hY65 2sORIxkxbhFt95UQsLZSh+TbVIgwme6X5isbmTJpmMZ3ZmnHwU1Zbc6q4SqUUhRv pA5RAg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784044298; x=1784649098; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=UjCW2KnZukssLQmuAHY3Tg9UeCyWnt5eIH8EmF45Ai8=; b=gBEBssNAHE+o2+0yzlBwT8fHTjx1Mnjy1hzSi/Ur1iTOgPK97ef4fujDXoXW5HM/vd 9mjFnvtz+1c9EPTG6MnCPU62bXEB1NHzB++76N4h3rwy2pRFI+CmFWR5mmKt4Glwmtc8 dPoE/q6FvAZ6Hi03m2XQrFDoEmNrUUc545hAzU1X7LsNqNd+MDgdZicVyU1WrMFHUBK5 k8wF11BGQr25T+27HbH6rtiRToW4DfpmRzt0mOIiZbbaYuzJgFnkgtTH1W1FGlAX+kud Le79R6NH9TZ4tcrvVIzanpqLNA7Oyk/LupJ6zhIpJ4Qk69qth1bkZ4qbwUGcZ7PAzRJJ 4GVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784044298; x=1784649098; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=UjCW2KnZukssLQmuAHY3Tg9UeCyWnt5eIH8EmF45Ai8=; b=X5MEVW+uoEikRj821Jjg1NGjYntvQhddbv0FggB8h7giduNZA7yXU0Sn8Rn4+RacaF rN9ZIzz6kPFe47DB3ZvJRePtbtKXHD2U7/VCAZ/e3fksPa4yQPrr+ABJfwjq/6RFSwWs 5eag1qjYh+rmJ/09jIWFE+FXkX/hKU8zWshUXhu1cA1QHsQl4U7MChVJVJeXWFX5R1X8 FoSsR48Rdn4cBPW2/MPnnkZaJwIX0DbXQ5b1aA6KzEEsPQp/r0XK1SiJsWDEa3YICopT L6O+LYqEMuv/k6lRhSFAFWZJaPdiDkE3IsR/qni2NbCvOTBRTYk1ONntDGbb7qBY1KG+ M7LA== X-Gm-Message-State: AOJu0YxYzBYk8g2whPS5SXjMWCVVH/XFQ4LfCIxVMeYbEi2rTvVfgr6c KK36Em1aZf72iAvuGIWtaGBaPgGxgBra1yi16YsvFSeugL/ojhSSG7tWbwVC6AYg0voLa8sKbO6 zFfmZZGGI21f7cN3QxdeE6S5UObMQihXbn7axQ9k9zTb9XFtoYs3JAZ6OFc8I89p9Sw== X-Gm-Gg: AfdE7ckK5sC6FEBC5CaZ6DMqI0jHkaWUuERCbsuHrshJeYaDM8NPw4MSxkyDovvvn8f jqu+qfd1jbK7N6X3WN/esyeypbX3mDGajW2tXPOF0b96r897s1pXYNchGOMbwuQd38QiIidvuDS dtbqv6no7OPxvOhKXjq1bvR1//kgiuN0oUADdK41b7RBgXKrhrUVDm/G8BzQJupxdn6JWSL8a4U WMombEqrY/4GWSsEDaccZFohO2YBf9SVSjJTyXm9fGXjbVvLfUwvAWjFQWd5xB1vD6uc9OTS/wt ousvCw8aksWN9Tfv4IlNvPtkjavCuY3TVxLJLKeVASQ4XEfUzPzHMq1VuvflUwVZAS5Iu4YM6rD OSroqCNir1W/WDaq1KRbm+L1UUW57zZdd3w5tWiKTG4arIy7Zd7yKecAhgl4= X-Received: by 2002:a05:6a20:6a28:b0:39b:a997:9e40 with SMTP id adf61e73a8af0-3c110a773cfmr14075850637.46.1784044298218; Tue, 14 Jul 2026 08:51:38 -0700 (PDT) X-Received: by 2002:a05:6a20:6a28:b0:39b:a997:9e40 with SMTP id adf61e73a8af0-3c110a773cfmr14075814637.46.1784044297727; Tue, 14 Jul 2026 08:51:37 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: ltaylorsimpson@gmail.com, Laurent Vivier , Thomas Huth , Paolo Bonzini , matheus.bernardino@oss.qualcomm.com, Fabiano Rosas , Brian Cain , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 6/7] tests/qtest: add L2VIC qtest Date: Tue, 14 Jul 2026 08:51:25 -0700 Message-Id: <20260714155126.3509544-7-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> References: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfX3Jc5/Ufcd6lG NfvLJdj52IyileOtYzkSuzncZeMCkzRB9FvELP62E6KbW0M4tFFZtFfEgGRJx1otX4wm+JwWJ/p /tY3H6ONY9U3RGAswAlkxFra9jnzyEY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfX8zLhXg6y+G4L UPpBULZHsrN28mqY00GNKIo83Pu3uKhQX2B1ODeqYoUNghd15MNb6SEtil9WUTDzH8cd0m4v24X e3Tqzb+EMYfK90XHgVNTJGB/M5I5cVJar2jIFhoaku0/q9poBnVK6eC4esuyvmURGsMz5XMkbF/ i87ojZAaM7Ux9TPtfwGB8+oM58mJeconAof/l7XPavhaZXG5131QU2Y0twwRd1LI7QGxHppy0qP DUscXsB8nVeMtnXxsRpegzxGeuv0b5KxkANA1K4In0BS8h76PYkrALB5EMwlDeW0S7zURd3qxFf RCVrZ9sHny8StbDih/6feYTs3N9Lrdnfk4R3LdhbLMDeq2wklHWdtEGTSTyMyufepPyx6kkIzyd Z+FUX9OefwhJwqPP+C6DoX0Z7VAw/eC9JoK+gizhzKvub/2ChnqF5eZGznmsmnh/8MRJFSkbbeS x7ARHCG/dxCH1k9NHEQ== X-Proofpoint-ORIG-GUID: NUFutn9laF0diMuEqFZ2zL3xZkO_lXYK X-Authority-Analysis: v=2.4 cv=NfPWEWD4 c=1 sm=1 tr=0 ts=6a565b0b cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=1LxsVcIvEUuLhGiP2wwA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: NUFutn9laF0diMuEqFZ2zL3xZkO_lXYK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_03,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1015 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140164 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784044351377158500 Add a qtest exercising the L2VIC interrupt controller's basic register access and interrupt enable/disable behavior. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 1 + tests/qtest/l2vic-test.c | 242 +++++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 2 +- 3 files changed, 244 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/l2vic-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 1240d180b85..8201e487000 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -252,6 +252,7 @@ S: Supported F: target/hexagon/ F: hw/intc/hex-l2vic.c F: include/hw/intc/hex-l2vic.h +F: tests/qtest/l2vic-test.c X: target/hexagon/idef-parser/ X: target/hexagon/gen_idef_parser_funcs.py F: linux-user/hexagon/ diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c new file mode 100644 index 00000000000..9887e458a6f --- /dev/null +++ b/tests/qtest/l2vic-test.c @@ -0,0 +1,242 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + * + * QTest testcase for the L2VIC Interrupt Controller + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" +#include "hw/intc/hex-l2vic.h" + +/* Base addresses for L2VIC */ +#define L2VIC_BASE 0xfc910000 +#define L2VIC_FAST_BASE 0xfc920000 + +/* Helper functions */ +static uint32_t l2vic_read32(uint64_t base, uint32_t offset) +{ + return readl(base + offset); +} + +static void l2vic_write32(uint64_t base, uint32_t offset, uint32_t value) +{ + writel(base + offset, value); +} + +/* Test basic register access */ +static void test_l2vic_register_access(void) +{ + uint32_t val; + + /* Test that basic registers can be read/written */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + /* Should have enabled interrupt 0 */ + g_assert_cmpuint(val & 0x1, =3D=3D, 0x1); + + /* Clear it */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + /* Should be cleared now */ + g_assert_cmpuint(val & 0x1, =3D=3D, 0x0); +} + +/* Test interrupt enable/disable */ +static void test_l2vic_interrupt_enable(void) +{ + uint32_t val; + + /* Initially all interrupts should be disabled */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + g_assert_cmpuint(val, =3D=3D, 0); + + /* Enable some interrupts */ + /* Enable IRQ 0 and 2 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x5); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + g_assert_cmpuint(val & 0x5, =3D=3D, 0x5); + + /* Disable one */ + /* Disable IRQ 0 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + g_assert_cmpuint(val & 0x1, =3D=3D, 0x0); /* IRQ 0 should be disabled= */ + g_assert_cmpuint(val & 0x4, =3D=3D, 0x4); /* IRQ 2 should still be en= abled */ +} + +/* Test register read/write without triggering interrupts */ +static void test_l2vic_basic_functionality(void) +{ + l2vic_read32(L2VIC_BASE, L2VIC_INT_ENABLEn); + l2vic_read32(L2VIC_BASE, L2VIC_INT_PENDINGn); + l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + l2vic_read32(L2VIC_BASE, L2VIC_INT_TYPEn); + + /* Exercise write-only registers */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0); +} + +/* + * Test L2VIC IRQ outputs + */ +static void test_l2vic_irq_outputs(void) +{ + uint32_t val; + + /* Clear any previous configuration */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0xFFFFFFFF); + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0xFFFFFFFF); + /* Reset all to level-triggered */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0); + + /* Test Group 0 interrupts (default group: IRQ2) */ + /* Configure interrupt 0 as edge-triggered (required for soft interrup= ts) */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x1); + /* Enable interrupt 0 and generate software interrupt */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x1); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x1); + + /* Verify interrupt is active (would assert IRQ2 in real hardware) */ + /* In L2VIC: pending interrupts become active and clear from pending */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x1, =3D=3D, 0x1); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x1); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x1, =3D=3D, 0x0); + + /* Test Group 1 interrupts: IRQ3 */ + /* Configure interrupt 1 as edge-triggered and to group 1 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x2); + /* Set bit 1 for interrupt 1 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_1, 0x2); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x2); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x2); + + /* Verify interrupt is active in group 1 (would assert IRQ3) */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x2, =3D=3D, 0x2); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_GRPn_1); + g_assert_cmpuint(val & 0x2, =3D=3D, 0x2); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x2); + + /* Test Group 2 interrupts: IRQ4 */ + /* Configure interrupt 2 as edge-triggered and to group 2 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x4); + /* Set bit 2 for interrupt 2 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_2, 0x4); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x4); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x4); + + /* Verify interrupt is active in group 2 (would assert IRQ4) */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x4, =3D=3D, 0x4); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_GRPn_2); + g_assert_cmpuint(val & 0x4, =3D=3D, 0x4); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x4); + + /* Test Group 3 interrupts: IRQ5 */ + /* Configure interrupt 3 as edge-triggered and to group 3 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x8); + /* Set bit 3 for interrupt 3 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_3, 0x8); + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x8); + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x8); + + /* Verify interrupt is active in group 3 (would assert IRQ5) */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x8, =3D=3D, 0x8); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_GRPn_3); + g_assert_cmpuint(val & 0x8, =3D=3D, 0x8); + + /* Clear the interrupt using INT_CLEARn register */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0x8); + + /* Test multiple pending interrupts (only one can be active at a time)= */ + /* Configure all interrupts 0-3 as edge-triggered */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0xF); + /* Enable interrupts 0-3 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0xF); + /* Generate all 4 interrupts */ + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0xF); + + /* Verify that highest prio interrupt becomes active */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + /* At least one bit should be set, but not necessarily all */ + g_assert_cmpuint(val & 0xF, !=3D, 0x0); + + /* Clear all active interrupts */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, val & 0xF); + + /* After clearing, check if more interrupts become active */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + /* Could be 0 if all processed, or have more if pending */ + + /* Test that software interrupts require edge-triggered configuration = */ + /* Configure interrupt 5 as level-triggered (default) */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x0); + /* Enable interrupt 5 */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_SETn, 0x20); + /* Try to generate level interrupt */ + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x20); + + /* Should not work - no interrupt should be active */ + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + /* No interrupt because level-triggered */ + g_assert_cmpuint(val & 0x20, =3D=3D, 0x0); + + /* Now configure as edge-triggered and try again */ + /* Set edge-triggered */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_TYPEn, 0x20); + /* Generate interrupt */ + l2vic_write32(L2VIC_BASE, L2VIC_SOFT_INTn, 0x20); + val =3D l2vic_read32(L2VIC_BASE, L2VIC_INT_STATUSn); + g_assert_cmpuint(val & 0x20, =3D=3D, 0x20); + + /* Clean up - clear all configuration */ + l2vic_write32(L2VIC_BASE, L2VIC_INT_ENABLE_CLEARn, 0xFFFFFFFF); + l2vic_write32(L2VIC_BASE, L2VIC_INT_CLEARn, 0xFFFFFFFF); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_0, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_1, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_2, 0); + l2vic_write32(L2VIC_BASE, L2VIC_INT_GRPn_3, 0); +} + +static void test_l2vic_on_machine(gconstpointer data) +{ + const char *machine =3D (const char *)data; + g_autofree char *args =3D g_strdup_printf("-machine %s", machine); + + qtest_start(args); + + /* Run all the L2VIC tests */ + test_l2vic_register_access(); + test_l2vic_interrupt_enable(); + test_l2vic_basic_functionality(); + test_l2vic_irq_outputs(); + + qtest_end(); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + /* Test on virt machine */ + qtest_add_data_func("/l2vic/virt/all-tests", "virt", + test_l2vic_on_machine); + + /* Test on V66G_1024 machine */ + qtest_add_data_func("/l2vic/V66G_1024/all-tests", "V66G_1024", + test_l2vic_on_machine); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 56ff860e216..a76863c7dd6 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -299,7 +299,7 @@ qtests_riscv64 =3D ['riscv-csr-test'] + \ ['iommu-riscv-test'] : []) + \ (config_all_devices.has_key('CONFIG_K230') ? ['k230-wdt-test'] : []) =20 -qtests_hexagon =3D ['boot-serial-test'] +qtests_hexagon =3D ['boot-serial-test', 'l2vic-test'] =20 qos_test_ss =3D ss.source_set() qos_test_ss.add( --=20 2.34.1 From nobody Sat Jul 25 18:54:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1784044311; cv=none; d=zohomail.com; s=zohoarc; b=FercAHKuMAbWv8tQlTEO1ZxWbE9RO3Ea069FTXyfiN4XQEB8NjWS/GCexGpDUBmjBbj8HkF5M549SLEAS/7G00Mcw77RK+GX7sfXmFH/8rac8WQpKlwkddChlupu3VjFBh5Qjb4OrVReqz0lljRqRo9YXtQlGEq7FsIQkBAqWT8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1784044311; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JGykux9+eIJ7NwUJM9z+tLu1ERVJ12Ocf9EAomW4Xh8=; b=LSnN/gJDmlgPSZp+k9U+UY/kOvC1WHKUHmxkapk8zmrO2AatNEkyiUBtH1+TYMaRcStjbL0BmIX6bBrJXZpVr8I724q5q8Tw43Ocwirf7zK5XyDG3NyIBYGGBTACNqiYTT6fV/08CcO5B9MxgJrljq5GGko97sc2iGIzXyk0QgA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784044310866154.84079021265973; Tue, 14 Jul 2026 08:51:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wjfQ9-00010Z-Qa; Tue, 14 Jul 2026 11:51:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfQ7-00010F-VS for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:43 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wjfQ5-000150-SS for qemu-devel@nongnu.org; Tue, 14 Jul 2026 11:51:43 -0400 Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66EEcjEA824481 for ; Tue, 14 Jul 2026 15:51:41 GMT Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fdbr4b43s-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 14 Jul 2026 15:51:40 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-84a251c2e3eso1705794b3a.1 for ; Tue, 14 Jul 2026 08:51:40 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b987fc629sm41343581c88.0.2026.07.14.08.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 08:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= JGykux9+eIJ7NwUJM9z+tLu1ERVJ12Ocf9EAomW4Xh8=; b=M5VmGoITh6ZByGES FKb/k9hgbPYmDZGHfsNo1oNTsL9TQEc0X2uF4Ydk/Tx4hCdLgRxHF8AMZq8bglHH E/kLy1DI8n7O0fwN8Lse881WGfTakXTRlYHz48OMSoGKsq+gEUEZ4b3B9EHcvsia U7XeGE5WdctmDA31tqRWFgBdpjVDboDzXZQzaJMx3MOngHCOwB2cn7e+BsXHyOek gFgIhxIGnqai60wVjjxPwAkRuAJ582XZiPuuiUevFITLtuDHepJUaj4ZNWLGMi+8 +FlSPQqYwFTV90naQrLNUCKKEASHkha4LABhhzTp+q1Qh1PDRzyrNgcIuddlps/K pOlAKA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784044300; x=1784649100; darn=nongnu.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=JGykux9+eIJ7NwUJM9z+tLu1ERVJ12Ocf9EAomW4Xh8=; b=VzOst14WN1U7u8nO5x5IOXCMNnerJ3UJZ2YyGfwAtfTFA18mJrImT3ukfUbfB73AmF x1r2OijJvFW9egScSEayddmTzzXSxyuXok/pQyNCsVNM2EXpJh/e+GXPNcpOkx29QcHv sL36GXHSqPq31acvcO29I9hqmkxtkCOFoelJ/7ls1HeOZQfwY8Npqurdue0cbZyxYuCA GQwFAQZ0tJyRpCwlHwCDb84Yujt7AC1BBpheh2VktEjI3RKD0K/bjEv4B3MJ8VEtC3XI qtA9Tpte5EXLpj0cspcAqk3iwUvz6Sq7RpG70L6HJZ6tusl7pupe/UkFDzmtV0G8bVZU Hb3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784044300; x=1784649100; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=JGykux9+eIJ7NwUJM9z+tLu1ERVJ12Ocf9EAomW4Xh8=; b=LM+35XAyD7gBZNHpS72NExKfdvcg2hMoaxzDTUCPq+GhjpljtDCWvyBMHHvF4kDPfL YBIS/6j2wlNma3uzFj39hJ46I5SmYZdsl4Xf9unG+FhkBGxKPAqTHYULmw/4bae7qZav uALbAyehe21Kx2NDguIUTkXn52OYsEuIRgSxE10y3HiMgAYDjPYrjWgIyjpgmhNgdDTC NvFwywiradHSpeARjh69Jdcie/NtL1asEXDUs47RjFzs1l/mSGNgBkYbZWlOPeLvmixD WBgunc/QVi3x+FsuYl40CFmtIPeoPRh497KI+zKZhzP9StyX7fYztoBKLfhBHNtLdhls DK4w== X-Gm-Message-State: AOJu0Yw/LuQU+0IIKTJAUsiifhbfbFtlscSfMZDqXjbw4aP9EMkgTQP4 wMMzGaU5IYaWufqAeTyFcnbVijhYFUHQZ9R1dFsXIcbv0tpe1LEhrjCB316zU7k3UCQF7jo3qD/ w+Ywz2280WuHQ7HoQHa+Y7AbHSMBLAmNmXIEcPxisfa0+or4M/46nH0Z2H8rsd90uLQ== X-Gm-Gg: AfdE7clrZXHnQoztpqID7bPClpeZA8d47yegt0ptoBcbMGsAAlOvldEhV2gC5MfcPKH 00I4uyvvVJSp5zpdjg4E48sYl6yeW3cS4uP9gniIuv4nl1L71xr8WWBGkokRu3sFnecawPerT21 msJ+g5dUa1/KViSnaLp9NOstNwq/5j6jQ0H/zigQimXkLLEbRK9GGh+epWlBgZDXxquVAF8aecv 63CmLhO1vJdXGaEiNo/7CwVCyB/J3omYIiolX1j0dQxicEHP8EuE76XEHWGnns4n2jN5L46XjzA TicxZW+SId1ym1Y8fV4Mm8gdMFu0GCIQdvUmlOYr1viP53qjMqFJeuwn39xxXCeKKo7zu1rDNx0 FhB3fUWydagupKIKJcWmb+DhYWlmbLPDXau/rP+or5y1BH8zqe6CeNMAc1lo= X-Received: by 2002:a05:6a21:4516:b0:3ba:d7b0:fcac with SMTP id adf61e73a8af0-3c0f085a7fcmr21151103637.5.1784044299595; Tue, 14 Jul 2026 08:51:39 -0700 (PDT) X-Received: by 2002:a05:6a21:4516:b0:3ba:d7b0:fcac with SMTP id adf61e73a8af0-3c0f085a7fcmr21151066637.5.1784044298976; Tue, 14 Jul 2026 08:51:38 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: ltaylorsimpson@gmail.com, Laurent Vivier , Thomas Huth , Paolo Bonzini , matheus.bernardino@oss.qualcomm.com, Fabiano Rosas , Brian Cain , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , philmd@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 7/7] tests/functional/hexagon: add arch_tests functional test Date: Tue, 14 Jul 2026 08:51:26 -0700 Message-Id: <20260714155126.3509544-8-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> References: <20260714155126.3509544-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: AeCTLTOCsR1DVKC9f8-CBF6uoSwPmOJm X-Proofpoint-ORIG-GUID: AeCTLTOCsR1DVKC9f8-CBF6uoSwPmOJm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfX70FycKifgYjL i268eUV7AaiInHUy4EQ+LgNnixVy+deh9V7bMcUPz+2rJauwdSVSqR7OlzqNYdAIGKe5zPZefql kNTNTessnOfGw3pKrNJNMAEuI3D1ALRsM39l5+gTt93+hs/MaLz0So8gfBBvu4twndfRqJwia3I gVP6SzG/D4kdNOKWcdWqtCzo6fxgBErfdiYxjPtfTk2n8ab/FDrcdYTrk2FndNTPzwtmN3FilJg H8xyHxyLOS2HS+qr2mN4ErwCy/6cEkwnoiMVllTC7p5NjeiW+LKmTNYNVl4dLKfudLj2P7DjSfb DcwEAPjrOZhI0a5W3wstCpJKFdEZmfzQrwjPEislECIkSuNuM645OHQUWGb9qvCDVnsnnadzI71 HaIyA+8D3n1k1hrv4hx5LMVzDzNCIauCsFnhp3mOksXbuHQI/w4/zaZGjgJp0+6FNVo+BwPWvjj 3X3Fvhh5XtBF6MCrEiQ== X-Authority-Analysis: v=2.4 cv=F5hnsKhN c=1 sm=1 tr=0 ts=6a565b0c cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=5vFef2XoAAAA:20 a=EUspDBNiAAAA:8 a=2-CgB73GCJ25MrH1sBkA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=bA3UWDv6hWIuX7UZL3qL:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDE2NCBTYWx0ZWRfX57NKRV2LDXlg F15OyTfNMrQM4ikplXCX2RjxFbXG2OXeDkVzin7oSS/Uh0mDhV3mBkPAmseJgE84FnSfmTp3PeA I46xD93VTAfQP7Qy4IPC3DaCDsP2KoQ= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_03,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 clxscore=1015 adultscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140164 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1784044313648158500 Add new test cases from hexagon-arch-tests to exercise exceptions, guest mode, interrupt steering, etc. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 1 + tests/functional/hexagon/meson.build | 5 ++ tests/functional/hexagon/test_arch_tests.py | 65 +++++++++++++++++++++ tests/functional/meson.build | 1 + 4 files changed, 72 insertions(+) create mode 100644 tests/functional/hexagon/meson.build create mode 100755 tests/functional/hexagon/test_arch_tests.py diff --git a/MAINTAINERS b/MAINTAINERS index 8201e487000..a9b134b323e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1361,6 +1361,7 @@ F: hw/hexagon/ F: include/hw/hexagon/ F: configs/devices/hexagon-softmmu/default.mak F: docs/system/hexagon/ +F: tests/functional/hexagon/ F: docs/devel/hexagon-sys.rst =20 LoongArch Machines diff --git a/tests/functional/hexagon/meson.build b/tests/functional/hexago= n/meson.build new file mode 100644 index 00000000000..2b5a1a8f264 --- /dev/null +++ b/tests/functional/hexagon/meson.build @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +tests_hexagon_system_thorough =3D [ + 'arch_tests', +] diff --git a/tests/functional/hexagon/test_arch_tests.py b/tests/functional= /hexagon/test_arch_tests.py new file mode 100755 index 00000000000..008822d5e5b --- /dev/null +++ b/tests/functional/hexagon/test_arch_tests.py @@ -0,0 +1,65 @@ +#!/usr/bin/env python3 +# +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os +from qemu_test import QemuSystemTest, Asset +from qemu_test.cmd import wait_for_console_pattern + + +class ArchTestsUart(QemuSystemTest): + """ + Hexagon architecture verification tests + + These are bare-metal tests from hexagon-arch-tests that exercise + system functionality. + + Tests output results via UART. + """ + timeout =3D 60 + + ASSET_TARBALL =3D Asset( + "https://github.com/qualcomm/qemu-hexagon-testing/releases/" + "download/v0.2.5/arch_tests_uart.tar.gz", + "edb4f37b877a3a72a0e10920477458a43b40045d34398fee8cb763fefd342f4f", + ) + + def run_uart_test(self, test_name: str, + machine: str =3D "virt") -> None: + """ + Run an arch test binary and verify PASS via UART console output. + """ + self.set_machine(machine) + self.archive_extract(self.ASSET_TARBALL) + target_bin =3D os.path.join(self.workdir, + 'arch_tests_uart_package', + 'bin', test_name) + self.vm.set_console() + self.set_vm_arg("-display", "none") + self.set_vm_arg("-kernel", target_bin) + self.vm.launch() + wait_for_console_pattern(self, "PASS") + + def test_exceptions(self) -> None: + """Tests exception delivery for trap instructions, privilege + violations, and verifies SSR cause codes and ELR values. + """ + self.run_uart_test("test_exceptions") + + def test_guest_mode(self) -> None: + """Tests guest mode entry/exit via CCR configuration, verifying + GSR fields, GELR, and guest event vector table dispatch. + """ + self.run_uart_test("test_guest_mode") + + def test_int_steering(self) -> None: + """Tests interrupt steering via priority-based routing to + specific threads using STID priority and iassignw. + """ + self.run_uart_test("test_int_steering") + + +if __name__ =3D=3D "__main__": + QemuSystemTest.main() diff --git a/tests/functional/meson.build b/tests/functional/meson.build index c158197c4b7..c7362dd00ef 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -14,6 +14,7 @@ subdir('aarch64') subdir('alpha') subdir('arm') subdir('avr') +subdir('hexagon') subdir('hppa') subdir('i386') subdir('loongarch64') --=20 2.34.1