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Sun, 12 Jul 2026 20:51:47 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang , Alistair Francis Subject: [PATCH v6 2/6] target/riscv: Enable Zicclsm for the compatible CPUs Date: Mon, 13 Jul 2026 11:51:31 +0800 Message-ID: <20260713035135.3996990-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260713035135.3996990-1-frank.chang@sifive.com> References: <20260713035135.3996990-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1783914761917158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang To support Zicclsm, let's enable Zicclsm for the following compatible CPUs: - Base 32 CPU (to be backward compatible) - Base 64 CPU (to be backward compatible) - XuanTie (T-Head) C908 - Tenstorrent Ascalon - Ventana Veyron V1 - XiangShan Kunminghu - MIPS P8700 (ISA doesn't include Zicclsm, but their datasheet claims that it has unaligned load/store support in hardware) Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/cpu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a82e6563bf..7ee89f6fc4b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3268,6 +3268,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zicbom =3D true, .cfg.ext_zicbop =3D true, .cfg.ext_zicboz =3D true, + .cfg.ext_zicclsm =3D true, .cfg.ext_zicntr =3D true, .cfg.ext_zicsr =3D true, .cfg.ext_zifencei =3D true, @@ -3340,6 +3341,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zicbom =3D true, .cfg.ext_zicbop =3D true, .cfg.ext_zicboz =3D true, + .cfg.ext_zicclsm =3D true, .cfg.ext_zicntr =3D true, .cfg.ext_zicsr =3D true, .cfg.ext_zifencei =3D true, @@ -3426,6 +3428,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zbs =3D true, .cfg.ext_zkt =3D true, .cfg.ext_zbkc =3D true, + .cfg.ext_zicclsm =3D true, .cfg.ext_zicsr =3D true, .cfg.ext_zifencei =3D true, .cfg.ext_zihintpause =3D true, @@ -3469,6 +3472,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zicbom =3D true, .cfg.ext_zicbop =3D true, .cfg.ext_zicboz =3D true, + .cfg.ext_zicclsm =3D true, .cfg.ext_zicntr =3D true, .cfg.ext_zicond =3D true, .cfg.ext_zicsr =3D true, @@ -3518,6 +3522,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { =20 /* ISA extensions */ .cfg.mmu =3D true, + .cfg.ext_zicclsm =3D true, .cfg.ext_zifencei =3D true, .cfg.ext_zicsr =3D true, .cfg.pmp =3D true, @@ -3577,6 +3582,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { * The RISC-V Instruction Set Manual: Volume I * Unprivileged Architecture */ + .cfg.ext_zicclsm =3D true, .cfg.ext_zicntr =3D true, .cfg.ext_zihpm =3D true, .cfg.ext_zihintntl =3D true, @@ -3633,6 +3639,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU, .priv_spec =3D PRIV_VERSION_1_12_0, .cfg.max_satp_mode =3D VM_1_10_SV48, + .cfg.ext_zicclsm =3D true, .cfg.ext_zifencei =3D true, .cfg.ext_zicsr =3D true, .cfg.mmu =3D true, --=20 2.43.0