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Thu, 09 Jul 2026 19:55:42 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL 01/40] hw/riscv/riscv-iommu.c: fix fault type for spa_fetch() faults Date: Fri, 10 Jul 2026 12:54:46 +1000 Message-ID: <20260710025525.1704417-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652171062158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Under certain circunstances, like the one described in [1] and [2], a read operation that faults will be logged as a write fault instead, and vice-versa, if they happen after the translation phase in riscv_iommu_spa_fetch(). The first problem is that we're overwriting iotlb->perm with PTE flags, so an IOMMU_RO access flag can be overwritten by whatever flags the PTE has. This will cause the wrong fault type to be thrown at the end of the function in case a fault happens. To solve the iotlb->perm overwrite we'll bit_and the original iotlb->perm access flags with the PTE access flags, preserving the original access type. So a IOMMU_RO access in a R+W PTE will result in a IOMMU_RO perm. Second, the resulting fault is received by riscv_iommu_translate(), which will then report the fault. To do that we require a transaction type (ttype). We're prioritizing checking "perm & IOMMU_RW" to set a UADDR_WR ttype, and then checking "perm & IOMMU_RO" to set UADDR_RD ttype. The issue with that is IOMMU_RO=3D1 and IOMMU_RW=3D3, thus checking "perm & IOMMU_RW" for a write then "perm & IOMMU_RO" for a read will cause the read fault to always be diagnosed as write. Make the iotlb->perm matches more strict: "perm & IOMMU_RW" must be exactly IOMMU_RW, ensuring that 'perm' has both flags. Then we can check perm & IOMMU_WO and perm & IOMMU_RO without worrying about overlapping with the RW flag. [1] https://gitlab.com/qemu-project/qemu/-/work_items/3557 [2] https://gitlab.com/qemu-project/qemu/-/work_items/3577 Fixes: 69a9ae4836 ("hw/riscv/riscv-iommu: add ATS support") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3557 Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3577 Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20260701124034.552271-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 974042d017..7f94ce152e 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -282,6 +282,7 @@ static hwaddr riscv_iommu_napot_page_mask(hwaddr ppn, h= waddr addr, hwaddr *out) static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ct= x, IOMMUTLBEntry *iotlb) { + IOMMUAccessFlags pte_perm; dma_addr_t addr, base; uint64_t satp, gatp, pte; bool en_s, en_g; @@ -509,8 +510,16 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, R= ISCVIOMMUContext *ctx, } /* Translation phase completed (GPA or SPA) */ iotlb->translated_addr =3D base; - iotlb->perm =3D (pte & PTE_W) ? ((pte & PTE_R) ? IOMMU_RW : IO= MMU_WO) - : IOMMU_RO; + + /* + * Do a bit_and between the PTE bits and the original + * request flags to determine the exact permission we + * need, i.e. if the original request is RO and the + * PTE has RW flags the actual perm is RO. + */ + pte_perm =3D (pte & PTE_W) ? ((pte & PTE_R) ? IOMMU_RW : IOMMU= _WO) + : IOMMU_RO; + iotlb->perm &=3D pte_perm; =20 /* Check MSI GPA address match */ if (pass =3D=3D S_STAGE && (iotlb->perm & IOMMU_WO) && @@ -1727,7 +1736,8 @@ done: if (fault) { unsigned ttype =3D RISCV_IOMMU_FQ_TTYPE_PCIE_ATS_REQ; =20 - if (iotlb->perm & IOMMU_RW) { + if ((iotlb->perm & IOMMU_RW) =3D=3D IOMMU_RW + || iotlb->perm & IOMMU_WO) { ttype =3D RISCV_IOMMU_FQ_TTYPE_UADDR_WR; } else if (iotlb->perm & IOMMU_RO) { ttype =3D RISCV_IOMMU_FQ_TTYPE_UADDR_RD; --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652272; cv=none; d=zohomail.com; s=zohoarc; b=DKPiBBjlkg019Shmfg3X22XF7RKC9gZGJTio4t3Wa3CzD5GDszcEHhjNGJs+4omVxWnW0tJ2ufwVqbg7O1LwBu6hw11q0rOdSIeFvFDyLlAcfyet/LdJUWRb+e8ttlVXZC7UslYblcqxWu+06tjkziZd2qMM1PubuS8K9pg3HDw= ARC-Message-Signature: i=1; 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Thu, 09 Jul 2026 19:55:45 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Nutty Liu , Chao Liu , Alistair Francis Subject: [PULL 02/40] hw/riscv/riscv-iommu.c: check for reserved PTE bits Date: Fri, 10 Jul 2026 12:54:47 +1000 Message-ID: <20260710025525.1704417-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652273572158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We need to fault if reserved PTE bits (60:54) are set. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3554 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Chao Liu Message-ID: <20260701121111.537654-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 7f94ce152e..6665ad9f7c 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -469,6 +469,8 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RI= SCVIOMMUContext *ctx, =20 if (!(pte & PTE_V)) { break; /* Invalid PTE */ + } else if (pte & PTE_RESERVED(false)) { + break; /* Reserved PTE bits set */ } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { base =3D PPN_PHYS(ppn); /* Inner PTE, continue walking */ } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 09 Jul 2026 19:55:48 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Nutty Liu , Chao Liu , Alistair Francis Subject: [PULL 03/40] hw/riscv/riscv-iommu.c: fault when !PTE_U and no priv access Date: Fri, 10 Jul 2026 12:54:48 +1000 Message-ID: <20260710025525.1704417-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=alistair23@gmail.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652227356158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza All IOMMU accesses are assumed to be user mode unless told otherwise, i.e. we have a process_id. In case we have a non-user mode leaf PTE (PTE_U isn't set) and we are running in user mode, we need to throw a fault. This also reflects on qos-riscv-iommu tests: the tests always run in user mode so our PTEs must have PTE_U (bit 0x10) set. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3553 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Chao Liu Message-ID: <20260701121111.537654-3-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- tests/qtest/libqos/qos-riscv-iommu.h | 4 ++-- hw/riscv/riscv-iommu.c | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/tests/qtest/libqos/qos-riscv-iommu.h b/tests/qtest/libqos/qos-= riscv-iommu.h index 90e69a5d73..c218e9d66d 100644 --- a/tests/qtest/libqos/qos-riscv-iommu.h +++ b/tests/qtest/libqos/qos-riscv-iommu.h @@ -54,8 +54,8 @@ * PTE masks for RISC-V IOMMU page tables. * Values match PTE_V, PTE_R, PTE_W, PTE_A, PTE_D in target/riscv/cpu_bits= .h */ -#define QRIOMMU_NON_LEAF_PTE_MASK 0x001 /* PTE_V */ -#define QRIOMMU_LEAF_PTE_RW_MASK 0x0c7 /* V|R|W|A|D */ +#define QRIOMMU_NON_LEAF_PTE_MASK 0x011 /* PTE_V | PTE_U */ +#define QRIOMMU_LEAF_PTE_RW_MASK 0x0d7 /* V | R | W | A | D | PTE_U */ #define QRIOMMU_PTE_PPN_MASK 0x003ffffffffffc00ull =20 /* Address-space base offset for test tables */ diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 6665ad9f7c..c35e9f0119 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -298,6 +298,7 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RI= SCVIOMMUContext *ctx, G_STAGE =3D 1, } pass; MemTxResult ret; + bool pv =3D !!ctx->process_id; =20 satp =3D get_field(ctx->satp, RISCV_IOMMU_ATP_MODE_FIELD); gatp =3D get_field(ctx->gatp, RISCV_IOMMU_ATP_MODE_FIELD); @@ -471,6 +472,13 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, R= ISCVIOMMUContext *ctx, break; /* Invalid PTE */ } else if (pte & PTE_RESERVED(false)) { break; /* Reserved PTE bits set */ + } else if (!(pte & PTE_U) && !pv) { + /* + * All accesses are assumed to be User mode unless + * process_id is valid (pv). In case we have a + * non-user mode PTE and !pv we need to fault. + */ + break; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { base =3D PPN_PHYS(ppn); /* Inner PTE, continue walking */ } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652386; cv=none; d=zohomail.com; s=zohoarc; b=f2r8adMYV8L46iXZBnCEciD6JtoysFZqRnvxF+ebEcbHgR0EDdwYNib0xbWIhJ8iqILkGggqoEc/rw6229oz5qq2jqgO+P3g/qyiCiTzUM0YDRnC4iI+Uj7o98lFBtl2EeemlYE1fhAHBo7qGmoUjUlZaFL73QLxQC98UXx1wdM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783652386; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 09 Jul 2026 19:55:51 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL 04/40] hw/riscv/riscv-iommu.c: fault for non-user PTE in G_STAGE Date: Fri, 10 Jul 2026 12:54:49 +1000 Message-ID: <20260710025525.1704417-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=alistair23@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652387951158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza riscv-iommu spec 1.0 says: "When checking the U bit in a second-stage PTE, the transaction is treated as not requesting supervisor privilege." We need to *always* fault in case we're on G_STAGE and PTE_U is cleared since we can't be on supervisor mode at this point. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3555 Signed-off-by: Daniel Henrique Barboza Message-ID: <20260701121111.537654-4-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index c35e9f0119..6b20940b89 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -495,6 +495,16 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, R= ISCVIOMMUContext *ctx, break; /* Access bit not set */ } else if ((iotlb->perm & IOMMU_WO) && !ade && !(pte & PTE_D)) { break; /* Dirty bit not set */ + } else if (pass =3D=3D G_STAGE && !(pte & PTE_U)) { + /* + * riscv-iommu spec 1.0: "When checking the U bit in a + * second-stage PTE, the transaction is treated as + * not requesting supervisor privilege." + * + * I.e. we need to fault if this is a non-user PTE since + * we are always in user mode at this point. + */ + break; } else { /* Leaf PTE, translation completed. */ sc[pass].step =3D sc[pass].levels; --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652181; cv=none; d=zohomail.com; s=zohoarc; b=UM1sD+f3L8BdBs2wvzVX0EyYDGUquOb1iECaUEm/1WdoI9exIzRtmhztvlaU/2mGJORF/uBW+2Uy5CrJROtvRS297TxkgAywl+fv3mCXXJE0MNMeQLMNvf1z7bNVw0JVQviD3hlFPuZ0Wu/2tNI27yiRh31N22SHjuzANbDSvl0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783652181; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 09 Jul 2026 19:55:55 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Nutty Liu , Alistair Francis Subject: [PULL 05/40] hw/riscv/riscv-iommu.c: check reserved MSI PTE basic bits Date: Fri, 10 Jul 2026 12:54:50 +1000 Message-ID: <20260710025525.1704417-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652183119158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We need to throw an MSI_MISCONFIGURED error when any of the reserved PTE bits (first doubleword only) are set. Fixes: Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3563 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Message-ID: <20260629125719.679626-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 6b20940b89..c3f9f052ae 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -677,6 +677,27 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUSta= te *s, =20 switch (get_field(pte[0], RISCV_IOMMU_MSI_PTE_M)) { case RISCV_IOMMU_MSI_PTE_M_BASIC: + /* + * riscv-iommu spec MSI PTE basic translate mode: + * "When an MSI PTE has fields V =3D 1, C =3D 0, and M =3D 3 + * (basic translate mode), the PTE's complete format is: + * First doubleword: bit 63 C, =3D 0 + * bits 53:10 PPN + * bits 2:1 M, =3D 3 + * bit 0 V, =3D 1 + * All other bits of the first doubleword are reserved + * and must be set to zeros by software. The second + * doubleword is ignored by an IOMMU so is free for + * software to use." + * + * In other words, bits 62:54 and 9:3 of pte[0] are reserved. + */ + if (pte[0] & (GENMASK_ULL(62, 54) | GENMASK_ULL(9, 3))) { + res =3D MEMTX_DECODE_ERROR; + cause =3D RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED; + goto err; + } + /* MSI Pass-through mode */ addr =3D PPN_PHYS(get_field(pte[0], RISCV_IOMMU_MSI_PTE_PPN)); =20 --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652173; cv=none; d=zohomail.com; s=zohoarc; b=imvGNTUq5/+xf5VBpSUJsujWeNNy8eNLGVbRofNvCYJ8uTArE3+mxZMIGeB2Pv9F9sBk/WgLiyeiizBE3SA2TN3Gq2NAzoA5Y0gQSzfpl7bjDHEI7j6JdPcnsv4RRcbA4/XuTPOlXyxnJVMfzoPlYo2ZG19Tmfn10YoB16L0im8= ARC-Message-Signature: i=1; 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Thu, 09 Jul 2026 19:55:58 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Nutty Liu , Alistair Francis Subject: [PULL 06/40] hw/riscv/riscv-iommu-sys.c: record fault on IOMMU-generated MSI write Date: Fri, 10 Jul 2026 12:54:51 +1000 Message-ID: <20260710025525.1704417-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652175224158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The riscv-iommu spec requires that the IOMMU records its own generated MSI write faults. Fixes: 01c1caa9d1 ("hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3572 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Message-ID: <20260629165954.1018123-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.h | 1 + hw/riscv/riscv-iommu-sys.c | 16 +++++++++++++++- hw/riscv/riscv-iommu.c | 3 +-- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h index a778e86fb7..da70e8bfa8 100644 --- a/hw/riscv/riscv-iommu.h +++ b/hw/riscv/riscv-iommu.h @@ -103,6 +103,7 @@ void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu= , PCIBus *bus, void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode= ); void riscv_iommu_reset(RISCVIOMMUState *s); void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type); +void riscv_iommu_fault(RISCVIOMMUState *s, struct riscv_iommu_fq_record *e= v); =20 typedef struct RISCVIOMMUContext RISCVIOMMUContext; /* Device translation context state. */ diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c index bf87b0b4ea..3314adeed2 100644 --- a/hw/riscv/riscv-iommu-sys.c +++ b/hw/riscv/riscv-iommu-sys.c @@ -26,6 +26,7 @@ #include "qemu/host-utils.h" #include "qemu/module.h" #include "qom/object.h" +#include "target/riscv/cpu_bits.h" #include "trace.h" =20 #include "riscv-iommu.h" @@ -143,7 +144,20 @@ static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStat= eSys *s, =20 address_space_stl_le(&address_space_memory, msi_addr, msi_data, MEMTXATTRS_UNSPECIFIED, &result); - trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result); + + if (result =3D=3D MEMTX_OK) { + trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result); + } else { + /* Record an access fault error in the fault queue */ + struct riscv_iommu_fq_record ev =3D { 0 }; + RISCVIOMMUState *iommu =3D &s->iommu; + + ev.hdr =3D set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_CAUSE, + RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT); + ev.hdr =3D set_field(ev.hdr, RISCV_IOMMU_FQ_HDR_TTYPE, + RISCV_IOMMU_FQ_TTYPE_UADDR_WR); + riscv_iommu_fault(iommu, &ev); + } } =20 static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu, diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index c3f9f052ae..12f20fa4bd 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -118,8 +118,7 @@ void riscv_iommu_notify(RISCVIOMMUState *s, int vec_typ= e) } } =20 -static void riscv_iommu_fault(RISCVIOMMUState *s, - struct riscv_iommu_fq_record *ev) +void riscv_iommu_fault(RISCVIOMMUState *s, struct riscv_iommu_fq_record *e= v) { uint32_t ctrl =3D riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FQCSR); uint32_t head =3D riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FQH) & s->f= q_mask; --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 09 Jul 2026 19:56:01 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Zephyr Li , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Daniel Henrique Barboza , Chao Liu Subject: [PULL 07/40] target/riscv: Remove unused tcg/tcg.h include Date: Fri, 10 Jul 2026 12:54:52 +1000 Message-ID: <20260710025525.1704417-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=alistair23@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652361911158500 From: Zephyr Li Signed-off-by: Zephyr Li Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Message-ID: <20260703180538.3346781-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4d2eb281bf..7664e686fa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -38,7 +38,6 @@ #include "system/tcg.h" #include "kvm/kvm_riscv.h" #include "tcg/tcg-cpu.h" -#include "tcg/tcg.h" #if !defined(CONFIG_USER_ONLY) #include "target/riscv/debug.h" #endif --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 09 Jul 2026 19:56:04 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 08/40] target/riscv: move valid_vm_* satp arrays to cpu.c Date: Fri, 10 Jul 2026 12:54:53 +1000 Message-ID: <20260710025525.1704417-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652217364158500 From: Daniel Henrique Barboza These satp arrays are used internally in both csr.c and in cpu.c. csr.c is going to be moved to the TCG subdir in the next patch, and we want the satp logic to be available for KVM with --disable-tcg builds. Move these arrays to cpu.c to keep them available for KVM with --disable-tcg. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260703180538.3346781-3-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 -- target/riscv/csr.h | 3 +++ target/riscv/cpu.c | 13 +++++++++++++ target/riscv/csr.c | 12 ------------ 4 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bdd28d329b..82362ef8d8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -968,8 +968,6 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error *= *errp); void riscv_add_satp_mode_properties(Object *obj); bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); =20 -extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; - void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); diff --git a/target/riscv/csr.h b/target/riscv/csr.h index c791260f83..66ec9546ed 100644 --- a/target/riscv/csr.h +++ b/target/riscv/csr.h @@ -72,6 +72,9 @@ enum { CSR_TABLE_SIZE =3D 0x1000 }; =20 +/* valid_vm_* arrays are shared with KVM via cpu.c */ +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7664e686fa..cae4e96232 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -65,6 +65,19 @@ const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF,= RVD, RVV, #define BYTE(x) (x) #endif =20 +/* SATP bits that are shared between TCG and KVM */ +const bool valid_vm_1_10_32[16] =3D { + [VM_1_10_MBARE] =3D true, + [VM_1_10_SV32] =3D true +}; + +const bool valid_vm_1_10_64[16] =3D { + [VM_1_10_MBARE] =3D true, + [VM_1_10_SV39] =3D true, + [VM_1_10_SV48] =3D true, + [VM_1_10_SV57] =3D true +}; + bool riscv_cpu_is_32bit(RISCVCPU *cpu) { return riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7168a4dc12..7818d81fb0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1875,18 +1875,6 @@ static const uint64_t hvien_writable_mask =3D LOCAL_= INTERRUPTS; =20 static const uint64_t vsip_writable_mask =3D MIP_VSSIP | LOCAL_INTERRUPTS; =20 -const bool valid_vm_1_10_32[16] =3D { - [VM_1_10_MBARE] =3D true, - [VM_1_10_SV32] =3D true -}; - -const bool valid_vm_1_10_64[16] =3D { - [VM_1_10_MBARE] =3D true, - [VM_1_10_SV39] =3D true, - [VM_1_10_SV48] =3D true, - [VM_1_10_SV57] =3D true -}; - /* Machine Information Registers */ static RISCVException read_zero(CPURISCVState *env, int csrno, target_ulong *val) --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652183; cv=none; d=zohomail.com; s=zohoarc; b=NX3s9jfnKTf3wtW+pqnE2QnwHG+DmqPP5RRLyvdOkJyEXcCqd7Z9GS5BAb/LNm8LKaHchQglrZh+oGXcR68RjH9MjbtPIE00rltGQyRNFSayri0703TJm6qogbSDrY0iDqy1ppD8IcHMB7i3Nzjd6P2vlsqufP6mzf5eZoLs7sM= ARC-Message-Signature: i=1; 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Thu, 09 Jul 2026 19:56:07 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 09/40] hw/riscv, target/riscv: move pmu fdt function to fdt-common.c Date: Fri, 10 Jul 2026 12:54:54 +1000 Message-ID: <20260710025525.1704417-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=alistair23@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652185246158500 From: Daniel Henrique Barboza riscv_pmu_generate_fdt_node() can be moved to fdt_common.c since it has no PMU TCG internals. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260703180538.3346781-4-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- include/hw/riscv/fdt-common.h | 1 + hw/riscv/fdt-common.c | 52 +++++++++++++++++++++++++++++++++++ hw/riscv/tt_atlantis.c | 1 - hw/riscv/virt.c | 1 - target/riscv/pmu.c | 52 ----------------------------------- 5 files changed, 53 insertions(+), 54 deletions(-) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 017278b611..1729a6abc6 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -35,4 +35,5 @@ void create_fdt_plic(void *fdt, hwaddr addr, uint64_t siz= e, uint32_t addr_cells, uint32_t *plic_cells, uint32_t cells_size, uint32_t ndev_sources, bool numa_enabled, int socket); +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); #endif diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index e0e31af09b..aa143a618b 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -230,3 +230,55 @@ void create_fdt_plic(void *fdt, hwaddr addr, uint64_t = size, } qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); } + +/* + * To keep it simple, any event can be mapped to any programmable counters= in + * QEMU. The generic cycle & instruction count events can also be monitored + * using programmable counters. In that case, mcycle & minstret must conti= nue + * to provide the correct value as well. Heterogeneous PMU per hart is not + * supported yet. Thus, number of counters are same across all harts. + */ +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) +{ + uint32_t fdt_event_ctr_map[15] =3D {}; + + /* + * The event encoding is specified in the SBI specification + * Event idx is a 20bits wide number encoded as follows: + * event_idx[19:16] =3D type + * event_idx[15:0] =3D code + * The code field in cache events are encoded as follows: + * event_idx.code[15:3] =3D cache_id + * event_idx.code[2:1] =3D op_id + * event_idx.code[0:0] =3D result_id + */ + + /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ + fdt_event_ctr_map[0] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[1] =3D cpu_to_be32(0x00000001); + fdt_event_ctr_map[2] =3D cpu_to_be32(cmask | 1 << 0); + + /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ + fdt_event_ctr_map[3] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[4] =3D cpu_to_be32(0x00000002); + fdt_event_ctr_map[5] =3D cpu_to_be32(cmask | 1 << 2); + + /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[6] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[7] =3D cpu_to_be32(0x00010019); + fdt_event_ctr_map[8] =3D cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[9] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[10] =3D cpu_to_be32(0x0001001B); + fdt_event_ctr_map[11] =3D cpu_to_be32(cmask); + + /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ + fdt_event_ctr_map[12] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[13] =3D cpu_to_be32(0x00010021); + fdt_event_ctr_map[14] =3D cpu_to_be32(cmask); + + /* This a OpenSBI specific DT property documented in OpenSBI docs */ + qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", + fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); +} diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index beaf64e0c1..d808bcc11c 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -17,7 +17,6 @@ #include "hw/core/sysbus.h" =20 #include "target/riscv/cpu.h" -#include "target/riscv/pmu.h" =20 #include "hw/riscv/boot.h" #include "hw/riscv/fdt-common.h" diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index bd9f77aad3..51bac47a91 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,7 +30,6 @@ #include "hw/char/serial-mm.h" #include "target/riscv/cpu.h" #include "hw/core/sysbus-fdt.h" -#include "target/riscv/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/iommu.h" #include "hw/riscv/riscv-iommu-bits.h" diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 3444400bd2..38ad2737e1 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -27,58 +27,6 @@ =20 #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ =20 -/* - * To keep it simple, any event can be mapped to any programmable counters= in - * QEMU. The generic cycle & instruction count events can also be monitored - * using programmable counters. In that case, mcycle & minstret must conti= nue - * to provide the correct value as well. Heterogeneous PMU per hart is not - * supported yet. Thus, number of counters are same across all harts. - */ -void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) -{ - uint32_t fdt_event_ctr_map[15] =3D {}; - - /* - * The event encoding is specified in the SBI specification - * Event idx is a 20bits wide number encoded as follows: - * event_idx[19:16] =3D type - * event_idx[15:0] =3D code - * The code field in cache events are encoded as follows: - * event_idx.code[15:3] =3D cache_id - * event_idx.code[2:1] =3D op_id - * event_idx.code[0:0] =3D result_id - */ - - /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ - fdt_event_ctr_map[0] =3D cpu_to_be32(0x00000001); - fdt_event_ctr_map[1] =3D cpu_to_be32(0x00000001); - fdt_event_ctr_map[2] =3D cpu_to_be32(cmask | 1 << 0); - - /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ - fdt_event_ctr_map[3] =3D cpu_to_be32(0x00000002); - fdt_event_ctr_map[4] =3D cpu_to_be32(0x00000002); - fdt_event_ctr_map[5] =3D cpu_to_be32(cmask | 1 << 2); - - /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[6] =3D cpu_to_be32(0x00010019); - fdt_event_ctr_map[7] =3D cpu_to_be32(0x00010019); - fdt_event_ctr_map[8] =3D cpu_to_be32(cmask); - - /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[9] =3D cpu_to_be32(0x0001001B); - fdt_event_ctr_map[10] =3D cpu_to_be32(0x0001001B); - fdt_event_ctr_map[11] =3D cpu_to_be32(cmask); - - /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ - fdt_event_ctr_map[12] =3D cpu_to_be32(0x00010021); - fdt_event_ctr_map[13] =3D cpu_to_be32(0x00010021); - fdt_event_ctr_map[14] =3D cpu_to_be32(cmask); - - /* This a OpenSBI specific DT property documented in OpenSBI docs */ - qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", - fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); -} - static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) { if (ctr_idx < 3 || ctr_idx >=3D RV_MAX_MHPMCOUNTERS || --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Thu, 09 Jul 2026 19:56:11 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 10/40] target/riscv: move TCG only files to tcg subdir Date: Fri, 10 Jul 2026 12:54:55 +1000 Message-ID: <20260710025525.1704417-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=alistair23@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652205669158500 From: Daniel Henrique Barboza We have *way* too much TCG-only code hanging around in target/riscv, where ideally we would have things that are shared between accelerators. We'll follow the example of other targets like i386 and loongarch and move everything to the tcg subir. This will not only cleanup target/riscv but it will also expose what is common code but it's buried inside a TCG helper. We're leaving some stuff behind because these require a little more case to not end up breaking KVM. We'll take care of them next. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260703180538.3346781-5-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/{ =3D> tcg}/pmu.h | 0 target/riscv/{ =3D> tcg}/vector_internals.h | 0 target/riscv/{ =3D> tcg}/bitmanip_helper.c | 0 target/riscv/{ =3D> tcg}/cpu_helper.c | 0 target/riscv/{ =3D> tcg}/crypto_helper.c | 0 target/riscv/{ =3D> tcg}/csr.c | 0 target/riscv/{ =3D> tcg}/debug.c | 0 target/riscv/{ =3D> tcg}/fpu_helper.c | 0 target/riscv/{ =3D> tcg}/m128_helper.c | 0 target/riscv/{ =3D> tcg}/mips_csr.c | 0 target/riscv/{ =3D> tcg}/op_helper.c | 0 target/riscv/{ =3D> tcg}/pmu.c | 0 target/riscv/{ =3D> tcg}/th_csr.c | 0 target/riscv/{ =3D> tcg}/translate.c | 0 target/riscv/{ =3D> tcg}/vcrypto_helper.c | 0 target/riscv/{ =3D> tcg}/vector_helper.c | 0 target/riscv/{ =3D> tcg}/vector_internals.c | 0 target/riscv/{ =3D> tcg}/zce_helper.c | 0 .../insn_trans/trans_privileged.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rva.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvb.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvbf16.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvd.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvf.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvh.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvi.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvk.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvm.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvv.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvvk.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzabha.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzacas.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzalasr.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzawrs.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzce.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzcmop.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzfa.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzfh.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzicbo.c.inc | 0 .../insn_trans/trans_rvzicfiss.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzicond.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_rvzimop.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_svinval.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_xlrbr.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_xmips.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_xthead.c.inc | 0 .../insn_trans/trans_xventanacondops.c.inc | 0 .../{ =3D> tcg}/insn_trans/trans_zilsd.c.inc | 0 target/riscv/meson.build | 16 ---------- target/riscv/tcg/meson.build | 30 +++++++++++++++++-- 50 files changed, 28 insertions(+), 18 deletions(-) rename target/riscv/{ =3D> tcg}/pmu.h (100%) rename target/riscv/{ =3D> tcg}/vector_internals.h (100%) rename target/riscv/{ =3D> tcg}/bitmanip_helper.c (100%) rename target/riscv/{ =3D> tcg}/cpu_helper.c (100%) rename target/riscv/{ =3D> tcg}/crypto_helper.c (100%) rename target/riscv/{ =3D> tcg}/csr.c (100%) rename target/riscv/{ =3D> tcg}/debug.c (100%) rename target/riscv/{ =3D> tcg}/fpu_helper.c (100%) rename target/riscv/{ =3D> tcg}/m128_helper.c (100%) rename target/riscv/{ =3D> tcg}/mips_csr.c (100%) rename target/riscv/{ =3D> tcg}/op_helper.c (100%) rename target/riscv/{ =3D> tcg}/pmu.c (100%) rename target/riscv/{ =3D> tcg}/th_csr.c (100%) rename target/riscv/{ =3D> tcg}/translate.c (100%) rename target/riscv/{ =3D> tcg}/vcrypto_helper.c (100%) rename target/riscv/{ =3D> tcg}/vector_helper.c (100%) rename target/riscv/{ =3D> tcg}/vector_internals.c (100%) rename target/riscv/{ =3D> tcg}/zce_helper.c (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_privileged.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rva.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvb.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvbf16.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvd.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvf.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvh.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvi.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvk.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvm.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvv.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvvk.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzabha.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzacas.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzalasr.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzawrs.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzce.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzcmop.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzfa.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzfh.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzicbo.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzicfiss.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzicond.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_rvzimop.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_svinval.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_xlrbr.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_xmips.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_xthead.c.inc (100%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_xventanacondops.c.inc (10= 0%) rename target/riscv/{ =3D> tcg}/insn_trans/trans_zilsd.c.inc (100%) diff --git a/target/riscv/pmu.h b/target/riscv/tcg/pmu.h similarity index 100% rename from target/riscv/pmu.h rename to target/riscv/tcg/pmu.h diff --git a/target/riscv/vector_internals.h b/target/riscv/tcg/vector_inte= rnals.h similarity index 100% rename from target/riscv/vector_internals.h rename to target/riscv/tcg/vector_internals.h diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/tcg/bitmanip_hel= per.c similarity index 100% rename from target/riscv/bitmanip_helper.c rename to target/riscv/tcg/bitmanip_helper.c diff --git a/target/riscv/cpu_helper.c b/target/riscv/tcg/cpu_helper.c similarity index 100% rename from target/riscv/cpu_helper.c rename to target/riscv/tcg/cpu_helper.c diff --git a/target/riscv/crypto_helper.c b/target/riscv/tcg/crypto_helper.c similarity index 100% rename from target/riscv/crypto_helper.c rename to target/riscv/tcg/crypto_helper.c diff --git a/target/riscv/csr.c b/target/riscv/tcg/csr.c similarity index 100% rename from target/riscv/csr.c rename to target/riscv/tcg/csr.c diff --git a/target/riscv/debug.c b/target/riscv/tcg/debug.c similarity index 100% rename from target/riscv/debug.c rename to target/riscv/tcg/debug.c diff --git a/target/riscv/fpu_helper.c b/target/riscv/tcg/fpu_helper.c similarity index 100% rename from target/riscv/fpu_helper.c rename to target/riscv/tcg/fpu_helper.c diff --git a/target/riscv/m128_helper.c b/target/riscv/tcg/m128_helper.c similarity index 100% rename from target/riscv/m128_helper.c rename to target/riscv/tcg/m128_helper.c diff --git a/target/riscv/mips_csr.c b/target/riscv/tcg/mips_csr.c similarity index 100% rename from target/riscv/mips_csr.c rename to target/riscv/tcg/mips_csr.c diff --git a/target/riscv/op_helper.c b/target/riscv/tcg/op_helper.c similarity index 100% rename from target/riscv/op_helper.c rename to target/riscv/tcg/op_helper.c diff --git a/target/riscv/pmu.c b/target/riscv/tcg/pmu.c similarity index 100% rename from target/riscv/pmu.c rename to target/riscv/tcg/pmu.c diff --git a/target/riscv/th_csr.c b/target/riscv/tcg/th_csr.c similarity index 100% rename from target/riscv/th_csr.c rename to target/riscv/tcg/th_csr.c diff --git a/target/riscv/translate.c b/target/riscv/tcg/translate.c similarity index 100% rename from target/riscv/translate.c rename to target/riscv/tcg/translate.c diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/tcg/vcrypto_helpe= r.c similarity index 100% rename from target/riscv/vcrypto_helper.c rename to target/riscv/tcg/vcrypto_helper.c diff --git a/target/riscv/vector_helper.c b/target/riscv/tcg/vector_helper.c similarity index 100% rename from target/riscv/vector_helper.c rename to target/riscv/tcg/vector_helper.c diff --git a/target/riscv/vector_internals.c b/target/riscv/tcg/vector_inte= rnals.c similarity index 100% rename from target/riscv/vector_internals.c rename to target/riscv/tcg/vector_internals.c diff --git a/target/riscv/zce_helper.c b/target/riscv/tcg/zce_helper.c similarity index 100% rename from target/riscv/zce_helper.c rename to target/riscv/tcg/zce_helper.c diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= tcg/insn_trans/trans_privileged.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_privileged.c.inc rename to target/riscv/tcg/insn_trans/trans_privileged.c.inc diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/tcg/ins= n_trans/trans_rva.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rva.c.inc rename to target/riscv/tcg/insn_trans/trans_rva.c.inc diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/tcg/ins= n_trans/trans_rvb.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvb.c.inc rename to target/riscv/tcg/insn_trans/trans_rvb.c.inc diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/tcg/= insn_trans/trans_rvbf16.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvbf16.c.inc rename to target/riscv/tcg/insn_trans/trans_rvbf16.c.inc diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/tcg/ins= n_trans/trans_rvd.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvd.c.inc rename to target/riscv/tcg/insn_trans/trans_rvd.c.inc diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/tcg/ins= n_trans/trans_rvf.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvf.c.inc rename to target/riscv/tcg/insn_trans/trans_rvf.c.inc diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/tcg/ins= n_trans/trans_rvh.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvh.c.inc rename to target/riscv/tcg/insn_trans/trans_rvh.c.inc diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/tcg/ins= n_trans/trans_rvi.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvi.c.inc rename to target/riscv/tcg/insn_trans/trans_rvi.c.inc diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/tcg/ins= n_trans/trans_rvk.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvk.c.inc rename to target/riscv/tcg/insn_trans/trans_rvk.c.inc diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/tcg/ins= n_trans/trans_rvm.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvm.c.inc rename to target/riscv/tcg/insn_trans/trans_rvm.c.inc diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/ins= n_trans/trans_rvv.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvv.c.inc rename to target/riscv/tcg/insn_trans/trans_rvv.c.inc diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/tcg/in= sn_trans/trans_rvvk.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvvk.c.inc rename to target/riscv/tcg/insn_trans/trans_rvvk.c.inc diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/tcg= /insn_trans/trans_rvzabha.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzabha.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzabha.c.inc diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/tcg= /insn_trans/trans_rvzacas.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzacas.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzacas.c.inc diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/tc= g/insn_trans/trans_rvzalasr.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzalasr.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzalasr.c.inc diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/tcg= /insn_trans/trans_rvzawrs.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzawrs.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzawrs.c.inc diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/tcg/i= nsn_trans/trans_rvzce.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzce.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzce.c.inc diff --git a/target/riscv/insn_trans/trans_rvzcmop.c.inc b/target/riscv/tcg= /insn_trans/trans_rvzcmop.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzcmop.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzcmop.c.inc diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/tcg/i= nsn_trans/trans_rvzfa.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzfa.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzfa.c.inc diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/tcg/i= nsn_trans/trans_rvzfh.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzfh.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzfh.c.inc diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/tcg= /insn_trans/trans_rvzicbo.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzicbo.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzicbo.c.inc diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/t= cg/insn_trans/trans_rvzicfiss.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzicfiss.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc diff --git a/target/riscv/insn_trans/trans_rvzicond.c.inc b/target/riscv/tc= g/insn_trans/trans_rvzicond.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzicond.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzicond.c.inc diff --git a/target/riscv/insn_trans/trans_rvzimop.c.inc b/target/riscv/tcg= /insn_trans/trans_rvzimop.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_rvzimop.c.inc rename to target/riscv/tcg/insn_trans/trans_rvzimop.c.inc diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/tcg= /insn_trans/trans_svinval.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_svinval.c.inc rename to target/riscv/tcg/insn_trans/trans_svinval.c.inc diff --git a/target/riscv/insn_trans/trans_xlrbr.c.inc b/target/riscv/tcg/i= nsn_trans/trans_xlrbr.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_xlrbr.c.inc rename to target/riscv/tcg/insn_trans/trans_xlrbr.c.inc diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/tcg/i= nsn_trans/trans_xmips.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_xmips.c.inc rename to target/riscv/tcg/insn_trans/trans_xmips.c.inc diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/tcg/= insn_trans/trans_xthead.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_xthead.c.inc rename to target/riscv/tcg/insn_trans/trans_xthead.c.inc diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/r= iscv/tcg/insn_trans/trans_xventanacondops.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_xventanacondops.c.inc rename to target/riscv/tcg/insn_trans/trans_xventanacondops.c.inc diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/tcg/i= nsn_trans/trans_zilsd.c.inc similarity index 100% rename from target/riscv/insn_trans/trans_zilsd.c.inc rename to target/riscv/tcg/insn_trans/trans_zilsd.c.inc diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 79f36abd63..61874ed0af 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -16,31 +16,15 @@ riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', =20 riscv_ss.add(files( 'cpu.c', - 'cpu_helper.c', - 'csr.c', - 'fpu_helper.c', 'gdbstub.c', - 'op_helper.c', - 'vector_helper.c', - 'vector_internals.c', - 'bitmanip_helper.c', - 'translate.c', - 'm128_helper.c', - 'crypto_helper.c', - 'zce_helper.c', - 'vcrypto_helper.c' )) =20 riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( 'arch_dump.c', 'pmp.c', - 'debug.c', 'monitor.c', 'machine.c', - 'mips_csr.c', - 'pmu.c', - 'th_csr.c', 'time_helper.c', 'riscv-qmp-cmds.c', )) diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build index 061df3d74a..5684fcf985 100644 --- a/target/riscv/tcg/meson.build +++ b/target/riscv/tcg/meson.build @@ -1,2 +1,28 @@ -riscv_ss.add(when: 'CONFIG_TCG', if_true: files( - 'tcg-cpu.c')) +if 'CONFIG_TCG' not in config_all_accel + subdir_done() +endif + +riscv_ss.add(files( + 'bitmanip_helper.c', + 'cpu_helper.c', + 'csr.c', + 'crypto_helper.c', + 'fpu_helper.c', + 'm128_helper.c', + 'op_helper.c', + 'translate.c', + 'tcg-cpu.c', + 'vcrypto_helper.c', + 'vector_helper.c', + 'vector_internals.c', + 'zce_helper.c')) + + +riscv_system_ss.add(files( + 'debug.c', + 'mips_csr.c', + 'pmu.c', + 'th_csr.c', +)) + + --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652234; cv=none; d=zohomail.com; s=zohoarc; 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<20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652235281158500 From: Daniel Henrique Barboza The PMP emulation isn't present in the KVM driver. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-6-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/machine.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ba96ceceef..ef0a8eae24 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "qemu/error-report.h" #include "system/kvm.h" +#include "system/tcg.h" #include "migration/cpu.h" #include "exec/icount.h" #include "target/riscv/debug.h" @@ -29,21 +30,25 @@ static bool pmp_needed(void *opaque) { RISCVCPU *cpu =3D opaque; =20 - return cpu->cfg.pmp; + if (kvm_enabled()) { + return false; + } + + return tcg_enabled() && cpu->cfg.pmp; } =20 static int pmp_post_load(void *opaque, int version_id) { +#ifdef CONFIG_TCG RISCVCPU *cpu =3D opaque; CPURISCVState *env =3D &cpu->env; - int i; uint8_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 - for (i =3D 0; i < pmp_regions; i++) { + for (int i =3D 0; i < pmp_regions; i++) { pmp_update_rule_addr(env, i); } pmp_update_rule_nums(env); - +#endif return 0; } =20 --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652299; cv=none; d=zohomail.com; s=zohoarc; b=ee9227kibCXN0VXj2cGQfAv6ExwR0fZDDfVN4Uq7uBPFNtXrjqNx6NmnOPYtHIbV2cFoWxqUfXUqYz9z4i8SzngVwOibzh8W/Ggj4rGpfRQQVRWtvtX/Q1Ubp0oYpKpASU5QfwKdv7HAcW6wBwALbDShVRJZeaYncgOiN5I31cg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783652299; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 09 Jul 2026 19:56:17 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Chao Liu Subject: [PULL 12/40] target/riscv: move pmp files to tcg subdir Date: Fri, 10 Jul 2026 12:54:57 +1000 Message-ID: <20260710025525.1704417-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652301618158500 From: Daniel Henrique Barboza A trivial header change is required too. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Chao Liu Message-ID: <20260703180538.3346781-7-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/{ =3D> tcg}/pmp.h | 0 target/riscv/{ =3D> tcg}/pmp.c | 0 target/riscv/meson.build | 1 - target/riscv/tcg/meson.build | 1 + 5 files changed, 2 insertions(+), 2 deletions(-) rename target/riscv/{ =3D> tcg}/pmp.h (100%) rename target/riscv/{ =3D> tcg}/pmp.c (100%) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 82362ef8d8..ecf2913d42 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -183,7 +183,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied= _rules[]; #define MMU_USER_IDX 3 =20 #if !defined(CONFIG_USER_ONLY) -#include "pmp.h" +#include "tcg/pmp.h" #endif =20 #define RV_VLEN_MAX 1024 diff --git a/target/riscv/pmp.h b/target/riscv/tcg/pmp.h similarity index 100% rename from target/riscv/pmp.h rename to target/riscv/tcg/pmp.h diff --git a/target/riscv/pmp.c b/target/riscv/tcg/pmp.c similarity index 100% rename from target/riscv/pmp.c rename to target/riscv/tcg/pmp.c diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 61874ed0af..42d0f6d538 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -22,7 +22,6 @@ riscv_ss.add(files( riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( 'arch_dump.c', - 'pmp.c', 'monitor.c', 'machine.c', 'time_helper.c', diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build index 5684fcf985..a05ab642f4 100644 --- a/target/riscv/tcg/meson.build +++ b/target/riscv/tcg/meson.build @@ -21,6 +21,7 @@ riscv_ss.add(files( riscv_system_ss.add(files( 'debug.c', 'mips_csr.c', + 'pmp.c', 'pmu.c', 'th_csr.c', )) --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 09 Jul 2026 19:56:21 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 13/40] target/riscv: tidy up riscv_sysemu_ops Date: Fri, 10 Jul 2026 12:54:58 +1000 Message-ID: <20260710025525.1704417-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=alistair23@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652307670158500 From: Daniel Henrique Barboza monitor_get_register at this moment has a TCG exclusive implementation for RISC-V, even though the callback is supposed to be arch independent. Until we address how KVM is going to implement it we need to filter it out in cpu.c. Same goes for get_phys_addr_debug - it has a TCG only implementation and KVM can't use it for now. It would also need to be filtered out, but since we're at it, let's convert it to the newer 'translate_for_debug' API too. Same restrictions apply. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260703180538.3346781-8-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 ++- target/riscv/cpu.c | 6 ++++-- target/riscv/monitor.c | 2 ++ target/riscv/tcg/cpu_helper.c | 14 ++++++++++---- 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ecf2913d42..18fbd4edb6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -665,7 +665,8 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retad= dr); -hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); +bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr addr, + TranslateForDebugResult *result); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cae4e96232..d17ba0474a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2693,11 +2693,13 @@ static int64_t riscv_get_arch_id(CPUState *cs) =20 static const struct SysemuCPUOps riscv_sysemu_ops =3D { .has_work =3D riscv_cpu_has_work, - .get_phys_addr_debug =3D riscv_cpu_get_phys_addr_debug, .write_elf64_note =3D riscv_cpu_write_elf64_note, .write_elf32_note =3D riscv_cpu_write_elf32_note, - .monitor_get_register =3D riscv_monitor_get_register_legacy, .legacy_vmsd =3D &vmstate_riscv_cpu, +#ifdef CONFIG_TCG + .translate_for_debug =3D riscv_cpu_translate_for_debug, + .monitor_get_register =3D riscv_monitor_get_register_legacy, +#endif }; #endif =20 diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 3e89dcaf7c..7aacd1d89c 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -245,6 +245,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) mem_info_svxx(mon, env); } =20 +#ifdef CONFIG_TCG static bool reg_is_ulong_integer(CPURISCVState *env, const char *name, target_ulong *val, bool is_gprh) { @@ -379,3 +380,4 @@ int riscv_monitor_get_register_legacy(CPUState *cs, con= st char *name, =20 return -EINVAL; } +#endif diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 2db07f5dfb..885b4172c0 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -1779,7 +1779,8 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, env->two_stage_indirect_lookup =3D two_stage_indirect; } =20 -hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) +bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr addr, + TranslateForDebugResult *result) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; @@ -1789,17 +1790,22 @@ hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, = vaddr addr) =20 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, true, env->virt_enabled, true, false)) { - return -1; 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Thu, 09 Jul 2026 19:56:24 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 14/40] target/riscv: move debug.h to tcg subdir Date: Fri, 10 Jul 2026 12:54:59 +1000 Message-ID: <20260710025525.1704417-15-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652430188158500 From: Daniel Henrique Barboza riscv_trigger_* APIs are TCG only. Wrap the usages we have of them in cpu.c with CONFIG_TCG. After that we can move the header to the tcg subdir. This will be enough to get this out of the way for the --disable-tcg build. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-9-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/{ =3D> tcg}/debug.h | 0 target/riscv/cpu.c | 8 +++++--- target/riscv/machine.c | 2 +- target/riscv/tcg/cpu_helper.c | 2 +- target/riscv/tcg/csr.c | 2 +- target/riscv/tcg/debug.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- 7 files changed, 10 insertions(+), 8 deletions(-) rename target/riscv/{ =3D> tcg}/debug.h (100%) diff --git a/target/riscv/debug.h b/target/riscv/tcg/debug.h similarity index 100% rename from target/riscv/debug.h rename to target/riscv/tcg/debug.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d17ba0474a..a2887adf16 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -39,7 +39,7 @@ #include "kvm/kvm_riscv.h" #include "tcg/tcg-cpu.h" #if !defined(CONFIG_USER_ONLY) -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #endif =20 /* RISC-V CPU definitions */ @@ -856,9 +856,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTyp= e type) env->vill =3D true; =20 #ifndef CONFIG_USER_ONLY +#ifdef CONFIG_TCG if (cpu->cfg.debug) { riscv_trigger_reset_hold(env); } +#endif =20 if (cpu->cfg.ext_smrnmi) { env->rnmip =3D 0; @@ -1016,7 +1018,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) =20 riscv_cpu_register_gdb_regs_for_features(cs); =20 -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) if (cpu->cfg.debug) { riscv_trigger_realize(&cpu->env); } @@ -1031,7 +1033,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) static void riscv_cpu_unrealize(DeviceState *dev) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) RISCVCPU *cpu =3D RISCV_CPU(dev); =20 if (cpu->cfg.debug) { diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ef0a8eae24..0ab613a298 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -23,7 +23,7 @@ #include "system/tcg.h" #include "migration/cpu.h" #include "exec/icount.h" -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #include "hw/riscv/machines-qom.h" =20 static bool pmp_needed(void *opaque) diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 885b4172c0..310c18db46 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -35,7 +35,7 @@ #include "semihosting/common-semi.h" #include "exec/icount.h" #include "cpu_bits.h" -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #include "pmp.h" #include "qemu/plugin.h" =20 diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 7818d81fb0..36d12b6a51 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -34,7 +34,7 @@ #include "tcg/insn-start-words.h" #include "internals.h" #if !defined(CONFIG_USER_ONLY) -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #endif =20 /* CSR function table public API */ diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index ba5bc6ae13..3c0fe70101 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -28,7 +28,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "cpu.h" -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #include "trace.h" #include "exec/helper-proto.h" #include "exec/watchpoint.h" diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b73e3e9dd4..fe6350f497 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -37,7 +37,7 @@ #include "hw/core/boards.h" #include "system/tcg.h" #include "exec/icount.h" -#include "target/riscv/debug.h" +#include "target/riscv/tcg/debug.h" #endif =20 /* Hash that stores user set extensions */ --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 09 Jul 2026 19:56:27 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 15/40] target/riscv: remove csr.h from kvm-cpu.c Date: Fri, 10 Jul 2026 12:55:00 +1000 Message-ID: <20260710025525.1704417-16-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652249518158501 From: Daniel Henrique Barboza Move riscv_new_csr_seed from csr.c to cpu.c since this function is shared with KVM. With that we can remove the csr.h from kvm-cpu.c. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-10-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 ++- target/riscv/csr.h | 3 --- target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++ target/riscv/kvm/kvm-cpu.c | 1 - target/riscv/tcg/csr.c | 29 ----------------------------- 5 files changed, 32 insertions(+), 34 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 18fbd4edb6..a8c7e21bec 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -970,7 +970,8 @@ void riscv_add_satp_mode_properties(Object *obj); bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); - +target_ulong riscv_new_csr_seed(target_ulong new_value, + target_ulong write_mask); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); =20 const char *priv_spec_to_str(int priv_version); diff --git a/target/riscv/csr.h b/target/riscv/csr.h index 66ec9546ed..53ba3b4a4d 100644 --- a/target/riscv/csr.h +++ b/target/riscv/csr.h @@ -12,9 +12,6 @@ #include "exec/target_long.h" #include "cpu_bits.h" =20 -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask); - RISCVException riscv_csrr(CPURISCVState *env, int csrno, target_ulong *ret_value); =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a2887adf16..ba75c0de39 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -21,6 +21,7 @@ #include "qemu/qemu-print.h" #include "qemu/ctype.h" #include "qemu/log.h" +#include "qemu/guest-random.h" #include "cpu.h" #include "cpu_vendorid.h" #include "target/riscv/csr.h" @@ -556,6 +557,35 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, = const RISCVCSR *csr_list) } #endif =20 +/* Used by csr.c and the KVM driver */ +target_ulong riscv_new_csr_seed(target_ulong new_value, + target_ulong write_mask) +{ + uint16_t random_v; + Error *random_e =3D NULL; + int random_r; + target_ulong rval; + + random_r =3D qemu_guest_getrandom(&random_v, 2, &random_e); + if (unlikely(random_r < 0)) { + /* + * Failed, for unknown reasons in the crypto subsystem. + * The best we can do is log the reason and return a + * failure indication to the guest. There is no reason + * we know to expect the failure to be transitory, so + * indicate DEAD to avoid having the guest spin on WAIT. + */ + qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", + __func__, error_get_pretty(random_e)); + error_free(random_e); + rval =3D SEED_OPST_DEAD; + } else { + rval =3D random_v | SEED_OPST_ES16; + } + + return rval; +} + static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 2a5440d584..dfcd6e3c77 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -31,7 +31,6 @@ #include "system/kvm.h" #include "system/kvm_int.h" #include "cpu.h" -#include "target/riscv/csr.h" #include "trace.h" #include "accel/accel-cpu-target.h" #include "hw/pci/pci.h" diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 36d12b6a51..9c7e9d0e4b 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -29,7 +29,6 @@ #include "exec/icount.h" #include "accel/tcg/cpu-loop.h" #include "accel/tcg/getpc.h" -#include "qemu/guest-random.h" #include "qapi/error.h" #include "tcg/insn-start-words.h" #include "internals.h" @@ -5572,34 +5571,6 @@ static RISCVException write_mnstatus(CPURISCVState *= env, int csrno, #endif =20 /* Crypto Extension */ -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask) -{ - uint16_t random_v; - Error *random_e =3D NULL; - int random_r; - target_ulong rval; - - random_r =3D qemu_guest_getrandom(&random_v, 2, &random_e); - if (unlikely(random_r < 0)) { - /* - * Failed, for unknown reasons in the crypto subsystem. - * The best we can do is log the reason and return a - * failure indication to the guest. There is no reason - * we know to expect the failure to be transitory, so - * indicate DEAD to avoid having the guest spin on WAIT. - */ - qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", - __func__, error_get_pretty(random_e)); - error_free(random_e); - rval =3D SEED_OPST_DEAD; - } else { - rval =3D random_v | SEED_OPST_ES16; - } - - return rval; -} - static RISCVException rmw_seed(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652449; cv=none; d=zohomail.com; s=zohoarc; b=j+qcUK4NaqaC8CS1S4IG2BJvfxrgKfDhzUSSM7p9z7wrd/t2pTtkwvZzg/Ta0KohE3YCGutKEoNjom5FdraRh3DNqS2ymfsNUtq0mPnJPPvp1vHwSEbdHwomPKUu/SjgT426yK4yJpKMl1eH6KyrebBHnipfnVy2cRHwp2siaZs= ARC-Message-Signature: i=1; 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Thu, 09 Jul 2026 19:56:30 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 16/40] target/riscv: move csr.h to tcg subdir Date: Fri, 10 Jul 2026 12:55:01 +1000 Message-ID: <20260710025525.1704417-17-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652450386158500 From: Daniel Henrique Barboza After KVM is no longer reliant on csr.h move it to the TGC only land. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-11-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/{ =3D> tcg}/csr.h | 0 target/riscv/cpu.c | 2 +- target/riscv/gdbstub.c | 2 +- target/riscv/monitor.c | 2 +- target/riscv/riscv-qmp-cmds.c | 2 +- target/riscv/tcg/csr.c | 2 +- target/riscv/tcg/mips_csr.c | 2 +- target/riscv/tcg/op_helper.c | 2 +- target/riscv/tcg/pmp.c | 2 +- target/riscv/tcg/th_csr.c | 2 +- 10 files changed, 9 insertions(+), 9 deletions(-) rename target/riscv/{ =3D> tcg}/csr.h (100%) diff --git a/target/riscv/csr.h b/target/riscv/tcg/csr.h similarity index 100% rename from target/riscv/csr.h rename to target/riscv/tcg/csr.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ba75c0de39..c5b03847bf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -24,7 +24,7 @@ #include "qemu/guest-random.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" #include "internals.h" #include "qapi/error.h" #include "qapi/visitor.h" diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a2bbaf7f07..f0a5e0d86f 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -21,7 +21,7 @@ #include "gdbstub/helpers.h" #include "cpu.h" #include "internals.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" =20 struct TypeSize { const char *gdb_type; diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 7aacd1d89c..f8042db9cd 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -22,7 +22,7 @@ #include "qemu/ctype.h" #include "qemu/qemu-print.h" #include "cpu.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" #include "cpu_bits.h" #include "monitor/monitor.h" #include "monitor/hmp.h" diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index b94e8391ed..2647deef91 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -35,7 +35,7 @@ #include "system/tcg.h" #include "cpu-qom.h" #include "cpu.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" =20 static void riscv_cpu_add_definition(gpointer data, gpointer user_data) { diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c index 9c7e9d0e4b..36f2004bc5 100644 --- a/target/riscv/tcg/csr.c +++ b/target/riscv/tcg/csr.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "qemu/timer.h" #include "cpu.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" #include "tcg/tcg-cpu.h" #include "pmu.h" #include "time_helper.h" diff --git a/target/riscv/tcg/mips_csr.c b/target/riscv/tcg/mips_csr.c index 609718f288..884030e91d 100644 --- a/target/riscv/tcg/mips_csr.c +++ b/target/riscv/tcg/mips_csr.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" =20 /* Static MIPS CSR state storage */ static struct { diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index 6d4849b135..ba3c7da375 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -20,7 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" #include "internals.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/riscv/tcg/pmp.c b/target/riscv/tcg/pmp.c index d93563c36b..41b55519a8 100644 --- a/target/riscv/tcg/pmp.c +++ b/target/riscv/tcg/pmp.c @@ -23,7 +23,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "cpu.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" #include "trace.h" #include "exec/cputlb.h" #include "exec/page-protection.h" diff --git a/target/riscv/tcg/th_csr.c b/target/riscv/tcg/th_csr.c index 431f4cc286..e6f642991c 100644 --- a/target/riscv/tcg/th_csr.c +++ b/target/riscv/tcg/th_csr.c @@ -22,7 +22,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "target/riscv/csr.h" +#include "target/riscv/tcg/csr.h" =20 /* Extended M-mode control registers of T-Head */ #define CSR_TH_MXSTATUS 0x7c0 --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 09 Jul 2026 19:56:33 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 17/40] target/riscv: move custom_csrs logic to tcg-cpu.c Date: Fri, 10 Jul 2026 12:55:02 +1000 Message-ID: <20260710025525.1704417-18-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=alistair23@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652454427158500 From: Daniel Henrique Barboza We have a couple of CPUs that has a set of custom CSRs that uses TCG specific APIs. Move the related code to tcg-cpu.c and do not set .custom_csrs if we're not in a TCG build. What we'll end up doing, sooner or later, is punting all these CPUs to tcg-cpu.c since they're all TCG specific and KVM has nothing to do with them. Another time. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-12-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 26 +++++--------------------- target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++ 3 files changed, 28 insertions(+), 21 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a8c7e21bec..82430ecec6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -591,7 +591,9 @@ typedef struct RISCVCPUDef { int32_t vext_spec; RISCVCPUConfig cfg; bool bare; +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) const RISCVCSR *custom_csrs; +#endif /* This is just a setter for env->num_triggers. */ uint32_t num_triggers; } RISCVCPUDef; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c5b03847bf..bbce58ee58 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -544,19 +544,6 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 -#ifndef CONFIG_USER_ONLY -static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_= list) -{ - for (size_t i =3D 0; csr_list[i].csr_ops.name; i++) { - int csrno =3D csr_list[i].csrno; - const riscv_csr_operations *csr_ops =3D &csr_list[i].csr_ops; - if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)= ) { - riscv_set_csr_ops(csrno, csr_ops); - } - } -} -#endif - /* Used by csr.c and the KVM driver */ target_ulong riscv_new_csr_seed(target_ulong new_value, target_ulong write_mask) @@ -1268,11 +1255,6 @@ static void riscv_cpu_init(Object *obj) if (mcc->def->vext_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { cpu->env.vext_ver =3D mcc->def->vext_spec; } -#ifndef CONFIG_USER_ONLY - if (mcc->def->custom_csrs) { - riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); - } -#endif =20 accel_cpu_instance_init(CPU(obj)); } @@ -2846,10 +2828,12 @@ static void riscv_cpu_class_base_init(ObjectClass *= c, const void *data) =20 riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg); =20 +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) if (def->custom_csrs) { assert(!mcc->def->custom_csrs); mcc->def->custom_csrs =3D def->custom_csrs; } +#endif } =20 if (!object_class_is_abstract(c)) { @@ -3202,7 +3186,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.mvendorid =3D THEAD_VENDOR_ID, =20 .cfg.max_satp_mode =3D VM_1_10_SV39, -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) .custom_csrs =3D th_csr_list, #endif ), @@ -3248,7 +3232,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { =20 .cfg.marchid =3D 0x8d143000, .cfg.mvendorid =3D THEAD_VENDOR_ID, -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) .custom_csrs =3D th_csr_list, #endif ), @@ -3454,7 +3438,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_xmipscmov =3D true, .cfg.marchid =3D 0x8000000000000201, .cfg.mvendorid =3D MIPS_VENDOR_ID, -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) .custom_csrs =3D mips_csr_list, #endif ), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index fe6350f497..fef66557c2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -38,6 +38,7 @@ #include "system/tcg.h" #include "exec/icount.h" #include "target/riscv/tcg/debug.h" +#include "target/riscv/tcg/csr.h" #endif =20 /* Hash that stores user set extensions */ @@ -1650,10 +1651,30 @@ static bool riscv_cpu_has_max_extensions(Object *cp= u_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; } =20 +#ifndef CONFIG_USER_ONLY +static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_= list) +{ + for (size_t i =3D 0; csr_list[i].csr_ops.name; i++) { + int csrno =3D csr_list[i].csrno; + const riscv_csr_operations *csr_ops =3D &csr_list[i].csr_ops; + if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)= ) { + riscv_set_csr_ops(csrno, csr_ops); + } + } +} +#endif + static void riscv_tcg_cpu_instance_init(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); Object *obj =3D OBJECT(cpu); +#ifndef CONFIG_USER_ONLY + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(obj); + + if (mcc->def->custom_csrs) { + riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); + } +#endif =20 misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 09 Jul 2026 19:56:36 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 18/40] target/riscv: move riscv_cpu_set_nmi() to tcg-cpu.c Date: Fri, 10 Jul 2026 12:55:03 +1000 Message-ID: <20260710025525.1704417-19-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=alistair23@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652259432158500 From: Daniel Henrique Barboza This function is related to Smrnmi and non-masked interrupts, firing up interrupts via env->rnmip from riscv_cpu_local_irq_pending(). This is all TCG only code. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-13-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 8 -------- target/riscv/tcg/tcg-cpu.c | 7 +++++++ 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bbce58ee58..508e8dc03e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1180,11 +1180,6 @@ static void riscv_cpu_set_irq(void *opaque, int irq,= int level) g_assert_not_reached(); } } - -static void riscv_cpu_set_nmi(void *opaque, int irq, int level) -{ - riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level); -} #endif /* CONFIG_USER_ONLY */ =20 static bool riscv_cpu_is_dynamic(Object *cpu_obj) @@ -1203,9 +1198,6 @@ static void riscv_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); - qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, - "riscv.cpu.rnmi", RNMI_MAX); - if (mcc->def->num_triggers) { env->num_triggers =3D mcc->def->num_triggers; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index fef66557c2..4af5cd9c73 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1662,6 +1662,11 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu= , const RISCVCSR *csr_list) } } } + +static inline void riscv_cpu_set_nmi(void *opaque, int irq, int level) +{ + riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level); +} #endif =20 static void riscv_tcg_cpu_instance_init(CPUState *cs) @@ -1674,6 +1679,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) if (mcc->def->custom_csrs) { riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); } + qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, + "riscv.cpu.rnmi", RNMI_MAX); #endif =20 misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 09 Jul 2026 19:56:39 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL 19/40] target/riscv: move some irq helpers to cpu.c Date: Fri, 10 Jul 2026 12:55:04 +1000 Message-ID: <20260710025525.1704417-20-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652398003158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza riscv_cpu_has_work() uses a handful of irq pending functions from cpu_helper.c. There is a very high possibility that KVM doesn't need the current implermentation of has_work(), but the common accel code needs an implementation of this callback (see cpu_exec_class_post_init) otherwise the KVM driver won't initialize. Move the relevant irq helpers to cpu.c to allow KVM to keep using the current has_work implementation, allowing --disable-tcg to work. We'll circle it back to evaluate a proper KVM implementation for it in a later date. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-14-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 + target/riscv/cpu.c | 187 ++++++++++++++++++++++++++++++++++ target/riscv/tcg/cpu_helper.c | 187 ---------------------------------- 3 files changed, 192 insertions(+), 187 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 82430ecec6..396d9253e6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -640,6 +640,11 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env); int riscv_cpu_mirq_pending(CPURISCVState *env); int riscv_cpu_sirq_pending(CPURISCVState *env); int riscv_cpu_vsirq_pending(CPURISCVState *env); +int riscv_cpu_pending_to_irq(CPURISCVState *env, + int extirq, unsigned int extirq_def_prio, + uint64_t pending, uint8_t *iprio); + + bool riscv_cpu_fp_enabled(CPURISCVState *env); uint8_t riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 508e8dc03e..fe24751379 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -745,6 +745,193 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) } =20 #ifndef CONFIG_USER_ONLY +/* + * Default priorities of local interrupts are defined in the + * RISC-V Advanced Interrupt Architecture specification. + * + * ---------------------------------------------------------------- + * Default | + * Priority | Major Interrupt Numbers + * ---------------------------------------------------------------- + * Highest | 47, 23, 46, 45, 22, 44, + * | 43, 21, 42, 41, 20, 40 + * | + * | 11 (0b), 3 (03), 7 (07) + * | 9 (09), 1 (01), 5 (05) + * | 12 (0c) + * | 10 (0a), 2 (02), 6 (06) + * | + * | 39, 19, 38, 37, 18, 36, + * Lowest | 35, 17, 34, 33, 16, 32 + * ---------------------------------------------------------------- + */ +static const uint8_t default_iprio[64] =3D { + /* Custom interrupts 48 to 63 */ + [63] =3D IPRIO_MMAXIPRIO, + [62] =3D IPRIO_MMAXIPRIO, + [61] =3D IPRIO_MMAXIPRIO, + [60] =3D IPRIO_MMAXIPRIO, + [59] =3D IPRIO_MMAXIPRIO, + [58] =3D IPRIO_MMAXIPRIO, + [57] =3D IPRIO_MMAXIPRIO, + [56] =3D IPRIO_MMAXIPRIO, + [55] =3D IPRIO_MMAXIPRIO, + [54] =3D IPRIO_MMAXIPRIO, + [53] =3D IPRIO_MMAXIPRIO, + [52] =3D IPRIO_MMAXIPRIO, + [51] =3D IPRIO_MMAXIPRIO, + [50] =3D IPRIO_MMAXIPRIO, + [49] =3D IPRIO_MMAXIPRIO, + [48] =3D IPRIO_MMAXIPRIO, + + /* Custom interrupts 24 to 31 */ + [31] =3D IPRIO_MMAXIPRIO, + [30] =3D IPRIO_MMAXIPRIO, + [29] =3D IPRIO_MMAXIPRIO, + [28] =3D IPRIO_MMAXIPRIO, + [27] =3D IPRIO_MMAXIPRIO, + [26] =3D IPRIO_MMAXIPRIO, + [25] =3D IPRIO_MMAXIPRIO, + [24] =3D IPRIO_MMAXIPRIO, + + [47] =3D IPRIO_DEFAULT_UPPER, + [23] =3D IPRIO_DEFAULT_UPPER + 1, + [46] =3D IPRIO_DEFAULT_UPPER + 2, + [45] =3D IPRIO_DEFAULT_UPPER + 3, + [22] =3D IPRIO_DEFAULT_UPPER + 4, + [44] =3D IPRIO_DEFAULT_UPPER + 5, + + [43] =3D IPRIO_DEFAULT_UPPER + 6, + [21] =3D IPRIO_DEFAULT_UPPER + 7, + [42] =3D IPRIO_DEFAULT_UPPER + 8, + [41] =3D IPRIO_DEFAULT_UPPER + 9, + [20] =3D IPRIO_DEFAULT_UPPER + 10, + [40] =3D IPRIO_DEFAULT_UPPER + 11, + + [11] =3D IPRIO_DEFAULT_M, + [3] =3D IPRIO_DEFAULT_M + 1, + [7] =3D IPRIO_DEFAULT_M + 2, + + [9] =3D IPRIO_DEFAULT_S, + [1] =3D IPRIO_DEFAULT_S + 1, + [5] =3D IPRIO_DEFAULT_S + 2, + + [12] =3D IPRIO_DEFAULT_SGEXT, + + [10] =3D IPRIO_DEFAULT_VS, + [2] =3D IPRIO_DEFAULT_VS + 1, + [6] =3D IPRIO_DEFAULT_VS + 2, + + [39] =3D IPRIO_DEFAULT_LOWER, + [19] =3D IPRIO_DEFAULT_LOWER + 1, + [38] =3D IPRIO_DEFAULT_LOWER + 2, + [37] =3D IPRIO_DEFAULT_LOWER + 3, + [18] =3D IPRIO_DEFAULT_LOWER + 4, + [36] =3D IPRIO_DEFAULT_LOWER + 5, + + [35] =3D IPRIO_DEFAULT_LOWER + 6, + [17] =3D IPRIO_DEFAULT_LOWER + 7, + [34] =3D IPRIO_DEFAULT_LOWER + 8, + [33] =3D IPRIO_DEFAULT_LOWER + 9, + [16] =3D IPRIO_DEFAULT_LOWER + 10, + [32] =3D IPRIO_DEFAULT_LOWER + 11, +}; + +uint8_t riscv_cpu_default_priority(int irq) +{ + if (irq < 0 || irq > 63) { + return IPRIO_MMAXIPRIO; + } + + return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; +}; + +int riscv_cpu_pending_to_irq(CPURISCVState *env, + int extirq, unsigned int extirq_def_prio, + uint64_t pending, uint8_t *iprio) +{ + int irq, best_irq =3D RISCV_EXCP_NONE; + unsigned int prio, best_prio =3D UINT_MAX; + + if (!pending) { + return RISCV_EXCP_NONE; + } + + irq =3D ctz64(pending); + if (!((extirq =3D=3D IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : + riscv_cpu_cfg(env)->ext_ssaia)) { + return irq; + } + + pending =3D pending >> irq; + while (pending) { + prio =3D iprio[irq]; + if (!prio) { + if (irq =3D=3D extirq) { + prio =3D extirq_def_prio; + } else { + prio =3D (riscv_cpu_default_priority(irq) < extirq_def_pri= o) ? + 1 : IPRIO_MMAXIPRIO; + } + } + if ((pending & 0x1) && (prio <=3D best_prio)) { + best_irq =3D irq; + best_prio =3D prio; + } + irq++; + pending =3D pending >> 1; + } + + return best_irq; +} + +/* + * Doesn't report interrupts inserted using mvip from M-mode firmware or + * using hvip bits 13:63 from HS-mode. Those are returned in + * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). + */ +uint64_t riscv_cpu_all_pending(CPURISCVState *env) +{ + uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); + uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + uint64_t vstip =3D (env->vstime_irq) ? MIP_VSTIP : 0; + + return (env->mip | vsgein | vstip) & env->mie; +} + +int riscv_cpu_mirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & + ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + + return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, + irqs, env->miprio); +} + +int riscv_cpu_sirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & ~env->hi= deleg; + uint64_t irqs_f =3D env->mvip & env->mvien & ~env->mideleg & env->sie; + + return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + irqs | irqs_f, env->siprio); +} + +int riscv_cpu_vsirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & env->hid= eleg; + uint64_t irqs_f_vs =3D env->hvip & env->hvien & ~env->hideleg & env->v= sie; + uint64_t vsbits; + + /* Bring VS-level bits to correct position */ + vsbits =3D irqs & VS_MODE_INTERRUPTS; + irqs &=3D ~VS_MODE_INTERRUPTS; + irqs |=3D vsbits >> 1; + + return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + (irqs | irqs_f_vs), env->hviprio); +} + bool riscv_cpu_has_work(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 310c18db46..250bb20481 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -330,193 +330,6 @@ int riscv_cpu_hviprio_index2irq(int index, int *out_i= rq, int *out_rdzero) return 0; } =20 -/* - * Default priorities of local interrupts are defined in the - * RISC-V Advanced Interrupt Architecture specification. - * - * ---------------------------------------------------------------- - * Default | - * Priority | Major Interrupt Numbers - * ---------------------------------------------------------------- - * Highest | 47, 23, 46, 45, 22, 44, - * | 43, 21, 42, 41, 20, 40 - * | - * | 11 (0b), 3 (03), 7 (07) - * | 9 (09), 1 (01), 5 (05) - * | 12 (0c) - * | 10 (0a), 2 (02), 6 (06) - * | - * | 39, 19, 38, 37, 18, 36, - * Lowest | 35, 17, 34, 33, 16, 32 - * ---------------------------------------------------------------- - */ -static const uint8_t default_iprio[64] =3D { - /* Custom interrupts 48 to 63 */ - [63] =3D IPRIO_MMAXIPRIO, - [62] =3D IPRIO_MMAXIPRIO, - [61] =3D IPRIO_MMAXIPRIO, - [60] =3D IPRIO_MMAXIPRIO, - [59] =3D IPRIO_MMAXIPRIO, - [58] =3D IPRIO_MMAXIPRIO, - [57] =3D IPRIO_MMAXIPRIO, - [56] =3D IPRIO_MMAXIPRIO, - [55] =3D IPRIO_MMAXIPRIO, - [54] =3D IPRIO_MMAXIPRIO, - [53] =3D IPRIO_MMAXIPRIO, - [52] =3D IPRIO_MMAXIPRIO, - [51] =3D IPRIO_MMAXIPRIO, - [50] =3D IPRIO_MMAXIPRIO, - [49] =3D IPRIO_MMAXIPRIO, - [48] =3D IPRIO_MMAXIPRIO, - - /* Custom interrupts 24 to 31 */ - [31] =3D IPRIO_MMAXIPRIO, - [30] =3D IPRIO_MMAXIPRIO, - [29] =3D IPRIO_MMAXIPRIO, - [28] =3D IPRIO_MMAXIPRIO, - [27] =3D IPRIO_MMAXIPRIO, - [26] =3D IPRIO_MMAXIPRIO, - [25] =3D IPRIO_MMAXIPRIO, - [24] =3D IPRIO_MMAXIPRIO, - - [47] =3D IPRIO_DEFAULT_UPPER, - [23] =3D IPRIO_DEFAULT_UPPER + 1, - [46] =3D IPRIO_DEFAULT_UPPER + 2, - [45] =3D IPRIO_DEFAULT_UPPER + 3, - [22] =3D IPRIO_DEFAULT_UPPER + 4, - [44] =3D IPRIO_DEFAULT_UPPER + 5, - - [43] =3D IPRIO_DEFAULT_UPPER + 6, - [21] =3D IPRIO_DEFAULT_UPPER + 7, - [42] =3D IPRIO_DEFAULT_UPPER + 8, - [41] =3D IPRIO_DEFAULT_UPPER + 9, - [20] =3D IPRIO_DEFAULT_UPPER + 10, - [40] =3D IPRIO_DEFAULT_UPPER + 11, - - [11] =3D IPRIO_DEFAULT_M, - [3] =3D IPRIO_DEFAULT_M + 1, - [7] =3D IPRIO_DEFAULT_M + 2, - - [9] =3D IPRIO_DEFAULT_S, - [1] =3D IPRIO_DEFAULT_S + 1, - [5] =3D IPRIO_DEFAULT_S + 2, - - [12] =3D IPRIO_DEFAULT_SGEXT, - - [10] =3D IPRIO_DEFAULT_VS, - [2] =3D IPRIO_DEFAULT_VS + 1, - [6] =3D IPRIO_DEFAULT_VS + 2, - - [39] =3D IPRIO_DEFAULT_LOWER, - [19] =3D IPRIO_DEFAULT_LOWER + 1, - [38] =3D IPRIO_DEFAULT_LOWER + 2, - [37] =3D IPRIO_DEFAULT_LOWER + 3, - [18] =3D IPRIO_DEFAULT_LOWER + 4, - [36] =3D IPRIO_DEFAULT_LOWER + 5, - - [35] =3D IPRIO_DEFAULT_LOWER + 6, - [17] =3D IPRIO_DEFAULT_LOWER + 7, - [34] =3D IPRIO_DEFAULT_LOWER + 8, - [33] =3D IPRIO_DEFAULT_LOWER + 9, - [16] =3D IPRIO_DEFAULT_LOWER + 10, - [32] =3D IPRIO_DEFAULT_LOWER + 11, -}; - -uint8_t riscv_cpu_default_priority(int irq) -{ - if (irq < 0 || irq > 63) { - return IPRIO_MMAXIPRIO; - } - - return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; -}; - -static int riscv_cpu_pending_to_irq(CPURISCVState *env, - int extirq, unsigned int extirq_def_pr= io, - uint64_t pending, uint8_t *iprio) -{ - int irq, best_irq =3D RISCV_EXCP_NONE; - unsigned int prio, best_prio =3D UINT_MAX; - - if (!pending) { - return RISCV_EXCP_NONE; - } - - irq =3D ctz64(pending); - if (!((extirq =3D=3D IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : - riscv_cpu_cfg(env)->ext_ssaia)) { - return irq; - } - - pending =3D pending >> irq; - while (pending) { - prio =3D iprio[irq]; - if (!prio) { - if (irq =3D=3D extirq) { - prio =3D extirq_def_prio; - } else { - prio =3D (riscv_cpu_default_priority(irq) < extirq_def_pri= o) ? - 1 : IPRIO_MMAXIPRIO; - } - } - if ((pending & 0x1) && (prio <=3D best_prio)) { - best_irq =3D irq; - best_prio =3D prio; - } - irq++; - pending =3D pending >> 1; - } - - return best_irq; -} - -/* - * Doesn't report interrupts inserted using mvip from M-mode firmware or - * using hvip bits 13:63 from HS-mode. Those are returned in - * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). - */ -uint64_t riscv_cpu_all_pending(CPURISCVState *env) -{ - uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); - uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; - uint64_t vstip =3D (env->vstime_irq) ? MIP_VSTIP : 0; - - return (env->mip | vsgein | vstip) & env->mie; -} - -int riscv_cpu_mirq_pending(CPURISCVState *env) -{ - uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & - ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); - - return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, - irqs, env->miprio); -} - -int riscv_cpu_sirq_pending(CPURISCVState *env) -{ - uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & ~env->hi= deleg; - uint64_t irqs_f =3D env->mvip & env->mvien & ~env->mideleg & env->sie; - - return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs | irqs_f, env->siprio); -} - -int riscv_cpu_vsirq_pending(CPURISCVState *env) -{ - uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & env->hid= eleg; - uint64_t irqs_f_vs =3D env->hvip & env->hvien & ~env->hideleg & env->v= sie; - uint64_t vsbits; - - /* Bring VS-level bits to correct position */ - vsbits =3D irqs & VS_MODE_INTERRUPTS; - irqs &=3D ~VS_MODE_INTERRUPTS; - irqs |=3D vsbits >> 1; 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Thu, 09 Jul 2026 19:56:42 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 20/40] target/riscv: move riscv_cpu_claim_interrupts to cpu.c Date: Fri, 10 Jul 2026 12:55:05 +1000 Message-ID: <20260710025525.1704417-21-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652275441158500 From: Daniel Henrique Barboza The function is used by hw/intc/ files that KVM cares about like riscv_aplic.c. Move it to cpu.c to be accessible for --disable-tcg builds. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-15-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 14 ++++++++++++++ target/riscv/tcg/cpu_helper.c | 11 ----------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fe24751379..2741047769 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -573,6 +573,20 @@ target_ulong riscv_new_csr_seed(target_ulong new_value, return rval; } =20 +#ifndef CONFIG_USER_ONLY +/* Used by lots of folks in hw/intc */ +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) +{ + CPURISCVState *env =3D &cpu->env; + if (env->miclaim & interrupts) { + return -1; + } else { + env->miclaim |=3D interrupts; + return 0; + } +} +#endif + static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 250bb20481..aded995a7f 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -572,17 +572,6 @@ void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, b= ool level) } } =20 -int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) -{ - CPURISCVState *env =3D &cpu->env; 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Thu, 09 Jul 2026 19:56:45 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 21/40] target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state Date: Fri, 10 Jul 2026 12:55:06 +1000 Message-ID: <20260710025525.1704417-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=alistair23@gmail.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652305738158500 From: Daniel Henrique Barboza riscv_dump_csr() is a TCG only function but we'll have to implement it at some capacity for KVM eventually, therefore put it under a CONFIG_TCG ifdef while making a note that this function is unimplemented in KVM. The csr_ops array is also TCG specific, thus the for loop inside dump_state that iterates it is also TCG only business. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260703180538.3346781-16-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2741047769..db18c52656 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -612,8 +612,10 @@ char *riscv_cpu_get_name(RISCVCPU *cpu) return cpu_model_from_type(typename); } =20 +/* Note: this function needs a KVM implementation. */ static void riscv_dump_csr(CPURISCVState *env, int csrno, FILE *f) { +#ifdef CONFIG_TCG target_ulong val =3D 0; RISCVException res =3D riscv_csrrw_debug(env, csrno, &val, 0, 0); =20 @@ -625,6 +627,7 @@ static void riscv_dump_csr(CPURISCVState *env, int csrn= o, FILE *f) qemu_fprintf(f, " %-13s " TARGET_FMT_lx "\n", csr_ops[csrno].name, val); } +#endif } =20 #if !defined(CONFIG_USER_ONLY) @@ -662,7 +665,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) } #endif qemu_fprintf(f, " %-13s %" PRIx64 "\n", "pc", env->pc); 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Thu, 09 Jul 2026 19:56:49 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 22/40] target/riscv: gate riscv_cpu_update_mip with tcg_enabled() Date: Fri, 10 Jul 2026 12:55:07 +1000 Message-ID: <20260710025525.1704417-23-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652357922158500 From: Daniel Henrique Barboza riscv_cpu_update_mip() is a TCG only call. Its KVM equivalent is kvm_riscv_set_irq(). cpu.c gates the KVM only function with a kvm_enabled() check, making it unavailable for TCG only builds. We need to do the same for riscv_cpu_update_mip() otherwise a KVM only build will fail because it doesn't know what this function is. Use tcg_enabled() for the couple of riscv_cpu_update_mip() calls we have unguarded in cpu.c. We have way more calls to deal with in time_helper.c which isn't using kvm_riscv_set_irq() at all, so create a riscv_accel_set_irq() local helper that will choose whether to use the KVM or TCG API. The reason we're going through all this hassle in time_helper.c is because hw/int/riscv_aclint.c uses it, and if we don't do something about we won't have riscv_aclint working for KVM. Whether this is a real problem or not and we should remove aclint support for KVM is question for another day. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-17-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 19 ++++++++++++++----- target/riscv/time_helper.c | 33 +++++++++++++++++++++++++-------- 2 files changed, 39 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db18c52656..6b79dcc5ee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1343,14 +1343,18 @@ static void riscv_cpu_set_irq(void *opaque, int irq= , int level) case IRQ_M_EXT: if (kvm_enabled()) { kvm_riscv_set_irq(cpu, irq, level); - } else { + } + + if (tcg_enabled()) { riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); } break; case IRQ_S_EXT: if (kvm_enabled()) { kvm_riscv_set_irq(cpu, irq, level); - } else { + } + + if (tcg_enabled()) { env->external_seip =3D level; riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level | env->software_se= ip)); @@ -1377,9 +1381,14 @@ static void riscv_cpu_set_irq(void *opaque, int irq,= int level) env->hgeip |=3D 1ULL << irq; } =20 - /* Update mip.SGEIP bit */ - riscv_cpu_update_mip(env, MIP_SGEIP, - BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); + if (kvm_enabled()) { + kvm_riscv_set_irq(cpu, irq, level); + } + if (tcg_enabled()) { + /* Update mip.SGEIP bit */ + riscv_cpu_update_mip(env, MIP_SGEIP, + BOOL_TO_MASK(!!(env->hgeie & env->hgeip))= ); + } } else { g_assert_not_reached(); } diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 400e917354..ede1a4c2a3 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -21,19 +21,34 @@ #include "cpu_bits.h" #include "time_helper.h" #include "hw/intc/riscv_aclint.h" +#include "kvm/kvm_riscv.h" +#include "system/kvm.h" +#include "system/tcg.h" + +static void riscv_accel_set_irq(RISCVCPU *cpu, int irq, int level) +{ + if (kvm_enabled()) { + kvm_riscv_set_irq(cpu, irq, level); + } + + if (tcg_enabled()) { + riscv_cpu_update_mip(&cpu->env, irq, level); + } +} + =20 static void riscv_vstimer_cb(void *opaque) { RISCVCPU *cpu =3D opaque; CPURISCVState *env =3D &cpu->env; env->vstime_irq =3D 1; - riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); + riscv_accel_set_irq(cpu, 0, BOOL_TO_MASK(1)); } =20 static void riscv_stimer_cb(void *opaque) { RISCVCPU *cpu =3D opaque; - riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1)); + riscv_accel_set_irq(cpu, MIP_STIP, BOOL_TO_MASK(1)); } =20 /* @@ -48,6 +63,7 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTi= mer *timer, RISCVAclintMTimerState *mtimer =3D env->rdtime_fn_arg; uint32_t timebase_freq; uint64_t rtc_r; + RISCVCPU *cpu; =20 if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn || !env->rdtime_fn_arg || !get_field(env->menvcfg, MENVCFG_STCE)) { @@ -63,6 +79,7 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTi= mer *timer, =20 timebase_freq =3D mtimer->timebase_freq; rtc_r =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; + cpu =3D env_archcpu(env); =20 if (timecmp <=3D rtc_r) { /* @@ -71,9 +88,9 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTi= mer *timer, */ if (timer_irq =3D=3D MIP_VSTIP) { env->vstime_irq =3D 1; - riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); + riscv_accel_set_irq(cpu, 0, BOOL_TO_MASK(1)); } else { - riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1)); + riscv_accel_set_irq(cpu, MIP_STIP, BOOL_TO_MASK(1)); } return; } @@ -81,9 +98,9 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTi= mer *timer, /* Clear the [VS|S]TIP bit in mip */ if (timer_irq =3D=3D MIP_VSTIP) { env->vstime_irq =3D 0; - riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0)); + riscv_accel_set_irq(cpu, 0, BOOL_TO_MASK(0)); } else { - riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0)); + riscv_accel_set_irq(cpu, timer_irq, BOOL_TO_MASK(0)); } =20 /* @@ -151,7 +168,7 @@ static void riscv_timer_disable_timecmp(CPURISCVState *= env, QEMUTimer *timer, { /* Disable S-mode Timer IRQ and HW-based STIP */ if ((timer_irq =3D=3D MIP_STIP) && !get_field(env->menvcfg, MENVCFG_ST= CE)) { - riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0)); + riscv_accel_set_irq(env_archcpu(env), timer_irq, BOOL_TO_MASK(0)); timer_del(timer); return; } @@ -161,7 +178,7 @@ static void riscv_timer_disable_timecmp(CPURISCVState *= env, QEMUTimer *timer, (!get_field(env->menvcfg, MENVCFG_STCE) || !get_field(env->henvcfg, HENVCFG_STCE))) { env->vstime_irq =3D 0; - riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0)); + riscv_accel_set_irq(env_archcpu(env), 0, BOOL_TO_MASK(0)); timer_del(timer); return; } --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652371; cv=none; d=zohomail.com; s=zohoarc; b=iUzwsjfoJTPqbPAVWppvkcCYf7oh3osB2kKmDNAJXicCSOyJgKKLRTOjhPRfN5pk142h6+20CiMa0+GAB6vZD6OGN7oD4G+6ttTifuoEvvcJDcRYQ4Ka1gsazNfTOc7x423DlpuIFe+QTaY2wH8khUlE8CwDJcjoKTEAdtAlLHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 09 Jul 2026 19:56:52 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 23/40] target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold() Date: Fri, 10 Jul 2026 12:55:08 +1000 Message-ID: <20260710025525.1704417-24-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=alistair23@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652371919158500 From: Daniel Henrique Barboza We have a lot of TCG only initialization in the common cpu_reset_hold callback that prevents --disable-tcg to work. Put a CONFIG_TCG ifdef around those bits to make the build work. Eventually we'll create a TCG specific reset function in tcg-cpu.c but for now this suffices. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-18-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b79dcc5ee..5a82e6563b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -965,10 +965,6 @@ bool riscv_cpu_has_work(CPUState *cs) =20 static void riscv_cpu_reset_hold(Object *obj, ResetType type) { -#ifndef CONFIG_USER_ONLY - uint8_t iprio; - int i, irq, rdzero; -#endif CPUState *cs =3D CPU(obj); RISCVCPU *cpu =3D RISCV_CPU(cs); RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(obj); @@ -1020,6 +1016,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetT= ype type) MENVCFG_ADUE : 0); env->henvcfg =3D 0; =20 +#ifdef CONFIG_TCG + uint8_t iprio; + int i, irq, rdzero; + /* Initialized default priorities of local interrupts. */ for (i =3D 0; i < ARRAY_SIZE(env->miprio); i++) { iprio =3D riscv_cpu_default_priority(i); @@ -1057,11 +1057,12 @@ static void riscv_cpu_reset_hold(Object *obj, Reset= Type type) } =20 pmp_unlock_entries(env); +#endif /* ifdef CONFIG_TCG */ #else env->priv =3D PRV_U; env->senvcfg =3D 0; env->menvcfg =3D 0; -#endif +#endif /* !CONFIG_USER_ONLY */ =20 /* on reset elp is clear */ env->elp =3D false; --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652228; cv=none; d=zohomail.com; s=zohoarc; b=FlNLinptTjqfkujlnfiYv5IXpXYXnrUBJprBEUOrVxBkdEMnO0vUhDBkJOmpcHZGH8IVnlrDcJU4ad1rVfRzOPyAJko017hRBnJJM4gJ2IbC2TSEyINfc2/YlvEA30Uuk0lz+OvYR9lBivBw2qFxQu2ju8qwWyOSzv9dojct2Eg= ARC-Message-Signature: i=1; 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Thu, 09 Jul 2026 19:56:55 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 24/40] hw/riscv/riscv_hart.c isolate tcg only bits Date: Fri, 10 Jul 2026 12:55:09 +1000 Message-ID: <20260710025525.1704417-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652229624158500 From: Daniel Henrique Barboza riscv_cpu_register_csr_qtest_callback(), vcsr_call() and csr_qtest_callback() are all TCG only and are not available in --disable-tcg builds. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260703180538.3346781-19-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv_hart.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index d1c7188369..747754be61 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -61,7 +61,7 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } =20 -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) { RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(cpu_num)); @@ -151,8 +151,10 @@ static void riscv_harts_realize(DeviceState *dev, Erro= r **errp) =20 s->harts =3D g_new0(RISCVCPU, s->num_harts); =20 -#ifndef CONFIG_USER_ONLY - riscv_cpu_register_csr_qtest_callback(); +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) + if (qtest_enabled()) { + riscv_cpu_register_csr_qtest_callback(); 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Thu, 09 Jul 2026 19:56:58 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 25/40] target/riscv/gdbstub.c: isolate TCG only checks Date: Fri, 10 Jul 2026 12:55:10 +1000 Message-ID: <20260710025525.1704417-26-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652261440158500 From: Daniel Henrique Barboza The following functions are TCG only and are broken, if they were ever usable in the first place, with KVM: - riscv_gdb_(get|se)t_csr - riscv_gdb_(get|set)_virtual - riscv_gen_dynamic_csr_feature Gate everything with TCG enabled to at least get them out of the way to enable --disable-tcg. As a note for the future: other archs have distincts gdbstub files for each accelerator. There's a strong case for RISC-V to do the same. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260703180538.3346781-20-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/gdbstub.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index f0a5e0d86f..9abbf5bcdf 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -164,6 +164,7 @@ static int riscv_gdb_set_vector(CPUState *cs, uint8_t *= mem_buf, int n) return 0; } =20 +#ifdef CONFIG_TCG static int riscv_gdb_get_csr(CPUState *cs, GByteArray *buf, int n) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -294,6 +295,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUSta= te *cs, int base_reg) =20 return &cpu->dyn_csr_feature; } +#endif /* CONFIG_TCG */ =20 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base= _reg) { @@ -336,7 +338,6 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPU= State *cs, int base_reg) =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; if (env->misa_ext & RVD) { @@ -351,6 +352,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState= *cs) riscv_gdb_set_vector, ricsv_gen_dynamic_vector_feature(cs, cs->= gdb_num_regs)); } + +#ifdef CONFIG_TCG + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); + switch (mcc->def->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, @@ -371,4 +376,5 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, riscv_gen_dynamic_csr_feature(cs, cs->gdb= _num_regs)); } +#endif } --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Thu, 09 Jul 2026 19:57:01 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 26/40] target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint Date: Fri, 10 Jul 2026 12:55:11 +1000 Message-ID: <20260710025525.1704417-27-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=alistair23@gmail.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652307631158500 From: Daniel Henrique Barboza There's no need for it to be in cpu_helper since riscv_aclint is the only caller. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-21-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 -- hw/intc/riscv_aclint.c | 8 ++++++++ target/riscv/tcg/cpu_helper.c | 7 ------- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 396d9253e6..d6c5d6c1db 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -682,8 +682,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint6= 4_t mask, void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), - void *arg); void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t pr= iv, aia_ireg_rmw_fn rmw_fn, void *rmw_fn_arg); diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index e27e5fb394..361a8d1bcb 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -40,6 +40,14 @@ typedef struct riscv_aclint_mtimer_callback { int num; } riscv_aclint_mtimer_callback; =20 +static void riscv_cpu_set_rdtime_fn(CPURISCVState *env, + uint64_t (*fn)(void *), + void *arg) +{ + env->rdtime_fn =3D fn; + env->rdtime_fn_arg =3D arg; +} + static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) { return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index aded995a7f..7a1ea53ae7 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -612,13 +612,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint= 64_t mask, uint64_t value) return old; } =20 -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), - void *arg) -{ - env->rdtime_fn =3D fn; - env->rdtime_fn_arg =3D arg; -} - void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t pr= iv, aia_ireg_rmw_fn rmw_fn, void *rmw_fn_arg) --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 09 Jul 2026 19:57:04 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 27/40] target/riscv/tcg: remove unused riscv_cpu_get_geilen() Date: Fri, 10 Jul 2026 12:55:12 +1000 Message-ID: <20260710025525.1704417-28-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652317636158500 From: Daniel Henrique Barboza No one uses it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260703180538.3346781-22-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/tcg/cpu_helper.c | 9 --------- 2 files changed, 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d6c5d6c1db..7618110412 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -646,7 +646,6 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env, =20 =20 bool riscv_cpu_fp_enabled(CPURISCVState *env); -uint8_t riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 7a1ea53ae7..6b39152ee2 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -526,15 +526,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) } } =20 -uint8_t riscv_cpu_get_geilen(CPURISCVState *env) -{ - if (!riscv_has_ext(env, RVH)) { - return 0; - } - - return env->geilen; -} - void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen) { if (!riscv_has_ext(env, RVH)) { --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652428; cv=none; d=zohomail.com; s=zohoarc; b=XoI3PU3HnBm3Zr/uMq1sanEBwp8VzgbrSPHczdbzOBiCSEkNt0MEgf36UQ2XWs7Pd8ODcJaUDDtsJGDEOEJ36PxVo9zNpoNgihDZvB4ICDb4xaSsiygWisEpXH9VnYmdO7fpmShQUXaZAkyl8Iuf0dWdqJ9i3GNERt9OcNICMUQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783652428; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 09 Jul 2026 19:57:07 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 28/40] target/riscv: move riscv_cpu_set_geilen() to riscv-imsic Date: Fri, 10 Jul 2026 12:55:13 +1000 Message-ID: <20260710025525.1704417-29-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=alistair23@gmail.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652430224158500 From: Daniel Henrique Barboza riscv_imsic.c is the only caller. Having it sitting in the TCG only cpu_helper.c gets in the way of --disable-tcg for no good reason. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-23-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - hw/intc/riscv_imsic.c | 13 +++++++++++++ target/riscv/tcg/cpu_helper.c | 13 ------------- 3 files changed, 13 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7618110412..7a4d8abe07 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -646,7 +646,6 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env, =20 =20 bool riscv_cpu_fp_enabled(CPURISCVState *env); -void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 7e5b5349ba..ebb55191c7 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -46,6 +46,19 @@ #define IMSIC_EISTATE_ENPEND (IMSIC_EISTATE_ENABLED | \ IMSIC_EISTATE_PENDING) =20 +static void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + if (geilen > (TARGET_LONG_BITS - 1)) { + return; + } + + env->geilen =3D geilen; +} + static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page) { uint32_t i, max_irq, base; diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 6b39152ee2..71a96a20ef 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -526,19 +526,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) } } =20 -void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen) -{ - if (!riscv_has_ext(env, RVH)) { - return; - } - - if (geilen > (TARGET_LONG_BITS - 1)) { - return; - } - - env->geilen =3D geilen; -} - void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level) { CPURISCVState *env =3D &cpu->env; --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 09 Jul 2026 19:57:10 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL 29/40] target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic Date: Fri, 10 Jul 2026 12:55:14 +1000 Message-ID: <20260710025525.1704417-30-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652436290158500 From: Daniel Henrique Barboza riscv_imsic.c is the only caller. Having it sitting in the TCG only cpu_helper.c gets in the way of --disable-tcg for no good reason. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-24-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 --- hw/intc/riscv_imsic.c | 11 +++++++++++ target/riscv/tcg/cpu_helper.c | 10 ---------- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7a4d8abe07..c9dfa7daff 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -680,9 +680,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint6= 4_t mask, void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ -void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t pr= iv, - aia_ireg_rmw_fn rmw_fn, - void *rmw_fn_arg); =20 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t); #endif /* !CONFIG_USER_ONLY */ diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index ebb55191c7..d6b46cdca2 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -376,6 +376,17 @@ static void riscv_imsic_reset_enter(Object *obj, Reset= Type type) } } =20 +static void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, + privilege_mode_t priv, + aia_ireg_rmw_fn rmw_fn, + void *rmw_fn_arg) +{ + if (priv <=3D PRV_M) { + env->aia_ireg_rmw_cb[priv] =3D rmw_fn; + env->aia_ireg_rmw_cb_arg[priv] =3D rmw_fn_arg; + } +} + static void riscv_imsic_realize(DeviceState *dev, Error **errp) { RISCVIMSICState *imsic =3D RISCV_IMSIC(dev); diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 71a96a20ef..07d9222652 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -590,16 +590,6 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint= 64_t mask, uint64_t value) return old; } =20 -void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t pr= iv, - aia_ireg_rmw_fn rmw_fn, - void *rmw_fn_arg) -{ - if (priv <=3D PRV_M) { - env->aia_ireg_rmw_cb[priv] =3D rmw_fn; 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Thu, 09 Jul 2026 19:57:14 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Zephyr Li , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 30/40] gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job Date: Fri, 10 Jul 2026 12:55:15 +1000 Message-ID: <20260710025525.1704417-31-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652428209158501 Content-Type: text/plain; charset="utf-8" From: Zephyr Li Add CI coverage for a riscv64 --disable-tcg cross build. This ensures that RISC-V no-TCG/KVM-only builds keep working and prevents TCG-only code from being accidentally pulled into common RISC-V sources again. The cross_accel_build_job template enables KVM by default via --enable-${ACCEL:-kvm}, so the extra options only need to disable TCG. Signed-off-by: Zephyr Li Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20260703180538.3346781-25-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- .gitlab-ci.d/crossbuilds.yml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index eaeeb533ce..a823aaaa21 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -59,6 +59,14 @@ cross-riscv64-user: variables: IMAGE: debian-riscv64-cross =20 +cross-riscv64-kvm-only: + extends: .cross_accel_build_job + needs: + - job: riscv64-debian-cross-container + variables: + IMAGE: debian-riscv64-cross + EXTRA_CONFIGURE_OPTS: --disable-tcg --without-default-features + cross-s390x-system: extends: .cross_system_build_job needs: --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 09 Jul 2026 19:57:17 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Chao Liu , Nutty Liu , Alistair Francis Subject: [PULL 31/40] hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN Date: Fri, 10 Jul 2026 12:55:16 +1000 Message-ID: <20260710025525.1704417-32-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=alistair23@gmail.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652394003158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We must check if IOHGATP_PPN is 16kb aligned for non-bare GATP modes. Fixes: 69a9ae4836 ("hw/riscv/riscv-iommu: add ATS support") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3550 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Reviewed-by: Nutty Liu Message-ID: <20260702203616.1795588-2-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 12f20fa4bd..d3710aa3a2 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -862,6 +862,21 @@ static bool riscv_iommu_validate_device_ctx(RISCVIOMMU= State *s, return false; } =20 + if (gatp !=3D RISCV_IOMMU_DC_IOHGATP_MODE_BARE) { + uint64_t iohgatp_ppn =3D get_field(ctx->gatp, + RISCV_IOMMU_DC_IOHGATP_PPN); + + /* + * One of the conditions for a misconfigured DDT entry + * according to the riscv-spec: "DC.iohgatp.MODE is not + * Bare and the root page table (address) determined by + * DC.iohgatp.PPN is not aligned to a 16-KiB boundary." + */ + if (PPN_PHYS(iohgatp_ppn) & ((1ULL << 14) - 1)) { + return false; + } + } + fsc_mode =3D get_field(ctx->satp, RISCV_IOMMU_DC_FSC_MODE); =20 if (ctx->tc & RISCV_IOMMU_DC_TC_PDTV) { --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1783652354; cv=none; d=zohomail.com; s=zohoarc; b=IobFY9cvn6oECu53PFoe7ta6mLCnkp5PidvJyoacdmEhn79E9wWCU89+W/x+UxJ9u6cOqKdzdRtMYOiwmEUQcwxIcvBsWNMcckwq2AcQqgQpzDox35HLNYxvlp5zHBmUBFVZ+tju23d+9tejKggrhDQv9ptxavGvCmOowL3QP20= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783652354; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 09 Jul 2026 19:57:20 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL 32/40] hw/riscv/riscv-iommu.c: update ioval2 when faulting in spa_fetch() Date: Fri, 10 Jul 2026 12:55:17 +1000 Message-ID: <20260710025525.1704417-33-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=alistair23@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652355802158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza riscv_iommu_translate(), the only caller of riscv_iommu_spa_fetch(), will use riscv_iommu_report_fault() for all faults it detects. And it will use iotlb->translated_addr as 'iotval2' every time. At this moment we're updating iotlb->translated_addr only after a translation step is completed, meaning any fault that occur before that will have a zeroed iotlb->translated_addr, and as a result iotval2 will also be zero later on. Keep iotlb->translated_addr updated with the latest translated addr we have. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3559 Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20260702171202.1322493-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index d3710aa3a2..bdc409adc9 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -574,6 +574,14 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, R= ISCVIOMMUContext *ctx, } } while (1); =20 + /* + * riscv_iommu_translate() will receive a fault and then call + * riscv_iommu_report_fault() using iotlb->translated_addr + * as iotval2. Update translated_addr it with the latest + * translated addr we have. + */ + iotlb->translated_addr =3D addr; + return (iotlb->perm & IOMMU_WO) ? (pass ? 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charset="utf-8" From: Daniel Henrique Barboza When capabilities.AMO_HWADD isn't set, DC.tc.GADE and DC.tc.SADE are reserved bits and setting them throws a DDT_MISCONFIGURED error. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3549 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Message-ID: <20260630172110.1866951-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu-bits.h | 1 + hw/riscv/riscv-iommu.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h index cc0b1c3ccd..924a1f8c21 100644 --- a/hw/riscv/riscv-iommu-bits.h +++ b/hw/riscv/riscv-iommu-bits.h @@ -86,6 +86,7 @@ struct riscv_iommu_pq_record { #define RISCV_IOMMU_CAP_SV57X4 BIT_ULL(19) #define RISCV_IOMMU_CAP_MSI_FLAT BIT_ULL(22) #define RISCV_IOMMU_CAP_MSI_MRIF BIT_ULL(23) +#define RISCV_IOMMU_CAP_AMO_HWAD BIT_ULL(24) #define RISCV_IOMMU_CAP_ATS BIT_ULL(25) #define RISCV_IOMMU_CAP_T2GPA BIT_ULL(26) #define RISCV_IOMMU_CAP_IGS GENMASK_ULL(29, 28) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index bdc409adc9..877d24bc47 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -417,6 +417,11 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, R= ISCVIOMMUContext *ctx, const bool ade =3D ctx->tc & (pass ? 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Thu, 09 Jul 2026 19:57:26 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Alistair Francis Subject: [PULL 34/40] hw/riscv/riscv-iommu.c: set ftype and iova in riscv_iommu_ctx() Date: Fri, 10 Jul 2026 12:55:19 +1000 Message-ID: <20260710025525.1704417-35-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=alistair23@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652369990158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We're hardcoding faulting type as READ, where it could very well be a write access, and we're not recording the faulting addr/iova. A note was added in the fault_type logic because I wasn't able to trivially handle a probable code repeitition it in this same patch. Something to do in a later date. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3564 Signed-off-by: Daniel Henrique Barboza Message-ID: <20260701092241.307801-1-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 877d24bc47..f6865d1e16 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -1430,6 +1430,7 @@ static void riscv_iommu_ctx_inval(RISCVIOMMUState *s,= GHFunc func, /* Find or allocate translation context for a given {device_id, process_id= } */ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s, unsigned devid, unsigned process= _id, + IOMMUAccessFlags perm, uint64_t = iova, void **ref) { GHashTable *ctx_cache; @@ -1439,6 +1440,7 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUS= tate *s, .process_id =3D process_id, }; unsigned mode =3D get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE); + uint32_t fault_type; =20 ctx_cache =3D g_hash_table_ref(s->ctx_cache); =20 @@ -1481,8 +1483,21 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMU= State *s, g_hash_table_unref(ctx_cache); *ref =3D NULL; =20 - riscv_iommu_report_fault(s, ctx, RISCV_IOMMU_FQ_TTYPE_UADDR_RD, - fault, !!process_id, 0, 0); + /* + * TODO: (1) do we need to distinguish other fault types + * for ctx fetching and (2) evaluate putting the 'fault_type' + * logic inside riscv_iommu_report_fault() - there's at + * least one other place (end of riscv_iommu_translate()) + * that does something similar. + */ + if (perm & IOMMU_RO) { + fault_type =3D RISCV_IOMMU_FQ_TTYPE_UADDR_RD; + } else { + fault_type =3D RISCV_IOMMU_FQ_TTYPE_UADDR_WR; + } + + riscv_iommu_report_fault(s, ctx, fault_type, fault, + !!process_id, iova, 0); =20 g_free(ctx); return NULL; @@ -2233,6 +2248,8 @@ static void riscv_iommu_process_dbg(RISCVIOMMUState *= s) uint64_t ctrl =3D riscv_iommu_reg_get64(s, RISCV_IOMMU_REG_TR_REQ_CTL); unsigned devid =3D get_field(ctrl, RISCV_IOMMU_TR_REQ_CTL_DID); unsigned pid =3D get_field(ctrl, RISCV_IOMMU_TR_REQ_CTL_PID); + IOMMUAccessFlags perm =3D ctrl & RISCV_IOMMU_TR_REQ_CTL_NW + ? IOMMU_RO : IOMMU_RW; RISCVIOMMUContext *ctx; void *ref; =20 @@ -2240,7 +2257,7 @@ static void riscv_iommu_process_dbg(RISCVIOMMUState *= s) return; } =20 - ctx =3D riscv_iommu_ctx(s, devid, pid, &ref); + ctx =3D riscv_iommu_ctx(s, devid, pid, perm, iova, &ref); if (ctx =3D=3D NULL) { riscv_iommu_reg_set64(s, RISCV_IOMMU_REG_TR_RESPONSE, RISCV_IOMMU_TR_RESPONSE_FAULT | @@ -2248,7 +2265,7 @@ static void riscv_iommu_process_dbg(RISCVIOMMUState *= s) } else { IOMMUTLBEntry iotlb =3D { .iova =3D iova, - .perm =3D ctrl & RISCV_IOMMU_TR_REQ_CTL_NW ? IOMMU_RO : IOMMU_= RW, + .perm =3D perm, .addr_mask =3D ~0, .target_as =3D NULL, }; @@ -2587,7 +2604,7 @@ static MemTxResult riscv_iommu_trap_write(void *opaqu= e, hwaddr addr, /* FIXME: PCIe bus remapping for attached endpoints. */ devid |=3D s->bus << 8; =20 - ctx =3D riscv_iommu_ctx(s, devid, 0, &ref); + ctx =3D riscv_iommu_ctx(s, devid, 0, IOMMU_RW, addr, &ref); if (ctx =3D=3D NULL) { res =3D MEMTX_ACCESS_ERROR; } else { @@ -2889,7 +2906,7 @@ static IOMMUTLBEntry riscv_iommu_memory_region_transl= ate( }; uint32_t devid =3D riscv_iommu_space_devid(as); =20 - ctx =3D riscv_iommu_ctx(as->iommu, devid, iommu_idx, &ref); + ctx =3D riscv_iommu_ctx(as->iommu, devid, iommu_idx, flag, addr, &ref); if (ctx =3D=3D NULL) { /* Translation disabled or invalid. */ iotlb.addr_mask =3D 0; --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 09 Jul 2026 19:57:29 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Tao Tang Subject: [PULL 35/40] hw/pci/pcie_doe: Check mailbox length for overflows Date: Fri, 10 Jul 2026 12:55:20 +1000 Message-ID: <20260710025525.1704417-36-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652434649158500 From: Alistair Francis It was possible that a guest could overflow the `doe_cap->write_mbox` buffer by writing more then PCI_DOE_DW_SIZE_MAX dwords. `doe_cap->write_mbox_len` would continue to increment and there were no bounds checks on the length when offsetting into doe_cap->write_mbox. This patch adds a check and reports a guest error if we would overflow. On an overflow we also silenty discard the entire object as instructed to do in the PCIe spec when the length specified in the header (up to PCI_DOE_DW_SIZE_MAX dwords) doesn't match the length of the object. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3679 Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Tao Tang Message-ID: <20260707020750.788960-1-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- hw/pci/pcie_doe.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/hw/pci/pcie_doe.c b/hw/pci/pcie_doe.c index 2210f86968..1bc2b45781 100644 --- a/hw/pci/pcie_doe.c +++ b/hw/pci/pcie_doe.c @@ -78,14 +78,21 @@ static bool pcie_doe_discovery(DOECap *doe_cap) return true; } =20 +static void pcie_doe_reset_write_mbox(DOECap *st) +{ + st->write_mbox_len =3D 0; + + memset(st->write_mbox, 0, PCI_DOE_DW_SIZE_MAX * DWORD_BYTE); +} + static void pcie_doe_reset_mbox(DOECap *st) { st->read_mbox_idx =3D 0; st->read_mbox_len =3D 0; - st->write_mbox_len =3D 0; =20 memset(st->read_mbox, 0, PCI_DOE_DW_SIZE_MAX * DWORD_BYTE); - memset(st->write_mbox, 0, PCI_DOE_DW_SIZE_MAX * DWORD_BYTE); + + pcie_doe_reset_write_mbox(st); } =20 void pcie_doe_init(PCIDevice *dev, DOECap *doe_cap, uint16_t offset, @@ -356,8 +363,20 @@ void pcie_doe_write_config(DOECap *doe_cap, if (size !=3D DWORD_BYTE) { return; } - doe_cap->write_mbox[doe_cap->write_mbox_len] =3D val; - doe_cap->write_mbox_len++; + if (doe_cap->write_mbox_len < PCI_DOE_DW_SIZE_MAX) { + doe_cap->write_mbox[doe_cap->write_mbox_len] =3D val; + doe_cap->write_mbox_len++; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "Mailbox write length (%d) overflow\n", + doe_cap->write_mbox_len); + /* + * Too much data has been written, it can't + * "match the Length indicated in DOE Data Object Header 2" + * so we drop the entire object. + */ + pcie_doe_reset_write_mbox(doe_cap); + } break; case PCI_EXP_DOE_CAP: /* fallthrough */ --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 09 Jul 2026 19:57:32 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Wang Yechao , Alistair Francis Subject: [PULL 36/40] target/riscv/kvm: add extensions after v7.1-rc4 update Date: Fri, 10 Jul 2026 12:55:21 +1000 Message-ID: <20260710025525.1704417-37-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652385938158500 Content-Type: text/plain; charset="utf-8" From: Wang Yechao Expose zilsd, zclsd and zalasr. Signed-off-by: Wang Yechao Acked-by: Alistair Francis Message-ID: <20260707072610.403595-1-wang.yechao255@zte.com.cn> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index dfcd6e3c77..495cb42dc8 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -303,10 +303,13 @@ static KVMCPUConfig kvm_multi_ext_cfgs[] =3D { KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPA= USE), KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), + KVM_EXT_CFG("zilsd", ext_zilsd, KVM_RISCV_ISA_EXT_ZILSD), KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP), KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP), + KVM_EXT_CFG("zclsd", ext_zclsd, KVM_RISCV_ISA_EXT_ZCLSD), KVM_EXT_CFG("zabha", ext_zabha, KVM_RISCV_ISA_EXT_ZABHA), KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), + KVM_EXT_CFG("zalasr", ext_zalasr, KVM_RISCV_ISA_EXT_ZALASR), KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS), KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), KVM_EXT_CFG("zfbfmin", ext_zfbfmin, KVM_RISCV_ISA_EXT_ZFBFMIN), --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 09 Jul 2026 19:57:35 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Bin Meng , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 37/40] gitlab-ci: Remove job building OpenSBI firmware binaries Date: Fri, 10 Jul 2026 12:55:22 +1000 Message-ID: <20260710025525.1704417-38-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=alistair23@gmail.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652325864158500 From: Bin Meng The OpenSBI firmware build job follows the same pattern as the EDK2 job [1] that was removed earlier [2]: it exists to produce firmware binaries from CI artifacts, but those outputs are not consumed by the tree. Remove the job definition and its project include to avoid maintaining bitrotting container and firmware build logic. [1] 71920809ceab ("gitlab-ci.yml: Add jobs to build EDK2 firmware binaries") [2] 690ceb71936f ("gitlab-ci: Remove job building EDK2 firmware binaries") Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260706161716.29488-1-bin.meng@processmission.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 2 - .gitlab-ci.d/opensbi.yml | 88 --------------------------------- .gitlab-ci.d/opensbi/Dockerfile | 34 ------------- .gitlab-ci.d/qemu-project.yml | 1 - 4 files changed, 125 deletions(-) delete mode 100644 .gitlab-ci.d/opensbi.yml delete mode 100644 .gitlab-ci.d/opensbi/Dockerfile diff --git a/MAINTAINERS b/MAINTAINERS index 6171cc7494..e25df9493c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4127,8 +4127,6 @@ R: Daniel Henrique Barboza L: qemu-riscv@nongnu.org S: Supported F: pc-bios/opensbi-* -F: .gitlab-ci.d/opensbi.yml -F: .gitlab-ci.d/opensbi/ =20 Clock framework M: Luc Michel diff --git a/.gitlab-ci.d/opensbi.yml b/.gitlab-ci.d/opensbi.yml deleted file mode 100644 index 42f137d624..0000000000 --- a/.gitlab-ci.d/opensbi.yml +++ /dev/null @@ -1,88 +0,0 @@ -# All jobs needing docker-opensbi must use the same rules it uses. -.opensbi_job_rules: - rules: - # Forks don't get pipelines unless QEMU_CI=3D1 or QEMU_CI=3D2 is set - - if: '$QEMU_CI !=3D "1" && $QEMU_CI !=3D "2" && $CI_PROJECT_NAMESPACE= !=3D "qemu-project"' - when: never - - # In forks, if QEMU_CI=3D1 is set, then create manual job - # if any files affecting the build output are touched - - if: '$QEMU_CI =3D=3D "1" && $CI_PROJECT_NAMESPACE !=3D "qemu-project= "' - changes: - - .gitlab-ci.d/opensbi.yml - - .gitlab-ci.d/opensbi/Dockerfile - - roms/opensbi/* - when: manual - - # In forks, if QEMU_CI=3D1 is set, then create manual job - # if the branch/tag starts with 'opensbi' - - if: '$QEMU_CI =3D=3D "1" && $CI_PROJECT_NAMESPACE !=3D "qemu-project= " && $CI_COMMIT_REF_NAME =3D~ /^opensbi/' - when: manual - - # In forks, if QEMU_CI=3D1 is set, then create manual job - # if the last commit msg contains 'OpenSBI' (case insensitive) - - if: '$QEMU_CI =3D=3D "1" && $CI_PROJECT_NAMESPACE !=3D "qemu-project= " && $CI_COMMIT_MESSAGE =3D~ /opensbi/i' - when: manual - - # Scheduled runs on mainline don't get pipelines except for the specia= l Coverity job - - if: '$CI_PROJECT_NAMESPACE =3D=3D $QEMU_CI_UPSTREAM && $CI_PIPELINE_= SOURCE =3D=3D "schedule"' - when: never - - # Run if any files affecting the build output are touched - - changes: - - .gitlab-ci.d/opensbi.yml - - .gitlab-ci.d/opensbi/Dockerfile - - roms/opensbi/* - when: on_success - - # Run if the branch/tag starts with 'opensbi' - - if: '$CI_COMMIT_REF_NAME =3D~ /^opensbi/' - when: on_success - - # Run if the last commit msg contains 'OpenSBI' (case insensitive) - - if: '$CI_COMMIT_MESSAGE =3D~ /opensbi/i' - when: on_success - -docker-opensbi: - extends: .opensbi_job_rules - stage: containers - image: docker:latest - services: - - docker:dind - variables: - GIT_DEPTH: 3 - IMAGE_TAG: $CI_REGISTRY_IMAGE:opensbi-cross-build - before_script: - - docker login -u $CI_REGISTRY_USER -p $CI_REGISTRY_PASSWORD $CI_REGIS= TRY - - until docker info; do sleep 1; done - script: - - docker pull $IMAGE_TAG || true - - docker build --cache-from $IMAGE_TAG --tag $CI_REGISTRY_IMAGE:$CI_CO= MMIT_SHA - --tag $IMAGE_TAG .gitlab-ci.d/o= pensbi - - docker push $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA - - docker push $IMAGE_TAG - -build-opensbi: - extends: .opensbi_job_rules - stage: build - needs: ['docker-opensbi'] - artifacts: - when: on_success - paths: # 'artifacts.zip' will contains the following files: - - pc-bios/opensbi-riscv32-generic-fw_dynamic.bin - - pc-bios/opensbi-riscv64-generic-fw_dynamic.bin - - opensbi32-generic-stdout.log - - opensbi32-generic-stderr.log - - opensbi64-generic-stdout.log - - opensbi64-generic-stderr.log - image: $CI_REGISTRY_IMAGE:opensbi-cross-build - variables: - GIT_DEPTH: 3 - script: # Clone the required submodules and build OpenSBI - - git submodule update --init roms/opensbi - - export JOBS=3D$(($(getconf _NPROCESSORS_ONLN) + 1)) - - echo "=3D=3D=3D Using ${JOBS} simultaneous jobs =3D=3D=3D" - - make -j${JOBS} -C roms/opensbi clean - - make -j${JOBS} -C roms opensbi32-generic 2>&1 1>opensbi32-generic-st= dout.log | tee -a opensbi32-generic-stderr.log >&2 - - make -j${JOBS} -C roms/opensbi clean - - make -j${JOBS} -C roms opensbi64-generic 2>&1 1>opensbi64-generic-st= dout.log | tee -a opensbi64-generic-stderr.log >&2 diff --git a/.gitlab-ci.d/opensbi/Dockerfile b/.gitlab-ci.d/opensbi/Dockerf= ile deleted file mode 100644 index 5ccf4151f4..0000000000 --- a/.gitlab-ci.d/opensbi/Dockerfile +++ /dev/null @@ -1,34 +0,0 @@ -# -# Docker image to cross-compile OpenSBI firmware binaries -# -FROM ubuntu:18.04 - -MAINTAINER Bin Meng - -# Install packages required to build OpenSBI -RUN apt update \ - && \ - \ - DEBIAN_FRONTEND=3Dnoninteractive \ - apt install --assume-yes --no-install-recommends \ - build-essential \ - ca-certificates \ - git \ - make \ - python3 \ - wget \ - && \ - \ - rm -rf /var/lib/apt/lists/* - -# Manually install the kernel.org "Crosstool" based toolchains for gcc-8.3 -RUN wget -O - \ - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/8= .3.0/x86_64-gcc-8.3.0-nolibc-riscv32-linux.tar.xz \ - | tar -C /opt -xJ -RUN wget -O - \ - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/8= .3.0/x86_64-gcc-8.3.0-nolibc-riscv64-linux.tar.xz \ - | tar -C /opt -xJ - -# Export the toolchains to the system path -ENV PATH=3D"/opt/gcc-8.3.0-nolibc/riscv32-linux/bin:${PATH}" -ENV PATH=3D"/opt/gcc-8.3.0-nolibc/riscv64-linux/bin:${PATH}" diff --git a/.gitlab-ci.d/qemu-project.yml b/.gitlab-ci.d/qemu-project.yml index 104a147b2d..72d02bc65b 100644 --- a/.gitlab-ci.d/qemu-project.yml +++ b/.gitlab-ci.d/qemu-project.yml @@ -11,7 +11,6 @@ default: include: - local: '/.gitlab-ci.d/base.yml' - local: '/.gitlab-ci.d/stages.yml' - - local: '/.gitlab-ci.d/opensbi.yml' - local: '/.gitlab-ci.d/containers.yml' - local: '/.gitlab-ci.d/crossbuilds.yml' - local: '/.gitlab-ci.d/buildtest.yml' --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 09 Jul 2026 19:57:38 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Heinrich Schuchardt , Alistair Francis Subject: [PULL 38/40] tests: allow differences in SPCR Date: Fri, 10 Jul 2026 12:55:23 +1000 Message-ID: <20260710025525.1704417-39-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652315821158500 Content-Type: text/plain; charset="utf-8" From: Heinrich Schuchardt For easier bisection add the SPCR table to bios-tables-test-allowed-diff.h. Signed-off-by: Heinrich Schuchardt Acked-by: Alistair Francis Message-ID: <20260705063147.199732-2-heinrich.schuchardt@canonical.com> Signed-off-by: Alistair Francis --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..2c7086d9de 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/loongarch64/virt/SPCR", +"tests/data/acpi/riscv64/virt/SPCR", --=20 2.54.0 From nobody Sun Jul 12 00:42:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Thu, 09 Jul 2026 19:57:41 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Heinrich Schuchardt , Alistair Francis Subject: [PULL 39/40] hw/acpi: correct field sequence in SPCR table Date: Fri, 10 Jul 2026 12:55:24 +1000 Message-ID: <20260710025525.1704417-40-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=alistair23@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652408084158501 Content-Type: text/plain; charset="utf-8" From: Heinrich Schuchardt On LoongArch and RISC-V invalid SPCR tables are created: Terminal Type : 00 Language : 03 The correct values are: Terminal Type : 03 Language : 00 This is due to commit 7dd0b070fa09 ("hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location") that swapped the fields. See the specification of the table in https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/serial-p= ort-console-redirection-table This page shows version 1.10. But the sequence of the fields was not changed since version 1.0. Our LoongArch and ARM code uses version 1.07 of the specification. Our RISC-V code uses version 1.10 of the specification. Fixes: 7dd0b070fa09 ("hw/arm/virt-acpi-build.c: Migrate SPCR creation to co= mmon location") Origin: https://lore.kernel.org/qemu-devel/20260326121947.51200-1-heinrich.= schuchardt@canonical.com/T/#u Bug-Ubuntu: https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/2146419 Signed-off-by: Heinrich Schuchardt Reviewed-by: Alistair Francis Message-ID: <20260705063147.199732-3-heinrich.schuchardt@canonical.com> Signed-off-by: Alistair Francis --- hw/acpi/aml-build.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 9b3cdd3781..990abc64cd 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2144,10 +2144,10 @@ void build_spcr(GArray *table_data, BIOSLinker *lin= ker, build_append_int_noprefix(table_data, f->stop_bits, 1); /* Flow Control */ build_append_int_noprefix(table_data, f->flow_control, 1); - /* Language */ - build_append_int_noprefix(table_data, f->language, 1); /* Terminal Type */ build_append_int_noprefix(table_data, f->terminal_type, 1); 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Thu, 09 Jul 2026 19:57:43 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: Heinrich Schuchardt , Alistair Francis Subject: [PULL 40/40] tests: update SPCR loongarch64 and riscv64 test data Date: Fri, 10 Jul 2026 12:55:25 +1000 Message-ID: <20260710025525.1704417-41-alistair.francis@wdc.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260710025525.1704417-1-alistair.francis@wdc.com> References: <20260710025525.1704417-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=alistair23@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783652394007158501 Content-Type: text/plain; charset="utf-8" From: Heinrich Schuchardt On LoongArch and RISC-V the SPCR test data contained: Terminal Type : 00 Language : 03 The corrected values are: Terminal Type : 03 Language : 00 See the specification of the table in https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/serial-p= ort-console-redirection-table The ACPI table data was rebuilt with tests/data/acpi/rebuild-expected-aml.sh. Remove SPCR expections from tests/qtest/bios-tables-test-allowed-diff.h. Signed-off-by: Heinrich Schuchardt Acked-by: Alistair Francis Message-ID: <20260705063147.199732-4-heinrich.schuchardt@canonical.com> Signed-off-by: Alistair Francis --- tests/qtest/bios-tables-test-allowed-diff.h | 2 -- tests/data/acpi/loongarch64/virt/SPCR | Bin 80 -> 80 bytes tests/data/acpi/riscv64/virt/SPCR | Bin 90 -> 90 bytes 3 files changed, 2 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 2c7086d9de..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/loongarch64/virt/SPCR", -"tests/data/acpi/riscv64/virt/SPCR", diff --git a/tests/data/acpi/loongarch64/virt/SPCR b/tests/data/acpi/loonga= rch64/virt/SPCR index 3cc9bbcfb8..7bb819cd0d 100644 Binary files a/tests/data/acpi/loongarch64/virt/SPCR and b/tests/data/acpi/= loongarch64/virt/SPCR differ diff --git a/tests/data/acpi/riscv64/virt/SPCR b/tests/data/acpi/riscv64/vi= rt/SPCR index 09617f8793..59d2c8f7f2 100644 Binary files a/tests/data/acpi/riscv64/virt/SPCR and b/tests/data/acpi/risc= v64/virt/SPCR differ --=20 2.54.0