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Bae" To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, berrange@redhat.com, seanjc@google.com, chang.seok.bae@intel.com, Zhao Liu Subject: [PATCH] i386/cpu: Remove AMX-TF32 CPUID bit Date: Wed, 8 Jul 2026 21:03:26 +0000 Message-ID: <20260708210326.402054-1-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=chang.seok.bae@intel.com; helo=mgamail.intel.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) AC_FROM_MANY_DOTS=2.499, BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 08 Jul 2026 18:03:56 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1783548294519158500 Content-Type: text/plain; charset="utf-8" A recent revision of the Intel document [1] removed AMX-TF32, confirming that the feature will not be implemented in future processors. Remove the feature bit definition and its enumeration from the Diamond Rapids CPU model. [1] Intel Architecture Instruction Set Extensions and Future Features (Rev.062) Cc: Zhao Liu Signed-off-by: Chang S. Bae Reviewed-by: Zhao Liu --- KVM side posting:=20 https://lore.kernel.org/all/20260708210118.402005-1-chang.seok.bae@intel.com --- target/i386/cpu.c | 5 ++--- target/i386/cpu.h | 2 -- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5805d33ab92d..bde501ad8f7b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1319,7 +1319,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "amx-int8-alias", "amx-bf16-alias", "amx-complex-alias", "amx-= fp16-alias", - "amx-fp8", NULL, "amx-tf32", "amx-avx512", + "amx-fp8", NULL, NULL, "amx-avx512", "amx-movrs", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -5726,8 +5726,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { CPUID_1E_1_EAX_AMX_INT8_ALIAS | CPUID_1E_1_EAX_AMX_BF16_ALIAS | CPUID_1E_1_EAX_AMX_COMPLEX_ALIAS | CPUID_1E_1_EAX_AMX_FP16_ALIAS | CPUID_1E_1_EAX_AMX_FP8 | - CPUID_1E_1_EAX_AMX_TF32 | CPUID_1E_1_EAX_AMX_AVX512 | - CPUID_1E_1_EAX_AMX_MOVRS, + CPUID_1E_1_EAX_AMX_AVX512 | CPUID_1E_1_EAX_AMX_MOVRS, .features[FEAT_29_0_EBX] =3D CPUID_29_0_EBX_APX_NCI_NDD_NF, /* * Though this bit will be set by avx_version=3D2, it's better to diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e6a197602d87..8354c0753f0d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1111,8 +1111,6 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define CPUID_1E_1_EAX_AMX_FP16_ALIAS (1U << 3) /* AMX_FP8 instruction */ #define CPUID_1E_1_EAX_AMX_FP8 (1U << 4) -/* AMX_TF32 instruction */ -#define CPUID_1E_1_EAX_AMX_TF32 (1U << 6) /* AMX_AVX512 instruction */ #define CPUID_1E_1_EAX_AMX_AVX512 (1U << 7) /* AMX_MOVRS instruction */ --=20 2.53.0