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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47a9e4d780csm43386298f8f.11.2026.07.08.05.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 05:10:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783512614; x=1784117414; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hl3euWWqIvIwDDEEHL5NykZRL5Wv/p/3R5Er6oJzFyY=; b=oxqyH6qAS2ZBN4bxpf1egAO2sWujdFC5Ew9c9KPs2vaR+4NBYk3qTNnpLsdTup2a9y Zko+9sPm201vxViEysLCOamr9S4zMeVUBuA6B5bNsNS1ISToHYaKRjB5ZbdOYCRmK1TV EpsLwsNzH7djzjfashcdO/3GLyEcsOufo5UoP7e/2bGY0VKhhYUHDwJBQFbMlzYWddus GPIH7keZwELd58mM7xNn1e/3pU9tOOoSGmZczAkB8VEpo+6KPOiRNyme5piM9VrVciE2 LREoKmFvYu+2cJp2ftW9PKeOHt3FrB7YxxNTFu6pdzNw4rJZSJOEyDhzi2iAXQFTR7KZ YtXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783512614; x=1784117414; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Hl3euWWqIvIwDDEEHL5NykZRL5Wv/p/3R5Er6oJzFyY=; b=ctHOZ5pEMVJuhF4NrmRntE8LQoDOC1K6Fd9PWEwH/w/46kaGpBa6JANZKbEnGxm+0s /cOGc7UhtHf8Xikxtw0UEeNm0bG+DcAbv69akHeXHAFtDuv4cPfjNNb52YTISN+j9MII KH6F9NxdyZ7WgEy7Zn0bfppGSSWRQPQiWVYWUwFqfIulvq+8Gpzdhc9Xi3rXHK3Hd7qb 4GfnpRGtOZkk5CRvJA3WeOJ5HJOrV5f5VVH59GX5nXJyAUaKG+Gu344+XahBonNy5l+i kFAGEddK4h6NFKZFsEjK1VBMvz684DKXr/d1cURUncYxfrzE+j1280MGoyKQuKmevzBB 2GSw== X-Gm-Message-State: AOJu0YzGGCm0KMkMWexRtvlAgEXvgwoju3lMS2toWhnEmG01FHoqA5bJ Gn6lfoirLa5fJ157qAb6xq5pMf1tUmMQTlEq1myJ7PdCrMhMlSYUAxXL6R9fwy0yIhp/S8jPErc 5VPx9Vmc5o7eV X-Gm-Gg: AfdE7clpS2bJnm8jG04Z3z0+IbaBvQfYdIANr8ww/Uf61Q5PKEJybbDDqDychWeDohF aLH/vbFkHW8umXg96q69jZxpHwInG3usi+PWRieSPu4kMOs4U3D2olHv4/dLQWHDqsArJ2KlmhB B3kNdHPLmLyu5dqcf4Mhzqw1XTu/EUSmvtnH7INi8FtZB/VGTytBr/+RCTW++ubpsGQ/Z3ZE+VK SrHkLgxaPGFwEPaTLYNlWrKWThr/RTYI49mrx9iCqzc0PzeckaQguKjZhr9yhyVJsbci9BcS4DR ZvDGhuToOXHcNvW+OFBMMtCDinAO/x8brP5GXFYpVVKihKx8ag1g/e/BYiPjBvXFrAol+bwYkAy 1CK501pQhGjDRmxfxlNLKmU+uqNwF9x1tQq7b0/KR4xP/XPrIvhcVlkxcKczwTB8W7XlCkdPCZr sfq78CI4XCwssLCk3dxOiPWa/mU+C4+bhrcNllnf3+XnuYf1bta8VtIET0lIFw4h/5kKWj2phyf h6w99yni77IT1ZiA1A+8Y1cypCMFIh/ X-Received: by 2002:a05:600c:a219:b0:493:df58:42b6 with SMTP id 5b1f17b1804b1-493e68f6840mr12477655e9.36.1783512614359; Wed, 08 Jul 2026 05:10:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, "Michael S. Tsirkin" , Mohamed Mediouni , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Isaku Yamahata , Sean Christopherson Subject: [PATCH 1/3] hw/pci-host/q35.c: Always initialize smram-region even if SMM disabled Date: Wed, 8 Jul 2026 13:10:09 +0100 Message-ID: <20260708121011.1653365-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708121011.1653365-1-peter.maydell@linaro.org> References: <20260708121011.1653365-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:31::2; envelope-from=peter.maydell@linaro.org; helo=mail-wm2-x02.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783512644339158500 Content-Type: text/plain; charset="utf-8" The MCHPCIState::smram_region looks like it ought to be SMM-specific, but it isn't, because its behaviour is "alias the PCI address space into system memory at the SMRAM_C_BASE offset", and it must be enabled for "hide SMRAM", and disabled for "show SMRAM". If the SMRAM regions are disabled, we want "hide SMRAM", so we need to initialize and place this MR. Do this in the minimal way, by moving the "bail out of realize if has_smm_ranges is false" check down below the initialization code. This fixes a bug where disabling SMM causes the VGA screen to be blank during seabios output, until the OS graphics driver is initialized. This is most obvious for accelerators which have no SMM support (e.g. NVMM, HVF, WHPX) as there smm=3Doff is the default, but you can also see it on KVM and TCG if you explicitly pass smm=3Doff: qemu-system-x86_64 -machine q35,accel=3Dkvm,smm=3Doff The early return is bug-prone, so we can refactor the code to clean it up, but this is the minimal bug fix for backports, and is what Debian used to work around this: https://salsa.debian.org/qemu-team/qemu/-/commit/6e0766f0f897dc2b75ab87dd5= 9da0d4639bb37ee Another proposed fix for this: https://patchew.org/QEMU/20260413170407.57574-1-mohamed@unpredictable.fr/ also moves an early return in mch_update-smram() and tweaks mch_update_smram() accordingly. This shouldn't be necessary, because in the no-SMM case smram_region should always be enabled and we don't want to allow the guest to make it disabled. NetBSD bug: https://gnats.NetBSD.org/59721 Cc: qemu-stable@nongnu.org Fixes: b07bf7b7 ("q35: Introduce smm_ranges property for q35-pci-host") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2608 Signed-off-by: Peter Maydell --- hw/pci-host/q35.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 4784b8f59b..47e726c41d 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -596,11 +596,14 @@ static void mch_realize(PCIDevice *d, Error **errp) PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } =20 - if (!mch->has_smm_ranges) { - return; - } - - /* if *disabled* show SMRAM to all CPUs */ + /* + * This memory region looks like it's SMM specific, but it is not. + * It's an alias that makes the pci_address_space appear in system + * memory at the SMRAM_C_BASE address. The alias is enabled when the + * CPU should not see SMRAM, and *disabled* when the low SMRAM should = be + * visible. So for non-SMM configs we need to create the alias, and + * leave it permanently enabled. + */ memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-regio= n", mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM= _C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); @@ -608,6 +611,10 @@ static void mch_realize(PCIDevice *d, Error **errp) &mch->smram_region, 1); memory_region_set_enabled(&mch->smram_region, true); =20 + if (!mch->has_smm_ranges) { + return; + } + memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-op= en-high", mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); --=20 2.43.0 From nobody Sun Jul 26 10:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783512639; cv=none; d=zohomail.com; s=zohoarc; b=itygg1L85Q+Ko+lyN2Pt8lhIPtsWl5yfOZ3d+HgLxrTEE6C3wi9J9epSju+eB7Rmx1R70ZYMBcUWusNh9MISQRl0tJnPn/Cef9HFqfXsZiZkWSRpT1gVJZ+//XQRB4P/zSKM6nUtQxAVU+NbcFl84JB72a5QmEYwIL3f7Kifp4s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783512639; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3xzKir4eMZg0At6RdgLttLphr54QRaQbGQkt+BPQ2AY=; b=Q3bjkWcVCJABQFPuQiL6LCrwHlbyDwDE6c7HZNBzW+uXVPAtJma25P7gRJaKLjR59bMOrLZ0tPbYSaqYMF6LgeR3Ui9mpj4Z1zyujuCxCYl9S3na3oZo8a1cKbAbiVZVQz7NpeD4vM7dKliCTLlrrJp8+aAOzxzTjoucjll9Nbc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17835126390491004.9528461375862; Wed, 8 Jul 2026 05:10:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1whR6c-0004Y8-G7; Wed, 08 Jul 2026 08:10:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1whR6Z-0004Vm-RG for qemu-devel@nongnu.org; Wed, 08 Jul 2026 08:10:19 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1whR6X-0005pW-3B for qemu-devel@nongnu.org; Wed, 08 Jul 2026 08:10:19 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-475cb71a4ebso566527f8f.0 for ; Wed, 08 Jul 2026 05:10:16 -0700 (PDT) Received: from lanath.. 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Tsirkin" , Mohamed Mediouni , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Isaku Yamahata , Sean Christopherson Subject: [PATCH 2/3] hw/pci-host/q35.c: Factor out creation of SMRAM MRs Date: Wed, 8 Jul 2026 13:10:10 +0100 Message-ID: <20260708121011.1653365-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708121011.1653365-1-peter.maydell@linaro.org> References: <20260708121011.1653365-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783512640507158500 Content-Type: text/plain; charset="utf-8" mch_realize has a large section that deals with initializing the SMRAM-specific MemoryRegions. Currently we do an early return from the realize function if mch->has_smm_ranges is false, but this has the potential for bugs if somebody adds new code at the end of the function that isn't SMM-specific. Pull the MR init code out into its own function, so we can do the smm-ranges specific handling in the realize function in a more obvious way. This commit shouldn't change behaviour at all. Signed-off-by: Peter Maydell Reviewed-by: Michael Tokarev --- hw/pci-host/q35.c | 91 ++++++++++++++++++++++++----------------------- 1 file changed, 47 insertions(+), 44 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 47e726c41d..e42b84b978 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -572,49 +572,9 @@ static void mch_reset(DeviceState *qdev) mch_update(mch); } =20 -static void mch_realize(PCIDevice *d, Error **errp) +static void mch_init_smram_regions(MCHPCIState *mch) { - int i; - MCHPCIState *mch =3D MCH_PCI_DEVICE(d); - - if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { - error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, - mch->ext_tseg_mbytes); - return; - } - - /* setup pci memory mapping */ - pc_pci_as_mapping_init(mch->system_memory, mch->pci_address_space); - - /* PAM */ - init_pam(&mch->pam_regions[0], OBJECT(mch), mch->ram_memory, - mch->system_memory, mch->pci_address_space, - PAM_BIOS_BASE, PAM_BIOS_SIZE); - for (i =3D 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) { - init_pam(&mch->pam_regions[i + 1], OBJECT(mch), mch->ram_memory, - mch->system_memory, mch->pci_address_space, - PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); - } - - /* - * This memory region looks like it's SMM specific, but it is not. - * It's an alias that makes the pci_address_space appear in system - * memory at the SMRAM_C_BASE address. The alias is enabled when the - * CPU should not see SMRAM, and *disabled* when the low SMRAM should = be - * visible. So for non-SMM configs we need to create the alias, and - * leave it permanently enabled. - */ - memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-regio= n", - mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM= _C_BASE, - MCH_HOST_BRIDGE_SMRAM_C_SIZE); - memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDG= E_SMRAM_C_BASE, - &mch->smram_region, 1); - memory_region_set_enabled(&mch->smram_region, true); - - if (!mch->has_smm_ranges) { - return; - } - + /* Initialize all the SMRAM specific MemoryRegions */ memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-op= en-high", mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); @@ -670,9 +630,52 @@ static void mch_realize(PCIDevice *d, Error **errp) memory_region_set_enabled(&mch->smbase_window, false); memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, &mch->smbase_window); +} =20 - object_property_add_const_link(qdev_get_machine(), "smram", - OBJECT(&mch->smram)); +static void mch_realize(PCIDevice *d, Error **errp) +{ + int i; + MCHPCIState *mch =3D MCH_PCI_DEVICE(d); + + if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { + error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, + mch->ext_tseg_mbytes); + return; + } + + /* setup pci memory mapping */ + pc_pci_as_mapping_init(mch->system_memory, mch->pci_address_space); + + /* PAM */ + init_pam(&mch->pam_regions[0], OBJECT(mch), mch->ram_memory, + mch->system_memory, mch->pci_address_space, + PAM_BIOS_BASE, PAM_BIOS_SIZE); + for (i =3D 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) { + init_pam(&mch->pam_regions[i + 1], OBJECT(mch), mch->ram_memory, + mch->system_memory, mch->pci_address_space, + PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); + } + + /* + * This memory region looks like it's SMM specific, but it is not. + * It's an alias that makes the pci_address_space appear in system + * memory at the SMRAM_C_BASE address. The alias is enabled when the + * CPU should not see SMRAM, and *disabled* when the low SMRAM should = be + * visible. So for non-SMM configs we need to create the alias, and + * leave it permanently enabled. + */ + memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-regio= n", + mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM= _C_BASE, + MCH_HOST_BRIDGE_SMRAM_C_SIZE); + memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDG= E_SMRAM_C_BASE, + &mch->smram_region, 1); + memory_region_set_enabled(&mch->smram_region, true); + + if (mch->has_smm_ranges) { + mch_init_smram_regions(mch); + object_property_add_const_link(qdev_get_machine(), "smram", + OBJECT(&mch->smram)); + } } =20 static const Property mch_props[] =3D { --=20 2.43.0 From nobody Sun Jul 26 10:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783512626; cv=none; d=zohomail.com; s=zohoarc; b=c9fwo15CwgaUOxYIBFEFEm4j1R6eCdJttSI7olhpa6Ys8pTyEx6oJxpHSzO+GGWbfoPSnJ9pei6S2CeZkVq1GGamTJQ3HMRZ582dwXhenH+0eToyHDTaxzpLSA6KZClBlt/hTaDWwZx0lHdYrRcfTLvxD51AjNB8Ii9IHHbO5o4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783512626; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=H3syJG05K/noDigcZ23muuOk703OZjKc29wGEoKgFAo=; b=amea1SGAJpi6z1IVTB5oY5I4FWpSf3FAcpEPVIAg+ZKa7Db/vX47v85u8x6XPCvO/vo8AQ7FbjKjSBjomnP+CcIHmZrD/Wa7v0ZRrjenL20KC4T0pmjAH0pWkLjJ2/rdnIGQtkFQwlPA/wXNULwpGknykbG/dqsRFfFesfBqo+E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783512626839956.0153178048973; Wed, 8 Jul 2026 05:10:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1whR6c-0004YJ-VB; Wed, 08 Jul 2026 08:10:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1whR6a-0004W7-3G for qemu-devel@nongnu.org; Wed, 08 Jul 2026 08:10:20 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1whR6Y-0005pf-A7 for qemu-devel@nongnu.org; Wed, 08 Jul 2026 08:10:19 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-493ba701891so4230035e9.3 for ; Wed, 08 Jul 2026 05:10:17 -0700 (PDT) Received: from lanath.. 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Tsirkin" , Mohamed Mediouni , Michael Tokarev , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Isaku Yamahata , Sean Christopherson Subject: [PATCH 3/3] hw/pci-host/q35.c: Avoid early return in mch_write_config() Date: Wed, 8 Jul 2026 13:10:11 +0100 Message-ID: <20260708121011.1653365-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708121011.1653365-1-peter.maydell@linaro.org> References: <20260708121011.1653365-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783512628407158500 Content-Type: text/plain; charset="utf-8" In mch_write_config() we return early if has_smm_ranges is false. This is slightly bug-prone because it leaves the door open to somebody later adding non-SMM-specific code at the bottom of the function. This case isn't as bad as the one in realize, because the function is a lot shorter. But putting the handling of the three SMM specific ranges into an if() rather than having an early return seems better. Signed-off-by: Peter Maydell Reviewed-by: Michael Tokarev --- hw/pci-host/q35.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index e42b84b978..f4556ad03a 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -485,22 +485,20 @@ static void mch_write_config(PCIDevice *d, mch_update_pciexbar(mch); } =20 - if (!mch->has_smm_ranges) { - return; - } + if (mch->has_smm_ranges) { + if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, + MCH_HOST_BRIDGE_SMRAM_SIZE)) { + mch_update_smram(mch); + } =20 - if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, - MCH_HOST_BRIDGE_SMRAM_SIZE)) { - mch_update_smram(mch); - } + if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { + mch_update_ext_tseg_mbytes(mch); + } =20 - if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, - MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { - mch_update_ext_tseg_mbytes(mch); - } - - if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { - mch_update_smbase_smram(mch); + if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { + mch_update_smbase_smram(mch); + } } } =20 --=20 2.43.0