From nobody Sun Jul 26 11:08:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783342403831398.13266699735607; Mon, 6 Jul 2026 05:53:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgio1-0001CN-1L; Mon, 06 Jul 2026 08:52:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQX-0002tH-UC for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:34 -0400 Received: from [115.124.28.220] (helo=out28-220.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQR-0005Ro-7D for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:33 -0400 Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iEEStoh_1783317363 cluster:ay29) by smtp.aliyun-inc.com; Mon, 06 Jul 2026 13:56:03 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436259|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0304456-0.000448784-0.969106; FP=16428971096157982427|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033068005250; MF=zhang_wei@open-hieco.net; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.iEEStoh_1783317363; From: zhang_wei@open-hieco.net To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, "Michael S . Tsirkin" , Paolo Bonzini , Marcelo Tosatti , Tina Zhang Subject: [PATCH v1 1/9] target/i386: Sync AMD CPUID aliases for Hygon Date: Mon, 6 Jul 2026 13:55:22 +0800 Message-ID: <20260706055530.1752094-2-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260706055530.1752094-1-zhang_wei@open-hieco.net> References: <20260706055530.1752094-1-zhang_wei@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.220 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.220; envelope-from=zhang_wei@open-hieco.net; helo=out28-220.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 06 Jul 2026 08:51:50 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1783342405142158500 Content-Type: text/plain; charset="utf-8" From: Tina Zhang AMD defines CPUID[0x80000001].EDX bits as aliases for a subset of CPUID[1].EDX. QEMU currently synchronizes those aliases only when the guest CPU vendor is AuthenticAMD. Hygon Dhyana uses the HygonGenuine vendor string, but implements the same AMD-compatible extended CPUID feature aliases. This can leave QEMU advertising a feature in CPUID[1].EDX while the matching extended alias in CPUID[0x80000001].EDX stays clear, for example MMX. Windows guests with Hyper-V enabled can fail to start the Hyper-V hypervisor when exposed to that inconsistent CPUID state. Apply the alias synchronization to Hygon CPUs as well. Gate the new behavior with x-hygon-vendor-abi-fixes and disable it for pc-11.0 and older machine types, because the CPUID result is guest-visible ABI and must remain migration-compatible. Add qtest coverage for the Dhyana model, including the Hygon vendor ABI fixes property. Signed-off-by: Tina Zhang --- hw/i386/pc.c | 4 +- target/i386/cpu.c | 23 +++++++-- target/i386/cpu.h | 12 +++++ tests/qtest/test-x86-cpuid-compat.c | 76 +++++++++++++++++++++++++++++ 4 files changed, 111 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 73a625327c..11dade642f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -73,7 +73,9 @@ #include "hw/xen/xen-bus.h" #endif =20 -GlobalProperty pc_compat_11_0[] =3D {}; +GlobalProperty pc_compat_11_0[] =3D { + { TYPE_X86_CPU, "x-hygon-vendor-abi-fixes", "false" }, +}; const size_t pc_compat_11_0_len =3D G_N_ELEMENTS(pc_compat_11_0); =20 GlobalProperty pc_compat_10_2[] =3D {}; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5805d33ab9..32b8bc9ebd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8608,6 +8608,20 @@ uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) } } =20 +/* + * AMD CPUs define CPUID[0x80000001].EDX aliases for selected CPUID[1].EDX + * feature bits. Hygon Dhyana follows the same extended feature alias rul= es. + * Enable the corrected Hygon behavior only for machine types where Hygon + * vendor ABI fixes are on. + */ +static bool x86_cpu_has_amd_cpuid_aliases(const X86CPU *cpu) +{ + const CPUX86State *env =3D &cpu->env; + + return IS_AMD_CPU(env) || + (cpu->hygon_vendor_abi_fixes && IS_HYGON_CPU(env)); +} + void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) @@ -10147,10 +10161,11 @@ static void x86_cpu_realizefn(DeviceState *dev, E= rror **errp) } } =20 - /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on - * CPUID[1].EDX. + /* + * CPUs that use AMD-compatible extended CPUID aliases must keep selec= ted + * CPUID[0x80000001].EDX bits synchronized with CPUID[1].EDX. */ - if (IS_AMD_CPU(env)) { + if (x86_cpu_has_amd_cpuid_aliases(cpu)) { env->features[FEAT_8000_0001_EDX] &=3D ~CPUID_EXT2_AMD_ALIASES; env->features[FEAT_8000_0001_EDX] |=3D (env->features[FEAT_1_EDX] & CPUID_EXT2_AMD_ALIASES); @@ -10810,6 +10825,8 @@ static const Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, tru= e), DEFINE_PROP_BOOL("x-vendor-cpuid-only-v2", X86CPU, vendor_cpuid_only_v= 2, true), + DEFINE_PROP_BOOL("x-hygon-vendor-abi-fixes", X86CPU, + hygon_vendor_abi_fixes, true), DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_fe= atures_only, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e6a197602d..3e75b03609 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1281,6 +1281,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define CPUID_VENDOR_ZHAOXIN1 "CentaurHauls" #define CPUID_VENDOR_ZHAOXIN2 " Shanghai " =20 +#define CPUID_VENDOR_HYGON_1 0x6f677948 /* "Hygo" */ +#define CPUID_VENDOR_HYGON_2 0x6e65476e /* "nGen" */ +#define CPUID_VENDOR_HYGON_3 0x656e6975 /* "uine" */ #define CPUID_VENDOR_HYGON "HygonGenuine" =20 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_INTEL_= 1 && \ @@ -1289,6 +1292,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_AMD_1 &&= \ (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_AMD_2 &&= \ (env)->cpuid_vendor3 =3D=3D CPUID_VENDOR_AMD_3) +#define IS_HYGON_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_HYGON_= 1 && \ + (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_HYGON_= 2 && \ + (env)->cpuid_vendor3 =3D=3D CPUID_VENDOR_HYGON_= 3) #define IS_ZHAOXIN1_CPU(env) \ ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_ZHAOXIN1_1 && \ (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_ZHAOXIN1_2 && \ @@ -2461,6 +2467,12 @@ struct ArchCPU { */ bool vendor_cpuid_only_v2; =20 + /* + * Enable Hygon vendor ABI fixes for new machine types. Old machine + * types disable this to preserve guest-visible CPU ABI. + */ + bool hygon_vendor_abi_fixes; + /* Only advertise TOPOEXT features that AMD defines */ bool amd_topoext_features_only; =20 diff --git a/tests/qtest/test-x86-cpuid-compat.c b/tests/qtest/test-x86-cpu= id-compat.c index 17c0965827..b7f8834052 100644 --- a/tests/qtest/test-x86-cpuid-compat.c +++ b/tests/qtest/test-x86-cpuid-compat.c @@ -113,6 +113,21 @@ typedef struct FeatureTestArgs { bool expected_value; } FeatureTestArgs; =20 +typedef struct BoolPropTestArgs { + /* Test name */ + const char *name; + /* CPU type */ + const char *cpu; + /* CPU features (may be NULL) */ + const char *cpufeat; + /* machine type (may be NULL to use default machine) */ + const char *machine; + /* CPU property to read */ + const char *property; + /* expected value of the property */ + bool expected_value; +} BoolPropTestArgs; + /* Get the value for a feature word in a X86CPUFeatureWordInfo list */ static uint32_t get_feature_word(QList *features, uint32_t eax, uint32_t e= cx, const char *reg) @@ -170,6 +185,38 @@ static void test_feature_flag(const void *data) g_free(cmdline); } =20 +static void test_bool_prop(const void *data) +{ + const BoolPropTestArgs *args =3D data; + char *cmdline; + char *save; + char *path; + bool value; + + cmdline =3D g_strdup_printf("-cpu %s", args->cpu); + + if (args->cpufeat) { + save =3D cmdline; + cmdline =3D g_strdup_printf("%s,%s", cmdline, args->cpufeat); + g_free(save); + } + if (args->machine) { + save =3D cmdline; + cmdline =3D g_strdup_printf("-machine %s %s", args->machine, cmdli= ne); + g_free(save); + } + + qtest_start(cmdline); + path =3D get_cpu0_qom_path(); + value =3D qom_get_bool(path, args->property); + qtest_end(); + + g_assert_cmpint(value, =3D=3D, args->expected_value); + + g_free(path); + g_free(cmdline); +} + static void test_plus_minus_subprocess(void) { char *path; @@ -407,6 +454,28 @@ static const FeatureTestArgs feature_tests[] =3D { "max", "mmx=3Doff", 1, 0, "EDX", 23, false, }, + { + "x86/cpuid/features/dhyana/ext-mmx", + "Dhyana", NULL, + 0x80000001, 0, "EDX", 23, true, + }, + { + "x86/cpuid/features/dhyana/ext-mmx/compat-off", + "Dhyana", "x-hygon-vendor-abi-fixes=3Doff", + 0x80000001, 0, "EDX", 23, false, + }, +}; + +static const BoolPropTestArgs bool_prop_tests[] =3D { + { + "x86/cpuid/props/dhyana/hygon-vendor-abi-fixes/default", + "Dhyana", NULL, NULL, "x-hygon-vendor-abi-fixes", true, + }, + { + "x86/cpuid/props/dhyana/hygon-vendor-abi-fixes/pc-i440fx-11.0", + "Dhyana", NULL, "pc-i440fx-11.0", + "x-hygon-vendor-abi-fixes", false, + }, }; =20 int main(int argc, char **argv) @@ -433,6 +502,13 @@ int main(int argc, char **argv) qtest_add_data_func(feature_tests[i].name, &feature_tests[i], test_feature_flag); } + for (int i =3D 0; i < ARRAY_SIZE(bool_prop_tests); i++) { + if (!qtest_has_cpu_model(bool_prop_tests[i].cpu)) { + continue; + } + qtest_add_data_func(bool_prop_tests[i].name, + &bool_prop_tests[i], test_bool_prop); + } =20 return g_test_run(); } --=20 2.43.7 From nobody Sun Jul 26 11:08:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783342405698563.1934695422963; Mon, 6 Jul 2026 05:53:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgint-0000wl-Hh; Mon, 06 Jul 2026 08:52:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQW-0002sG-Gi for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:32 -0400 Received: from [115.124.28.193] (helo=out28-193.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQR-0005Ru-75 for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:32 -0400 Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iEEStpQ_1783317364 cluster:ay29) by smtp.aliyun-inc.com; Mon, 06 Jul 2026 13:56:04 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.0743885|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0678529-0.000905267-0.931242; FP=7205585317544953051|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033037028158; MF=zhang_wei@open-hieco.net; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.iEEStpQ_1783317364; From: zhang_wei@open-hieco.net To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, "Michael S . Tsirkin" , Paolo Bonzini , Marcelo Tosatti , Tina Zhang Subject: [PATCH v1 2/9] target/i386: Hide Intel cache CPUID leaves for Hygon Date: Mon, 6 Jul 2026 13:55:23 +0800 Message-ID: <20260706055530.1752094-3-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260706055530.1752094-1-zhang_wei@open-hieco.net> References: <20260706055530.1752094-1-zhang_wei@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.193 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.193; envelope-from=zhang_wei@open-hieco.net; helo=out28-193.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 06 Jul 2026 08:51:52 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1783342407318158500 Content-Type: text/plain; charset="utf-8" From: Tina Zhang When x-vendor-cpuid-only is enabled, QEMU suppresses CPUID leaves 2 and 4 for AuthenticAMD CPUs because those leaves describe Intel cache information. Hygon Dhyana uses the HygonGenuine vendor string, so it currently skips that filtering and can expose Intel cache leaves together with AMD/Hygon extended cache leaves. That is inconsistent guest-visible CPUID: Hygon Dhyana provides cache information through the extended cache leaves, so it should not also advertise the Intel cache descriptor and deterministic cache parameter leaves. Apply the same leaf 2 and leaf 4 filtering to Hygon CPUs when Hygon vendor ABI fixes are enabled. The property keeps the old CPUID output for pc-11.0 and older machine types. Signed-off-by: Tina Zhang --- target/i386/cpu.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 32b8bc9ebd..f0cad38c94 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8622,6 +8622,21 @@ static bool x86_cpu_has_amd_cpuid_aliases(const X86C= PU *cpu) (cpu->hygon_vendor_abi_fixes && IS_HYGON_CPU(env)); } =20 +/* + * CPUID leaves 2 and 4 describe Intel cache information. AMD CPUs use + * extended cache leaves instead, and Hygon Dhyana follows that AMD/Hygon + * convention. Enable the corrected Hygon behavior only for machine types + * where Hygon vendor ABI fixes are on. + */ +static bool x86_cpu_filter_intel_cache_leaves(const X86CPU *cpu) +{ + const CPUX86State *env =3D &cpu->env; + + return cpu->vendor_cpuid_only && + (IS_AMD_CPU(env) || + (cpu->hygon_vendor_abi_fixes && IS_HYGON_CPU(env))); +} + void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) @@ -8707,7 +8722,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; - } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { + } else if (x86_cpu_filter_intel_cache_leaves(cpu)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; break; } @@ -8743,7 +8758,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, CPU_TOPOLOGY_LEVEL_SOCKET), 4095) << 14; } } - } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { + } else if (x86_cpu_filter_intel_cache_leaves(cpu)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; --=20 2.43.7 From nobody Sun Jul 26 11:08:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783342372161948.550385307531; Mon, 6 Jul 2026 05:52:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wginr-0000o3-9X; Mon, 06 Jul 2026 08:52:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQV-0002s3-Iq for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:31 -0400 Received: from [115.124.28.5] (helo=out28-5.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQR-0005Rq-6o for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:31 -0400 Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iEEStq6_1783317364 cluster:ay29) by smtp.aliyun-inc.com; Mon, 06 Jul 2026 13:56:05 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07468145|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.253112-0.000743695-0.746145; FP=7196585128222115019|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033037021130; MF=zhang_wei@open-hieco.net; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.iEEStq6_1783317364; From: zhang_wei@open-hieco.net To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, "Michael S . Tsirkin" , Paolo Bonzini , Marcelo Tosatti , Tina Zhang Subject: [PATCH v1 3/9] target/i386: Hide ARCH_CAPABILITIES for Hygon Date: Mon, 6 Jul 2026 13:55:24 +0800 Message-ID: <20260706055530.1752094-4-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260706055530.1752094-1-zhang_wei@open-hieco.net> References: <20260706055530.1752094-1-zhang_wei@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.5 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.5; envelope-from=zhang_wei@open-hieco.net; helo=out28-5.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 06 Jul 2026 08:51:44 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1783342373414158500 Content-Type: text/plain; charset="utf-8" From: Tina Zhang IA32_ARCH_CAPABILITIES is an Intel-defined MSR. KVM can synthesize the CPUID bit and read-only MSR for non-Intel guests, and QEMU already hides that interface for AMD CPU models because Windows may not expect it on AMD-compatible CPUs. Hygon Dhyana uses the HygonGenuine vendor string, so it currently skips that AMD filter. If arch-capabilities=3Don is requested, QEMU can expose CPUID.7.0.EDX[ARCH_CAPABILITIES] and the associated MSR feature word to a Hygon guest. That creates a vendor-inconsistent CPU ABI: the guest sees an AMD-compatible vendor and cache/topology interface, but also sees an Intel-specific architectural capabilities MSR. Guests that choose CPU mitigation or feature paths from the vendor can mis-handle that combination; Windows is known to be sensitive to ARCH_CAPABILITIES on AMD-compatible CPUs. Apply the same ARCH_CAPABILITIES hiding rule to Hygon CPUs when Hygon vendor ABI fixes are enabled. Keep arch_cap_always_on as the migration escape hatch, and keep the old Hygon CPUID/MSR output for pc-11.0 and older machine types via x-hygon-vendor-abi-fixes=3Dfalse. Signed-off-by: Tina Zhang --- target/i386/cpu.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f0cad38c94..47f48f4a96 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8209,6 +8209,8 @@ static uint8_t x86_cpu_get_host_avx10_version(void) return ebx & 0xff; } =20 +static bool x86_cpu_should_hide_arch_capabilities(const X86CPU *cpu); + uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) { FeatureWordInfo *wi =3D &feature_word_info[w]; @@ -8294,15 +8296,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w) break; =20 case FEAT_7_0_EDX: - /* - * Windows does not like ARCH_CAPABILITIES on AMD machines at all. - * Do not show the fake ARCH_CAPABILITIES MSR that KVM sets up, - * except if needed for migration. - * - * When arch_cap_always_on is removed, this tweak can move to - * kvm_arch_get_supported_cpuid. - */ - if (cpu && IS_AMD_CPU(&cpu->env) && !cpu->arch_cap_always_on) { + if (cpu && x86_cpu_should_hide_arch_capabilities(cpu)) { unavail =3D CPUID_7_0_EDX_ARCH_CAPABILITIES; } break; @@ -8608,6 +8602,27 @@ uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) } } =20 +/* + * Windows does not like ARCH_CAPABILITIES on AMD machines at all. + * Do not show the fake ARCH_CAPABILITIES MSR that KVM sets up, + * except if needed for migration. Apply the same rule to Hygon CPUs when + * Hygon vendor ABI fixes are enabled. + * + * When arch_cap_always_on is removed, this tweak can move to + * kvm_arch_get_supported_cpuid. + */ +static bool x86_cpu_should_hide_arch_capabilities(const X86CPU *cpu) +{ + const CPUX86State *env =3D &cpu->env; + + if (cpu->arch_cap_always_on) { + return false; + } + + return IS_AMD_CPU(env) || + (cpu->hygon_vendor_abi_fixes && IS_HYGON_CPU(env)); +} + /* * AMD CPUs define CPUID[0x80000001].EDX aliases for selected CPUID[1].EDX * feature bits. Hygon Dhyana follows the same extended feature alias rul= es. --=20 2.43.7 From nobody Sun Jul 26 11:08:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783342367712591.4518272654034; Mon, 6 Jul 2026 05:52:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgio0-0001Bj-Ht; Mon, 06 Jul 2026 08:52:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQU-0002ro-C8 for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:30 -0400 Received: from [115.124.28.5] (helo=out28-5.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQR-0005Rr-6P for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:30 -0400 Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iEEStqt_1783317365 cluster:ay29) by smtp.aliyun-inc.com; Mon, 06 Jul 2026 13:56:05 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07472231|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00900542-0.00101272-0.989982; FP=2852828158138205695|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033045220102; MF=zhang_wei@open-hieco.net; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.iEEStqt_1783317365; From: zhang_wei@open-hieco.net To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, "Michael S . Tsirkin" , Paolo Bonzini , Marcelo Tosatti , Tina Zhang Subject: [PATCH v1 4/9] target/i386/kvm: Use AMD MCE status encoding for Hygon Date: Mon, 6 Jul 2026 13:55:25 +0800 Message-ID: <20260706055530.1752094-5-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260706055530.1752094-1-zhang_wei@open-hieco.net> References: <20260706055530.1752094-1-zhang_wei@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.5 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.5; envelope-from=zhang_wei@open-hieco.net; helo=out28-5.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 06 Jul 2026 08:51:19 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1783342369398158500 Content-Type: text/plain; charset="utf-8" From: Tina Zhang QEMU's KVM memory-failure injection path builds synthetic MCI_STATUS records for the guest CPU. The status encoding is vendor-specific: Intel-style records use bits such as MCI_STATUS_S and MCI_STATUS_AR for action-required events, while the AMD path uses the AMD memory-failure encoding. Today QEMU selects the AMD status encoding only for AuthenticAMD guests. Hygon guests therefore get Intel-style injected status bits, including MCI_STATUS_S and MCI_STATUS_AR for action-required events, and a non-deferred action-optional record. Use the AMD injected-memory-failure MCE status encoding for Hygon guests as well. This does not depend on Hygon exposing CPUID 0x80000007.EBX recovery features such as SUCCOR, and it does not advertise any new recovery capability. The change is limited to QEMU's synthetic KVM memory-failure MCE status; it does not change CPUID, MCE bank state, or migrated CPU state. Signed-off-by: Tina Zhang --- target/i386/kvm/kvm.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 64cc421abe..8e2bfbbe1d 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -698,6 +698,15 @@ static int kvm_get_mce_cap_supported(KVMState *s, uint= 64_t *mce_cap, return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); } =20 +/* + * Use AMD-style MCE status records for QEMU-injected memory failures on + * AMD and Hygon CPUs. + */ +static bool kvm_mce_inject_uses_amd_status(const CPUX86State *env) +{ + return IS_AMD_CPU(env) || IS_HYGON_CPU(env); +} + static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) { CPUState *cs =3D CPU(cpu); @@ -707,7 +716,7 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, i= nt code) uint64_t mcg_status =3D MCG_STATUS_MCIP | MCG_STATUS_RIPV; int flags =3D 0; =20 - if (!IS_AMD_CPU(env)) { + if (!kvm_mce_inject_uses_amd_status(env)) { status |=3D MCI_STATUS_S | MCI_STATUS_UC; if (code =3D=3D BUS_MCEERR_AR) { status |=3D MCI_STATUS_AR | 0x134; --=20 2.43.7 From nobody Sun Jul 26 11:08:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783342363058986.9521827500658; Mon, 6 Jul 2026 05:52:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wginq-0000jP-Gv; Mon, 06 Jul 2026 08:52:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQU-0002rn-8h for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:30 -0400 Received: from [115.124.28.217] (helo=out28-217.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQR-0005Rm-6V for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:30 -0400 Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iEEStrb_1783317365 cluster:ay29) by smtp.aliyun-inc.com; Mon, 06 Jul 2026 13:56:06 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436261|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.228352-0.00012945-0.771519; FP=7097510869165867103|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033068005250; MF=zhang_wei@open-hieco.net; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.iEEStrb_1783317365; From: zhang_wei@open-hieco.net To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, "Michael S . Tsirkin" , Paolo Bonzini , Marcelo Tosatti , Tina Zhang Subject: [PATCH v1 5/9] target/i386/kvm: Use AMD PMU MSR paths for Hygon Date: Mon, 6 Jul 2026 13:55:26 +0800 Message-ID: <20260706055530.1752094-6-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260706055530.1752094-1-zhang_wei@open-hieco.net> References: <20260706055530.1752094-1-zhang_wei@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.217 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.217; envelope-from=zhang_wei@open-hieco.net; helo=out28-217.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 06 Jul 2026 08:51:12 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1783342366030158500 Content-Type: text/plain; charset="utf-8" From: Tina Zhang On SVM, KVM uses the AMD PMU implementation and AMD PMU CPUID/MSR layout. Hygon guests that enable PMU and request AMD PMU CPUID features such as perfctr-core need QEMU's KVM PMU setup and MSR state paths to use that layout too. The relevant QEMU KVM PMU paths are currently restricted to AuthenticAMD guests: host/guest PMU compatibility checks, AMD PMU information initialization, and AMD PMU MSR save/restore. As a result, a Hygon Dhyana guest can be rejected as unsupported because the guest vendor is HygonGenuine rather than AuthenticAMD. If the VM continues, QEMU still skips AMD PMU setup and the AMD PMU MSR get/put paths. Treat Hygon as using the AMD PMU CPUID/MSR layout for these KVM PMU paths. Because the PMU MSR layout is shared, accept both AMD and Hygon hosts for guests using that layout. This intentionally allows the PMU compatibility check to pass for AMD-host/Hygon-guest and Hygon-host/AMD-guest combinations. This does not enable PMU, perfctr-core, or perfmon-v2 by default for the Dhyana CPU model. On backward migration to older QEMU, Hygon PMU MSR state may still be dropped because older QEMU did not write that state back through the AMD PMU MSR KVM paths for Hygon guests. Signed-off-by: Tina Zhang --- target/i386/kvm/kvm.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 8e2bfbbe1d..215e0c8f03 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2175,6 +2175,21 @@ static void kvm_init_pmu_info_amd(struct kvm_cpuid2 = *cpuid, X86CPU *cpu) } } =20 +/* + * KVM exposes the AMD PMU CPUID/MSR layout for Hygon guests, so QEMU must + * use the AMD PMU setup and MSR state paths for Hygon too. + */ +static bool kvm_pmu_uses_amd_msrs(const CPUX86State *env) +{ + return IS_AMD_CPU(env) || IS_HYGON_CPU(env); +} + +static bool host_cpu_uses_amd_pmu_msrs(const char *host_vendor) +{ + return g_str_equal(host_vendor, CPUID_VENDOR_AMD) || + g_str_equal(host_vendor, CPUID_VENDOR_HYGON); +} + static bool is_host_compat_vendor(CPUX86State *env) { char host_vendor[CPUID_VENDOR_SZ + 1]; @@ -2191,8 +2206,8 @@ static bool is_host_compat_vendor(CPUX86State *env) return true; } =20 - return g_str_equal(host_vendor, CPUID_VENDOR_AMD) && - IS_AMD_CPU(env); + return host_cpu_uses_amd_pmu_msrs(host_vendor) && + kvm_pmu_uses_amd_msrs(env); } =20 static void kvm_init_pmu_info(struct kvm_cpuid2 *cpuid, X86CPU *cpu) @@ -2222,7 +2237,7 @@ static void kvm_init_pmu_info(struct kvm_cpuid2 *cpui= d, X86CPU *cpu) =20 if (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) { kvm_init_pmu_info_intel(cpuid); - } else if (IS_AMD_CPU(env)) { + } else if (kvm_pmu_uses_amd_msrs(env)) { kvm_init_pmu_info_amd(cpuid, cpu); } } @@ -4309,7 +4324,7 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState leve= l) } } =20 - if (IS_AMD_CPU(env) && pmu_version > 0) { + if (kvm_pmu_uses_amd_msrs(env) && pmu_version > 0) { uint32_t sel_base =3D MSR_K7_EVNTSEL0; uint32_t ctr_base =3D MSR_K7_PERFCTR0; /* @@ -4871,7 +4886,7 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 - if (IS_AMD_CPU(env) && pmu_version > 0) { + if (kvm_pmu_uses_amd_msrs(env) && pmu_version > 0) { uint32_t sel_base =3D MSR_K7_EVNTSEL0; uint32_t ctr_base =3D MSR_K7_PERFCTR0; /* --=20 2.43.7 From nobody Sun Jul 26 11:08:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783342406574281.56555761289735; Mon, 6 Jul 2026 05:53:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgins-0000rl-7i; Mon, 06 Jul 2026 08:52:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQV-0002sA-PG for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:31 -0400 Received: from [115.124.28.4] (helo=out28-4.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQQ-0005Rn-VV for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:31 -0400 Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iEEStsW_1783317366 cluster:ay29) by smtp.aliyun-inc.com; Mon, 06 Jul 2026 13:56:06 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08311087|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0297137-0.00931817-0.960968; FP=7187543794714895573|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033032053168; MF=zhang_wei@open-hieco.net; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.iEEStsW_1783317366; From: zhang_wei@open-hieco.net To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, "Michael S . Tsirkin" , Paolo Bonzini , Marcelo Tosatti , Tina Zhang Subject: [PATCH v1 6/9] target/i386: Do not broadcast injected MCEs for Hygon Date: Mon, 6 Jul 2026 13:55:27 +0800 Message-ID: <20260706055530.1752094-7-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260706055530.1752094-1-zhang_wei@open-hieco.net> References: <20260706055530.1752094-1-zhang_wei@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.4 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.4; envelope-from=zhang_wei@open-hieco.net; helo=out28-4.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 06 Jul 2026 08:51:46 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1783342407161158500 Content-Type: text/plain; charset="utf-8" From: Tina Zhang cpu_x86_support_mca_broadcast() excludes AMD CPUs because QEMU handles AMD injected MCEs as local machine checks, not as Intel-style broadcast MCEs. Hygon Dhyana missed that exclusion: it is not an AMD vendor CPU and its family is greater than 6, so QEMU reported MCA broadcast support. This affects QEMU's synthetic MCE injection paths. KVM memory-failure injection uses this helper to decide whether to set MCE_INJECT_BROADCAST. HMP 'mce -b' uses it to decide whether a broadcast request is valid. With a multi-vCPU Dhyana guest, QEMU could fan out an injected MCE to secondary vCPUs and populate extra bank records. Linux routes Hygon through the AMD MCE feature initialization path and does not use Intel/Zhaoxin LMCE broadcast handling for Hygon. Do not advertise Intel-style MCA broadcast support for Hygon in QEMU's injected MCE paths. This is limited to the MCE broadcast-support decision. It does not claim that all Hygon MCE/MCA behavior is identical to AMD. Signed-off-by: Tina Zhang --- target/i386/helper.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/i386/helper.c b/target/i386/helper.c index 6836214162..0e71b52f13 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -95,7 +95,11 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) int family =3D 0; int model =3D 0; =20 - if (IS_AMD_CPU(env)) { + /* + * Injected AMD and Hygon MCEs follow the local MCE model; do not use + * Intel-style MCA broadcast for these vendors. + */ + if (IS_AMD_CPU(env) || IS_HYGON_CPU(env)) { return 0; } =20 --=20 2.43.7 From nobody Sun Jul 26 11:08:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783342401305943.0315934020289; Mon, 6 Jul 2026 05:53:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wginr-0000nm-6c; Mon, 06 Jul 2026 08:52:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQX-0002sq-9m for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:33 -0400 Received: from [115.124.28.124] (helo=out28-124.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQR-0005Rv-99 for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:33 -0400 Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iEESttH_1783317367 cluster:ay29) by smtp.aliyun-inc.com; Mon, 06 Jul 2026 13:56:07 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436273|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0135109-3.74173e-05-0.986452; FP=7603985663140579731|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033037021130; MF=zhang_wei@open-hieco.net; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.iEESttH_1783317367; From: zhang_wei@open-hieco.net To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, "Michael S . Tsirkin" , Paolo Bonzini , Marcelo Tosatti , Tina Zhang , Yanjing Zhou Subject: [PATCH v1 7/9] hw/i386: Apply AMD IOMMU HT GPA hole to Hygon Date: Mon, 6 Jul 2026 13:55:28 +0800 Message-ID: <20260706055530.1752094-8-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260706055530.1752094-1-zhang_wei@open-hieco.net> References: <20260706055530.1752094-1-zhang_wei@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.124 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.124; envelope-from=zhang_wei@open-hieco.net; helo=out28-124.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 06 Jul 2026 08:51:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1783342403685158500 Content-Type: text/plain; charset="utf-8" From: Tina Zhang QEMU reserves the HyperTransport special GPA range near the 1 TiB boundary only for AMD vCPUs. That range is reserved by the AMD IOMMU GPA layout, and Linux validates VFIO DMA mappings against IOMMU reserved regions. If guest RAM, hotplug address space, or 64-bit MMIO windows overlap the range, VFIO DMA_MAP can fail with -EINVAL or the IOMMU can report faults such as INVALID_DEVICE_REQUEST. The Linux AMD IOMMU driver also handles Hygon systems and reserves the HT range unless the IOMMU advertises FEATURE_HT_RANGE_IGNORE. Treat Hygon vCPUs as using the same AMD IOMMU HT GPA-hole layout in QEMU's PC memory layout code. This changes the guest physical memory map for Hygon, so gate the new Hygon behavior with x-hygon-vendor-abi-fixes. pc-11.0 and older machine types keep the previous Hygon memory layout, while the existing enforce_amd_1tb_hole compatibility keeps the old AMD behavior for pc/q35 <=3D 7.0. Add functional coverage for Dhyana on the current q35 machine type and for the pc-q35-11.0 compatibility case. Signed-off-by: Yanjing Zhou Signed-off-by: Tina Zhang --- hw/i386/pc.c | 18 +++++++--- .../functional/x86_64/test_mem_addr_space.py | 36 +++++++++++++++++++ 2 files changed, 49 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 11dade642f..4c029d6a4b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -735,6 +735,12 @@ static hwaddr pc_max_used_gpa(PCMachineState *pcms, ui= nt64_t pci_hole64_size) #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) =20 +static bool x86_cpu_has_amd_iommu_ht_gpa_hole(const X86CPU *cpu) +{ + return IS_AMD_CPU(&cpu->env) || + (IS_HYGON_CPU(&cpu->env) && cpu->hygon_vendor_abi_fixes); +} + void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, @@ -759,12 +765,14 @@ void pc_memory_init(PCMachineState *pcms, linux_boot =3D (machine->kernel_filename !=3D NULL); =20 /* - * The HyperTransport range close to the 1T boundary is unique to AMD - * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation - * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false = in - * older machine types (<=3D 7.0) for compatibility purposes. + * The HyperTransport range close to the 1T boundary is reserved by the + * AMD IOMMU GPA layout. Apply the ram-above-4g relocation only to vC= PUs + * that use that layout. @enforce_amd_1tb_hole preserves older AMD + * machine types (<=3D 7.0), and x-hygon-vendor-abi-fixes preserves ol= der + * Hygon machine types (<=3D 11.0). */ - if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { + if (x86_cpu_has_amd_iommu_ht_gpa_hole(cpu) && + pcmc->enforce_amd_1tb_hole) { /* Bail out if max possible address does not cross HT range */ if (pc_max_used_gpa(pcms, pci_hole64_size) >=3D AMD_HT_START) { x86ms->above_4g_mem_start =3D AMD_ABOVE_1TB_START; diff --git a/tests/functional/x86_64/test_mem_addr_space.py b/tests/functio= nal/x86_64/test_mem_addr_space.py index 61b4a190b4..e4b4aee008 100755 --- a/tests/functional/x86_64/test_mem_addr_space.py +++ b/tests/functional/x86_64/test_mem_addr_space.py @@ -208,6 +208,24 @@ def test_phybits_low_tcg_q35_71_amd(self): self.assertEqual(self.vm.exitcode(), 1, "QEMU exit code should be = 1") self.assertRegex(self.vm.get_log(), r'phys-bits too low') =20 + def test_phybits_low_tcg_q35_hygon(self): + """ + Check that Dhyana on the default q35 machine follows the AMD IOMMU + HT reserved GPA range on new machine types. + """ + self.ensure_64bit_binary() + self.set_machine('q35') + self.vm.add_args('-S', '-cpu', 'Dhyana,phys-bits=3D40', + '-m', '512,slots=3D1,maxmem=3D976G', + '-display', 'none', + '-object', 'memory-backend-ram,id=3Dmem1,size=3D1= G', + '-device', 'pc-dimm,id=3Dvm0,memdev=3Dmem1') + self.vm.set_qmp_monitor(enabled=3DFalse) + self.vm.launch() + self.vm.wait() + self.assertEqual(self.vm.exitcode(), 1, "QEMU exit code should be = 1") + self.assertRegex(self.vm.get_log(), r'phys-bits too low') + def test_phybits_ok_tcg_q35_70_amd(self): """ Same as q35-7.0 AMD case except that here we check that QEMU can @@ -225,6 +243,24 @@ def test_phybits_ok_tcg_q35_70_amd(self): self.vm.shutdown() self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') =20 + def test_phybits_ok_tcg_q35_110_hygon(self): + """ + Same as the default q35 Dhyana case except that here we check that + the q35-11.0 compatibility setting keeps the old memory layout. + """ + self.ensure_64bit_binary() + self.set_machine('pc-q35-11.0') + self.vm.add_args('-S', '-cpu', 'Dhyana,phys-bits=3D40', + '-m', '512,slots=3D1,maxmem=3D976G', + '-display', 'none', + '-object', 'memory-backend-ram,id=3Dmem1,size=3D1= G', + '-device', 'pc-dimm,id=3Dvm0,memdev=3Dmem1') + self.vm.set_qmp_monitor(enabled=3DFalse) + self.vm.launch() + time.sleep(self.DELAY_Q35_BOOT_SEQUENCE) + self.vm.shutdown() + self.assertNotRegex(self.vm.get_log(), r'phys-bits too low') + def test_phybits_ok_tcg_q35_71_amd(self): """ Same as q35-7.1 AMD case except that here we check that QEMU can --=20 2.43.7 From nobody Sun Jul 26 11:08:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783342409416526.7259356800919; Mon, 6 Jul 2026 05:53:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgins-0000rE-1T; Mon, 06 Jul 2026 08:52:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQW-0002sB-0O for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:32 -0400 Received: from [115.124.28.170] (helo=out28-170.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQR-0005Rp-6e for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:31 -0400 Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iEEStuJ_1783317367 cluster:ay29) by smtp.aliyun-inc.com; Mon, 06 Jul 2026 13:56:07 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.0854889|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0164078-0.000604772-0.982987; FP=16418801770556892254|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033045213054; MF=zhang_wei@open-hieco.net; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.iEEStuJ_1783317367; From: zhang_wei@open-hieco.net To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, "Michael S . Tsirkin" , Paolo Bonzini , Marcelo Tosatti , Tina Zhang Subject: [PATCH v1 8/9] target/i386: Use AMD legacy cache fallback for Hygon Date: Mon, 6 Jul 2026 13:55:29 +0800 Message-ID: <20260706055530.1752094-9-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260706055530.1752094-1-zhang_wei@open-hieco.net> References: <20260706055530.1752094-1-zhang_wei@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.170 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.170; envelope-from=zhang_wei@open-hieco.net; helo=out28-170.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 06 Jul 2026 08:51:54 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1783342411196158500 Content-Type: text/plain; charset="utf-8" From: Tina Zhang When legacy-cache=3Don, x86_cpu_realizefn() builds a hardcoded cache model. It selected the AMD legacy cache table only for CPUs with the AuthenticAMD vendor ID. Dhyana uses the HygonGenuine vendor ID, so this explicit compatibility path fell back to QEMU's old Intel legacy cache table. The wrong table is visible through AMD extended cache leaves. With the Intel legacy table, Dhyana reports 32 KiB, 8-way L1 caches in CPUID 0x80000005 and a 4 MiB, 16-way L2 cache in CPUID 0x80000006. Linux uses the AMD/Hygon cache enumeration path for Hygon and reads these AMD extended cache leaves. Use the AMD legacy cache table for Hygon in this fallback path when the new Hygon vendor ABI fixes are enabled. Keep the old fallback for pc-11.0 and older machine types through x-hygon-vendor-abi-fixes=3Dfalse. The default Dhyana model is unchanged because it provides EPYC cache_info and therefore defaults legacy-cache to off. The guest-visible change is limited to users who explicitly configure legacy-cache=3Don on new machine types. Signed-off-by: Tina Zhang --- target/i386/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 47f48f4a96..279c9b3ae7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10342,7 +10342,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Err= or **errp) env->enable_legacy_vendor_cache =3D true; } =20 - if (IS_AMD_CPU(env)) { + if (IS_AMD_CPU(env) || + (IS_HYGON_CPU(env) && cpu->hygon_vendor_abi_fixes)) { env->cache_info =3D legacy_amd_cache_info; } else { env->cache_info =3D legacy_intel_cache_info; --=20 2.43.7 From nobody Sun Jul 26 11:08:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783342410149517.7214181343902; Mon, 6 Jul 2026 05:53:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgins-0000tW-S0; Mon, 06 Jul 2026 08:52:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQW-0002sC-41 for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:32 -0400 Received: from [115.124.28.173] (helo=out28-173.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgcQR-0005Rt-7X for qemu-devel@nongnu.org; Mon, 06 Jul 2026 02:03:31 -0400 Received: from localhost.localdomain(mailfrom:zhang_wei@open-hieco.net fp:SMTPD_---.iEEStvD_1783317368 cluster:ay29) by smtp.aliyun-inc.com; Mon, 06 Jul 2026 13:56:08 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436462|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.00386058-0.000288194-0.995851; FP=16568572874340175179|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033068005250; MF=zhang_wei@open-hieco.net; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.iEEStvD_1783317368; From: zhang_wei@open-hieco.net To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, "Michael S . Tsirkin" , Paolo Bonzini , Marcelo Tosatti , Tina Zhang Subject: [PATCH v1 9/9] target/i386: Use AMD ucode-rev default for Hygon Date: Mon, 6 Jul 2026 13:55:30 +0800 Message-ID: <20260706055530.1752094-10-zhang_wei@open-hieco.net> X-Mailer: git-send-email 2.43.7 In-Reply-To: <20260706055530.1752094-1-zhang_wei@open-hieco.net> References: <20260706055530.1752094-1-zhang_wei@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.173 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.173; envelope-from=zhang_wei@open-hieco.net; helo=out28-173.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 06 Jul 2026 08:51:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1783342411228158500 Content-Type: text/plain; charset="utf-8" From: Tina Zhang QEMU currently gives named Hygon Dhyana CPUs the non-AMD default ucode-rev value, 0x100000000. That is the Intel/KVM-VMX-shaped encoding, where the visible revision is in the high 32 bits. Linux reads MSR 0x8b for Hygon CPUs through the AMD patch-level path, using MSR_AMD64_PATCH_LEVEL and storing the low 32 bits as cpuinfo_x86.microcode. With the old QEMU default, a Dhyana guest sees microcode revision 0. Use the AMD/KVM-SVM-shaped default, 0x01000065, for Hygon on this specific MSR 0x8b default path. This does not route Hygon through AMD microcode loading and does not claim that Hygon CPUs are otherwise identical to AMD CPUs. Preserve migration ABI through the Hygon vendor ABI fixes property. pc-11.0 and older machine types leave it off, so they retain the previous ucode-rev default. Explicit user-provided ucode-rev values still override the default. Add qtest coverage for the new default, the compatibility cases, and an explicit user override. Signed-off-by: Tina Zhang --- target/i386/cpu.c | 8 ++++++-- tests/qtest/test-x86-cpuid-compat.c | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 279c9b3ae7..af1e5f2857 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10232,10 +10232,14 @@ static void x86_cpu_realizefn(DeviceState *dev, E= rror **errp) if (cpu->ucode_rev =3D=3D 0) { /* * The default is the same as KVM's. Note that this check - * needs to happen after the evenual setting of ucode_rev in + * needs to happen after the eventual setting of ucode_rev in * accel-specific code in cpu_exec_realizefn. + * + * Hygon uses the AMD patch-level MSR 0x8b encoding, where the vis= ible + * microcode revision is in the low 32 bits. */ - if (IS_AMD_CPU(env)) { + if (IS_AMD_CPU(env) || + (IS_HYGON_CPU(env) && cpu->hygon_vendor_abi_fixes)) { cpu->ucode_rev =3D 0x01000065; } else { cpu->ucode_rev =3D 0x100000000ULL; diff --git a/tests/qtest/test-x86-cpuid-compat.c b/tests/qtest/test-x86-cpu= id-compat.c index b7f8834052..06cbf35d76 100644 --- a/tests/qtest/test-x86-cpuid-compat.c +++ b/tests/qtest/test-x86-cpuid-compat.c @@ -404,6 +404,25 @@ static const CpuidTestArgs cpuid_tests[] =3D { "486", "xlevel2=3D0xC0000002,xstore=3Don", NULL, "xlevel2", 0xC0000002, }, + { + "x86/cpuid/props/dhyana/ucode-rev/default", + "Dhyana", NULL, NULL, "ucode-rev", 0x01000065, + }, + { + "x86/cpuid/props/dhyana/ucode-rev/compat-off", + "Dhyana", "x-hygon-vendor-abi-fixes=3Doff", NULL, + "ucode-rev", 0x100000000LL, + }, + { + "x86/cpuid/props/dhyana/ucode-rev/pc-i440fx-11.0", + "Dhyana", NULL, "pc-i440fx-11.0", + "ucode-rev", 0x100000000LL, + }, + { + "x86/cpuid/props/dhyana/ucode-rev/user", + "Dhyana", "ucode-rev=3D0x12345678", NULL, + "ucode-rev", 0x12345678, + }, }; =20 /* --=20 2.43.7