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Sat, 04 Jul 2026 21:37:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com, Daniel Henrique Barboza Subject: [PATCH v2 01/46] cpu: Move BREAKPOINT definitions to 'exec/breakpoint.h' Date: Sat, 4 Jul 2026 21:36:40 -0700 Message-ID: <20260705043725.1373137-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226365332158500 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20260630220100.1289-18-philmd@oss.qualcomm.com> --- include/exec/breakpoint.h | 14 ++++++++++++++ include/hw/core/cpu.h | 14 -------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index 95f0482e6d..cc6fedd09f 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -12,6 +12,20 @@ #include "exec/vaddr.h" #include "exec/memattrs.h" =20 +/* Breakpoint/watchpoint flags */ +#define BP_MEM_READ 0x01 +#define BP_MEM_WRITE 0x02 +#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) +#define BP_STOP_BEFORE_ACCESS 0x04 +/* 0x08 currently unused */ +#define BP_GDB 0x10 +#define BP_CPU 0x20 +#define BP_ANY (BP_GDB | BP_CPU) +#define BP_HIT_SHIFT 6 +#define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT) +#define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT) +#define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) + typedef struct CPUBreakpoint { vaddr pc; int flags; /* BP_* */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 59d601465b..c3959607df 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1138,20 +1138,6 @@ void qemu_init_vcpu(CPUState *cpu); */ void cpu_single_step(CPUState *cpu, int enabled); =20 -/* Breakpoint/watchpoint flags */ -#define BP_MEM_READ 0x01 -#define BP_MEM_WRITE 0x02 -#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) -#define BP_STOP_BEFORE_ACCESS 0x04 -/* 0x08 currently unused */ -#define BP_GDB 0x10 -#define BP_CPU 0x20 -#define BP_ANY (BP_GDB | BP_CPU) -#define BP_HIT_SHIFT 6 -#define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT) -#define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT) -#define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) - int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint); int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson [rth: Don't rename mask variables to flags] Message-ID: <20260630220100.1289-19-philmd@oss.qualcomm.com> --- include/accel/tcg/cpu-ops.h | 6 ++++-- include/exec/breakpoint.h | 3 ++- include/exec/watchpoint.h | 8 +++++--- include/hw/core/cpu.h | 9 +++++---- accel/tcg/cputlb.c | 12 +++++++----- accel/tcg/tcg-accel-ops.c | 10 +++++----- accel/tcg/user-exec-stub.c | 11 ++++++----- accel/tcg/watchpoint.c | 9 +++++---- cpu-common.c | 6 +++--- system/watchpoint.c | 6 +++--- target/arm/tcg/debug.c | 4 ++-- target/arm/tcg/mte_helper.c | 3 ++- target/ppc/cpu.c | 2 +- target/ppc/kvm.c | 5 +++-- target/riscv/cpu_helper.c | 2 +- target/riscv/debug.c | 6 +++--- target/s390x/tcg/debug.c | 3 ++- target/xtensa/dbg_helper.c | 2 +- 18 files changed, 60 insertions(+), 47 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 710da12b82..f64d94b2b5 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -298,7 +298,8 @@ struct TCGCPUOps { * specified by @flags. Exit via exception with a hit. */ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, - MemTxAttrs attrs, int flags, uintptr_t ra); + MemTxAttrs attrs, BreakpointFlags flags, + uintptr_t ra); =20 /** * cpu_watchpoint_address_matches: @@ -309,7 +310,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, * Return the watchpoint flags that apply to [addr, addr+len). * If no watchpoint is registered for the range, the result is 0. */ -int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); +BreakpointFlags cpu_watchpoint_address_matches(CPUState *cpu, + vaddr addr, vaddr len); =20 /* * Common pointer_wrap implementations. diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index cc6fedd09f..0c3cc0c8ff 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -12,6 +12,7 @@ #include "exec/vaddr.h" #include "exec/memattrs.h" =20 +typedef int BreakpointFlags; /* Breakpoint/watchpoint flags */ #define BP_MEM_READ 0x01 #define BP_MEM_WRITE 0x02 @@ -28,7 +29,7 @@ =20 typedef struct CPUBreakpoint { vaddr pc; - int flags; /* BP_* */ + BreakpointFlags flags; QTAILQ_ENTRY(CPUBreakpoint) entry; } CPUBreakpoint; =20 diff --git a/include/exec/watchpoint.h b/include/exec/watchpoint.h index c4d069425b..a09daf47f1 100644 --- a/include/exec/watchpoint.h +++ b/include/exec/watchpoint.h @@ -8,11 +8,13 @@ #ifndef EXEC_WATCHPOINT_H #define EXEC_WATCHPOINT_H =20 +#include "exec/breakpoint.h" + int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - int flags, CPUWatchpoint **watchpoint); + BreakpointFlags flags, CPUWatchpoint **watchpoin= t); int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, - vaddr len, int flags); + vaddr len, BreakpointFlags flags); void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); -void cpu_watchpoint_remove_all(CPUState *cpu, int mask); +void cpu_watchpoint_remove_all(CPUState *cpu, BreakpointFlags mask); =20 #endif /* EXEC_WATCHPOINT_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c3959607df..2c58ea5e4c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1138,14 +1138,15 @@ void qemu_init_vcpu(CPUState *cpu); */ void cpu_single_step(CPUState *cpu, int enabled); =20 -int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, +int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, CPUBreakpoint **breakpoint); -int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); +int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, BreakpointFlags flags); void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint= ); -void cpu_breakpoint_remove_all(CPUState *cpu, int mask); +void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask); =20 /* Return true if PC matches an installed breakpoint. */ -static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) +static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, + BreakpointFlags mask) { CPUBreakpoint *bp; =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6e66f3c6e9..dbbcf1dbf4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1032,7 +1032,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; vaddr addr_page; - int asidx, wp_flags, prot; + int asidx, prot; + BreakpointFlags wp_flags; bool is_ram, is_romd; =20 assert_cpu_is_self(cpu); @@ -1498,8 +1499,8 @@ void *probe_access(CPUArchState *env, vaddr addr, int= size, if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { /* Handle watchpoints. */ if (flags & TLB_WATCHPOINT) { - int wp_access =3D (access_type =3D=3D MMU_DATA_STORE - ? BP_MEM_WRITE : BP_MEM_READ); + BreakpointFlags wp_access =3D (access_type =3D=3D MMU_DATA_STO= RE + ? BP_MEM_WRITE : BP_MEM_READ); cpu_check_watchpoint(env_cpu(env), addr, size, full->attrs, wp_access, retaddr); } @@ -1701,7 +1702,8 @@ static void mmu_watch_or_dirty(CPUState *cpu, MMULook= upPageData *data, =20 /* On watchpoint hit, this will longjmp out. */ if (flags & TLB_WATCHPOINT) { - int wp =3D access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_M= EM_READ; + BreakpointFlags wp =3D access_type =3D=3D MMU_DATA_STORE ? BP_MEM_= WRITE + : BP_MEM_READ; cpu_check_watchpoint(cpu, addr, size, full->attrs, wp, ra); flags &=3D ~TLB_WATCHPOINT; } @@ -1884,7 +1886,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr a= ddr, MemOpIdx oi, } =20 if (unlikely(tlb_addr & TLB_WATCHPOINT)) { - int wp_flags =3D 0; + BreakpointFlags wp_flags =3D 0; =20 if (full->slow_flags[MMU_DATA_STORE] & TLB_WATCHPOINT) { wp_flags |=3D BP_MEM_WRITE; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index c179cd4ade..7ba682592c 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -115,20 +115,20 @@ static bool tcg_supports_guest_debug(void) } =20 /* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ -static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) +static inline BreakpointFlags xlat_gdb_type(CPUState *cpu, int gdbtype) { - static const int xlat[] =3D { + static const BreakpointFlags xlat[] =3D { [GDB_WATCHPOINT_WRITE] =3D BP_GDB | BP_MEM_WRITE, [GDB_WATCHPOINT_READ] =3D BP_GDB | BP_MEM_READ, [GDB_WATCHPOINT_ACCESS] =3D BP_GDB | BP_MEM_ACCESS, }; =20 - int cputype =3D xlat[gdbtype]; + BreakpointFlags cpuflags =3D xlat[gdbtype]; =20 if (cpu->cc->gdb_stop_before_watchpoint) { - cputype |=3D BP_STOP_BEFORE_ACCESS; + cpuflags |=3D BP_STOP_BEFORE_ACCESS; } - return cputype; + return cpuflags; } =20 static int tcg_insert_breakpoint(CPUState *cs, int type, vaddr addr, vaddr= len) diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index 28286e11a6..a10ff03922 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -22,13 +22,13 @@ void cpu_exec_reset_hold(CPUState *cpu) } =20 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - int flags, CPUWatchpoint **watchpoint) + BreakpointFlags flags, CPUWatchpoint **watchpoin= t) { return -ENOSYS; } =20 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, - vaddr len, int flags) + vaddr len, BreakpointFlags flags) { return -ENOSYS; } @@ -37,17 +37,18 @@ void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWat= chpoint *wp) { } =20 -void cpu_watchpoint_remove_all(CPUState *cpu, int mask) +void cpu_watchpoint_remove_all(CPUState *cpu, BreakpointFlags mask) { } =20 -int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len) +BreakpointFlags cpu_watchpoint_address_matches(CPUState *cpu, + vaddr addr, vaddr len) { return 0; } =20 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, - MemTxAttrs atr, int fl, uintptr_t ra) + MemTxAttrs atr, BreakpointFlags flags, uintptr_t= ra) { } =20 diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index c75ed27845..5ea66e9763 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -52,10 +52,11 @@ static inline bool watchpoint_address_matches(CPUWatchp= oint *wp, } =20 /* Return flags for watchpoints that match addr + prot. */ -int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len) +BreakpointFlags cpu_watchpoint_address_matches(CPUState *cpu, + vaddr addr, vaddr len) { CPUWatchpoint *wp; - int ret =3D 0; + BreakpointFlags ret =3D 0; =20 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (watchpoint_address_matches(wp, addr, len)) { @@ -67,7 +68,7 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr a= ddr, vaddr len) =20 /* Generate a debug exception if a watchpoint has been hit. */ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, - MemTxAttrs attrs, int flags, uintptr_t ra) + MemTxAttrs attrs, BreakpointFlags flags, uintptr= _t ra) { CPUWatchpoint *wp; =20 @@ -91,7 +92,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vadd= r len, =20 assert((flags & ~BP_MEM_ACCESS) =3D=3D 0); QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - int hit_flags =3D wp->flags & flags; + BreakpointFlags hit_flags =3D wp->flags & flags; =20 if (hit_flags && watchpoint_address_matches(wp, addr, len)) { if (replay_running_debug()) { diff --git a/cpu-common.c b/cpu-common.c index 988d057d84..bc77835aea 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -389,7 +389,7 @@ void process_queued_cpu_work(CPUState *cpu) } =20 /* Add a breakpoint. */ -int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, +int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, CPUBreakpoint **breakpoint) { CPUBreakpoint *bp; @@ -419,7 +419,7 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int = flags, } =20 /* Remove a specific breakpoint. */ -int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) +int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, BreakpointFlags flags) { CPUBreakpoint *bp; =20 @@ -446,7 +446,7 @@ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBre= akpoint *bp) } =20 /* Remove all matching breakpoints. */ -void cpu_breakpoint_remove_all(CPUState *cpu, int mask) +void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask) { CPUBreakpoint *bp, *next; =20 diff --git a/system/watchpoint.c b/system/watchpoint.c index 21d0bb36ca..3785ffff46 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -26,7 +26,7 @@ =20 /* Add a watchpoint. */ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - int flags, CPUWatchpoint **watchpoint) + BreakpointFlags flags, CPUWatchpoint **watchpoin= t) { CPUWatchpoint *wp; vaddr in_page; @@ -65,7 +65,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vadd= r len, =20 /* Remove a specific watchpoint. */ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, - int flags) + BreakpointFlags flags) { CPUWatchpoint *wp; =20 @@ -90,7 +90,7 @@ void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatch= point *watchpoint) } =20 /* Remove all matching watchpoints. */ -void cpu_watchpoint_remove_all(CPUState *cpu, int mask) +void cpu_watchpoint_remove_all(CPUState *cpu, BreakpointFlags mask) { CPUWatchpoint *wp, *next; =20 diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 07a52643e7..11043ecd58 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -550,7 +550,7 @@ void hw_watchpoint_update(ARMCPU *cpu, int n) vaddr wvr =3D env->cp15.dbgwvr[n]; uint64_t wcr =3D env->cp15.dbgwcr[n]; int mask; - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + BreakpointFlags flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; =20 if (env->cpu_watchpoint[n]) { cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); @@ -656,7 +656,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) uint64_t bcr =3D env->cp15.dbgbcr[n]; vaddr addr; int bt; - int flags =3D BP_CPU; + BreakpointFlags flags =3D BP_CPU; =20 if (env->cpu_breakpoint[n]) { cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index dca4ef5a94..17f920b3f3 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -190,7 +190,8 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int= ptr_mmu_idx, =20 /* Any debug exception has priority over a tag check exception. */ if (!probe && unlikely(flags & TLB_WATCHPOINT)) { - int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; + BreakpointFlags wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_RE= AD + : BP_MEM_WRITE; assert(ra !=3D 0); cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra); } diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 41edb18643..913920d55b 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -145,7 +145,7 @@ void ppc_update_daw(CPUPPCState *env, int rid) bool sv =3D extract32(dawrx, PPC_BIT_NR(62), 1); bool pr =3D extract32(dawrx, PPC_BIT_NR(62), 1); vaddr len; - int flags; + BreakpointFlags flags; =20 if (env->dawr_watchpoint[rid]) { cpu_watchpoint_remove_by_ref(cs, env->dawr_watchpoint[rid]); diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index b94c2997a0..2a3711fb1d 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1429,7 +1429,7 @@ static int find_hw_breakpoint(target_ulong addr, int = type) return -1; } =20 -static int find_hw_watchpoint(target_ulong addr, int *flag) +static int find_hw_watchpoint(target_ulong addr, BreakpointFlags *flag) { int n; =20 @@ -1575,7 +1575,6 @@ static int kvm_handle_hw_breakpoint(CPUState *cs, { int handle =3D DEBUG_RETURN_GUEST; int n; - int flag =3D 0; =20 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { @@ -1585,6 +1584,8 @@ static int kvm_handle_hw_breakpoint(CPUState *cs, } } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | KVMPPC_DEBUG_WATCH_WRITE)) { + BreakpointFlags flag =3D 0; + n =3D find_hw_watchpoint(arch_info->address, &flag); if (n >=3D 0) { handle =3D DEBUG_RETURN_GDB; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2db07f5dfb..c318dcd633 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -2000,7 +2000,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } else if (probe) { return false; } else { - int wp_access =3D 0; + BreakpointFlags wp_access =3D 0; =20 if (access_type =3D=3D MMU_DATA_LOAD) { wp_access |=3D BP_MEM_READ; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index ba5bc6ae13..fa47b2724e 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -480,7 +480,7 @@ static void type2_breakpoint_insert(CPURISCVState *env,= target_ulong index) target_ulong addr =3D env->tdata2[index]; bool enabled =3D type2_breakpoint_enabled(ctrl); CPUState *cs =3D env_cpu(env); - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + BreakpointFlags flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; uint32_t size, def_size; =20 if (!enabled) { @@ -605,7 +605,7 @@ static void type6_breakpoint_insert(CPURISCVState *env,= target_ulong index) target_ulong addr =3D env->tdata2[index]; bool enabled =3D type6_breakpoint_enabled(ctrl); CPUState *cs =3D env_cpu(env); - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + BreakpointFlags flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; uint32_t size; =20 if (!enabled) { @@ -994,7 +994,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) target_ulong ctrl; target_ulong addr; int trigger_type; - int flags; + BreakpointFlags flags; int i; =20 for (i =3D 0; i < env->num_triggers; i++) { diff --git a/target/s390x/tcg/debug.c b/target/s390x/tcg/debug.c index 99140b1ac9..d10e9ed892 100644 --- a/target/s390x/tcg/debug.c +++ b/target/s390x/tcg/debug.c @@ -14,7 +14,8 @@ =20 void s390_cpu_recompute_watchpoints(CPUState *cs) { - const int wp_flags =3D BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS; + const BreakpointFlags wp_flags =3D BP_CPU | BP_MEM_WRITE + | BP_STOP_BEFORE_ACCESS; CPUS390XState *env =3D cpu_env(cs); =20 /* We are called when the watchpoints have changed. First diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 3b91f7c38a..990012f60e 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -85,7 +85,7 @@ static void set_dbreak(CPUXtensaState *env, unsigned i, u= int32_t dbreaka, uint32_t dbreakc) { CPUState *cs =3D env_cpu(env); - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + BreakpointFlags flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; uint32_t mask =3D dbreakc | ~DBREAKC_MASK; =20 if (env->cpu_watchpoint[i]) { --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226890; cv=none; d=zohomail.com; s=zohoarc; b=L8TAHKf9UpqtFJXVqfSh5KDxH1MheWruzmwB0t8l5Y+44rxM4x/TYPkVhZVhjIdZpHztmEkLrkv+rrEALFHYWMUwUSxIGM67he4ch88oVBh714oezCOSxWrwAeLnF1jxHCWDIKPKGgnDLS8XzK0e/fAdbteqHyFlGgfHpyQRNdo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226890; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7F1gvRjgVsXT9ENvQ+iUAk5S2n1vMDcJKaBswrQ8elA=; b=mw/lFvfR3unQPixHEoA86JUMZ11x5/JwFCatQZqS1yTKYcf0rgdg/CMat0wBofqUi48Qv/c3yRr3la+d+JRZ1EIQ9AIehuLsnRRGx/sVsx96e1reZyNRjwLoIKE3NTtdBDrBoWlImxXg7QvCZ3Ziii8i014eHiTEjZVX0qGuPuU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226890966650.1841108825037; Sat, 4 Jul 2026 21:48:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEbx-0004nH-Ni; Sun, 05 Jul 2026 00:37:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEbq-0004ij-Ao for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:38 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbj-0003yt-97 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:38 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2cc80b585bfso2696675ad.0 for ; Sat, 04 Jul 2026 21:37:30 -0700 (PDT) Received: from stoup.. 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Merge both. No logical change intended. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20260630220100.1289-25-philmd@oss.qualcomm.com> --- target/arm/tcg/debug.c | 40 +++++++++++++++++----------------------- 1 file changed, 17 insertions(+), 23 deletions(-) diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 11043ecd58..7171501d40 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -351,28 +351,6 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_= wp) return true; } =20 -static bool check_watchpoints(ARMCPU *cpu) -{ - CPUARMState *env =3D &cpu->env; - int n; - - /* - * If watchpoints are disabled globally or we can't take debug - * exceptions here then watchpoint firings are ignored. - */ - if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 - || !arm_generate_debug_exceptions(env)) { - return false; - } - - for (n =3D 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) { - if (bp_wp_matches(cpu, n, true)) { - return true; - } - } - return false; -} - bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -426,8 +404,24 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatch= point *wp) * is also an architectural watchpoint match. */ ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + int n; =20 - return check_watchpoints(cpu); + /* + * If watchpoints are disabled globally or we can't take debug + * exceptions here then watchpoint firings are ignored. + */ + if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 + || !arm_generate_debug_exceptions(env)) { + return false; + } + + for (n =3D 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) { + if (bp_wp_matches(cpu, n, true)) { + return true; + } + } + return false; } =20 /* --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226861; cv=none; d=zohomail.com; s=zohoarc; b=mmFDwGlVwiQSsgp96D3cG2PFc3X2u9NnlJHbFlzyURa1jVfvIpcmJNRF6SU3QI3I4yTOWDD7hnkSs8aIREMrCwFJqkRv8853bsfOCaskTy2l7TTJ6SMzj3ZkgWNcnQ55DrURsQtpKCgtBIjW9GbuJPgXI9R61Ngk8BD4D7fk+vw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226861; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zZQKYJz7acBPOxECmB0e2sZSXiKoHybMCyGFRMtMCII=; b=A0dWrFX5tLrxg0246HLevMw8sb6DWrOwEerqYfkNUmfDiSsG7azDq/aC0KvyhdDgEXmn9MyB1j1KryULnbzoeHp4AyPCfKB8VVuOstfOBO3Da4fKSR+Z0D6b9gQ6HnYDFMlhZUgl/RuNiZAGomsdglVJZICQCxnKFTrr3m85coE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178322686129739.364403659641425; Sat, 4 Jul 2026 21:47:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEc8-0004u3-J5; Sun, 05 Jul 2026 00:37:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEbr-0004jx-O8 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:40 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbk-00040c-7O for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:39 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2cace91f112so14395205ad.0 for ; Sat, 04 Jul 2026 21:37:31 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20260630220100.1289-29-philmd@oss.qualcomm.com> --- include/accel/tcg/cpu-ops.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f64d94b2b5..568d82cdd3 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -250,14 +250,13 @@ struct TCGCPUOps { int mmu_idx, uintptr_t retaddr); =20 /** - * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by A= RM + * @adjust_watchpoint_address: hack for cpu_check_watchpoint (used by = ARM) */ vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); =20 /** * @debug_check_watchpoint: return true if the architectural - * watchpoint whose address has matched should really fire, used by ARM - * and RISC-V + * watchpoint whose address has matched should really fire. */ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); =20 --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226977; cv=none; d=zohomail.com; s=zohoarc; b=S6MZXA1L9pqoecJMzxH46Z/JKnAnYND1TcO/Q9Q9b1lv8ay/tBIUDnNfO5/0Uml2RwcOQxYqoMvwhYOxMrecr+OorJI74iY63V6+LRhgM00xC8+EqcukvHINzxMsCmUaTV4qFE3z8OTRRROhimn/Z0qi1G0h3EzjkcTHq1p6gw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226977; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aDmvLx7tFb72uym/SedzgMtxN4MKiCwduhbZZrMhn/8=; b=nXZf6IzyENrbTE23MSQgUxn+wKC3Gph/FLIsqUwEAKBIX7YI0uMzpHEmx9tpnRWFlQNs+C5zPiqVXr0mbwv1EfZ6wjJhbLWJCwBv3e1tmKmeaGP1Slb3TqP/QrCRfFgLKMcecsct7U8ZJTkNAHrTUNOe2MKJsQghXBppIyVff7g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226977943816.7502365768906; Sat, 4 Jul 2026 21:49:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEcA-0004w3-4Z; Sun, 05 Jul 2026 00:37:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEbr-0004jw-Mf for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:40 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbk-00041v-Ls for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:39 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2cae134bdc8so8703225ad.3 for ; Sat, 04 Jul 2026 21:37:32 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 17 +---------------- cpu-common.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2c58ea5e4c..71ed1f17a4 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1143,22 +1143,7 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, B= reakpointFlags flags, int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, BreakpointFlags flags); void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint= ); void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask); - -/* Return true if PC matches an installed breakpoint. */ -static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, - BreakpointFlags mask) -{ - CPUBreakpoint *bp; - - if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D pc && (bp->flags & mask)) { - return true; - } - } - } - return false; -} +bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, BreakpointFlags mask); =20 /** * cpu_get_address_space: diff --git a/cpu-common.c b/cpu-common.c index bc77835aea..ba2676cbad 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -388,6 +388,21 @@ void process_queued_cpu_work(CPUState *cpu) qemu_cond_broadcast(&qemu_work_cond); } =20 +/* Return true if PC matches an installed breakpoint. */ +bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, BreakpointFlags mask) +{ + CPUBreakpoint *bp; + + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc =3D=3D pc && (bp->flags & mask)) { + return true; + } + } + } + return false; +} + /* Add a breakpoint. */ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, CPUBreakpoint **breakpoint) --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226725; cv=none; d=zohomail.com; s=zohoarc; b=oHhgpMxtPpV3lX4EG4yB1TCTOAt8oNQNEmU024/m2vBwbg/yj2SXhLAuSuHi9OIgoGt2kWAJ06+w8vNRPca2zHrjnAFDJZkH0TAlsGMdCkXBwuVSEyrE/+nLPMow9JYrOpusteOJOgWrz3bldXK/4Xyw3LlmolUNR76QoJc3E5Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226725; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/67beO8XTF3m4SA3ioSNOjxwdmfJ7kOkKLq2brE5jyQ=; b=JhRB6f5T5g2swH/fXMS+0a9KSR/30rlnavUAMwt3yH7J4GFpzkMUIanfQ8TLWkP1NZBdkqqS5hSph38bNJRozcuN79BnlNSMAHlNT/60An5FdObLQWUP65K9u2iQdMiqB0cT3Afb9K+ZqLUd4War79fj0ptxiZLR9q5RRcJ6lxQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226725278772.0958592800936; Sat, 4 Jul 2026 21:45:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEcf-0005QU-2C; Sun, 05 Jul 2026 00:38:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEbu-0004lz-7G for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:42 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbl-00042N-Ai for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:41 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-2c7cfa17fedso18582945ad.3 for ; Sat, 04 Jul 2026 21:37:32 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- include/exec/breakpoint.h | 7 +++++++ include/hw/core/cpu.h | 7 ------- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index 0c3cc0c8ff..b06d7ed3c3 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -42,4 +42,11 @@ typedef struct CPUWatchpoint { QTAILQ_ENTRY(CPUWatchpoint) entry; } CPUWatchpoint; =20 +int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, + CPUBreakpoint **breakpoint); +int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, BreakpointFlags flags); +void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint= ); +void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask); +bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, BreakpointFlags mask); + #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 71ed1f17a4..e05e261883 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1138,13 +1138,6 @@ void qemu_init_vcpu(CPUState *cpu); */ void cpu_single_step(CPUState *cpu, int enabled); =20 -int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, - CPUBreakpoint **breakpoint); -int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, BreakpointFlags flags); -void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint= ); -void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask); -bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, BreakpointFlags mask); - /** * cpu_get_address_space: * @cpu: CPU to get address space from --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226364; cv=none; d=zohomail.com; s=zohoarc; b=eHDv9hmhfVVEnIxsU/q3ryaEckmAUSmXC5MJgmS3Hh/+Z/1wMTxFkJToFrjUOpAJ1poHaLhE7TbbDp2Hzo3WWwSm7argotT0lkF0gjhOIqGSSAoZl9oBzdMpzho+M8y7W3AdI3aO7PII9mwtzsinzNQYiWvlUFuo6iK3/bOaSCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226364; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0F3fk8w9xyY/qTXkRVeJjfw3GEmLZW+XiteX2I3+/OU=; b=QdErjfKgBYA4Yz8NjRkJTfj0VAy/9q7jqtWuW2QL+df44P/jy1o6q57/U1PJE3CG/O5gzj9mD2DAlkv3EtAVIRLMwe1eG+fHxfyAuHAhT3C+4Y2Ry/E0GBdSpy5l8KwE9oAhpvmpuPUZqtiHQVhZCfR8s5bo2j+3EnVwBwwnt2c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226364053360.21802596308135; Sat, 4 Jul 2026 21:39:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEcp-0005hx-Dz; Sun, 05 Jul 2026 00:38:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEbw-0004my-Fx for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:44 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbn-000435-1G for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:43 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-2cc7e86e7aeso3365415ad.2 for ; Sat, 04 Jul 2026 21:37:34 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226253; x=1783831053; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=0F3fk8w9xyY/qTXkRVeJjfw3GEmLZW+XiteX2I3+/OU=; b=U6/MMxrQYDGwqzNcEZwXroaUYvFgmsTIaHUKbh/hxVCJr6T6pcbyvVEvsrQXbRGsT1 ZusbAJmbeqYeHcbY4KXYsgfLHHkG2PA+FRLB3X+yDc5MNM0YdfV3X56rYnjaqfdxBK0h F2humGvGco5JW9rwxcNYoinY3sSmPFp/mF9VXBEygFtPqmmnkQiVmiooSxiJAkctq2XG kBnbGocVM2+pGvNuGvyNZWJqc3eds391nxKn9BgDRJ0zQ8LQWP+BiYfdRwZal/O9b77d J9hfCOGDzLL4rXqr+OmYW10ZRgBUb6vO8Spa8288sdpWOj55pGd0Ze/5Lrojl55XWa7G Qy7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226253; x=1783831053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=0F3fk8w9xyY/qTXkRVeJjfw3GEmLZW+XiteX2I3+/OU=; b=JQie/cPG8Np0w0o/QsiFXEh4YHTTpih9kQGEIMxIxTYjtfZ+aIOcG8Hu0+OsLPhZWx 0/6a5vspmrTU0Ot/Q0saAhY8B7rCT4n2UFm10O2EutyHKn1+LfIsvDMKkPqjPgLICGQo bOmnK9/avrQ8+UIzPXGIccHzd4cbWdS3F2Qw+Hxn5LG+dbqstkhylUPxVNhlNoQ3HSOs szF3Qqbjt/rRTZAh+yoHYLJrp3z8gOAZd/5FWBK23Q3RZCy8feDnu2iH+4njKevu6gPp N1nng0nL1AZhN94W3sZcVl3kgYNi1WJGoi0Yit5i4JwGL0nZeaq8hs3bJ4On0hNDvonu Tjsw== X-Gm-Message-State: AOJu0YzETrRzFeg0tG1xy37ujC5mZcznpvKmTPpfqX9rBK40TxGvr0cw ISCGvDpRa8s5XUF5NXMyBMDB1SQHQTg/iAXUtMvrSU1SPsKd/EJnWyl6PEfFMilWgBrdVI74+Y6 XRDbV X-Gm-Gg: AfdE7ckESvZMvZJ+wVxiSUiWgve5J/G8HmJYrm9zcmKPSqmSjLyTXn2EUIUbJ4U1YHn sDyI8aDtjU8oKJnWnmb90ewIF/xlYqtfLRWRUFvoLugtsPsWXoLKWsF8+jSnux/MwmMAL0roj9X RIs2kjxImycRbvR2D/0upHybMvTjNlCRvG7VppQdreJXNED4MXw5vlsviGbg6QLWBuTEiL9F7vP HVgFWQLkomlobZdGrpooPN+ackcYVpoSDEjocz/Yy7Kcl9uQyuzEcaFbznL2/O4035es/lQs/ZV w4YGRlj7FL3gyUduoZKsJOBQp7e+/spUSwtNAJsRfpZ9hJ6YNioGkykc9qd/Bi1XSqagIBk/g3K qrMsEbZZXqW20LOoWiUGp8jz3/ITqcNTnjINtljVw01+Z+/lB7m+Ykj49P+OjpOXpCAmRZl5Q6R PPNmKH/1BeON0kNtgiLo+zDG2hV5hXj7zfbYJuxPibj9rBR9c= X-Received: by 2002:a17:903:41ca:b0:2c2:62ee:5a0d with SMTP id d9443c01a7336-2cbb9c39bd4mr53629515ad.14.1783226253221; Sat, 04 Jul 2026 21:37:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 07/46] exec/breakpoint: Merge watchpoint.h Date: Sat, 4 Jul 2026 21:36:46 -0700 Message-ID: <20260705043725.1373137-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226365405158500 Content-Type: text/plain; charset="utf-8" Move the contents of watchpoint.h into breakpoint.h. Adjust all users of exec/watchpoint.h. Signed-off-by: Richard Henderson --- include/exec/breakpoint.h | 7 +++++++ include/exec/watchpoint.h | 20 -------------------- accel/tcg/tcg-accel-ops.c | 2 +- accel/tcg/user-exec-stub.c | 2 +- system/watchpoint.c | 2 +- target/arm/debug_helper.c | 2 +- target/arm/tcg/debug.c | 2 +- target/i386/cpu.c | 2 +- target/i386/machine.c | 2 +- target/i386/tcg/system/bpt_helper.c | 2 +- target/ppc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/debug.c | 2 +- target/s390x/helper.c | 1 - target/s390x/tcg/debug.c | 1 - target/xtensa/dbg_helper.c | 2 +- 16 files changed, 19 insertions(+), 34 deletions(-) delete mode 100644 include/exec/watchpoint.h diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index b06d7ed3c3..4a025edc96 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -49,4 +49,11 @@ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBrea= kpoint *breakpoint); void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask); bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, BreakpointFlags mask); =20 +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, + BreakpointFlags flags, CPUWatchpoint **watchpoin= t); +int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, + vaddr len, BreakpointFlags flags); +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); +void cpu_watchpoint_remove_all(CPUState *cpu, BreakpointFlags mask); + #endif diff --git a/include/exec/watchpoint.h b/include/exec/watchpoint.h deleted file mode 100644 index a09daf47f1..0000000000 --- a/include/exec/watchpoint.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * CPU watchpoints - * - * Copyright (c) 2012 SUSE LINUX Products GmbH - * SPDX-License-Identifier: LGPL-2.1-or-later - */ - -#ifndef EXEC_WATCHPOINT_H -#define EXEC_WATCHPOINT_H - -#include "exec/breakpoint.h" - -int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - BreakpointFlags flags, CPUWatchpoint **watchpoin= t); -int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, - vaddr len, BreakpointFlags flags); -void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); -void cpu_watchpoint_remove_all(CPUState *cpu, BreakpointFlags mask); - -#endif /* EXEC_WATCHPOINT_H */ diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 7ba682592c..38e0a038c4 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -39,7 +39,7 @@ #include "exec/hwaddr.h" #include "exec/tb-flush.h" #include "exec/translation-block.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "gdbstub/enums.h" =20 #include "hw/core/cpu.h" diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index a10ff03922..973bdbcd7a 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -2,7 +2,7 @@ #include "hw/core/cpu.h" #include "accel/tcg/cpu-ops.h" #include "exec/replay-core.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "internal-common.h" =20 void cpu_resume(CPUState *cpu) diff --git a/system/watchpoint.c b/system/watchpoint.c index 3785ffff46..67e4560e78 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -21,7 +21,7 @@ #include "qemu/error-report.h" #include "exec/cputlb.h" #include "exec/target_page.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "hw/core/cpu.h" =20 /* Add a watchpoint. */ diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 8477ca5def..2c3a56c7d5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -11,7 +11,7 @@ #include "internals.h" #include "cpu-features.h" #include "cpregs.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "system/tcg.h" =20 /* diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 7171501d40..f245d5b072 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -12,7 +12,7 @@ #include "internals.h" #include "cpu-features.h" #include "cpregs.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "system/tcg.h" =20 /* Return the Exception Level targeted by debug exceptions. */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5805d33ab9..7a7cd38b14 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -39,7 +39,7 @@ #include "standard-headers/asm-x86/kvm_para.h" #include "hw/core/qdev-properties.h" #include "hw/i386/topology.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #ifndef CONFIG_USER_ONLY #include "confidential-guest.h" #include "monitor/hmp.h" diff --git a/target/i386/machine.c b/target/i386/machine.c index 1f5c517e56..cc1974126e 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -7,7 +7,7 @@ #include "hw/i386/x86.h" #include "kvm/kvm_i386.h" #include "hw/xen/xen.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "system/kvm.h" #include "system/kvm_xen.h" #include "system/tcg.h" diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index 2feea69c8a..0ba2f01016 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -21,7 +21,7 @@ #include "accel/tcg/cpu-loop.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "tcg/helper-tcg.h" =20 =20 diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 913920d55b..0306e2f57a 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -22,7 +22,7 @@ #include "cpu-models.h" #include "cpu-qom.h" #include "exec/log.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "fpu/softfloat-helpers.h" #include "mmu-hash64.h" #include "helper_regs.h" diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index a02187ce5a..6211a586e7 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -41,7 +41,7 @@ #include "disas/capstone.h" #include "fpu/softfloat.h" #include "exec/page-protection.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "helper_regs.h" #include "internal.h" #include "spr_common.h" diff --git a/target/riscv/debug.c b/target/riscv/debug.c index fa47b2724e..b8fea64bec 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -31,7 +31,7 @@ #include "target/riscv/debug.h" #include "trace.h" #include "exec/helper-proto.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "system/cpu-timers.h" #include "exec/icount.h" =20 diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 1a2658eaf9..dabf8571cd 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -27,7 +27,6 @@ #include "system/memory.h" #include "system/runstate.h" #include "exec/target_page.h" -#include "exec/watchpoint.h" =20 void s390x_tod_timer(void *opaque) { diff --git a/target/s390x/tcg/debug.c b/target/s390x/tcg/debug.c index d10e9ed892..7a838775ec 100644 --- a/target/s390x/tcg/debug.c +++ b/target/s390x/tcg/debug.c @@ -6,7 +6,6 @@ =20 #include "qemu/osdep.h" #include "exec/breakpoint.h" -#include "exec/watchpoint.h" #include "accel/tcg/cpu-loop.h" #include "target/s390x/cpu.h" #include "target/s390x/s390x-internal.h" diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 990012f60e..e180096b42 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -30,7 +30,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" -#include "exec/watchpoint.h" +#include "exec/breakpoint.h" #include "system/address-spaces.h" =20 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226693; 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226254; x=1783831054; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HOLBFbN0uOhvFbQGnMluLfThJPMU4L7hEEZlVe52VyI=; b=J8+4iAwUSOzyiEobgLUyIIP8HviJ3PzRh0Rlyh5fpvpzzAcXox2JhYcIw9V62we0vE 0649N4GEcAE5dmQY38jXy+OEiREQnNZw2Lf2YEQZTQjkSpaulwNH+DhmqPYeCp0Sk/up oNh+5W6E92TwbaKGE1ybyhxeyZRSzHeq8XMNPlLSme08DkAKplM/GMzzDI+kt6naVGUd KAk5qZ3G5GxPqRHzK3vgjCYvjW/49vSHfNI/CgXahZJiOL7LIuhdvCU4iqBoaO4yDMjv u/rG7JKkB7aINosgK3ElzSBStLhrfwZmB6yoG4i96i6AJh5hVDg9AdWmJ870R00IR4pl FNKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226254; x=1783831054; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=HOLBFbN0uOhvFbQGnMluLfThJPMU4L7hEEZlVe52VyI=; b=emXSwiSD/mlu239gQ7PN56C0HAERtEsjwSLlFl4NJhKAmld9ICoILu9gtAFCGoJgex tv59guKdccjp9qnLonCAV+SBeJdVDc+3WoNgD4z9nf81uk6ayoiKGy+vv6/383E785cB zf2g5Pb5oFnhpkvfVImUctDB/kgAU0vzi5o8QeCkxKSxGy4zfb5u8feTSH1Vtm4YSHSV dc8+C1LP0DFDCcbeCKUSaqfl8MCumKPmzRoRt7SQzNR1CzuOXxokCTvZDT9R6yeMM23F +mzi2daF1AV4OowMUcQe+jRzo/4/iBPYwpCnkCQyI+C19arkId4tgUfof2xTpdMy3nY/ BpuQ== X-Gm-Message-State: AOJu0YxGXd4jU6Nl4AEM6XNNKkwd1f+eXstXy+nNAyOT0b6njKyIqRLi 0M8xVED7IuEKvVafmkRzd8UdSbZ8o5pcdGZc92yebAQz8vjqFE2GXZ/lrnEZZcSZSAhvOirqZGv FyYKv X-Gm-Gg: AfdE7ckHA3CoXC60uVhrmTnzuxrtPpsp5UQ0j5B8JXtCVj+rmL5w9bXO+bvFwre4Myb ZXPqcA04sFstJQCTBs3fvszoXy6y7s2whGzygslnXkazT0Dy6yTKgId670uBeQkpLljMBnQSxdt n3eUKlZh2fLpiJC2nrOk7FO9N92l0DcY+99Ol19ksKWisWWxlCfiDZ8XIe0XMlI7efehrZnHLu2 6HVQqjRiq2OVGGkhbg7yEBYKD9W19Lww02iMya6z5WGc58W5Sr9caATUiWAWaV4uXNmqCIaV7V7 RPGSCclMoeXvAM/uesBJHBSbx48CAaSEBlAIVneyYs+EmSvEJr7DrP7U5DgVuuu6GN9x9DbFkQH q6i3U8KVWyGhMo34+R0oo7+OTsrIr+P+yaJRv+7zhqZjE+yH6SLW/DLtyyxao7MTA67tvjGyJzm MHUhqG+gDyN/4QFZG/KgsQPljX8WhTJrh39Z6aGOD23xRTw88= X-Received: by 2002:a17:903:2c8:b0:2c8:25c8:85a6 with SMTP id d9443c01a7336-2cbb83679b2mr51676015ad.2.1783226254013; Sat, 04 Jul 2026 21:37:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 08/46] qemu/typedefs: Declare CPUBreakpoint and CPUWatchpoint globally Date: Sat, 4 Jul 2026 21:36:47 -0700 Message-ID: <20260705043725.1373137-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226693730158500 Content-Type: text/plain; charset="utf-8" Adjust all uses of 'struct' in the uses of this type. Signed-off-by: Richard Henderson --- include/exec/breakpoint.h | 8 ++++---- include/hw/core/cpu.h | 2 -- include/qemu/typedefs.h | 2 ++ target/arm/cpu.h | 4 ++-- target/i386/cpu.h | 4 ++-- target/ppc/cpu.h | 4 ++-- target/riscv/cpu.h | 4 ++-- target/xtensa/cpu.h | 4 ++-- target/riscv/debug.c | 4 ++-- 9 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index 4a025edc96..1a3391ac09 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -27,20 +27,20 @@ typedef int BreakpointFlags; #define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT) #define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) =20 -typedef struct CPUBreakpoint { +struct CPUBreakpoint { vaddr pc; BreakpointFlags flags; QTAILQ_ENTRY(CPUBreakpoint) entry; -} CPUBreakpoint; +}; =20 -typedef struct CPUWatchpoint { +struct CPUWatchpoint { vaddr vaddr; vaddr len; vaddr hitaddr; MemTxAttrs hitattrs; int flags; /* BP_* */ QTAILQ_ENTRY(CPUWatchpoint) entry; -} CPUWatchpoint; +}; =20 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, CPUBreakpoint **breakpoint); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e05e261883..160db776d8 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -84,8 +84,6 @@ DECLARE_CLASS_CHECKERS(CPUClass, CPU, typedef struct ArchCPU CpuInstanceType; \ OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); =20 -typedef struct CPUWatchpoint CPUWatchpoint; - /* see physmem.c */ struct CPUAddressSpace; =20 diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 2344c92182..919fe8ebff 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -39,9 +39,11 @@ typedef struct Chardev Chardev; typedef struct Clock Clock; typedef struct ConfidentialGuestSupport ConfidentialGuestSupport; typedef struct CPUArchState CPUArchState; +typedef struct CPUBreakpoint CPUBreakpoint; typedef struct CPUPluginState CPUPluginState; typedef struct CPUState CPUState; typedef struct CPUTLBEntryFull CPUTLBEntryFull; +typedef struct CPUWatchpoint CPUWatchpoint; typedef struct DeviceState DeviceState; typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot; typedef struct DisasContextBase DisasContextBase; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 84d33e87dc..973522cd55 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -754,8 +754,8 @@ typedef struct CPUArchState { ARMVectorReg za[ARM_MAX_VQ * 16]; } za_state; =20 - struct CPUBreakpoint *cpu_breakpoint[16]; - struct CPUWatchpoint *cpu_watchpoint[16]; + CPUBreakpoint *cpu_breakpoint[16]; + CPUWatchpoint *cpu_watchpoint[16]; =20 /* Optional fault info across tlb lookup. */ ARMMMUFaultInfo *tlb_fi; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e6a197602d..9dbfa7c9b9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2185,8 +2185,8 @@ typedef struct CPUArchState { target_ulong exception_next_eip; target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ union { - struct CPUBreakpoint *cpu_breakpoint[4]; - struct CPUWatchpoint *cpu_watchpoint[4]; + CPUBreakpoint *cpu_breakpoint[4]; + CPUWatchpoint *cpu_watchpoint[4]; }; /* break/watchpoints for dr[0..3] */ int old_exception; /* exception in flight */ =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 057c54bbb8..d06f3dfd7f 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1320,8 +1320,8 @@ struct CPUArchState { /* MMU context, only relevant for full system emulation */ #if defined(TARGET_PPC64) ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ - struct CPUBreakpoint *ciabr_breakpoint; - struct CPUWatchpoint *dawr_watchpoint[2]; + CPUBreakpoint *ciabr_breakpoint; + CPUWatchpoint *dawr_watchpoint[2]; #endif target_ulong sr[32]; /* segment registers */ uint32_t nb_BATs; /* number of BATs */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bdd28d329b..9cd38d10a3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -491,8 +491,8 @@ struct CPUArchState { uint64_t *tdata1; uint64_t *tdata2; uint64_t *tdata3; - struct CPUBreakpoint **cpu_breakpoint; - struct CPUWatchpoint **cpu_watchpoint; + CPUBreakpoint **cpu_breakpoint; + CPUWatchpoint **cpu_watchpoint; QEMUTimer **itrigger_timer; int64_t last_icount; bool itrigger_enabled; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 442e98bd1b..ab42b4be00 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -545,9 +545,9 @@ struct CPUArchState { unsigned static_vectors; =20 /* Watchpoints for DBREAK registers */ - struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; + CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; /* Breakpoints for IBREAK registers */ - struct CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK]; + CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK]; }; =20 /** diff --git a/target/riscv/debug.c b/target/riscv/debug.c index b8fea64bec..67c09b1a53 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -1060,8 +1060,8 @@ void riscv_trigger_realize(CPURISCVState *env) env->tdata1 =3D g_new0(uint64_t, env->num_triggers); env->tdata2 =3D g_new0(uint64_t, env->num_triggers); env->tdata3 =3D g_new0(uint64_t, env->num_triggers); - env->cpu_breakpoint =3D g_new0(struct CPUBreakpoint *, env->num_trigge= rs); - env->cpu_watchpoint =3D g_new0(struct CPUWatchpoint *, env->num_trigge= rs); + env->cpu_breakpoint =3D g_new0(CPUBreakpoint *, env->num_triggers); + env->cpu_watchpoint =3D g_new0(CPUWatchpoint *, env->num_triggers); env->itrigger_timer =3D g_new0(QEMUTimer *, env->num_triggers); =20 for (i =3D 0; i < env->num_triggers; i++) { --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226441; cv=none; d=zohomail.com; s=zohoarc; b=Aa20hR/rSk6B5tPwFuK9O3G3lXtuWjqxqyQo1pnylk38TC6zG+Bjo8bwCGPivEprEGs1hGafEN1fsHTqL8z1Bu3dn/ZYpBFh17Jxe455qE309oFvw/u1EfxjY0p17+hJ6qUEBU8BjBba9U+dhzSLWruz59h44UfK6BAip0T3b2I= ARC-Message-Signature: i=1; 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226255; x=1783831055; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IGDPhHwhZn4CtpoFYLi1kN7SQDwt8mZK08F0u+/IPxo=; b=P4iDrzxuiqP9WkWRlO+s7/yDn94SvkU5cqghNu5oDBLM8XYLH2lazv2ogb2Z5l/wey Qdq5BRnLB+W5kiWoRj9Up4whQ6Wnj/gWAmg/AS+NTZTHFLoC0q8ujgmDtLhTv+PLIP/t 1g+goHRNciltObCkgS2j4XkbaYaoJIHsHKDtE178Sx+ArEBYnmPwgR7d1xUaLz5PG6sP 18L9gYksouRpi7Upzkw4Le4OWj6PMmLZRMcFlRBMOvBQ/60cKXSx9kg/M0bFs9mt6o1o Sxipl4861HHiNx+qW71CSz/nlKUsJPiJX/ffjvBYFfSZVbArYG/2Af5jcHMdCVmG2Tc2 rEgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226255; x=1783831055; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=IGDPhHwhZn4CtpoFYLi1kN7SQDwt8mZK08F0u+/IPxo=; b=iYsN94ePnwn0mY1lZzSrFiDtl4We+WWy/by5wznvese96FD2VV/cJIouqlTAwJ5T+R 3akDfUZ26DluP68joyiiySAN/wAIdCguMlXIgvUkd/zkJAv/5mJfSPYSmZ4lsaeuC2La zQX1ma+JQrQtf6oDOFj4yN4njezsM8ej/SkVRMEsEVN0xCx/rtD0awOWBPzhILz2yPTU jkgtCq+PyKW+ClJ11Byj0PToRsZAqjjIE1PRQy1P+oSayX2x+Jo0F/ryR/AeaHgyb/F9 l2LONuEgJ1HbUtnAZD9pnzXJNNSUF0CtDfHWIJ6tFZ4Ui7dp6PzlE/J7LIOJd15jiZ2u /5eg== X-Gm-Message-State: AOJu0Yzy26wxMtyIBo+yvaxYv0bXjhNa8q4+2SavHgt1LCyUq85beoFX l7XbSl2bmxM73vpS+c+HkIkw2ovPVTIDP38tTsoCEMX67dEMeMRnpQtoHUpLxnaV7KsOm+2LEQA GHNt/ X-Gm-Gg: AfdE7clQZhpbgGxSPS6Y7TVucf7Afhb1LNfqWOSGoAwCEejkUTvTjrRXbIDcU9cChPJ avUL/aGS/6QCDeJ/vWzJeaW9WqtIPhrFUCb8EEJFJwECPLTpUjDNefpF+206yveBPu5wZw12SHk Nk+HuWyn674JVZrq3SqRcX9+2nbSeC07w6LZhnU5vTq5BbiFzTXBkR3Obyw9yb06gxcfaAr7UuW FOM7lHANeJvvs2AdFyY85wNrrkA/f/Cc3Ajbb/HBQjfdn4gRagi0L/EM3BD+yT0Us6+TokNl5mi eQqeRQ0gDhdmVGU1QWOLrp/RVKIKHitawpE/DvVf3jJZ9Mh4EO7mRYsMEi2qUWze49+M0dZgEia Kz3xyPx1jXl8pRxycmP1r7X+1KaRaiN1W2/XpGNXZ1SYs5WctG7SL9G8J+dYtNKuQaCsxtnwVky G7JBU0u+BVd+lbEtx0ke1Drjko1rw0tM4NxXFV9CumXuw9bcbD3S3j9Qwqng== X-Received: by 2002:a17:902:f60a:b0:2c7:f12d:5d37 with SMTP id d9443c01a7336-2cbb9e264d9mr49486075ad.17.1783226254795; Sat, 04 Jul 2026 21:37:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 09/46] hw/core/cpu: Remove exec/breakpoint.h include Date: Sat, 4 Jul 2026 21:36:48 -0700 Message-ID: <20260705043725.1373137-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226443016158500 Content-Type: text/plain; charset="utf-8" This is no longer required in the generic header. Add includes where required elsewhere in the code base. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 - accel/tcg/tcg-accel-ops.c | 1 + cpu-common.c | 1 + gdbstub/system.c | 1 + gdbstub/user.c | 1 + target/i386/kvm/kvm.c | 1 + target/ppc/kvm.c | 1 + target/s390x/kvm/kvm.c | 1 + target/xtensa/helper.c | 1 + 9 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 160db776d8..ca0b0c7978 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -22,7 +22,6 @@ =20 #include "hw/core/qdev.h" #include "disas/dis-asm.h" -#include "exec/breakpoint.h" #include "exec/hwaddr.h" #include "exec/vaddr.h" #include "exec/memattrs.h" diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 38e0a038c4..5c30a7be88 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -31,6 +31,7 @@ #include "accel/tcg/cpu-loop.h" #include "system/tcg.h" #include "system/replay.h" +#include "exec/breakpoint.h" #include "exec/icount.h" #include "qemu/main-loop.h" #include "qemu/guest-random.h" diff --git a/cpu-common.c b/cpu-common.c index ba2676cbad..af64bb1126 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "exec/cpu-common.h" +#include "exec/breakpoint.h" #include "hw/core/cpu.h" #include "qemu/lockable.h" #include "trace/trace-root.h" diff --git a/gdbstub/system.c b/gdbstub/system.c index 2063b63b2f..0b810477ee 100644 --- a/gdbstub/system.c +++ b/gdbstub/system.c @@ -15,6 +15,7 @@ #include "qemu/error-report.h" #include "qemu/cutils.h" #include "exec/gdbstub.h" +#include "exec/breakpoint.h" #include "gdbstub/syscalls.h" #include "gdbstub/commands.h" #include "exec/hwaddr.h" diff --git a/gdbstub/user.c b/gdbstub/user.c index 97eb13e796..05fe18f906 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -14,6 +14,7 @@ #include "qemu/cutils.h" #include "qemu/sockets.h" #include "qapi/error.h" +#include "exec/breakpoint.h" #include "exec/hwaddr.h" #include "exec/gdbstub.h" #include "gdbstub/commands.h" diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 64cc421abe..54bee753fa 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -68,6 +68,7 @@ #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "migration/blocker.h" +#include "exec/breakpoint.h" #include "exec/memattrs.h" #include "exec/target_page.h" #include "trace.h" diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 2a3711fb1d..c44edac41f 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -40,6 +40,7 @@ #include "system/watchdog.h" #include "trace.h" #include "gdbstub/enums.h" +#include "exec/breakpoint.h" #include "exec/memattrs.h" #include "system/ramblock.h" #include "system/hostmem.h" diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index fdef8f9e8a..9658534fa6 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -48,6 +48,7 @@ #include "hw/s390x/s390-pci-bus.h" #include "hw/s390x/ipl.h" #include "hw/s390x/ebcdic.h" +#include "exec/breakpoint.h" #include "exec/memattrs.h" #include "hw/s390x/s390-virtio-ccw.h" #include "hw/s390x/s390-hypercall.h" diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 5a0e865514..0db5502287 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -30,6 +30,7 @@ #include "cpu.h" #include "exec/cputlb.h" #include "exec/target_page.h" +#include "exec/breakpoint.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-loop.h" --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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For all targets the index of the hardware breakpoint resource is to hand. Signed-off-by: Richard Henderson --- include/exec/breakpoint.h | 3 ++- accel/tcg/tcg-accel-ops.c | 2 +- cpu-common.c | 3 ++- gdbstub/user.c | 2 +- linux-user/main.c | 2 +- target/arm/tcg/debug.c | 2 +- target/i386/tcg/system/bpt_helper.c | 2 +- target/ppc/cpu.c | 2 +- target/riscv/debug.c | 5 +++-- target/xtensa/dbg_helper.c | 4 ++-- 10 files changed, 15 insertions(+), 12 deletions(-) diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index 1a3391ac09..b22b6dabf2 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -30,6 +30,7 @@ typedef int BreakpointFlags; struct CPUBreakpoint { vaddr pc; BreakpointFlags flags; + unsigned id; QTAILQ_ENTRY(CPUBreakpoint) entry; }; =20 @@ -43,7 +44,7 @@ struct CPUWatchpoint { }; =20 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, - CPUBreakpoint **breakpoint); + unsigned id, CPUBreakpoint **breakpoint); int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, BreakpointFlags flags); void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint= ); void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask); diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 5c30a7be88..44bc5faf08 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -141,7 +141,7 @@ static int tcg_insert_breakpoint(CPUState *cs, int type= , vaddr addr, vaddr len) case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: CPU_FOREACH(cpu) { - err =3D cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + err =3D cpu_breakpoint_insert(cpu, addr, BP_GDB, 0, NULL); if (err) { break; } diff --git a/cpu-common.c b/cpu-common.c index af64bb1126..9476bb612a 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -406,7 +406,7 @@ bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, Break= pointFlags mask) =20 /* Add a breakpoint. */ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, - CPUBreakpoint **breakpoint) + unsigned id, CPUBreakpoint **breakpoint) { CPUBreakpoint *bp; =20 @@ -418,6 +418,7 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, Brea= kpointFlags flags, =20 bp->pc =3D pc; bp->flags =3D flags; + bp->id =3D id; =20 /* keep all GDB-injected breakpoints in front */ if (flags & BP_GDB) { diff --git a/gdbstub/user.c b/gdbstub/user.c index 05fe18f906..abcb2ec5f0 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -812,7 +812,7 @@ int gdb_breakpoint_insert(CPUState *cs, int type, vaddr= addr, vaddr len) case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: CPU_FOREACH(cpu) { - err =3D cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + err =3D cpu_breakpoint_insert(cpu, addr, BP_GDB, 0, NULL); if (err) { break; } diff --git a/linux-user/main.c b/linux-user/main.c index c08c73fd80..83b9c88ac4 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -260,7 +260,7 @@ CPUArchState *cpu_copy(CPUArchState *env) BP_CPU break/watchpoints are handled correctly on clone. */ QTAILQ_INIT(&new_cpu->breakpoints); QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); + cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, 0, NULL); } =20 return new_env; diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index f245d5b072..73d694ca4f 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -726,7 +726,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) return; } =20 - cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); + cpu_breakpoint_insert(CPU(cpu), addr, flags, n, &env->cpu_breakpoint[n= ]); } =20 void hw_breakpoint_update_all(ARMCPU *cpu) diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index 0ba2f01016..d847d77d71 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -62,7 +62,7 @@ static int hw_breakpoint_insert(CPUX86State *env, int ind= ex) switch (hw_breakpoint_type(dr7, index)) { case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(dr7, index)) { - err =3D cpu_breakpoint_insert(cs, drN, BP_CPU, + err =3D cpu_breakpoint_insert(cs, drN, BP_CPU, index, &env->cpu_breakpoint[index]); } break; diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 0306e2f57a..d77b88505f 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -121,7 +121,7 @@ void ppc_update_ciabr(CPUPPCState *env) } =20 if (priv) { - cpu_breakpoint_insert(cs, ciea, BP_CPU, &env->ciabr_breakpoint); + cpu_breakpoint_insert(cs, ciea, BP_CPU, 0, &env->ciabr_breakpoint); } } =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 67c09b1a53..bf9accf6e8 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -488,7 +488,7 @@ static void type2_breakpoint_insert(CPURISCVState *env,= target_ulong index) } =20 if (ctrl & TYPE2_EXEC) { - cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]= ); + cpu_breakpoint_insert(cs, addr, flags, 0, &env->cpu_breakpoint[ind= ex]); } =20 if (ctrl & TYPE2_LOAD) { @@ -613,7 +613,8 @@ static void type6_breakpoint_insert(CPURISCVState *env,= target_ulong index) } =20 if (ctrl & TYPE6_EXEC) { - cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]= ); + cpu_breakpoint_insert(cs, addr, flags, index, + &env->cpu_breakpoint[index]); } =20 if (ctrl & TYPE6_LOAD) { diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index e180096b42..4cf147bbfb 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -43,7 +43,7 @@ void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32= _t v) if (change & (1 << i)) { if (v & (1 << i)) { cpu_breakpoint_insert(cs, env->sregs[IBREAKA + i], - BP_CPU, &env->cpu_breakpoint[i]); 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For most targets the index of the hardware breakpoint resource is to hand. For s390x, there is only one resource so use id 0. Signed-off-by: Richard Henderson --- include/exec/breakpoint.h | 4 +++- accel/tcg/tcg-accel-ops.c | 2 +- accel/tcg/user-exec-stub.c | 3 ++- system/watchpoint.c | 3 ++- target/arm/tcg/debug.c | 2 +- target/i386/tcg/system/bpt_helper.c | 4 ++-- target/ppc/cpu.c | 3 ++- target/riscv/debug.c | 8 ++++---- target/s390x/tcg/debug.c | 11 +++++------ target/xtensa/dbg_helper.c | 2 +- 10 files changed, 23 insertions(+), 19 deletions(-) diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index b22b6dabf2..963ea992cb 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -40,6 +40,7 @@ struct CPUWatchpoint { vaddr hitaddr; MemTxAttrs hitattrs; int flags; /* BP_* */ + unsigned id; QTAILQ_ENTRY(CPUWatchpoint) entry; }; =20 @@ -51,7 +52,8 @@ void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointF= lags mask); bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, BreakpointFlags mask); =20 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - BreakpointFlags flags, CPUWatchpoint **watchpoin= t); + BreakpointFlags flags, unsigned id, + CPUWatchpoint **watchpoint); int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, BreakpointFlags flags); void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 44bc5faf08..37cdd354f0 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -152,7 +152,7 @@ static int tcg_insert_breakpoint(CPUState *cs, int type= , vaddr addr, vaddr len) case GDB_WATCHPOINT_ACCESS: CPU_FOREACH(cpu) { err =3D cpu_watchpoint_insert(cpu, addr, len, - xlat_gdb_type(cpu, type), NULL); + xlat_gdb_type(cpu, type), 0, NULL); if (err) { break; } diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index 973bdbcd7a..42e4861868 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -22,7 +22,8 @@ void cpu_exec_reset_hold(CPUState *cpu) } =20 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - BreakpointFlags flags, CPUWatchpoint **watchpoin= t) + BreakpointFlags flags, unsigned id, + CPUWatchpoint **watchpoint) { return -ENOSYS; } diff --git a/system/watchpoint.c b/system/watchpoint.c index 67e4560e78..a618bb5acd 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -26,7 +26,8 @@ =20 /* Add a watchpoint. */ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - BreakpointFlags flags, CPUWatchpoint **watchpoin= t) + BreakpointFlags flags, unsigned id, + CPUWatchpoint **watchpoint) { CPUWatchpoint *wp; vaddr in_page; diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 73d694ca4f..50b90ad675 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -622,7 +622,7 @@ void hw_watchpoint_update(ARMCPU *cpu, int n) wvr +=3D basstart; } =20 - cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, + cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, n, &env->cpu_watchpoint[n]); } =20 diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index d847d77d71..662ffbacfc 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -76,7 +76,7 @@ static int hw_breakpoint_insert(CPUX86State *env, int ind= ex) if (hw_breakpoint_enabled(dr7, index)) { err =3D cpu_watchpoint_insert(cs, drN, hw_breakpoint_len(dr7, index), - BP_CPU | BP_MEM_WRITE, + BP_CPU | BP_MEM_WRITE, index, &env->cpu_watchpoint[index]); } break; @@ -85,7 +85,7 @@ static int hw_breakpoint_insert(CPUX86State *env, int ind= ex) if (hw_breakpoint_enabled(dr7, index)) { err =3D cpu_watchpoint_insert(cs, drN, hw_breakpoint_len(dr7, index), - BP_CPU | BP_MEM_ACCESS, + BP_CPU | BP_MEM_ACCESS, index, &env->cpu_watchpoint[index]); } break; diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index d77b88505f..cf4d97285e 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -169,7 +169,8 @@ void ppc_update_daw(CPUPPCState *env, int rid) flags |=3D BP_MEM_WRITE; } =20 - cpu_watchpoint_insert(cs, deaw, len, flags, &env->dawr_watchpoint[rid]= ); + cpu_watchpoint_insert(cs, deaw, len, flags, rid, + &env->dawr_watchpoint[rid]); } =20 void ppc_store_dawr0(CPUPPCState *env, target_ulong val) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index bf9accf6e8..1b88cd136c 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -501,12 +501,12 @@ static void type2_breakpoint_insert(CPURISCVState *en= v, target_ulong index) if (flags & BP_MEM_ACCESS) { size =3D type2_breakpoint_size(env, ctrl); if (size !=3D 0) { - cpu_watchpoint_insert(cs, addr, size, flags, + cpu_watchpoint_insert(cs, addr, size, flags, index, &env->cpu_watchpoint[index]); } else { def_size =3D riscv_cpu_mxl(env) =3D=3D MXL_RV64 ? 8 : 4; =20 - cpu_watchpoint_insert(cs, addr, def_size, flags, + cpu_watchpoint_insert(cs, addr, def_size, flags, index, &env->cpu_watchpoint[index]); } } @@ -628,10 +628,10 @@ static void type6_breakpoint_insert(CPURISCVState *en= v, target_ulong index) if (flags & BP_MEM_ACCESS) { size =3D extract32(ctrl, 16, 4); if (size !=3D 0) { - cpu_watchpoint_insert(cs, addr, size, flags, + cpu_watchpoint_insert(cs, addr, size, flags, index, &env->cpu_watchpoint[index]); } else { - cpu_watchpoint_insert(cs, addr, 8, flags, + cpu_watchpoint_insert(cs, addr, 8, flags, index, &env->cpu_watchpoint[index]); } } diff --git a/target/s390x/tcg/debug.c b/target/s390x/tcg/debug.c index 7a838775ec..25968d9a3c 100644 --- a/target/s390x/tcg/debug.c +++ b/target/s390x/tcg/debug.c @@ -34,19 +34,18 @@ void s390_cpu_recompute_watchpoints(CPUState *cs) if (env->cregs[10] =3D=3D 0 && env->cregs[11] =3D=3D -1LL) { /* We can't create a watchoint spanning the whole memory range, so split it in two parts. */ - cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL); - cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL); + cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, 0, NULL); + cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, 0, NUL= L); } else if (env->cregs[10] > env->cregs[11]) { /* The address range loops, create two watchpoints. */ cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10], - wp_flags, NULL); - cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL); - + wp_flags, 0, NULL); + cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, 0, NULL= ); } else { /* Default case, create a single watchpoint. */ cpu_watchpoint_insert(cs, env->cregs[10], env->cregs[11] - env->cregs[10] + 1, - wp_flags, NULL); + wp_flags, 0, NULL); } } =20 diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 4cf147bbfb..20ddc527f8 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -105,7 +105,7 @@ static void set_dbreak(CPUXtensaState *env, unsigned i,= uint32_t dbreaka, mask =3D 0xffffffff << (32 - clo32(mask)); } if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, - flags, &env->cpu_watchpoint[i])) { + flags, i, &env->cpu_watchpoint[i])) { env->cpu_watchpoint[i] =3D NULL; qemu_log_mask(LOG_GUEST_ERROR, "Failed to set data breakpoint at 0x%08x/%d\n", --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226968; cv=none; d=zohomail.com; s=zohoarc; b=GJY8ZeBnaY8mjaMF72Q1AekhOqFGl/saM7Hewh2S8AODoZBxbkY9FGMm4zuwYnmDwLt3j1oqyMYqvyz1Z1M/uJtJ9UOt5kKmoWJ619RgqgejHkWDgIdorFTL616BJGxxC0E62BSR2DLS4CT8s7xqUSl4MOh0GV5C08qyQPqu+jc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226968; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2pSHmPBg36l6D2QIL/M1qutRoTdoTNtzz/aXqVPUCxo=; b=aDsktoMQSlfYJuFQ9nCAkiHHR9IVp+5wPBO5gbVkAz6rJaNga9OK46UqLfqeGeSIBBM3lwfplUwqJd5QjKqcsejffezGtko9NGAtoHplPeR914NWQuc9HnXleg86PmlHlWqyEarbgTqZdWbHQ3Z1wovY2XQHFRdlL93wRn29568= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226968453888.6937244392199; Sat, 4 Jul 2026 21:49:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEcx-00062Q-Sa; Sun, 05 Jul 2026 00:38:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEc4-0004rf-9D for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:53 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbr-00047k-Ho for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:51 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2cae134bdc8so8703525ad.3 for ; Sat, 04 Jul 2026 21:37:38 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 2 +- target/arm/internals.h | 2 +- target/ppc/internal.h | 2 +- target/riscv/debug.h | 2 +- target/xtensa/cpu.h | 2 +- accel/tcg/cpu-exec.c | 2 +- target/arm/tcg/debug.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/ppc/tcg-excp_helper.c | 2 +- target/riscv/debug.c | 2 +- target/xtensa/dbg_helper.c | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 568d82cdd3..3988bef520 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -264,7 +264,7 @@ struct TCGCPUOps { * @debug_check_breakpoint: return true if the architectural * breakpoint whose PC has matched should really fire. */ - bool (*debug_check_breakpoint)(CPUState *cpu); + bool (*debug_check_breakpoint)(CPUState *cpu, CPUBreakpoint *bp); =20 /** * @io_recompile_replay_branch: Callback for cpu_io_recompile. diff --git a/target/arm/internals.h b/target/arm/internals.h index fcce3804f3..370876851e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -680,7 +680,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n); void hw_breakpoint_update_all(ARMCPU *cpu); =20 /* Callback function for checking if a breakpoint should trigger. */ -bool arm_debug_check_breakpoint(CPUState *cs); +bool arm_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); =20 /* Callback function for checking if a watchpoint should trigger. */ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index a3bb12afd9..ec057afa92 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -304,7 +304,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr= ); void ppc_cpu_debug_excp_handler(CPUState *cs); -bool ppc_cpu_debug_check_breakpoint(CPUState *cs); +bool ppc_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 G_NORETURN void powerpc_checkstop(CPUPPCState *env, const char *reason); diff --git a/target/riscv/debug.h b/target/riscv/debug.h index a25d099b37..8eb9eccd4c 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -144,7 +144,7 @@ void tdata_csr_write(CPURISCVState *env, int tdata_inde= x, target_ulong val); target_ulong tinfo_csr_read(CPURISCVState *env); =20 void riscv_cpu_debug_excp_handler(CPUState *cs); -bool riscv_cpu_debug_check_breakpoint(CPUState *cs); +bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 void riscv_trigger_realize(CPURISCVState *env); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index ab42b4be00..590371c4dc 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -591,7 +591,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t reta= ddr); hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); -bool xtensa_debug_check_breakpoint(CPUState *cs); +bool xtensa_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); #endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void xtensa_count_regs(const XtensaConfig *config, diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 9c754b0365..66ec656861 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -328,7 +328,7 @@ static bool check_for_breakpoints_slow(CPUState *cpu, v= addr pc, #else const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; assert(tcg_ops->debug_check_breakpoint); - match_bp =3D tcg_ops->debug_check_breakpoint(cpu); + match_bp =3D tcg_ops->debug_check_breakpoint(cpu, bp); #endif } =20 diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 50b90ad675..306106b7e8 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -351,7 +351,7 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_w= p) return true; } =20 -bool arm_debug_check_breakpoint(CPUState *cs) +bool arm_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6f5dc06b3b..86832cfdf2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -132,7 +132,7 @@ static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) } =20 #ifndef CONFIG_USER_ONLY -static bool x86_debug_check_breakpoint(CPUState *cs) +static bool x86_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index b04f07a637..eb78a6a104 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -331,7 +331,7 @@ void ppc_cpu_debug_excp_handler(CPUState *cs) #endif } =20 -bool ppc_cpu_debug_check_breakpoint(CPUState *cs) +bool ppc_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp) { #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 1b88cd136c..5c378dd2e8 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -941,7 +941,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) } } =20 -bool riscv_cpu_debug_check_breakpoint(CPUState *cs) +bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *ignore) { RISCVCPU *cpu =3D RISCV_CPU(cs); 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Hoist the separate bp/wp code into the respective callers. Signed-off-by: Richard Henderson --- target/arm/tcg/debug.c | 49 +++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 29 deletions(-) diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 306106b7e8..519a06fbc7 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -252,41 +252,16 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) return contextidr =3D=3D (uint32_t)env->cp15.dbgbvr[lbn]; } =20 -static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) +static bool bp_wp_matches(ARMCPU *cpu, uint64_t cr, int access_el) { CPUARMState *env =3D &cpu->env; - uint64_t cr; int pac, hmc, ssc, wt, lbn; /* * Note that for watchpoints the check is against the CPU security * state, not the S/NS attribute on the offending data access. */ bool is_secure =3D arm_is_secure(env); - int access_el =3D arm_current_el(env); =20 - if (is_wp) { - CPUWatchpoint *wp =3D env->cpu_watchpoint[n]; - - if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) { - return false; - } - cr =3D env->cp15.dbgwcr[n]; - if (wp->hitattrs.user) { - /* - * The LDRT/STRT/LDT/STT "unprivileged access" instructions sh= ould - * match watchpoints as if they were accesses done at EL0, eve= n if - * the CPU is at EL1 or higher. - */ - access_el =3D 0; - } - } else { - uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; - - if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc !=3D pc)= { - return false; - } - cr =3D env->cp15.dbgbcr[n]; - } /* * The WATCHPOINT_HIT flag guarantees us that the watchpoint is * enabled and that the address and access type match; for breakpoints @@ -390,14 +365,16 @@ bool arm_debug_check_breakpoint(CPUState *cs, CPUBrea= kpoint *bp) */ =20 for (n =3D 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { - if (bp_wp_matches(cpu, n, false)) { + if (env->cpu_breakpoint[n] && + env->cpu_breakpoint[n]->pc !=3D pc && + bp_wp_matches(cpu, env->cp15.dbgbcr[n], arm_current_el(env))) { return true; } } return false; } =20 -bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *ignore) { /* * Called by core code when a CPU watchpoint fires; need to check if t= his @@ -417,7 +394,21 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatch= point *wp) } =20 for (n =3D 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) { - if (bp_wp_matches(cpu, n, true)) { + CPUWatchpoint *wp =3D env->cpu_watchpoint[n]; + int access_el; + + if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) { + continue; + } + + /* + * The LDRT/STRT/LDT/STT "unprivileged access" instructions should + * match watchpoints as if they were accesses done at EL0, even if + * the CPU is at EL1 or higher. + */ + access_el =3D (wp->hitattrs.user ? 0 : arm_current_el(env)); + + if (bp_wp_matches(cpu, env->cp15.dbgwcr[n], access_el)) { return true; } } --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226676; cv=none; d=zohomail.com; s=zohoarc; b=cW0OKSYiE33OAaZjiEbDGyeYTl5B2aHu4uSENnM3Se5Lf1hU7TG7Pnv2UbhdKcbQmcJUovOZ7Vm1+FJ8Psmb6NPQhpwQaPnNZjOGyumhlXIa2xpmt2GJg5cD8a4APLgzmgTAWJISrb9YtBevLxJWmxjGsrPBm/ToSn0xiEqe9f8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226676; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=T8Nke7VBw79ok0DwBulA/6kCjtrNSHe+I6s+oojEmf0=; b=R1gy5Txu7CZzVcdXmwgTvGcBAHMirPitXXthI2Ibprc5mg/9cmF68ybt+48YIQHKayhxEGdmy6g4lTHY0g2/9vjzLXtlTOsixWRd3A4JOabli6QDKjg7Ol7YWLey2ljIzjEklq8ZExZS1gpaA3ySjsXC/6ossc/AwyR9neRqc24= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226676891928.3083566122383; Sat, 4 Jul 2026 21:44:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEd8-0006QU-Rx; Sun, 05 Jul 2026 00:38:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEc7-0004tZ-7G for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:55 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbt-0004Am-Gd for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:54 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-ca1328b8584so1150984a12.1 for ; Sat, 04 Jul 2026 21:37:40 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- target/arm/tcg/debug.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 519a06fbc7..2389830b2a 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -331,7 +331,6 @@ bool arm_debug_check_breakpoint(CPUState *cs, CPUBreakp= oint *bp) ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; vaddr pc; - int n; =20 /* * If breakpoints are disabled globally or we can't take debug @@ -363,15 +362,7 @@ bool arm_debug_check_breakpoint(CPUState *cs, CPUBreak= point *bp) * TODO: We would need to look up the page for PC and verify that * it is present and executable. */ - - for (n =3D 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { - if (env->cpu_breakpoint[n] && - env->cpu_breakpoint[n]->pc !=3D pc && - bp_wp_matches(cpu, env->cp15.dbgbcr[n], arm_current_el(env))) { - return true; - } - } - return false; + return bp_wp_matches(cpu, env->cp15.dbgbcr[bp->id], arm_current_el(env= )); } =20 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *ignore) --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226883; cv=none; d=zohomail.com; s=zohoarc; b=NxVNQeO6Bk6/p4TriyDhlPx3ppdjGbcyfGtuR1PNMUtudTH9AIH0MoFgA9tNfh2SoVI2iGpBpfN/FYNdiWDUG85qLAVaKTtTrViwjSfvKVh1sh7HMvLWtHir8tRVbD6x/Tmq0Jt/u6I0Ui5Z6wJkR9ceu1Hr9/hH1nDS5r7P3Gs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226883; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=w/QoPchMBLEoPNwVaZS+xZRRFREK+x04Oz5t5RgPWdc=; b=neWznJ6xBSeWrmcYDdOFBfHGjERTLhVBAyv+mLk1jyZO30TNm5T1R3+1NmkaSfvx5CsiL2obxV+tnYrVTQA/ZAhJorjcUYVox3LkgazDVIzbE2LgqQAeLpmr7wrA8cgfw+SCfam9++tD/PuwIcrjqEDrqTcVrd7qHVDHOBEIvA0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178322688320392.53630373557962; Sat, 4 Jul 2026 21:48:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdQ-00078w-Bg; Sun, 05 Jul 2026 00:39:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEc8-0004wQ-Ug for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:57 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbu-0004BJ-73 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:55 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2c9bd2f8bf7so29047575ad.1 for ; Sat, 04 Jul 2026 21:37:41 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226261; x=1783831061; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w/QoPchMBLEoPNwVaZS+xZRRFREK+x04Oz5t5RgPWdc=; b=Tf9aT3Gs3ol5ms8gia9ihB6o55s9u46Py3omuAAliBt8w2dIJETgppMjNEscfCbh6m 3mjCNSQi2GUIkCQkElK6O6Cu63hGszNeDWe3vWw9bjNjc3J33DBuFk81oQvbqKDPlMcn UCIESibt35rvSLlawKd9WqSxhawWSpOXB6R14vDYJQF7ncSF8aT5tYhfVpn8n9/AWAJz HD3FHKN0ZgnPyy9xVsK/sR4Mp+C563GmBBi2fu6U+6J5crP+UERjoiG+/1iH6VA3Dame DO1AJ3OgHu3IRsThLRU4OBjogWw5fCB59htUlw1cGGB6CRZMwetcS68ZpWEmr31cWMSi 9Xmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226261; x=1783831061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=w/QoPchMBLEoPNwVaZS+xZRRFREK+x04Oz5t5RgPWdc=; b=XZ4ILvv9ygttgsWn/9ZhldbRB6UvWdDGBAUeLoPZzWXw36CQOMQZAWcKNbzFa341FC /+D1xBgJ5Ef7UzBU5IGnnV74XcM6bRdJt6exFTUUtQ5NAOp7rZWNvT9/qU7ED1O6xN/E fE/Qz61WGFn9Z0S+fATXEo3xNQpUrZm+dWNjIuUAWwvdgryJSRImSMknmbM/vhj9aYpV uQzv7YKICKGBNXrJC7jWbaF3R+GsX/7R7jhQTcnHizJpj9til919je0niP3TV7VFxZgr EE/xowxyze43+bz8w5htmMcNeaBlVzRKC8FFs+S5FwxgpKMWN+WjX1KMaQFKAprVdkCZ broA== X-Gm-Message-State: AOJu0YztxJibDODsmFwokJDx7Aj0BU3A6TcZWRzPa28kYe5Dr4AWzao/ I53krTavuTB/77sNsK7W8vvTTiuwInxajkfDTWbu+f9g6d6zdEakiXsJLM8IAJ7Kw+bCs4XEoq+ q+AM/ X-Gm-Gg: AfdE7cktpP+Sg/Kny/qyIOULREx+ta+pThFzX4//bGTB8Vb9WP4kowmEZ366UNuVNZs kmwyh5VSApwNlgwRBXBZDxzSqKehNrYkEt2q8lwwZ/zyo66P6FNriPmv6thFVk7Vh2KmPGsNiLi ZpTaCIFtWoxxxsMHJDxKKZPjfTP93xqgwl8yGoUUM4V6xId7wmGpoVVmrqkcAWBQ0IQfmpHXruj dHZreVHN0hMuV4qjhkFxe0NaMXq3R/SdJktuyOMnW2DF4q+xyPqlUgNwjS38apYqU/SkaOhNcrw SZaxIpLXH2LGZ6nu/MCM2+XniovyMUizQ0gZtyD5OR4tWMgAiQiX664Hs/q7ChtQohhtNDo28GR /fQKXgFcApkt3QUSvV4p7CpI7O4CPIeujOd57KeXmt9ql9ImKkSPQwIu/Iz1+ICU4wv9JJf8o/Z O1I7jxrXIqZgL3NzLBhk5Fxa8TYh8yqEaFkCucL4qDHBZ7yVc= X-Received: by 2002:a17:903:90b:b0:2c9:d277:2cdb with SMTP id d9443c01a7336-2cc08df17bcmr41444215ad.9.1783226260602; Sat, 04 Jul 2026 21:37:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 15/46] target/arm: Use wp argument in arm_debug_check_watchpoint Date: Sat, 4 Jul 2026 21:36:54 -0700 Message-ID: <20260705043725.1373137-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226884310158500 Content-Type: text/plain; charset="utf-8" Use the matched watchpoint instead of looping over all. Signed-off-by: Richard Henderson --- target/arm/tcg/debug.c | 35 ++++++----------------------------- 1 file changed, 6 insertions(+), 29 deletions(-) diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 2389830b2a..daad2ac440 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -365,7 +365,7 @@ bool arm_debug_check_breakpoint(CPUState *cs, CPUBreakp= oint *bp) return bp_wp_matches(cpu, env->cp15.dbgbcr[bp->id], arm_current_el(env= )); } =20 -bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *ignore) +bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) { /* * Called by core code when a CPU watchpoint fires; need to check if t= his @@ -373,37 +373,14 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatc= hpoint *ignore) */ ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - int n; - /* - * If watchpoints are disabled globally or we can't take debug - * exceptions here then watchpoint firings are ignored. + * The LDRT/STRT/LDT/STT "unprivileged access" instructions should + * match watchpoints as if they were accesses done at EL0, even if + * the CPU is at EL1 or higher. */ - if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 - || !arm_generate_debug_exceptions(env)) { - return false; - } + int access_el =3D wp->hitattrs.user ? 0 : arm_current_el(env); =20 - for (n =3D 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) { - CPUWatchpoint *wp =3D env->cpu_watchpoint[n]; - int access_el; - - if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) { - continue; - } - - /* - * The LDRT/STRT/LDT/STT "unprivileged access" instructions should - * match watchpoints as if they were accesses done at EL0, even if - * the CPU is at EL1 or higher. - */ - access_el =3D (wp->hitattrs.user ? 0 : arm_current_el(env)); - - if (bp_wp_matches(cpu, env->cp15.dbgwcr[n], access_el)) { - return true; - } - } - return false; + return bp_wp_matches(cpu, env->cp15.dbgwcr[wp->id], access_el); } =20 /* --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783227047; cv=none; d=zohomail.com; s=zohoarc; b=KQPyUnEjrHrDous8kMxGxrL60AIxBKhGkrFvYwevCX4SiM+7A7G8mO2tOTsFuh0S2TRKaLTCMifnWv38ZSQbv+a6Zcw7CVocHqzj4h7tKDWE9XP7iO1t88TocVsxri8PX+pmuSKP91B5g4Wn+Xy2/UlHYadwliMwt6sS234xRa8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783227047; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=k40Ct/scLRA6POY4s+1/g3ylMfrjfxUVUANTHep1r88=; b=nFNxLZIbPwcMFhYLX39b4ArhOXVS/bdiMBweUIfwVIpjTQYTrP4Df4NR0bf99x7bFiszGqc1F/CpDZXr6Z6iF8ZNPYMnX8pA7X1+n+0snTNgquRL7McnVY4OgF2H5nLrIEdcvkx3Yxb/+UGhAq/UwOGlILMUOxRt96PKRedSXMI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783227047627477.87740629394875; Sat, 4 Jul 2026 21:50:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdI-0006jM-HL; Sun, 05 Jul 2026 00:39:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEc9-0004wT-37 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:57 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbv-0004C0-Dz for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:56 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-2cacf197759so28985885ad.2 for ; Sat, 04 Jul 2026 21:37:42 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226261; x=1783831061; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=k40Ct/scLRA6POY4s+1/g3ylMfrjfxUVUANTHep1r88=; b=PGN7yxEMwlbmTnowoonLDItVi2yHqLlUsxChCb286X8cfSQXLL/iVUt/5GD6/3api5 /y4KKFj8f/+plalKgU/N1iWr0tVmDP7wNdXvfmNRYLdlximaC7WBnnbmbUC6l8cbVWu1 5KcxT5UT/sjtMkgzhgyX1e2J/H9I5vgml0jwevHT3QaBSOftnNr69Z8zJvCVBITvqrSa f9NvT7G+xjdCqfrBXutW0sukCClx1fo6ESmqUySaEAI/+KaZv5gTMWxpNVgNfxNz+KCF 8ENpMYH50YwmNIT0rAZJ9Lwe41ScF/ZkOHdbADzgXjaluDJx3YP78+CjOvJXCC58q8dw GN6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226261; x=1783831061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=k40Ct/scLRA6POY4s+1/g3ylMfrjfxUVUANTHep1r88=; b=Tn2bmImZWwDwAw6VBV4St8H9Ag0t58C5I9rc+6aFdsZ0QGQkwXDcqdYesF8Wa2iftJ YzrrqT13FDxPRvnXsL05+//WE6SPiqeKRmV9FgVVfpTrozZdvlBftYsnaGX/LO4aWduw FiHz2f9eVJ8AXOxs47BHuIUquikAeZp8rO+v6AtqPSdC91P2s+QyfxXiiHIZWx2ddCPY 2GPefzX1MrvWMOr68GBhp6caljDepvzxa+fvKzGjCCuH/LsPrJ+n9MmVmufvQ3msCuzl BBtA3iD3Rrnus3qERY0FPvXu6lWekLPvxVR2vF0OtoqO/gl7zegdtFm//wFhj+RGdQ09 nCsA== X-Gm-Message-State: AOJu0YzNiXoHW+x1ZyOmfkqzRgM0xaUvQb0pk1Pa5DG+vgFbA4CxXjaU FTb3d04k+cTGICKj7FzSYzzD1lbDfyEYegp6Ha/47UA4u5KBGhfjqo2vQ1RiJEntuePJYMie31F VaCk6 X-Gm-Gg: AfdE7cnZl+a8ToJXAHO05NI2NPji/OaJkeU+cRIFQjv7JrXJ3e8iwMEdJC75mY3lVOA /wEKmpIykOQIKVcd0qTA4uRv8ONaOp57QbQLWJJXp0WtyBUJgrw236i/pysThUCbVz1gOFKO8tO /3Gwq6lOfI2c5g/ESLQRnMz5M3iKcMsp7a/x3n1L1Wo5lyASFtVpFNKh1GSalMAR5OCnzC/R8Ch YAXvGle3+C+94QcwkpmEgURKYddu5wZ0ZZNOpqabQIuPROk4Jvp41/t5V//do8aDpI2Uwx44dTF YI/PvrOMXjkR7LITzPRrTwb/jm3B74bONh+1yWCUdCShXyXauV2efjWEktYRMeymZAbY5d4vtWH Hif578DMOEeUGYgEtHe3dJ7tl1TAY1DueR/rOZl3Fh7G/tjhpDNTLOTefWFWobJcszFOyOT7Yvm rECFnDHQhR4M7URj3Cc+LSQVi7NzqL53v0lgOdreqkkwrMsg8= X-Received: by 2002:a17:903:1746:b0:2bd:c925:3a16 with SMTP id d9443c01a7336-2cb97e43356mr58462405ad.2.1783226261455; Sat, 04 Jul 2026 21:37:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 16/46] target/riscv: Use bp argument in riscv_cpu_debug_check_breakpoint Date: Sat, 4 Jul 2026 21:36:55 -0700 Message-ID: <20260705043725.1373137-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783227048894158500 Content-Type: text/plain; charset="utf-8" Use the ID of the breakpoint instead of a loop over all. Signed-off-by: Richard Henderson --- target/riscv/debug.c | 44 ++++++-------------------------------------- 1 file changed, 6 insertions(+), 38 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 5c378dd2e8..511a69c28d 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -941,48 +941,16 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) } } =20 -bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *ignore) +bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - CPUBreakpoint *bp; - target_ulong ctrl; - target_ulong pc; - int trigger_type; - int i; + int i =3D bp->id; + trigger_type_t trigger_type =3D get_trigger_type(env, i); =20 - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - for (i =3D 0; i < env->num_triggers; i++) { - trigger_type =3D get_trigger_type(env, i); - - if (!trigger_common_match(env, trigger_type, i)) { - continue; - } - - switch (trigger_type) { - case TRIGGER_TYPE_AD_MATCH: - ctrl =3D env->tdata1[i]; - pc =3D env->tdata2[i]; - - if ((ctrl & TYPE2_EXEC) && (bp->pc =3D=3D pc)) { - env->badaddr =3D pc; - return true; - } - break; - case TRIGGER_TYPE_AD_MATCH6: - ctrl =3D env->tdata1[i]; - pc =3D env->tdata2[i]; - - if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { - env->badaddr =3D pc; - return true; - } - break; - default: - /* other trigger types are not supported or irrelevant */ - break; - } - } + if (trigger_common_match(env, trigger_type, i)) { + env->badaddr =3D env->tdata2[i]; + return true; } =20 return false; --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226525; cv=none; d=zohomail.com; s=zohoarc; b=U5La/8XGt7LPrZ2Zz0fTFY7RC3pfxV3VgzjxFcp8kgYE//TxVlE6/Ke+UquAl0nAOML/WDkyJJtHbLQQq+3slVfhGnOy7WTya/+Oato6yRJR862UXVXn6nioukMuZpHz3rz54mWGqJQgYckqB2T6b6QdqYdMsZs2zQSWMd2B0Rg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226525; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Lg/N8LFKGp5ELLy+c1KbExFW/0dtEAJ/1CeA/sfoCRs=; b=HmL/K2qQukNdxjADeV/dDU0Cc7YA86RKk64o+Q3kQdyxJw4pPZZ4kczJwCiSRzHBjPzU/gZ1tZkkn4dQVIFpmnkxPNPuK4SIIbK0j5Vb7Yx5IbHsiWGvQsOopdtxvYWAWOikmwkfHCtbKZfaOxYIJ7v1woRoAE7wRaVDcF5BFAM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226525451722.2400102669376; Sat, 4 Jul 2026 21:42:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdZ-0007MJ-En; Sun, 05 Jul 2026 00:39:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcA-0004ys-Ux for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:59 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbw-0004DI-4B for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:58 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-2c6b67d5fa1so18032105ad.2 for ; Sat, 04 Jul 2026 21:37:43 -0700 (PDT) Received: from stoup.. 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This fixes a bug in which addr was compared against wp->vaddr, so that we never recognized watchpoints that didn't trigger at the start of the region. Signed-off-by: Richard Henderson --- target/riscv/debug.c | 55 +++----------------------------------------- 1 file changed, 3 insertions(+), 52 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 511a69c28d..56ae1e6107 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -960,59 +960,10 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, C= PUWatchpoint *wp) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - target_ulong ctrl; - target_ulong addr; - int trigger_type; - BreakpointFlags flags; - int i; + int i =3D wp->id; + trigger_type_t trigger_type =3D get_trigger_type(env, i); =20 - for (i =3D 0; i < env->num_triggers; i++) { - trigger_type =3D get_trigger_type(env, i); - - if (!trigger_common_match(env, trigger_type, i)) { - continue; - } - - switch (trigger_type) { - case TRIGGER_TYPE_AD_MATCH: - ctrl =3D env->tdata1[i]; - addr =3D env->tdata2[i]; - flags =3D 0; - - if (ctrl & TYPE2_LOAD) { - flags |=3D BP_MEM_READ; - } - if (ctrl & TYPE2_STORE) { - flags |=3D BP_MEM_WRITE; - } - - if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - return true; - } - break; - case TRIGGER_TYPE_AD_MATCH6: - ctrl =3D env->tdata1[i]; - addr =3D env->tdata2[i]; - flags =3D 0; - - if (ctrl & TYPE6_LOAD) { - flags |=3D BP_MEM_READ; - } - if (ctrl & TYPE6_STORE) { - flags |=3D BP_MEM_WRITE; - } - - if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - return true; - } - break; - default: - /* other trigger types are not supported */ - break; - } - } - - return false; + return trigger_common_match(env, trigger_type, i); } =20 void riscv_trigger_realize(CPURISCVState *env) --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226923; cv=none; d=zohomail.com; s=zohoarc; b=U4ATy25myKgp9dTH/MsQiGjlyNWUcVzgtxwcHnSMvWXu4shUSBat1EuSxVQdg0ZDnmqCayIBM4aCTENYo9tSy17C7WKHRBKJeMa9g5o8AXN1oDREE3wl8X6I1FYX66VSmMLLqBMDwTRHjd0fmA02u4R2C8FHwRRiAxoVxqpu5Js= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226923; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sqD0i4B4xHusdPHG8dIAD4vZ8p3PsgamfaStAkj5bxU=; b=ckadJXbIPdanfy4XIuyhS6j0HhvwMywffDAMb/ApBksYy51CnMlCjY7zE4olhA9soHgrbtUOzjJMUDf6Fm5EFYS5SF6y2VZ3TTEP7BTOR3WcWjPHz08SX1lr7aqi7tRK5WHapNAJC60XYLSd5azIYP0acNWU16wcm6PHxlC2I70= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226922905795.7121626936955; Sat, 4 Jul 2026 21:48:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdn-0007gu-AK; Sun, 05 Jul 2026 00:39:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcC-000517-Gk for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:01 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbw-0004Dq-IA for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:37:59 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2caced6038eso18829005ad.0 for ; Sat, 04 Jul 2026 21:37:44 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226263; x=1783831063; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sqD0i4B4xHusdPHG8dIAD4vZ8p3PsgamfaStAkj5bxU=; b=AzRG0dZYLvts+avzH/A+mJrVNbhh+ARKRpJMI+794bitl6nnhGFag5yCuc3mBDqXR2 LSulufFK91D721ToyE3xdd1kxJU2HTzeMLMQAPWNv7HEbdONqZxZHI5ZHzhVVEaT5xYn gIg58jOhjPmD3vT9c8RsZCIcwr5En0TODqxna/xQPaSu2Mn3yAuVvWBR+JurRFq93Huz bkNCX3EGwXU6ftljpz+zncBrlPT/ZN0DHzQdZFBviefJncNw9AkM+Mz2vyQzTzIfBLER 2T3RogMQBtSYlTtQsuh8hFi6JAHbP/RxR85ROYq6Gedj/VzFeyBwxdfrUtCC+OTRh8h6 WwdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226263; x=1783831063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=sqD0i4B4xHusdPHG8dIAD4vZ8p3PsgamfaStAkj5bxU=; b=YK7Cq7pzlKrkf4cam056h4+Zx03Sw/YYsC9nJaYvt8h1lRFE+k0SnYfyl6FC/omIvp QtsK1CgRoassUVaT+M7sKb9D9YsSrvgFbzuvQ7YPtNxmsWZEN69PTcRxZkyIguXXEmvN Zdk+MkY3H868IsA60+x1aKGVJQLjpyb8AIpwLW7RAYSrJPt2YcCzAKmRMzRSBw8OLCEu XX+vQWZAM/7eNhMRdl8znH7zgQyTiqKRO0F92I0L/sLWu069F1AiD2xslROFpJK4EHgJ ohzir/i13NlZd/EJF23Xu0k86wDkyDXf0izNE0iPlNOylq6Y2EydH2AazUBtgjAoeqe/ tLtA== X-Gm-Message-State: AOJu0YxIdAX64mvb9CB/UjtM6YKMb1ZOa3979vCU8JzcfAEniPvocYd3 /smWdT0N3JiWzUfW0rJnCAYBQ/d1lZR2P02thr1b4OK71W+VSowKNW1f+kzuoTFNLu8ruP6zV7K cfr9U X-Gm-Gg: AfdE7ckXjt3dlXzsv0nCQkD2pmiUNa2RKugNfE1Q93MY7DpQF9tVZOzTtIihXQcWs14 cWfaeZuDVX+lkd1vq9hNaUR5ovb9eqQJCVcUItdjitXlXu1HuYExREP/Jh9yueEdGhFs1qrAXau vSvRNg4wg8O+nL5DolZTfY/CwKsfPCPuJOTW18Rwlj6ACTBNHcG5yKU38Ggs48pf9pmuSdohr3r fYDqcW+3nMDPoLoSvt8MV1l7noL5THH2iWBNzgE61Jg+bHBkwjulR6KV5ZSKOM10GlNheooqYpw 5Z7IGfapXh5CHMpyiiCxJbx+AARhuw2RmcoKW3oqJicgvp4sAPgqGirx+NB3Trl5lDajk+frsPf YCKkqSY+TD2fXqVVXLjygtH+bEEn+JNxfVGiE/Wg1uI5HSigp34BuxY7uJN9e9OPnE6tDamK9uw HDuZSqSP7E/QHIHlj60tQsSmtyfU98ltcw83WbsR2szlSK9DY= X-Received: by 2002:a17:902:d551:b0:2c9:c517:d08b with SMTP id d9443c01a7336-2cc0b23ef33mr42159675ad.22.1783226263046; Sat, 04 Jul 2026 21:37:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 18/46] target/xtensa: Use bp argument in xtensa_debug_check_breakpoint Date: Sat, 4 Jul 2026 21:36:57 -0700 Message-ID: <20260705043725.1373137-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226924374158500 Content-Type: text/plain; charset="utf-8" Use the ID of the breakpoint instead of a loop over all. Signed-off-by: Richard Henderson --- target/xtensa/dbg_helper.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 557a7852c8..b08bd03435 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -67,18 +67,11 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t = i, uint32_t v) bool xtensa_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp) { CPUXtensaState *env =3D cpu_env(cs); - unsigned int i; =20 if (xtensa_get_cintlevel(env) >=3D env->config->debug_level) { return false; } - for (i =3D 0; i < env->config->nibreak; ++i) { - if (env->sregs[IBREAKENABLE] & (1 << i) && - env->sregs[IBREAKA + i] =3D=3D env->pc) { - return true; - } - } - return false; + return (env->sregs[IBREAKENABLE] >> bp->id) & 1; } =20 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783227047; cv=none; d=zohomail.com; s=zohoarc; b=NQ0DmXD5B3ZDIshYoJtgk/2DXYKn+zGegMSC5y5W2w98jhLsfRYXJ4/dW5x75Ji/VuznnE8QVDUUjk/gBtM1fpjC0yRWAau8z3jRe6AI4JToKSUJ3UpJoxDUC4qD6NfdRhPvGPttskfjd4g4Ov+FXd5sYhLX0hokS8ANH+2CG7s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783227047; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mVi2jco+eDzhedCRgpvAhh0t0Y9yVrShv+ERuBTeajY=; b=i/KEv7Cts7gydg4EcObv8y2Ed9LmVOWcqrYf+VtgllQrUxyMUE9ysdSTo43W2cIw423fItrwM4G6uWNnz79/FlfcXEacVJU+8P8d9aAJ9/JHkhOvuby1ldBYVunDZpRVXDsLQESnDJTPpT8Dt5aoznqiyEiqpYBLG5qDWU9L7+g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783227047597578.3924560671946; Sat, 4 Jul 2026 21:50:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdO-0006xF-Jb; Sun, 05 Jul 2026 00:39:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcC-00051h-TD for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:02 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEbx-0004EP-GF for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:00 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-2c9b1edf2bdso19453005ad.1 for ; Sat, 04 Jul 2026 21:37:44 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226264; x=1783831064; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mVi2jco+eDzhedCRgpvAhh0t0Y9yVrShv+ERuBTeajY=; b=vponuLwQ+mvSGPqjVKRxTD1D09ZwBFIs4kihE6Dv726RcSWW9QB1W+YHZyTh0MsJgh 1wKB10jCINE4ZDlu7VUvFXC1ASnHCtAfPMBPf9E/uiXWSC1xFsKwcw4qXAR90OtbWUWZ /ic8tvmzUvFBf++YJPDh3OzJq5KdXyq4NVPacyJ+90xEKJc1PgFTP8JgRXrrxLkSaHvA +lT6wS85DOd6EoZkiWUQ/RZcqA4Mss3Yo0MC+Ve8lbSLQu6aZmQ8Oo6pVqwq5s4RASul COKgiW9kYHI3f15Of5TBP7X9HUlxEB4X9PSEgQBGpKsByI+raSA6gpNGIh0feFT8McBR jIGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226264; x=1783831064; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=mVi2jco+eDzhedCRgpvAhh0t0Y9yVrShv+ERuBTeajY=; b=fkIlevWYbf8LPBMzllq5/uhp/XWHqqx6yRU2C6IHL6Dll4Sbi7yJ/VF4YWpdEhj+xx sJyE+bJUtH3KIMT2v8oZnM2cDtaPTNy5I1RF3nXq8jfK7CPYAvh5gjYEr202TEmuFIGS Hd36i6Z9XF47EslGNSKEN3fA7lwY4+j6HbaJW0TOQuFGA34Edv2Hp1LdREz+C4Tx3Ypg Y62wBpfJ3WRFdSTr8/Z4oVSGIIJduWO+SOas9kw9wyGpE6Kup9HHXjOjhqNi6wK1vp91 sv619qeaAvCJ7+r0KOUmEw7n7+hpUa1lfhqcswY3J7frZuDfpDjr0/JKc0+Z1fy7Ypww jYTQ== X-Gm-Message-State: AOJu0YxqyVX8z7dUwhrWIhwdaQ/3pHJWs/+CjPRgUALzJ2CTjgPGrxg4 VgcroI2qiX/Exd0ALLuHFqHziWsUUfmBVwOCTEtiyiyi+QB620NTYvXqoYerFw/CTHp5jbasjoz ou2v5 X-Gm-Gg: AfdE7cnjRRQNegvcYhUHa4Ox6HCpdW/j0TVchya2e6UeGtW+n8We3F3XdjRhVvlTK2X QK874mXkT4+QqSLPpqbHak02qe54A06BJvOdTvAPMsdCNZOYFaqxb3SA+hTWFxPfXxh0u+Z3/RT 9vUTRJZ4xqeM4Zs4GEZRbkIu4E7OeszQDG/8AR9ppudRxH5yHLGeEyzUcUbahvdwvSu+e7EiuXv kSJXjd7D6TGKL2BLdWa/qC18yFHFNPvTfQGZK4xaLo1HawnM9HIGRyc2ga3n29MlrhlvJdEQAJg OcRDk9lHg67gvZICF25+DWMw8G18ZHBof9yJw4CPXv01J+MrMC1fas/k6A6Y1/UMozODn1+hbSn YrDTx3knDHfvTqkMS1Qt5AQrKCvqRd6uzW190yUjC7IIuRDOvB9+O8PhDrnxw2Pe7mycfAMQHjB rB1TxrveiRES5m3WjBtaBgKcydGMQaNdMp+bpDEb4e6bp3xh4= X-Received: by 2002:a17:903:240a:b0:2cc:61e8:5fba with SMTP id d9443c01a7336-2cc61e86312mr44557505ad.32.1783226263770; Sat, 04 Jul 2026 21:37:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 19/46] cpu: Use interval-tree for CPUBreakpoint Date: Sat, 4 Jul 2026 21:36:58 -0700 Message-ID: <20260705043725.1373137-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783227049016158500 Content-Type: text/plain; charset="utf-8" Use a balanced binary tree rather than a simple list for breakpoints. Using an interval tree makes it easy to probe for all breakpoints on a virtual page. Signed-off-by: Richard Henderson --- include/exec/breakpoint.h | 4 +-- include/hw/core/cpu.h | 3 +- accel/tcg/cpu-exec.c | 58 +++++++++++++++++++++---------------- accel/whpx/whpx-common.c | 9 +++--- cpu-common.c | 46 +++++++++++++++-------------- hw/core/cpu-common.c | 1 - linux-user/main.c | 14 ++++++--- target/i386/whpx/whpx-all.c | 15 +++++----- 8 files changed, 84 insertions(+), 66 deletions(-) diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index 963ea992cb..5f0025a3c9 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -8,6 +8,7 @@ #ifndef EXEC_BREAKPOINT_H #define EXEC_BREAKPOINT_H =20 +#include "qemu/interval-tree.h" #include "qemu/queue.h" #include "exec/vaddr.h" #include "exec/memattrs.h" @@ -28,10 +29,9 @@ typedef int BreakpointFlags; #define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) =20 struct CPUBreakpoint { - vaddr pc; + IntervalTreeNode itree; /* start =3D=3D last =3D=3D pc */ BreakpointFlags flags; unsigned id; - QTAILQ_ENTRY(CPUBreakpoint) entry; }; =20 struct CPUWatchpoint { diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ca0b0c7978..b6368c2c2f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -30,6 +30,7 @@ #include "qapi/qapi-types-machine.h" #include "qapi/qapi-types-run-state.h" #include "qemu/bitmap.h" +#include "qemu/interval-tree.h" #include "qemu/rcu_queue.h" #include "qemu/queue.h" #include "qemu/lockcnt.h" @@ -523,7 +524,7 @@ struct CPUState { QTAILQ_ENTRY(CPUState) node; =20 /* ice debug support */ - QTAILQ_HEAD(, CPUBreakpoint) breakpoints; + IntervalTreeRoot breakpoints; =20 QTAILQ_HEAD(, CPUWatchpoint) watchpoints; CPUWatchpoint *watchpoint_hit; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 66ec656861..5812cb57aa 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -296,8 +296,8 @@ static void log_cpu_exec(vaddr pc, CPUState *cpu, static bool check_for_breakpoints_slow(CPUState *cpu, vaddr pc, uint32_t *cflags) { + IntervalTreeNode *n; CPUBreakpoint *bp; - bool match_page =3D false; =20 /* * Singlestep overrides breakpoints. @@ -312,33 +312,34 @@ static bool check_for_breakpoints_slow(CPUState *cpu,= vaddr pc, return false; } =20 - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - /* - * If we have an exact pc match, trigger the breakpoint. - * Otherwise, note matches within the page. - */ - if (pc =3D=3D bp->pc) { - bool match_bp =3D false; - - if (bp->flags & BP_GDB) { - match_bp =3D true; - } else if (bp->flags & BP_CPU) { + n =3D interval_tree_iter_first(&cpu->breakpoints, pc, pc); + if (n) { #ifdef CONFIG_USER_ONLY - g_assert_not_reached(); + bp =3D container_of(n, CPUBreakpoint, itree); + assert(bp->flags & BP_GDB); + goto found; #else - const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; - assert(tcg_ops->debug_check_breakpoint); - match_bp =3D tcg_ops->debug_check_breakpoint(cpu, bp); -#endif + /* Prefer GDB breakpoint over architectural breakpoint. */ + do { + bp =3D container_of(n, CPUBreakpoint, itree); + if (bp->flags & BP_GDB) { + goto found; } + n =3D interval_tree_iter_next(n, pc, pc); + } while (n); =20 - if (match_bp) { - cpu->exception_index =3D EXCP_DEBUG; - return true; + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; + assert(tcg_ops->debug_check_breakpoint); + + for (n =3D interval_tree_iter_first(&cpu->breakpoints, pc, pc); n; + n =3D interval_tree_iter_next(n, pc, pc)) { + bp =3D container_of(n, CPUBreakpoint, itree); + if ((bp->flags & BP_CPU) && + tcg_ops->debug_check_breakpoint(cpu, bp)) { + goto found; } - } else if (((pc ^ bp->pc) & TARGET_PAGE_MASK) =3D=3D 0) { - match_page =3D true; } +#endif } =20 /* @@ -353,17 +354,24 @@ static bool check_for_breakpoints_slow(CPUState *cpu,= vaddr pc, * invalidated, nor would any TB need to be invalidated as * breakpoints are removed. */ - if (match_page) { + n =3D interval_tree_iter_first(&cpu->breakpoints, + pc & TARGET_PAGE_MASK, + pc | ~TARGET_PAGE_MASK); + if (n) { *cflags =3D (*cflags & ~CF_COUNT_MASK) | CF_NO_GOTO_TB | CF_BP_PAG= E | 1; } return false; + + found: + cpu->exception_index =3D EXCP_DEBUG; + return true; } =20 static inline bool check_for_breakpoints(CPUState *cpu, vaddr pc, uint32_t *cflags) { - return unlikely(!QTAILQ_EMPTY(&cpu->breakpoints)) && - check_for_breakpoints_slow(cpu, pc, cflags); + return unlikely(!interval_tree_is_empty(&cpu->breakpoints)) && + check_for_breakpoints_slow(cpu, pc, cflags); } =20 /** diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index 247e12db81..74113b1ec1 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -112,16 +112,17 @@ int whpx_first_vcpu_starting(CPUState *cpu) =20 g_assert(bql_locked()); =20 - if (!QTAILQ_EMPTY(&cpu->breakpoints) || + if (!interval_tree_is_empty(&cpu->breakpoints) || (whpx->breakpoints.breakpoints && whpx->breakpoints.breakpoints->used)) { - CPUBreakpoint *bp; + IntervalTreeNode *n; int i =3D 0; bool update_pending =3D false; =20 - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + for (n =3D interval_tree_iter_first(&cpu->breakpoints, 0, -1); n; + n =3D interval_tree_iter_next(n, 0, -1)) { if (i >=3D whpx->breakpoints.original_address_count || - bp->pc !=3D whpx->breakpoints.original_addresses[i]) { + n->start !=3D whpx->breakpoints.original_addresses[i]) { update_pending =3D true; } =20 diff --git a/cpu-common.c b/cpu-common.c index 9476bb612a..0287022de4 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -392,13 +392,13 @@ void process_queued_cpu_work(CPUState *cpu) /* Return true if PC matches an installed breakpoint. */ bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, BreakpointFlags mask) { - CPUBreakpoint *bp; + IntervalTreeNode *n; =20 - if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D pc && (bp->flags & mask)) { - return true; - } + for (n =3D interval_tree_iter_first(&cpu->breakpoints, pc, pc); n; + n =3D interval_tree_iter_next(n, pc, pc)) { + CPUBreakpoint *bp =3D container_of(n, CPUBreakpoint, itree); + if (bp->flags & mask) { + return true; } } return false; @@ -414,18 +414,14 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, Br= eakpointFlags flags, pc =3D cpu->cc->gdb_adjust_breakpoint(cpu, pc); } =20 - bp =3D g_malloc(sizeof(*bp)); + bp =3D g_new0(CPUBreakpoint, 1); =20 - bp->pc =3D pc; + bp->itree.start =3D pc; + bp->itree.last =3D pc; bp->flags =3D flags; bp->id =3D id; =20 - /* keep all GDB-injected breakpoints in front */ - if (flags & BP_GDB) { - QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); - } else { - QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); - } + interval_tree_insert(&bp->itree, &cpu->breakpoints); =20 if (breakpoint) { *breakpoint =3D bp; @@ -438,36 +434,42 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, Br= eakpointFlags flags, /* Remove a specific breakpoint. */ int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, BreakpointFlags flags) { - CPUBreakpoint *bp; + IntervalTreeNode *n; =20 if (cpu->cc->gdb_adjust_breakpoint) { pc =3D cpu->cc->gdb_adjust_breakpoint(cpu, pc); } =20 - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D pc && bp->flags =3D=3D flags) { + for (n =3D interval_tree_iter_first(&cpu->breakpoints, pc, pc); n; + n =3D interval_tree_iter_next(n, pc, pc)) { + CPUBreakpoint *bp =3D container_of(n, CPUBreakpoint, itree); + if (bp->flags =3D=3D flags) { cpu_breakpoint_remove_by_ref(cpu, bp); return 0; } } + return -ENOENT; } =20 /* Remove a specific breakpoint by reference. */ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp) { - QTAILQ_REMOVE(&cpu->breakpoints, bp, entry); - - trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags); + interval_tree_remove(&bp->itree, &cpu->breakpoints); + trace_breakpoint_remove(cpu->cpu_index, bp->itree.start, bp->flags); g_free(bp); } =20 /* Remove all matching breakpoints. */ void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask) { - CPUBreakpoint *bp, *next; + IntervalTreeNode *n; =20 - QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { + n =3D interval_tree_iter_first(&cpu->breakpoints, 0, -1); + while (n) { + CPUBreakpoint *bp =3D container_of(n, CPUBreakpoint, itree); + + n =3D interval_tree_iter_next(n, 0, -1); if (bp->flags & mask) { cpu_breakpoint_remove_by_ref(cpu, bp); } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index e314f916f8..5c2d7ed42c 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -322,7 +322,6 @@ static void cpu_common_initfn(Object *obj) qemu_mutex_init(&cpu->work_mutex); qemu_lockcnt_init(&cpu->in_ioctl_lock); QSIMPLEQ_INIT(&cpu->work_list); - QTAILQ_INIT(&cpu->breakpoints); QTAILQ_INIT(&cpu->watchpoints); =20 cpu_exec_initfn(cpu); diff --git a/linux-user/main.c b/linux-user/main.c index 83b9c88ac4..4372d0b5a6 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -239,7 +239,6 @@ CPUArchState *cpu_copy(CPUArchState *env) CPUState *cpu =3D env_cpu(env); CPUState *new_cpu =3D cpu_create(cpu_type); CPUArchState *new_env =3D cpu_env(new_cpu); - CPUBreakpoint *bp; =20 /* Reset non arch specific state */ cpu_reset(new_cpu); @@ -258,9 +257,16 @@ CPUArchState *cpu_copy(CPUArchState *env) /* Clone all break/watchpoints. Note: Once we support ptrace with hw-debug register access, make su= re BP_CPU break/watchpoints are handled correctly on clone. */ - QTAILQ_INIT(&new_cpu->breakpoints); - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, 0, NULL); + if (!interval_tree_is_empty(&cpu->breakpoints)) { + IntervalTreeNode *n; + + memset(&new_cpu->breakpoints, 0, sizeof(new_cpu->breakpoints)); + for (n =3D interval_tree_iter_first(&cpu->breakpoints, 0, -1); n; + n =3D interval_tree_iter_next(n, 0, -1)) { + CPUBreakpoint *bp =3D container_of(n, CPUBreakpoint, itree); + cpu_breakpoint_insert(new_cpu, bp->itree.start, + bp->flags, bp->id, NULL); + } } =20 return new_env; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index e626acef2f..4fcda9f273 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -1688,8 +1688,8 @@ void whpx_translate_cpu_breakpoints( CPUState *cpu, int cpu_breakpoint_count) { - CPUBreakpoint *bp; int cpu_bp_index =3D 0; + IntervalTreeNode *n; =20 breakpoints->original_addresses =3D g_renew(vaddr, breakpoints->original_addresses, cpu_breakpoint_cou= nt); @@ -1721,14 +1721,15 @@ void whpx_translate_cpu_breakpoints( } =20 /* 2. Map all CPU breakpoints to WHPX breakpoints */ - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - int i; + for (n =3D interval_tree_iter_first(&cpu->breakpoints, 0, -1); n; + n =3D interval_tree_iter_next(n, 0, -1)) { + vaddr pc =3D n->start; bool found =3D false; =20 /* This will be used to detect changed CPU breakpoints later. */ - breakpoints->original_addresses[cpu_bp_index++] =3D bp->pc; + breakpoints->original_addresses[cpu_bp_index++] =3D pc; =20 - for (i =3D 0; i < new_breakpoints->used; i++) { + for (int i =3D 0; i < new_breakpoints->used; i++) { /* * WARNING: This loop has O(N^2) complexity, where N is the * number of breakpoints. It should not be a bottleneck in @@ -1738,7 +1739,7 @@ void whpx_translate_cpu_breakpoints( * high-level breakpoint objects in a tree or hash map. */ =20 - if (new_breakpoints->data[i].address =3D=3D bp->pc) { + if (new_breakpoints->data[i].address =3D=3D pc) { /* There was already a breakpoint at this address. */ if (new_breakpoints->data[i].state =3D=3D WHPX_BP_CLEAR_PE= NDING) { new_breakpoints->data[i].state =3D WHPX_BP_SET; @@ -1753,7 +1754,7 @@ void whpx_translate_cpu_breakpoints( =20 if (!found && new_breakpoints->used < new_breakpoints->allocated) { /* No WHPX breakpoint at this address. Create one. */ - new_breakpoints->data[new_breakpoints->used].address =3D bp->p= c; + new_breakpoints->data[new_breakpoints->used].address =3D pc; new_breakpoints->data[new_breakpoints->used].state =3D WHPX_BP_SET_PENDING; new_breakpoints->used++; --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226392; cv=none; d=zohomail.com; s=zohoarc; b=Jxb673USwHYFn9DBfmOPi56FCGAFYziZy0S66Ush5bnXxXNpaY52lz593BHT2aQiov/B1e+O2v3/YtJBnOS0/6JoysQFyrg2xyhwppxQBGXejejNP/UDrwGpRXmOM+w8dGazdMT/Z3dGvYypUrHsZi4tk4kAhusm0G2Uf8uXBIw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226392; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LWeC8sovUKFGxLFpRs93xUZHyuZOaYN5bdNXTrhkucI=; b=n/Xg4GHgIiepTWJ/Mvza5wScU6aiMKjZG0VMIfHNLizDEv6JndmxJL+GPuNBhuZvl5knOoJbECAYDjk5dmBWf/+ssuQVxMg2vlJNNW8A6m48Z8FdhXYHQ7rnEFjBO3MNlnq3N1nM/3dP7IyqR3kWcXn5QXCtkoeSmlnsbmaj8OE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226392376856.8657238096349; Sat, 4 Jul 2026 21:39:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdH-0006gI-6H; Sun, 05 Jul 2026 00:39:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcE-00051t-5K for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:03 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEby-0004F5-69 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:01 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2c6b67d5fa1so18032285ad.2 for ; Sat, 04 Jul 2026 21:37:45 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226265; x=1783831065; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LWeC8sovUKFGxLFpRs93xUZHyuZOaYN5bdNXTrhkucI=; b=cC9q01OUBlRXqol6yGorabAnkYudCFr7BfXr78NWmn4JfsHKSBJDUX7RvvIKPV8TJG ztyUygPuVJfsqiyLp3JlGcw8TyII+YyXZcoW3V+fBYXI069r2Xk3X7zyNqmSskr0kc0T S069kHha9ZmWAnmVDRdGPOx7va3pyx36gAmnLOAZlIsrW/bwG60tigP9QOpD7x6vkhRa y4J39ISJfC33S5Oql0hHagmeeKUI1QVaJui7zQPSD8+FwP0dmhStyS5Ok2Qx6MGTtGRS xR6Vhqg9mBjM73AC1bOx29DB0Ny+t5EqSGmMeF+KiuTRhKVm5NVYOPKFkiY/GgjAdjXP NvOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226265; x=1783831065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=LWeC8sovUKFGxLFpRs93xUZHyuZOaYN5bdNXTrhkucI=; b=GFcmcuBEdUDCBrK8QMTtzxUGOQPQo4Vasx3B6k5vYkd4m36b7+u34+vOb1tSHUiQ7B z3ccGk+zVIVgsbCh0Mi6cXjd/jDFOvTqg4sefBcMuYtLywh6doKv0REhNCXbb+l7n36I K9SmMEB8m480oOMNIBIUaNNTPk3lE/wkwxscynPlxV1SkQA5R48Db7guZSLUB5fInl/E VI5ROT2+IDRYjzCxpRnAuuJKIHyRxZLKilKuiWDPTaxjzRrC6/Zq0ndXNDpjPpLNDQHO YdPQmS3Eag/rXVKAJicrCFXHMhQewIv1jTLgxhBuykSPqUiWqmtApSXnPIUQvDXIUf2D cPfA== X-Gm-Message-State: AOJu0Yyvttq4cjuVR/p3lscxGOScvSK6rYxow+FTrdie1QtLcmLBB4M5 JZC8L4PLDusk7d5xcuv8HX5rqcZAnHNsHVUcFbqoIzzoU2Pe30Ue8/rQQyxN1oAmnjgyxmvDeuB bDhZh X-Gm-Gg: AfdE7cneYNHGuwrootZqaZ6ODNKIj/RPw+P/6GQL1vnjFSqxypcQNyPC2B1cEQAr7Q7 mowjfRfVVMO1frXtyaZFPeOaVBiEJcAC/D66h93+E/IZurWgrW5kVH22CZPueCgrO0qJ0c1UZTz G5bRRYYUugV95a327wyxB5nLX39zLF+14vwP6pbPtmA5gtaX+BgqWvre1IC5NEfFoohZy07eJsE K9SMctw4NG+/zQvldfCPMsfbKIUtGclOBRxGOo85brzfVvAU9ikj7QLwPc1aZgx6BqGknLmmprx LyyUapaZBI3BVEpdELW96bhYji4rDRdHeLbSqUEOxSoUOpyNyCTJ36Q/1G/Y7H1QHHGlGZefMkW 5GomSkC+is+6NlFtHXGbughF+Ns6XuP/hI35MteNxkDZDTo9CJtd4c8KO1cBlFSyAA+bSyZnlFH B9zxALWiCaUBCL1ARb+/dHlzjiSW4nV1328I8RqtbWDe4CNFc= X-Received: by 2002:a17:902:d4c7:b0:2c9:e261:95ce with SMTP id d9443c01a7336-2cbb9ee3915mr50012645ad.30.1783226264680; Sat, 04 Jul 2026 21:37:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 20/46] target/arm: Make check_watchpoint_in_range static Date: Sat, 4 Jul 2026 21:36:59 -0700 Message-ID: <20260705043725.1373137-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226392841158500 Content-Type: text/plain; charset="utf-8" This function is not used outside hyp_gdbstub.c. Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 - target/arm/hyp_gdbstub.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 370876851e..53091fc73e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1966,7 +1966,6 @@ bool find_hw_breakpoint(CPUState *cpu, vaddr pc); int insert_hw_breakpoint(vaddr pc); int delete_hw_breakpoint(vaddr pc); =20 -bool check_watchpoint_in_range(int i, vaddr addr); CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr); int insert_hw_watchpoint(vaddr addr, vaddr len, int type); int delete_hw_watchpoint(vaddr addr, vaddr len, int type); diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c index bb5969720c..456a09e766 100644 --- a/target/arm/hyp_gdbstub.c +++ b/target/arm/hyp_gdbstub.c @@ -182,7 +182,7 @@ int insert_hw_watchpoint(vaddr addr, vaddr len, int typ= e) return 0; } =20 -bool check_watchpoint_in_range(int i, vaddr addr) +static bool check_watchpoint_in_range(int i, vaddr addr) { HWWatchpoint *wp =3D get_hw_wp(i); uint64_t addr_top, addr_bottom =3D wp->wvr; --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226380; cv=none; d=zohomail.com; s=zohoarc; b=QkXg2HFqGvAnId9z1RnnnKPIM1YN081tXpX/qjbu9Qbdafao1YT0uavNtFO8thSEJtx89lA6zYvSI5v/7OhoDNlFBk6JLpDN0e6bHihHg1Iof8Avr0WGFcizQa6hSfCEBiN+eBOmecsPGS9ja5L5ydDPcEZLqW9IEQ2VcMwAyVk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226380; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DjegbvMJwPTXHgna3JNNhxJJiZH5knkOZAN2effugW0=; b=fKpz74+xsLIeGRPl8dVOWQqRIGVyy+slqLqLGTvGBk28mqFJbmYjVXusfeVU92AajFKG2hcMgHFSaKvmAAK+lU+oR234vTjChG/f5575nzugvlPbK0T1DZCersCUkg12DqmKbYqXdgCbpv6O4IntZ/jtKMxZL46dWNQ/tDirfDY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226379949615.4591110271559; Sat, 4 Jul 2026 21:39:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdU-0007Fz-GN; Sun, 05 Jul 2026 00:39:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcF-000528-Ct for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:03 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEby-0004FX-UJ for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:03 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2c7cfa17fedso18583935ad.3 for ; Sat, 04 Jul 2026 21:37:46 -0700 (PDT) Received: from stoup.. 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Adjust all virtualization hosts which construct a dummy CPUWatchpoint structure. Signed-off-by: Richard Henderson --- gdbstub/system.c | 4 ++-- target/arm/hvf/hvf.c | 1 + target/arm/kvm.c | 1 + target/i386/kvm/kvm.c | 4 ++-- target/ppc/kvm.c | 4 ++-- target/s390x/kvm/kvm.c | 2 +- 6 files changed, 9 insertions(+), 7 deletions(-) diff --git a/gdbstub/system.c b/gdbstub/system.c index 0b810477ee..017585187f 100644 --- a/gdbstub/system.c +++ b/gdbstub/system.c @@ -165,10 +165,10 @@ static void gdb_vm_state_change(void *opaque, bool ru= nning, RunState state) } trace_gdbstub_hit_watchpoint(type, gdb_get_cpu_index(cpu), - cpu->watchpoint_hit->vaddr); + cpu->watchpoint_hit->hitaddr); g_string_printf(buf, "T%02xthread:%s;%swatch:%" VADDR_PRIx ";", GDB_SIGNAL_TRAP, tid->str, type, - cpu->watchpoint_hit->vaddr); + cpu->watchpoint_hit->hitaddr); cpu->watchpoint_hit =3D NULL; goto send_packet; } else { diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8b902c6882..0a383b9295 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -2377,6 +2377,7 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcp= u_exit_exception_t *excp) if (!wp) { error_report("EXCP_DEBUG but unknown hw watchpoint"); } + wp->hitaddr =3D excp->virtual_address; cpu->watchpoint_hit =3D wp; break; } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index a54ef51ec2..72a53bd7c3 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1519,6 +1519,7 @@ static bool kvm_arm_handle_debug(ARMCPU *cpu, { CPUWatchpoint *wp =3D find_hw_watchpoint(cs, debug_exit->far); if (wp) { + wp->hitaddr =3D debug_exit->far; cs->watchpoint_hit =3D wp; return true; } diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 54bee753fa..8c9304ddaf 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -6262,13 +6262,13 @@ static int kvm_handle_debug(X86CPU *cpu, case 0x1: ret =3D EXCP_DEBUG; cs->watchpoint_hit =3D &hw_watchpoint; - hw_watchpoint.vaddr =3D hw_breakpoint[n].addr; + hw_watchpoint.hitaddr =3D hw_breakpoint[n].addr; hw_watchpoint.flags =3D BP_MEM_WRITE; break; case 0x3: ret =3D EXCP_DEBUG; cs->watchpoint_hit =3D &hw_watchpoint; - hw_watchpoint.vaddr =3D hw_breakpoint[n].addr; + hw_watchpoint.hitaddr =3D hw_breakpoint[n].addr; hw_watchpoint.flags =3D BP_MEM_ACCESS; break; } diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index c44edac41f..82c1396970 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1587,11 +1587,11 @@ static int kvm_handle_hw_breakpoint(CPUState *cs, KVMPPC_DEBUG_WATCH_WRITE)) { BreakpointFlags flag =3D 0; =20 - n =3D find_hw_watchpoint(arch_info->address, &flag); + n =3D find_hw_watchpoint(arch_info->address, &flag); if (n >=3D 0) { handle =3D DEBUG_RETURN_GDB; cs->watchpoint_hit =3D &hw_watchpoint; - hw_watchpoint.vaddr =3D hw_debug_points[n].addr; + hw_watchpoint.hitaddr =3D arch_info->address; hw_watchpoint.flags =3D flag; } } diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 9658534fa6..7cd199578b 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -1862,7 +1862,7 @@ static int kvm_arch_handle_debug_exit(S390CPU *cpu) case KVM_HW_WP_WRITE: if (find_hw_breakpoint(arch_info->addr, -1, arch_info->type)) { cs->watchpoint_hit =3D &hw_watchpoint; - hw_watchpoint.vaddr =3D arch_info->addr; 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Using an interval tree makes it easy to probe for any overlapping address. Signed-off-by: Richard Henderson --- include/exec/breakpoint.h | 7 +- include/hw/core/cpu.h | 3 +- accel/tcg/cpu-exec.c | 8 +- accel/tcg/watchpoint.c | 155 +++++++++++++++++++++----------------- hw/core/cpu-common.c | 1 - system/watchpoint.c | 43 ++++++----- target/arm/hyp_gdbstub.c | 3 +- 7 files changed, 119 insertions(+), 101 deletions(-) diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index 5f0025a3c9..3ea6e26fa4 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -9,7 +9,6 @@ #define EXEC_BREAKPOINT_H =20 #include "qemu/interval-tree.h" -#include "qemu/queue.h" #include "exec/vaddr.h" #include "exec/memattrs.h" =20 @@ -35,13 +34,11 @@ struct CPUBreakpoint { }; =20 struct CPUWatchpoint { - vaddr vaddr; - vaddr len; + IntervalTreeNode itree; vaddr hitaddr; MemTxAttrs hitattrs; - int flags; /* BP_* */ + BreakpointFlags flags; unsigned id; - QTAILQ_ENTRY(CPUWatchpoint) entry; }; =20 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b6368c2c2f..ccfcab6a8a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -525,8 +525,7 @@ struct CPUState { =20 /* ice debug support */ IntervalTreeRoot breakpoints; - - QTAILQ_HEAD(, CPUWatchpoint) watchpoints; + IntervalTreeRoot watchpoints; CPUWatchpoint *watchpoint_hit; =20 void *opaque; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5812cb57aa..24b72c358d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -682,10 +682,12 @@ static inline bool cpu_handle_halt(CPUState *cpu) static inline void cpu_handle_debug_exception(CPUState *cpu) { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; - CPUWatchpoint *wp; + IntervalTreeNode *n; =20 - if (!cpu->watchpoint_hit) { - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { + for (n =3D interval_tree_iter_first(&cpu->watchpoints, 0, -1); n; + n =3D interval_tree_iter_next(n, 0, -1)) { + CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + if (wp !=3D cpu->watchpoint_hit) { wp->flags &=3D ~BP_WATCHPOINT_HIT; } } diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index 5ea66e9763..a7ce5fa9dd 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -30,38 +30,18 @@ #include "hw/core/cpu.h" #include "internal-common.h" =20 -/* - * Return true if this watchpoint address matches the specified - * access (ie the address range covered by the watchpoint overlaps - * partially or completely with the address range covered by the - * access). - */ -static inline bool watchpoint_address_matches(CPUWatchpoint *wp, - vaddr addr, vaddr len) -{ - /* - * We know the lengths are non-zero, but a little caution is - * required to avoid errors in the case where the range ends - * exactly at the top of the address space and so addr + len - * wraps round to zero. - */ - vaddr wpend =3D wp->vaddr + wp->len - 1; - vaddr addrend =3D addr + len - 1; - - return !(addr > wpend || wp->vaddr > addrend); -} - /* Return flags for watchpoints that match addr + prot. */ BreakpointFlags cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len) { - CPUWatchpoint *wp; + vaddr last =3D addr + len - 1; BreakpointFlags ret =3D 0; + IntervalTreeNode *n; =20 - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (watchpoint_address_matches(wp, addr, len)) { - ret |=3D wp->flags; - } + for (n =3D interval_tree_iter_first(&cpu->watchpoints, addr, last); n; + n =3D interval_tree_iter_next(n, addr, last)) { + CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + ret |=3D wp->flags; } return ret; } @@ -70,7 +50,10 @@ BreakpointFlags cpu_watchpoint_address_matches(CPUState = *cpu, void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, MemTxAttrs attrs, BreakpointFlags flags, uintptr= _t ra) { - CPUWatchpoint *wp; + vaddr last =3D addr + len - 1; + IntervalTreeNode *n; + CPUWatchpoint *found_wp =3D NULL; + bool have_cpu_wp =3D false; =20 assert(tcg_enabled()); if (cpu->watchpoint_hit) { @@ -88,56 +71,90 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, if (cpu->cc->tcg_ops->adjust_watchpoint_address) { /* this is currently used only by ARM BE32 */ addr =3D cpu->cc->tcg_ops->adjust_watchpoint_address(cpu, addr, le= n); + last =3D addr + len - 1; } =20 assert((flags & ~BP_MEM_ACCESS) =3D=3D 0); - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - BreakpointFlags hit_flags =3D wp->flags & flags; =20 - if (hit_flags && watchpoint_address_matches(wp, addr, len)) { - if (replay_running_debug()) { - /* - * replay_breakpoint reads icount. - * Force recompile to succeed, because icount may - * be read only at the end of the block. - */ - if (!cpu->neg.can_do_io) { - /* Force execution of one insn next time. */ - cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(cpu= ); - cpu_loop_exit_restore(cpu, ra); - } - /* - * Don't process the watchpoints when we are - * in a reverse debugging operation. - */ - replay_breakpoint(); - return; - } + for (n =3D interval_tree_iter_first(&cpu->watchpoints, addr, last); n; + n =3D interval_tree_iter_next(n, addr, last)) { + CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); =20 - wp->flags |=3D hit_flags << BP_HIT_SHIFT; - wp->hitaddr =3D MAX(addr, wp->vaddr); - wp->hitattrs =3D attrs; - - if (wp->flags & BP_CPU - && cpu->cc->tcg_ops->debug_check_watchpoint - && !cpu->cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { + if (wp->flags & flags) { + /* + * Prefer GDB over CPU watchpoint, so we can take the first + * GDB watchpoint that we see. + */ + if (wp->flags & BP_GDB) { wp->flags &=3D ~BP_WATCHPOINT_HIT; - continue; - } - cpu->watchpoint_hit =3D wp; + wp->flags |=3D flags << BP_HIT_SHIFT; + wp->hitaddr =3D MAX(addr, wp->itree.start); + wp->hitattrs =3D attrs; =20 - /* This call also restores vCPU state */ - tb_check_watchpoint(cpu, ra); - if (wp->flags & BP_STOP_BEFORE_ACCESS) { - cpu->exception_index =3D EXCP_DEBUG; - cpu_loop_exit(cpu); - } else { - /* Force execution of one insn next time. */ - cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(cpu); - cpu_loop_exit_noexc(cpu); + found_wp =3D wp; + goto found; } - } else { - wp->flags &=3D ~BP_WATCHPOINT_HIT; + have_cpu_wp =3D true; } } + + if (have_cpu_wp) { + const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; + + for (n =3D interval_tree_iter_first(&cpu->watchpoints, addr, last)= ; n; + n =3D interval_tree_iter_next(n, addr, last)) { + CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + + if ((wp->flags & BP_CPU) && (wp->flags & flags)) { + wp->flags &=3D ~BP_WATCHPOINT_HIT; + wp->flags |=3D flags << BP_HIT_SHIFT; + wp->hitaddr =3D MAX(addr, wp->itree.start); + wp->hitattrs =3D attrs; + + if (tcg_ops->debug_check_watchpoint + && !tcg_ops->debug_check_watchpoint(cpu, wp)) { + wp->flags &=3D ~BP_WATCHPOINT_HIT; + continue; + } + + found_wp =3D wp; + goto found; + } + } + } + return; + + found: + if (replay_running_debug()) { + /* + * replay_breakpoint reads icount. + * Force recompile to succeed, because icount may + * be read only at the end of the block. + */ + if (!cpu->neg.can_do_io) { + /* Force execution of one insn next time. */ + cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(cpu); + cpu_loop_exit_restore(cpu, ra); + } + /* + * Don't process the watchpoints when we are + * in a reverse debugging operation. + */ + replay_breakpoint(); + return; + } + + cpu->watchpoint_hit =3D found_wp; + + /* This call also restores vCPU state */ + tb_check_watchpoint(cpu, ra); + if (found_wp->flags & BP_STOP_BEFORE_ACCESS) { + cpu->exception_index =3D EXCP_DEBUG; + cpu_loop_exit(cpu); + } else { + /* Force execution of one insn next time. */ + cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(cpu); + cpu_loop_exit_noexc(cpu); + } + qemu_build_not_reached(); } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 5c2d7ed42c..868c7c4d46 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -322,7 +322,6 @@ static void cpu_common_initfn(Object *obj) qemu_mutex_init(&cpu->work_mutex); qemu_lockcnt_init(&cpu->in_ioctl_lock); QSIMPLEQ_INIT(&cpu->work_list); - QTAILQ_INIT(&cpu->watchpoints); =20 cpu_exec_initfn(cpu); =20 diff --git a/system/watchpoint.c b/system/watchpoint.c index a618bb5acd..ed505da403 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -30,26 +30,23 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, va= ddr len, CPUWatchpoint **watchpoint) { CPUWatchpoint *wp; + vaddr last =3D addr + len - 1; vaddr in_page; =20 /* forbid ranges which are empty or run off the end of the address spa= ce */ - if (len =3D=3D 0 || (addr + len - 1) < addr) { + if (len =3D=3D 0 || last < addr) { error_report("tried to set invalid watchpoint at %" VADDR_PRIx ", len=3D%" VADDR_PRIu, addr, len); return -EINVAL; } - wp =3D g_malloc(sizeof(*wp)); =20 - wp->vaddr =3D addr; - wp->len =3D len; + wp =3D g_new0(CPUWatchpoint, 1); + + wp->itree.start =3D addr; + wp->itree.last =3D last; wp->flags =3D flags; =20 - /* keep all GDB-injected watchpoints in front */ - if (flags & BP_GDB) { - QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); - } else { - QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); - } + interval_tree_insert(&wp->itree, &cpu->watchpoints); =20 in_page =3D -(addr | TARGET_PAGE_MASK); if (len <=3D in_page) { @@ -68,11 +65,16 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, va= ddr len, int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, BreakpointFlags flags) { - CPUWatchpoint *wp; + vaddr last =3D addr + len - 1; + IntervalTreeNode *n; =20 - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (addr =3D=3D wp->vaddr && len =3D=3D wp->len - && flags =3D=3D (wp->flags & ~BP_WATCHPOINT_HIT)) { + for (n =3D interval_tree_iter_first(&cpu->watchpoints, addr, addr); n; + n =3D interval_tree_iter_next(n, addr, addr)) { + CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + + if (addr =3D=3D wp->itree.start && + last =3D=3D wp->itree.last && + flags =3D=3D (wp->flags & ~BP_WATCHPOINT_HIT)) { cpu_watchpoint_remove_by_ref(cpu, wp); return 0; } @@ -83,19 +85,20 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, va= ddr len, /* Remove a specific watchpoint by reference. */ void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) { - QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); - - tlb_flush_page(cpu, watchpoint->vaddr); - + interval_tree_remove(&watchpoint->itree, &cpu->watchpoints); + tlb_flush_page(cpu, watchpoint->itree.start); g_free(watchpoint); } =20 /* Remove all matching watchpoints. */ void cpu_watchpoint_remove_all(CPUState *cpu, BreakpointFlags mask) { - CPUWatchpoint *wp, *next; + IntervalTreeNode *n =3D interval_tree_iter_first(&cpu->watchpoints, 0,= -1); =20 - QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { + while (n) { + CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + + n =3D interval_tree_iter_next(n, 0, -1); if (wp->flags & mask) { cpu_watchpoint_remove_by_ref(cpu, wp); } diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c index 456a09e766..5ecc0939e9 100644 --- a/target/arm/hyp_gdbstub.c +++ b/target/arm/hyp_gdbstub.c @@ -130,7 +130,8 @@ int insert_hw_watchpoint(vaddr addr, vaddr len, int typ= e) HWWatchpoint wp =3D { .wcr =3D R_DBGWCR_E_MASK, /* E=3D1, enable */ .wvr =3D addr & (~0x7ULL), - .details =3D { .vaddr =3D addr, .len =3D len } + .details.itree.start =3D addr, + .details.itree.last =3D addr + len - 1, }; =20 if (cur_hw_wps >=3D max_hw_wps) { --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226267; x=1783831067; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e4K8RhxfUacDFKhHYVq83mau4+fuBNq23ZKV7DxrKlc=; b=JqIIH0xvJUuj0PZb7pAIjQs08WClc6QUfiVN2ofEpufs+8sCDHVKaok8YMD9JofRMB o43SdnVkuoBuKZ7814aqAkAVsJfs1ITPP95FAHgBxSmAZtjnxLPjmc9bZi0rYEPXgdc1 T2QJXSGIEuhmX695Ho4+laau0gpkSL1JICNVfKIkSN9+lxwotGZCx+9IRslAnIHsmNXc rdjEvqKLE37iJcGUfKdTpfEiPmyhjFO3lc3uO8Cz0BDQ8XHqzj5ToPzFlzhHsaEF4dek A8Dn4DhgQPokhHLgFSbLZQO7ddH+0TCwkjxiLqjcYmyu4nfP3yu5qXBxQyYGETqmJDNy h6xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226267; x=1783831067; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=e4K8RhxfUacDFKhHYVq83mau4+fuBNq23ZKV7DxrKlc=; b=K6uussaeE6GKMbSlD7deoBRsVFx1MGKlWLcIJAngIh0Pa6nQlSYhmkqAzICU/3fgfg 66+O1GSCa15uyGEKSwmhNZxCz31U21YDAoBmJUpN+C+0cleqOVV86/aO6DXlJCUMlpps eoCmUtgwZ4j5H4/2lfEDWQwEyjk5CY2s7PX7Utr4ImVgRXmau6WLoDsYvyK3mvxHmkXT b7c8TopOzXlWURROs3XyOxnkYsE0qP8GC1ztfqmEZmHjM0NMzzovU/5LnU4UryGtcGaZ sxyweQZn3Ggw6DzyQER4Jwt5rTzUtZJoz2+UFwnKdfn8DidtUkYcjAYVuc4AKesAz0T1 td/A== X-Gm-Message-State: AOJu0YwUZhAktSqsN32xWj44AJaIOwNqJB3uNQV0TcDMGfScezdjeVon CpQSzHne6a1nSKw9aPhpz3Uen3Wm03ynFPbe783bU9RD2kwYuUfLYVP/IxdvLigaBwpoBtoIk46 81FqE X-Gm-Gg: AfdE7cnExdWOTvbM7XvVMY6//+Pp3lU4pQHZva9zypmEoTpBiTJ+6xcweXc/HJeLe8K PISS461KMmnsCI1/7RElCnfINEUMqM48/sMs/mQ4QDWZ5ofZWB5GOG7cvKQFDPVOgYDGF+wnajE cvly17DcxZlLzyfhPhr4mMTPVfxPVVqKL6P65AssV5/Us3FL6KWH80ZgWFAH1MJwthbQTtCnnfD pPIsdBLk2syTfUl2hyWMIK1eHzwGct14n/TsphyFQagAh8+HNITvCE359XWiuETeQfSsGz/NP5w /w/jHHJHI6/OtygNKRCQpeQ6Jy4hFswnQrsLYTmlhMwOPmt81zCWBr8m9XszbeKVFEvzepIQfav clFQC6VhhQu8frfGWvu/unPHCSFx0J1j752IijkbxrYNs0yNXlkRK8qQ9bBoCkzj0SGKr3HveB6 9Q/irqDSGJeGgEHqRyYYfjSOjKG7atDFpQKeyO1q8bEa71/xY= X-Received: by 2002:a17:902:d585:b0:2c7:f2c6:89e0 with SMTP id d9443c01a7336-2cb97e5405emr54895295ad.4.1783226266934; Sat, 04 Jul 2026 21:37:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 23/46] exec/breakpoint: Return the new bp from cpu_breakpoint_insert Date: Sat, 4 Jul 2026 21:37:02 -0700 Message-ID: <20260705043725.1373137-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226968917158500 Content-Type: text/plain; charset="utf-8" The cpu_breakpoint_insert function cannot fail, so the error return value isn't actually used. Instead of returning the new breakpoint by reference, return it directly. Signed-off-by: Richard Henderson --- include/exec/breakpoint.h | 4 ++-- accel/tcg/tcg-accel-ops.c | 7 ++----- cpu-common.c | 11 +++-------- gdbstub/user.c | 8 ++------ linux-user/main.c | 2 +- target/arm/tcg/debug.c | 2 +- target/i386/tcg/system/bpt_helper.c | 3 +-- target/ppc/cpu.c | 2 +- target/riscv/debug.c | 5 ++--- target/xtensa/dbg_helper.c | 6 +++--- 10 files changed, 18 insertions(+), 32 deletions(-) diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index 3ea6e26fa4..90bfe5e237 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -41,8 +41,8 @@ struct CPUWatchpoint { unsigned id; }; =20 -int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, - unsigned id, CPUBreakpoint **breakpoint); +CPUBreakpoint *cpu_breakpoint_insert(CPUState *cpu, vaddr pc, + BreakpointFlags flags, unsigned id); int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, BreakpointFlags flags); void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint= ); void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask); diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 37cdd354f0..9d9ecf542c 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -141,12 +141,9 @@ static int tcg_insert_breakpoint(CPUState *cs, int typ= e, vaddr addr, vaddr len) case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: CPU_FOREACH(cpu) { - err =3D cpu_breakpoint_insert(cpu, addr, BP_GDB, 0, NULL); - if (err) { - break; - } + cpu_breakpoint_insert(cpu, addr, BP_GDB, 0); } - return err; + return 0; case GDB_WATCHPOINT_WRITE: case GDB_WATCHPOINT_READ: case GDB_WATCHPOINT_ACCESS: diff --git a/cpu-common.c b/cpu-common.c index 0287022de4..fcc9bc77a3 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -405,8 +405,8 @@ bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, Break= pointFlags mask) } =20 /* Add a breakpoint. */ -int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, BreakpointFlags flags, - unsigned id, CPUBreakpoint **breakpoint) +CPUBreakpoint *cpu_breakpoint_insert(CPUState *cpu, vaddr pc, + BreakpointFlags flags, unsigned id) { CPUBreakpoint *bp; =20 @@ -422,13 +422,8 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, Bre= akpointFlags flags, bp->id =3D id; =20 interval_tree_insert(&bp->itree, &cpu->breakpoints); - - if (breakpoint) { - *breakpoint =3D bp; - } - trace_breakpoint_insert(cpu->cpu_index, pc, flags); - return 0; + return bp; } =20 /* Remove a specific breakpoint. */ diff --git a/gdbstub/user.c b/gdbstub/user.c index abcb2ec5f0..9abe42280e 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -806,18 +806,14 @@ bool gdb_supports_guest_debug(void) int gdb_breakpoint_insert(CPUState *cs, int type, vaddr addr, vaddr len) { CPUState *cpu; - int err =3D 0; =20 switch (type) { case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: CPU_FOREACH(cpu) { - err =3D cpu_breakpoint_insert(cpu, addr, BP_GDB, 0, NULL); - if (err) { - break; - } + cpu_breakpoint_insert(cpu, addr, BP_GDB, 0); } - return err; + return 0; default: /* user-mode doesn't support watchpoints */ return -ENOSYS; diff --git a/linux-user/main.c b/linux-user/main.c index 4372d0b5a6..54d39627f6 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -265,7 +265,7 @@ CPUArchState *cpu_copy(CPUArchState *env) n =3D interval_tree_iter_next(n, 0, -1)) { CPUBreakpoint *bp =3D container_of(n, CPUBreakpoint, itree); cpu_breakpoint_insert(new_cpu, bp->itree.start, - bp->flags, bp->id, NULL); + bp->flags, bp->id); } } =20 diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index daad2ac440..2c73ca1080 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -685,7 +685,7 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) return; } =20 - cpu_breakpoint_insert(CPU(cpu), addr, flags, n, &env->cpu_breakpoint[n= ]); + env->cpu_breakpoint[n] =3D cpu_breakpoint_insert(CPU(cpu), addr, flags= , n); } =20 void hw_breakpoint_update_all(ARMCPU *cpu) diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index 662ffbacfc..23f2d05126 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -62,8 +62,7 @@ static int hw_breakpoint_insert(CPUX86State *env, int ind= ex) switch (hw_breakpoint_type(dr7, index)) { case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(dr7, index)) { - err =3D cpu_breakpoint_insert(cs, drN, BP_CPU, index, - &env->cpu_breakpoint[index]); + env->cpu_breakpoint[index] =3D cpu_breakpoint_insert(cs, drN, = BP_CPU, index); } break; =20 diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index cf4d97285e..c91e60940a 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -121,7 +121,7 @@ void ppc_update_ciabr(CPUPPCState *env) } =20 if (priv) { - cpu_breakpoint_insert(cs, ciea, BP_CPU, 0, &env->ciabr_breakpoint); + env->ciabr_breakpoint =3D cpu_breakpoint_insert(cs, ciea, BP_CPU, = 0); } } =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 56ae1e6107..d6bba24c81 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -488,7 +488,7 @@ static void type2_breakpoint_insert(CPURISCVState *env,= target_ulong index) } =20 if (ctrl & TYPE2_EXEC) { - cpu_breakpoint_insert(cs, addr, flags, 0, &env->cpu_breakpoint[ind= ex]); + env->cpu_breakpoint[index] =3D cpu_breakpoint_insert(cs, addr, fla= gs, 0); } =20 if (ctrl & TYPE2_LOAD) { @@ -613,8 +613,7 @@ static void type6_breakpoint_insert(CPURISCVState *env,= target_ulong index) } =20 if (ctrl & TYPE6_EXEC) { - cpu_breakpoint_insert(cs, addr, flags, index, - &env->cpu_breakpoint[index]); + env->cpu_breakpoint[index] =3D cpu_breakpoint_insert(cs, addr, fla= gs, index); } =20 if (ctrl & TYPE6_LOAD) { diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index b08bd03435..9df0c519b3 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -42,8 +42,8 @@ void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32= _t v) for (i =3D 0; i < env->config->nibreak; ++i) { if (change & (1 << i)) { if (v & (1 << i)) { - cpu_breakpoint_insert(cs, env->sregs[IBREAKA + i], - BP_CPU, i, &env->cpu_breakpoint[i]); + env->cpu_breakpoint[i] =3D + cpu_breakpoint_insert(cs, env->sregs[IBREAKA + i], BP_= CPU, i); } else { cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[i]); env->cpu_breakpoint[i] =3D NULL; @@ -59,7 +59,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i,= uint32_t v) CPUState *cs =3D env_cpu(env); =20 cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[i]); - cpu_breakpoint_insert(cs, v, BP_CPU, i, &env->cpu_breakpoint[i]); + env->cpu_breakpoint[i] =3D cpu_breakpoint_insert(cs, v, BP_CPU, i); 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226268; x=1783831068; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=G80BIhmHv+bQcepwqHTSRclxi+Da20PNHFYyztrE4Ag=; b=OPXd7n894wMc9G86nZH9X43zeGoYmSvwR/pWoInvilPNa9T3jom+XtozXNl+rGwFpE YP+sJJUqeCnRI7RLyDWY8zoMPFf1SNZOGUrHr8WXx8dRtGaIxLm+K1E3Fg2fjlJElhJ2 jtOEAIF+TOgQ8G1sYLaqlOCUmVWDDCD1FnZJ0f52++hTxpu3ZW0DX34I0z2TsJHZUOqO AMSLUCPtl4fB2dSJbepoU7DNrjLNgGaNoIOSj9yuHUABSGScIhPmk/tweEE5enL1cYd4 eQSRdPXX2gvj//sCykcmQ3uZJp5q0Pmj8gUzl21dzKr2P8QuSZNQtwcqHCU01MUt6Qb5 +IyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226268; x=1783831068; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=G80BIhmHv+bQcepwqHTSRclxi+Da20PNHFYyztrE4Ag=; b=tRTwd0DnmG2EWyw9lMOmDk9JYftOCNNrkZZIw3XmEAwIf8gkMD3NujVZly9KosKcYS J5nih/fGHy2cv2WVHil7qJRdBEBoFtXwbHOkCZaZGmGnDNA2sY0Qh08wa2ShfiBqlEx2 K0QmByldFqkvhgp7EUwNd7I1/JDABij+pqT7Zi9XY54V+m46pXkbUSvOLVgQVPZa2ajn jJ9k2cxsfn7sCKqLVQww0x6hoZf/y/QOxeNRFDDTiZ1vdEXYrLiUY/hYgVgF8dl9pK8T Pc61/sEEoSy+hCb3vx3m20Rs/eLfubr4LV/6UZro6qCCTkan8kO7cQRGtq1iWlpwSaEx BQkw== X-Gm-Message-State: AOJu0Yxlk78xa2ArVK1i7zqdVyE9KhVUJmsAV0mojtnkj3FObLhA1Xeo zpZ+c13SLMdf45ifszmoFEgPovHb0BQmnL3Gru8wxODbRgVgGHWs5+Geu+rRr59AuEVaM9phC0D mhFgT X-Gm-Gg: AfdE7cnbCp1fpN3Pudl/dTlZfIm9vNPc6f3rPew7M/1if6zxhggdgDIy5nJm0F6meBV W5sseh4VH34JwHY11rP1XiiJiV0/lPoOphnz5hB1zIcj01PGMWBe0h7OD1HMxQYxhH6R8/BQ3K+ mYWRMhxkuupf9YNPXkIEe5Kg4zIC0HaSS7rA3VZtq/dj0r/qhi2XDZaNewReRdRaNlXthCH1tH9 ZR94EeJyDwcEVIlThJdiuWwTuaxqfQJNEH70XHWbbrdO1rrxsfH7kwQsAuldKChSkxIwLwfPp3m bk21/fJq2EIxY1wFSPXqbfBT6OqsGNFIVqEqWPbulIFH6utJmTjaF6rwyzalSYazrF2FgWwdi0d 5m74HO0l5cSyhyYSMcipBpZvNNd9rSLXDTUxiMUrG1M4KHps6exhkMqocTPahn0RG2XqfU25x0h lUUkqJyH0gYx7YCDoy7ymb2JVUPrl58Aa9LeUvyBIv+OWdyts= X-Received: by 2002:a17:902:f78c:b0:2c9:c95e:5836 with SMTP id d9443c01a7336-2cb97e42fedmr53057565ad.5.1783226267658; Sat, 04 Jul 2026 21:37:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 24/46] system: Remove cpu_watchpoint_insert error return path Date: Sat, 4 Jul 2026 21:37:03 -0700 Message-ID: <20260705043725.1373137-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226900365158500 Content-Type: text/plain; charset="utf-8" Move the validation of the address range to tcg_insert_breakpoint, which has to deal with gdbstub inputs. Leave assertions behind in cpu_watchpoint_insert, but no error return path. Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops.c | 3 +++ system/watchpoint.c | 9 ++------- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 9d9ecf542c..8954514f24 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -147,6 +147,9 @@ static int tcg_insert_breakpoint(CPUState *cs, int type= , vaddr addr, vaddr len) case GDB_WATCHPOINT_WRITE: case GDB_WATCHPOINT_READ: case GDB_WATCHPOINT_ACCESS: + if (len =3D=3D 0 || addr + (len - 1) < addr) { + return -EINVAL; + } CPU_FOREACH(cpu) { err =3D cpu_watchpoint_insert(cpu, addr, len, xlat_gdb_type(cpu, type), 0, NULL); diff --git a/system/watchpoint.c b/system/watchpoint.c index ed505da403..01cf0f61a8 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -18,7 +18,6 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/error-report.h" #include "exec/cputlb.h" #include "exec/target_page.h" #include "exec/breakpoint.h" @@ -33,12 +32,8 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vad= dr len, vaddr last =3D addr + len - 1; vaddr in_page; =20 - /* forbid ranges which are empty or run off the end of the address spa= ce */ - if (len =3D=3D 0 || last < addr) { - error_report("tried to set invalid watchpoint at %" - VADDR_PRIx ", len=3D%" VADDR_PRIu, addr, len); - return -EINVAL; - } + assert(len !=3D 0); + assert(last >=3D addr); =20 wp =3D g_new0(CPUWatchpoint, 1); =20 --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226849; cv=none; d=zohomail.com; s=zohoarc; b=Y2J97DdA/ZBqH5vv/7aStxVPqOuNa3cOJbOp7RvT5dkwieDDNxKIWsuijVJrFD7xo9DPyV1w7Vti1HJ+LNi5IQyFg4k/nRuOZMuDnJ4VBXEaXxNfZRi/X9rHDey6KEyDagzyrUSj8Ytf7XgBtZXUiG4z7YuhS8SaN9F3tsVK6zk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226849; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/XLZ7YKA7/g2kmg2T8PCV+riLxmZ783WmnVxd6hC718=; b=gf8FEkmRUWJZy2iuktYH8gn3rQt8WY+2pmB6qOMURv66amjSbm/bLpM7HGW4+JpmTMAOQWUvG3ymEc4UF+wa+BtGBX4mPoMLlyNw7JjLTWVK2u6orb/UhA0pSGi+Y1dofFI/yCeQL4dnsTv3OMx0A4fryAw2ZtRgkW8CMv+ymi0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226849682296.14822527218826; Sat, 4 Jul 2026 21:47:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEds-0008FO-Eb; Sun, 05 Jul 2026 00:39:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcM-000581-Na for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:13 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEc2-0004Hk-6p for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:10 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-ca1328b8584so1151039a12.1 for ; Sat, 04 Jul 2026 21:37:49 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226268; x=1783831068; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=/XLZ7YKA7/g2kmg2T8PCV+riLxmZ783WmnVxd6hC718=; b=YEcYqncrhifIlE2aTE1pm8Y5fkU90r+q9tPu1AUHClIZgs9p2/M0QgnV3GejKWk8x5 axp43GonA7+ALIsRhUGImtDOHPjNK9yjNDJwjbYIebGArHzaniSOGx5MWtg1ZJ6sdapi dz39kZyo05X8spFpwaSeCWw/TLdw+6QCAeGp4Y8bcc2hSwhsrWZjgg/mz827rUC0I4xF vOAYDzBw3osbbCDEmGM8vHhk0mzmo0pUf+mYsVB0pKFWW6dt1PZLWyPh1+17LjxFFyBK mR+Jl6JyLJzHJRE5S1au79mmeTiDxyRPEnrLxQ8Z89C6O1KUvFsuxRhYhSYiizDYMHuW 1iWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226268; x=1783831068; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=/XLZ7YKA7/g2kmg2T8PCV+riLxmZ783WmnVxd6hC718=; b=QD4b3abUq+b7CDkR9In/VCyvKk8TTCzyd0kGAdP/AYLtqka8JKrSqBT6A+/zkhMq7r ok8GEDaL/Brkr634GmI7EFAj1V3n3hXbL/eAzv6A2CeXfTbq7eVvyl3SSGCca8qioKCW AeOSCSVJX0OoH4/M6Z7mqpqlv4WV3kdTjsjZ5quP0WANC9V2jCfl9bg4nx1bvkRvac79 NtDtNLr4jJRHchj4ACm6dqYpYEXEzxxPvCd7lS8oUXgL4Nb4AuSDFI6VCS7sOM5s6ggL PS+Skp4KXoe2WMgvQnWu1/bbeAFV92+L7Wwh8ajyFvvHQuEisX/sjC9cxlhFmBFz8Fsc MHjw== X-Gm-Message-State: AOJu0Yyel1oR0y7TNQieeHVxjQivv/QQ/Uf8wz0MBpY/U4Jrsrjr76MS 4x9K9TYJ2t5RX5TqYEnBwP4HZojwbO+5Vhjl206UdyDX3qYYMo5bDO1COEFUwTx6mK7P8+J6lqy W/9I9 X-Gm-Gg: AfdE7ckkeWy5GVYuHmpFjf/769qv/tb7xsxeh1R0rOc4hG54j973yyYdb6i8XgzP1pm bzf1zJfkTU2tgnV8CGNsRp71UBJR7NEpyNKkNUTTdUi2haVCCDmarZyqpH07ayB6CMKmwbSQVKB V008We4b2aXyp58ymMQc6vAOE5F1tg4w4KCbTE1eaIhSfhjfHwVKE7EyDM9z97vgO36y17nVoYp 7NdjNzCKdEZpxibMtfkaZ+lcT8RcBq+QJ0nplxtwqWj2JGJTJDI9ZWZm07mhijxEWfRc95qvz0q dDj6EClPwbkqapzeZ6N3PQk3oefGl34jmdyRllQJcf4/BNNIL0EXv4e8a/Q0MHg+ytA9HXkJrFu uhGJhDOAjaGtUE8M8bxx5GX5pR76CwgFgmPbjfLEg0tsvPIwTrLA9N352UWBkuBS2010byMBBr+ p1dCtw1XwQ7D5jV32ghDDd6AX8d7Jjgt9ilD37XEPfoIDFFfELGui0l++Qgw== X-Received: by 2002:a17:902:f706:b0:2ca:20b1:3e0a with SMTP id d9443c01a7336-2cbb1e31588mr52386385ad.3.1783226268397; Sat, 04 Jul 2026 21:37:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 25/46] exec/breakpoint: Return the new wp from cpu_watchpoint_insert Date: Sat, 4 Jul 2026 21:37:04 -0700 Message-ID: <20260705043725.1373137-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226852429158500 Content-Type: text/plain; charset="utf-8" The cpu_watchpoint_insert function cannot fail, so the error return value isn't actually used. Instead of returning the new watchpoint by reference, return it directly. Signed-off-by: Richard Henderson --- include/exec/breakpoint.h | 5 ++--- accel/tcg/tcg-accel-ops.c | 9 ++------- accel/tcg/user-exec-stub.c | 7 +++---- system/watchpoint.c | 11 +++-------- target/arm/tcg/debug.c | 4 ++-- target/i386/tcg/system/bpt_helper.c | 20 ++++++++------------ target/ppc/cpu.c | 4 ++-- target/riscv/debug.c | 28 +++++++++------------------- target/s390x/tcg/debug.c | 10 +++++----- target/xtensa/dbg_helper.c | 10 +++------- 10 files changed, 39 insertions(+), 69 deletions(-) diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index 90bfe5e237..254762c9b2 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -48,9 +48,8 @@ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreak= point *breakpoint); void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask); bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, BreakpointFlags mask); =20 -int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - BreakpointFlags flags, unsigned id, - CPUWatchpoint **watchpoint); +CPUWatchpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, + BreakpointFlags flags, unsigned id); int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, BreakpointFlags flags); void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 8954514f24..54717e1946 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -135,7 +135,6 @@ static inline BreakpointFlags xlat_gdb_type(CPUState *c= pu, int gdbtype) static int tcg_insert_breakpoint(CPUState *cs, int type, vaddr addr, vaddr= len) { CPUState *cpu; - int err =3D 0; =20 switch (type) { case GDB_BREAKPOINT_SW: @@ -151,13 +150,9 @@ static int tcg_insert_breakpoint(CPUState *cs, int typ= e, vaddr addr, vaddr len) return -EINVAL; } CPU_FOREACH(cpu) { - err =3D cpu_watchpoint_insert(cpu, addr, len, - xlat_gdb_type(cpu, type), 0, NULL); - if (err) { - break; - } + cpu_watchpoint_insert(cpu, addr, len, xlat_gdb_type(cpu, type)= , 0); } - return err; + return 0; default: return -ENOSYS; } diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index 42e4861868..bf8b7113b8 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -21,11 +21,10 @@ void cpu_exec_reset_hold(CPUState *cpu) { } =20 -int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - BreakpointFlags flags, unsigned id, - CPUWatchpoint **watchpoint) +CPUWatchpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, + BreakpointFlags flags, unsigned id) { - return -ENOSYS; + g_assert_not_reached(); } =20 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, diff --git a/system/watchpoint.c b/system/watchpoint.c index 01cf0f61a8..183b194403 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -24,9 +24,8 @@ #include "hw/core/cpu.h" =20 /* Add a watchpoint. */ -int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - BreakpointFlags flags, unsigned id, - CPUWatchpoint **watchpoint) +CPUWatchpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, + BreakpointFlags flags, unsigned id) { CPUWatchpoint *wp; vaddr last =3D addr + len - 1; @@ -49,11 +48,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vad= dr len, } else { tlb_flush(cpu); } - - if (watchpoint) { - *watchpoint =3D wp; - } - return 0; + return wp; } =20 /* Remove a specific watchpoint. */ diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 2c73ca1080..e75fd39fb6 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -581,8 +581,8 @@ void hw_watchpoint_update(ARMCPU *cpu, int n) wvr +=3D basstart; } =20 - cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, n, - &env->cpu_watchpoint[n]); + env->cpu_watchpoint[n] =3D cpu_watchpoint_insert(CPU(cpu), wvr, len, + flags, n); } =20 void hw_watchpoint_update_all(ARMCPU *cpu) diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index 23f2d05126..c0c63e3e89 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -57,7 +57,6 @@ static int hw_breakpoint_insert(CPUX86State *env, int ind= ex) CPUState *cs =3D env_cpu(env); target_ulong dr7 =3D env->dr[7]; target_ulong drN =3D env->dr[index]; - int err =3D 0; =20 switch (hw_breakpoint_type(dr7, index)) { case DR7_TYPE_BP_INST: @@ -73,25 +72,22 @@ static int hw_breakpoint_insert(CPUX86State *env, int i= ndex) =20 case DR7_TYPE_DATA_WR: if (hw_breakpoint_enabled(dr7, index)) { - err =3D cpu_watchpoint_insert(cs, drN, - hw_breakpoint_len(dr7, index), - BP_CPU | BP_MEM_WRITE, index, - &env->cpu_watchpoint[index]); + env->cpu_watchpoint[index] =3D + cpu_watchpoint_insert(cs, drN, + hw_breakpoint_len(dr7, index), + BP_CPU | BP_MEM_WRITE, index); } break; =20 case DR7_TYPE_DATA_RW: if (hw_breakpoint_enabled(dr7, index)) { - err =3D cpu_watchpoint_insert(cs, drN, - hw_breakpoint_len(dr7, index), - BP_CPU | BP_MEM_ACCESS, index, - &env->cpu_watchpoint[index]); + env->cpu_watchpoint[index] =3D + cpu_watchpoint_insert(cs, drN, + hw_breakpoint_len(dr7, index), + BP_CPU | BP_MEM_ACCESS, index); } break; } - if (err) { - env->cpu_breakpoint[index] =3D NULL; - } return 0; } =20 diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index c91e60940a..262cb92dd2 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -169,8 +169,8 @@ void ppc_update_daw(CPUPPCState *env, int rid) flags |=3D BP_MEM_WRITE; } =20 - cpu_watchpoint_insert(cs, deaw, len, flags, rid, - &env->dawr_watchpoint[rid]); + env->dawr_watchpoint[rid] =3D + cpu_watchpoint_insert(cs, deaw, len, flags, rid); } =20 void ppc_store_dawr0(CPUPPCState *env, target_ulong val) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index d6bba24c81..6777f1a905 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -481,7 +481,6 @@ static void type2_breakpoint_insert(CPURISCVState *env,= target_ulong index) bool enabled =3D type2_breakpoint_enabled(ctrl); CPUState *cs =3D env_cpu(env); BreakpointFlags flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; - uint32_t size, def_size; =20 if (!enabled) { return; @@ -499,16 +498,12 @@ static void type2_breakpoint_insert(CPURISCVState *en= v, target_ulong index) } =20 if (flags & BP_MEM_ACCESS) { - size =3D type2_breakpoint_size(env, ctrl); - if (size !=3D 0) { - cpu_watchpoint_insert(cs, addr, size, flags, index, - &env->cpu_watchpoint[index]); - } else { - def_size =3D riscv_cpu_mxl(env) =3D=3D MXL_RV64 ? 8 : 4; - - cpu_watchpoint_insert(cs, addr, def_size, flags, index, - &env->cpu_watchpoint[index]); + uint32_t size =3D type2_breakpoint_size(env, ctrl); + if (size =3D=3D 0) { + size =3D riscv_cpu_mxl(env) =3D=3D MXL_RV64 ? 8 : 4; } + env->cpu_watchpoint[index] =3D + cpu_watchpoint_insert(cs, addr, size, flags, index); } } =20 @@ -606,7 +601,6 @@ static void type6_breakpoint_insert(CPURISCVState *env,= target_ulong index) bool enabled =3D type6_breakpoint_enabled(ctrl); CPUState *cs =3D env_cpu(env); BreakpointFlags flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; - uint32_t size; =20 if (!enabled) { return; @@ -625,14 +619,10 @@ static void type6_breakpoint_insert(CPURISCVState *en= v, target_ulong index) } =20 if (flags & BP_MEM_ACCESS) { - size =3D extract32(ctrl, 16, 4); - if (size !=3D 0) { - cpu_watchpoint_insert(cs, addr, size, flags, index, - &env->cpu_watchpoint[index]); - } else { - cpu_watchpoint_insert(cs, addr, 8, flags, index, - &env->cpu_watchpoint[index]); - } + uint32_t size =3D extract32(ctrl, 16, 4) ? : 8; + + env->cpu_watchpoint[index] =3D + cpu_watchpoint_insert(cs, addr, size, flags, index); } } =20 diff --git a/target/s390x/tcg/debug.c b/target/s390x/tcg/debug.c index 25968d9a3c..bd30b85ada 100644 --- a/target/s390x/tcg/debug.c +++ b/target/s390x/tcg/debug.c @@ -34,18 +34,18 @@ void s390_cpu_recompute_watchpoints(CPUState *cs) if (env->cregs[10] =3D=3D 0 && env->cregs[11] =3D=3D -1LL) { /* We can't create a watchoint spanning the whole memory range, so split it in two parts. */ - cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, 0, NULL); - cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, 0, NUL= L); + cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, 0); + cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, 0); } else if (env->cregs[10] > env->cregs[11]) { /* The address range loops, create two watchpoints. */ cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10], - wp_flags, 0, NULL); - cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, 0, NULL= ); + wp_flags, 0); + cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, 0); } else { /* Default case, create a single watchpoint. */ cpu_watchpoint_insert(cs, env->cregs[10], env->cregs[11] - env->cregs[10] + 1, - wp_flags, 0, NULL); + wp_flags, 0); } } =20 diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 9df0c519b3..ae3791ac23 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -97,13 +97,9 @@ static void set_dbreak(CPUXtensaState *env, unsigned i, = uint32_t dbreaka, /* cut mask after the first zero bit */ mask =3D 0xffffffff << (32 - clo32(mask)); } - if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, - flags, i, &env->cpu_watchpoint[i])) { - env->cpu_watchpoint[i] =3D NULL; - qemu_log_mask(LOG_GUEST_ERROR, - "Failed to set data breakpoint at 0x%08x/%d\n", - dbreaka & mask, ~mask + 1); - } + + env->cpu_watchpoint[i] =3D + cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, flags, i); 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226269; x=1783831069; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FgdeNV+kSDtwWzzSUG7k6o21nzzJqi9iKyuHEyE17qI=; b=Nhnt3moBKGl9Biusc2l6zMQqGogOZDw681FOZ9fZxVu0svtf9RUyP5OkeWg842CM2Y AHqFubYUHM2uH79FmTO1PWQ2DV4uOmZpWpduZJiRcrd340RUZbQC7OKs51xoZOQ9lBC9 +xJvqm/yHH3kAbqcvHu00fK0YnzLT4oKM8ROhXLtYk2DoUfZ5Mtj+Fiocc9nTrj8P0Q6 yS17b/gCpYkWciqDVrx9g78jijPGbAYBG0haVgDdVgFOaKvxGksFYfLa8BpxPdtlmldd gwU70yOEp56AzYAG22lBe+hauNYruEPyDQRejXRykWcb8DdSWj6wyr14tNEY3aXl5bKe 0KoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226269; x=1783831069; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=FgdeNV+kSDtwWzzSUG7k6o21nzzJqi9iKyuHEyE17qI=; b=aqniHjqo2Ud6V+MMIDXUAEN2xt2c/38qeWKILOdZ1MChYbOT6nMlcxawJspKkB8wH8 6TRo7MYWiBkd/SnHP9I2nebRtNJJRNlv/qDJqXPVDovsdI1ekyXOx5554mzppFwp0RVH F3ofkE7oM6sPV3qVo+OL6MwOwrCWOmizF4IGQyoYesrSOHxPsn+ZNXFCbw4SC1iawhXd uQ38BKoS2q74mPVs3UeraZBiXrhImoRrZTPG5VewNjFpNDfAqKyy7z7NPtxQdlALytrM AD62khIAK1o1decsfBBDSrxPSkF7WEr97xQ9bozDsOZNFJip2MB5wTvqkARr/pN6iUSo 7KNw== X-Gm-Message-State: AOJu0Yz8MExBXs4I7Mlc9xKq3PaZySfFsO6+tUpwaLB+Q2isK55XpPRN brEiPauaZTCGmRphp2KghNtp/QVwKPzlisnVJB4oS8IrT7NZQVpG4j8iUIRvCBXnm1C4gJUhIrj Z9kWc X-Gm-Gg: AfdE7clmGxUpzI/GsHF5cqXuIyrBAY536izwiG3bqTdLTeoxpzz6lVQFpLjqRjhGiGU WRqaVcod9GmfNvttBj0CbZEMTFZ1Pe7gCuLVPzI52SPZgAtw0avb7a90c6G5g273/Ljpo92M9qj WJGQ6ryFjLE68UoScN6aU41I0VDdE6c674GoqKaAKkRIBeMBiVJi0VTq61Hkh9v50CKv16h5HMw vcWR+soEr6I9sB954y5pxn5QFpHpDNaoK4QuwmQ8UCcxEDIo0XjrCR9RYvUPsrX4bXTFh4/7cTv IYO1pD39M1as24Ug1JqJhECeWzOk4P27Z0PM+4lp1GAg3LjvbvlPak8Fe3klJAXOgo9ijnz79kZ LR7qmYXFdTpgQ2uGt9gvG0bNHZ6hLdnLI9Kg9KBADxVMtsieY96OtvvoF8clgdKtBPKWIRtlo0t 3pTfcMfxHwEz9lk3MlJVGPC+16MxzR2++99poKHd2Zmnohc4s= X-Received: by 2002:a17:903:3bcb:b0:2ca:e08e:9e70 with SMTP id d9443c01a7336-2cbb9f479a9mr54297515ad.46.1783226269175; Sat, 04 Jul 2026 21:37:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 26/46] system: Validate flags in cpu_watchpoint_insert Date: Sat, 4 Jul 2026 21:37:05 -0700 Message-ID: <20260705043725.1373137-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226884290158500 Content-Type: text/plain; charset="utf-8" Flags must watch reads, writes, or both. Flags must specify GDB or CPU but not both. Flags must not contain extraneous bits. Signed-off-by: Richard Henderson --- system/watchpoint.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/system/watchpoint.c b/system/watchpoint.c index 183b194403..fbaebba7cf 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -33,6 +33,9 @@ CPUWatchpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr= addr, vaddr len, =20 assert(len !=3D 0); assert(last >=3D addr); + assert(flags & BP_MEM_ACCESS); + assert(ctpop32(flags & BP_ANY) =3D=3D 1); + assert(!(flags & ~(BP_ANY | BP_MEM_ACCESS | BP_STOP_BEFORE_ACCESS))); =20 wp =3D g_new0(CPUWatchpoint, 1); =20 --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226437; cv=none; d=zohomail.com; s=zohoarc; b=S4Ka8ZA2eqD0DYHBTkAJxYLT7/szBMiYo0iV5CbxA8Fg9Az/7kKqBQfP5AlL7wQOa7Fyp9jG5KFkz/VURHYKkz57ETyMXl8WQQE75/3ZTonFwjGCQiBMqnUsQ/qhzDD79vsBc6aazI7eJmjqUwVlbLzmgbn0+Qyk1X8BjpLZzuo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226437; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YQ0VkN+fXYkTd5pIzgNSNc34KFa66jXvc0dQc3T9c/U=; b=GsnutnoA5cYzpYAfkXjhIx+ZnIB1KLSPK3R6zKWlPdbEwMwaBq/xFcKUMv+WWL/gKTEq97o8i0piZE2jMMtJfgjPUeaDbkXDMipt4uNgZk4QpxbGpxSfJAZc0FME+O5esfHx/K3wLz4DizRiE5dpGK830elGO23CnWxqLIdMjzQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226437450616.531583670537; Sat, 4 Jul 2026 21:40:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdj-0007Uz-8y; Sun, 05 Jul 2026 00:39:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcN-00058Q-TX for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:14 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEc3-0004Ja-N2 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:11 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-2caf4496889so7507365ad.1 for ; Sat, 04 Jul 2026 21:37:51 -0700 (PDT) Received: from stoup.. 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Flags must not contain extraneous bits. Signed-off-by: Richard Henderson --- cpu-common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/cpu-common.c b/cpu-common.c index fcc9bc77a3..80a4a191f4 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -410,6 +410,9 @@ CPUBreakpoint *cpu_breakpoint_insert(CPUState *cpu, vad= dr pc, { CPUBreakpoint *bp; =20 + assert(!(flags & ~BP_ANY)); + assert(ctpop32(flags) =3D=3D 1); + if (cpu->cc->gdb_adjust_breakpoint) { pc =3D cpu->cc->gdb_adjust_breakpoint(cpu, pc); } --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226970; cv=none; d=zohomail.com; s=zohoarc; b=Vj2iH9Id2IyJb3J2Z6U6o9BvHsHQxg4/DBG9DcdDTvhvxLhDK/PJJDBvk46jM5jedRVB/dyEmGwPtLLWaVHKiVJcvVLeCKGSeagmwoDa2/JCMQmX32vWcOtuxU6XLRiU5xDpYl3wA4tkZoJV1yY12kVreSxNjQLQ+OPT1/J0nw8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226970; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kzGgogh2drGaxG2qqYgsAosa8MuuctrHRN1e6nlJ7Xc=; b=M/z4XfRxOkDQf8QPttOjI2yIfo/uT3R3QZYIpEmicYVAEn6L3b35B2zqYcyseco/X3zSNVVgZXSxfDGjjmqkSAJDAnUmjlTTtRRP4vdJDlRlZY2xhRtkZQcMUtcDW1sjh2nvYYhE/fh1WJceuVo/Wmnug8qj2a2SBFBL/gM5Ibk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226970153287.14290694019917; Sat, 4 Jul 2026 21:49:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdu-0008QJ-O5; Sun, 05 Jul 2026 00:39:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcO-00058R-BI for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:14 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEc4-0004KT-M0 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:12 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-2cac59f8b64so21323615ad.0 for ; Sat, 04 Jul 2026 21:37:51 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- include/exec/breakpoint.h | 1 + accel/tcg/watchpoint.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index 254762c9b2..175d0cc670 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -36,6 +36,7 @@ struct CPUBreakpoint { struct CPUWatchpoint { IntervalTreeNode itree; vaddr hitaddr; + vaddr hitlast; MemTxAttrs hitattrs; BreakpointFlags flags; unsigned id; diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index a7ce5fa9dd..edd1d5708b 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -89,6 +89,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vadd= r len, wp->flags &=3D ~BP_WATCHPOINT_HIT; wp->flags |=3D flags << BP_HIT_SHIFT; wp->hitaddr =3D MAX(addr, wp->itree.start); + wp->hitlast =3D MIN(last, wp->itree.last); wp->hitattrs =3D attrs; =20 found_wp =3D wp; @@ -109,6 +110,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, wp->flags &=3D ~BP_WATCHPOINT_HIT; wp->flags |=3D flags << BP_HIT_SHIFT; wp->hitaddr =3D MAX(addr, wp->itree.start); + wp->hitlast =3D MIN(last, wp->itree.last); wp->hitattrs =3D attrs; =20 if (tcg_ops->debug_check_watchpoint --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226907; cv=none; d=zohomail.com; s=zohoarc; b=aXJK4fOrJiD7odzWUfVaAbNWvkVQyAHMlxBlBZW97OoocZ94VtYyj5oSFGDYB4KPilgei/gPTFUxhL7FgJPv7hWxSM6DT6IX6UAzVC1ejHhoyL6IFdI2u2DDutFgAhprRA+nzng8yz2A8kF6YaXQkowJWU8zjkoX2n2SeMiuBJg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226907; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LARvyjgG3F/Bsgp0fUy+k11p26dRPrq56NsCYy2bXIQ=; b=QkPmSumEn4yu8DTiM8/LUfU653wyrh+QuwwFhe40ltuwKJ75CtbOT6Kt6xmcaj7e2z9Mg5e0swvP5faDIGDPrcc/crq4WLSM147sTlqJ9GU1qIAvUr6aPBRX/fUSA0lgg/d638zCtgo50pB00rsKa280zXRPhqCKQOCzoDets50= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226907036927.2171539536478; Sat, 4 Jul 2026 21:48:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdp-00082z-Er; Sun, 05 Jul 2026 00:39:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcQ-0005Be-Oa for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:15 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEc5-0004LZ-AT for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:14 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2cad4170e8eso21507055ad.3 for ; Sat, 04 Jul 2026 21:37:52 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226272; x=1783831072; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LARvyjgG3F/Bsgp0fUy+k11p26dRPrq56NsCYy2bXIQ=; b=kl42pAz07JmJy++pE4oojPoaQXMu9Vd+xv7eIvvpufYp9qmEVLpOOeAff0XZFGziAb 5pj8bIQHCEWurm1jOJqh+35iNictB7iJ7r6+Ee/mKafWGZNjCA+oRoI8t/RBojGHbYpB CNrj/cPs1YtNYBy5T+b1GbqH8WCEpFncarp9o1Mj93b2xKHaM450ItZ4mJ/PJ/gTYEv3 k7Gh9lg/Xw1Mxlk4o209LAbw5QX7GrPrbgv8JdO0pJIUmIU8DwWVVlxW0qT9idv9YMST LBSvIQst+nA8e4jQl81ZGZ60ewzV3Mjx4ycnwp1j6i5rsEdlAnTTMMmv5DCyLezpyzNh sQXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226272; x=1783831072; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=LARvyjgG3F/Bsgp0fUy+k11p26dRPrq56NsCYy2bXIQ=; b=YE2BaHGgUoPGCEuIb0xssAcgr5kMTvhfoApkAsxJkVC9LHKqDa6I0FTzROOH/tzd/q 1tpnQK3zwyv+funsQ9/JMjXLjjvsIHLk28qGH5NqKhWMcSATZObFu7kXOzJI1hkI2l8t J7thseStMMnyuduccIkwiDp2gGvrorKC9v2CaVjMf4AbjzxST5X8xiSoMz7XgEiETiUR +SVcoiI4B7nSKkzF+2BwaE53vS42s2Ali2ZfHSs8uuTyFukq82USgyh2YhuEU0yB56UO IB2I8fj0eB5j5dSm1g3Dn7QBGIfO+AWmfnJne9OAemH+tdZJCquIN0koTV8kBFinLcO3 S2Bw== X-Gm-Message-State: AOJu0YyuE+bv+j77Zzqtt/8EczHsNztxbRWE65n64121eEK5J0dFY72W 3g1464qUHBzjhQvuNnDaqOB7UsdqQhvTP7OWyNfqhFbOQdVPonG/0QESVcb0gHPzOjLYH691RVz VScAf X-Gm-Gg: AfdE7cm2p0FqQO7qqiACvlSYPbdy9sWv6iXTq4WIbwLag6dhQNMNmA1HuA0u1B1ujsx zTE5qnO84Nh8yFv9RX6rfugiuuUfqHWJSif6Ejf3hxwKiXMxvA0W6w0zHAMKQtKbtySmFUCkxJR jZE2q6nWNcUfDzNu1r0OMeBDsFmBASwRgOl2+4ttPtIfyMZNpcPHeytUZ51c+rQ6cCE8obNdNAW sS3zvlxbG9TCAchql/5eCfTgEzi0905zaNT76kOZExHJ8rY74dIBi4xY1hgmUblYepv+1UlBvU9 PhCyFpxMhXYKwFJYKO/az8e9PHygVntLdxOWsGeh6NTsuBDHRawdNBPvJzUmOHJxpi6M/c/WUkF prx4G94zSd2RYyVD/I2ZdswVYxEp/fNQ43gP/RwS/Ox9q2v0IyBJt8hzlqKj4YXG6RGj1TNaC9S DUsFaS9f1FK4GZHkmOu5EHde3ytsDa8Z0jEt2sD0SmCKUBHUxKo+LdOdhz2Q== X-Received: by 2002:a17:903:2f8a:b0:2c9:97a7:71b1 with SMTP id d9443c01a7336-2cbb9f31c68mr50154265ad.44.1783226271690; Sat, 04 Jul 2026 21:37:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 29/46] exec/breakpoint: Merge CPUBreakpoint and CPUWatchpoint Date: Sat, 4 Jul 2026 21:37:08 -0700 Message-ID: <20260705043725.1373137-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226908486158500 Content-Type: text/plain; charset="utf-8" Drop the CPUBreakpoint structure and rename CPUWatchpoint to CPUBreakpoint. Mechanical change to adjust all uses. Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 2 +- include/exec/breakpoint.h | 10 ++-------- include/hw/core/cpu.h | 2 +- include/qemu/typedefs.h | 1 - target/arm/cpu.h | 2 +- target/arm/internals.h | 8 ++++---- target/i386/cpu.h | 2 +- target/ppc/cpu.h | 2 +- target/ppc/internal.h | 2 +- target/riscv/cpu.h | 2 +- target/riscv/debug.h | 2 +- target/xtensa/cpu.h | 2 +- accel/tcg/cpu-exec.c | 2 +- accel/tcg/user-exec-stub.c | 4 ++-- accel/tcg/watchpoint.c | 8 ++++---- system/watchpoint.c | 12 ++++++------ target/arm/hvf/hvf.c | 2 +- target/arm/hyp_gdbstub.c | 2 +- target/arm/kvm.c | 2 +- target/arm/tcg/debug.c | 4 ++-- target/i386/kvm/kvm.c | 2 +- target/ppc/kvm.c | 2 +- target/ppc/tcg-excp_helper.c | 2 +- target/riscv/debug.c | 4 ++-- target/s390x/kvm/kvm.c | 2 +- target/s390x/tcg/debug.c | 2 +- 26 files changed, 40 insertions(+), 47 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 3988bef520..2dde42cf29 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -258,7 +258,7 @@ struct TCGCPUOps { * @debug_check_watchpoint: return true if the architectural * watchpoint whose address has matched should really fire. */ - bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); + bool (*debug_check_watchpoint)(CPUState *cpu, CPUBreakpoint *wp); =20 /** * @debug_check_breakpoint: return true if the architectural diff --git a/include/exec/breakpoint.h b/include/exec/breakpoint.h index 175d0cc670..66014d2f89 100644 --- a/include/exec/breakpoint.h +++ b/include/exec/breakpoint.h @@ -28,12 +28,6 @@ typedef int BreakpointFlags; #define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) =20 struct CPUBreakpoint { - IntervalTreeNode itree; /* start =3D=3D last =3D=3D pc */ - BreakpointFlags flags; - unsigned id; -}; - -struct CPUWatchpoint { IntervalTreeNode itree; vaddr hitaddr; vaddr hitlast; @@ -49,11 +43,11 @@ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBre= akpoint *breakpoint); void cpu_breakpoint_remove_all(CPUState *cpu, BreakpointFlags mask); bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, BreakpointFlags mask); =20 -CPUWatchpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, +CPUBreakpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, BreakpointFlags flags, unsigned id); int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, BreakpointFlags flags); -void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *watchpoint= ); void cpu_watchpoint_remove_all(CPUState *cpu, BreakpointFlags mask); =20 #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ccfcab6a8a..8d24aaff44 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -526,7 +526,7 @@ struct CPUState { /* ice debug support */ IntervalTreeRoot breakpoints; IntervalTreeRoot watchpoints; - CPUWatchpoint *watchpoint_hit; + CPUBreakpoint *watchpoint_hit; =20 void *opaque; =20 diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 919fe8ebff..4c69bf7760 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -43,7 +43,6 @@ typedef struct CPUBreakpoint CPUBreakpoint; typedef struct CPUPluginState CPUPluginState; typedef struct CPUState CPUState; typedef struct CPUTLBEntryFull CPUTLBEntryFull; -typedef struct CPUWatchpoint CPUWatchpoint; typedef struct DeviceState DeviceState; typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot; typedef struct DisasContextBase DisasContextBase; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 973522cd55..29d7908643 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -755,7 +755,7 @@ typedef struct CPUArchState { } za_state; =20 CPUBreakpoint *cpu_breakpoint[16]; - CPUWatchpoint *cpu_watchpoint[16]; + CPUBreakpoint *cpu_watchpoint[16]; =20 /* Optional fault info across tlb lookup. */ ARMMMUFaultInfo *tlb_fi; diff --git a/target/arm/internals.h b/target/arm/internals.h index 53091fc73e..5ef31aea50 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -683,7 +683,7 @@ void hw_breakpoint_update_all(ARMCPU *cpu); bool arm_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); =20 /* Callback function for checking if a watchpoint should trigger. */ -bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); +bool arm_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp); =20 /* Adjust addresses (in BE32 mode) before testing against watchpoint * addresses. @@ -1944,13 +1944,13 @@ typedef struct { /* * The watchpoint registers can cover more area than the requested * watchpoint so we need to store the additional information - * somewhere. We also need to supply a CPUWatchpoint to the GDB stub + * somewhere. We also need to supply a CPUBreakpoint to the GDB stub * when the watchpoint is hit. */ typedef struct { uint64_t wcr; uint64_t wvr; - CPUWatchpoint details; + CPUBreakpoint details; } HWWatchpoint; =20 /* Maximum and current break/watch point counts */ @@ -1966,7 +1966,7 @@ bool find_hw_breakpoint(CPUState *cpu, vaddr pc); int insert_hw_breakpoint(vaddr pc); int delete_hw_breakpoint(vaddr pc); =20 -CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr); +CPUBreakpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr); int insert_hw_watchpoint(vaddr addr, vaddr len, int type); int delete_hw_watchpoint(vaddr addr, vaddr len, int type); =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9dbfa7c9b9..efff7b97f7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2186,7 +2186,7 @@ typedef struct CPUArchState { target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ union { CPUBreakpoint *cpu_breakpoint[4]; - CPUWatchpoint *cpu_watchpoint[4]; + CPUBreakpoint *cpu_watchpoint[4]; }; /* break/watchpoints for dr[0..3] */ int old_exception; /* exception in flight */ =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d06f3dfd7f..ecfa5b267d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1321,7 +1321,7 @@ struct CPUArchState { #if defined(TARGET_PPC64) ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ CPUBreakpoint *ciabr_breakpoint; - CPUWatchpoint *dawr_watchpoint[2]; + CPUBreakpoint *dawr_watchpoint[2]; #endif target_ulong sr[32]; /* segment registers */ uint32_t nb_BATs; /* number of BATs */ diff --git a/target/ppc/internal.h b/target/ppc/internal.h index ec057afa92..80f4195378 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -305,7 +305,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, MemTxResult response, uintptr_t retaddr= ); void ppc_cpu_debug_excp_handler(CPUState *cs); bool ppc_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); -bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); +bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp); =20 G_NORETURN void powerpc_checkstop(CPUPPCState *env, const char *reason); void powerpc_excp(PowerPCCPU *cpu, int excp); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9cd38d10a3..a48bf61576 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -492,7 +492,7 @@ struct CPUArchState { uint64_t *tdata2; uint64_t *tdata3; CPUBreakpoint **cpu_breakpoint; - CPUWatchpoint **cpu_watchpoint; + CPUBreakpoint **cpu_watchpoint; QEMUTimer **itrigger_timer; int64_t last_icount; bool itrigger_enabled; diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 8eb9eccd4c..f5234ff763 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -145,7 +145,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env); =20 void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); -bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp); =20 void riscv_trigger_realize(CPURISCVState *env); void riscv_trigger_unrealize(CPURISCVState *env); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 590371c4dc..c256ab3cc8 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -545,7 +545,7 @@ struct CPUArchState { unsigned static_vectors; =20 /* Watchpoints for DBREAK registers */ - CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; + CPUBreakpoint *cpu_watchpoint[MAX_NDBREAK]; /* Breakpoints for IBREAK registers */ CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK]; }; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 24b72c358d..c4ee6afe13 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -686,7 +686,7 @@ static inline void cpu_handle_debug_exception(CPUState = *cpu) =20 for (n =3D interval_tree_iter_first(&cpu->watchpoints, 0, -1); n; n =3D interval_tree_iter_next(n, 0, -1)) { - CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + CPUBreakpoint *wp =3D container_of(n, CPUBreakpoint, itree); if (wp !=3D cpu->watchpoint_hit) { wp->flags &=3D ~BP_WATCHPOINT_HIT; } diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index bf8b7113b8..c45e31e2fa 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -21,7 +21,7 @@ void cpu_exec_reset_hold(CPUState *cpu) { } =20 -CPUWatchpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, +CPUBreakpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, BreakpointFlags flags, unsigned id) { g_assert_not_reached(); @@ -33,7 +33,7 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, return -ENOSYS; } =20 -void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *wp) +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *wp) { } =20 diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index edd1d5708b..bf4c46c393 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -40,7 +40,7 @@ BreakpointFlags cpu_watchpoint_address_matches(CPUState *= cpu, =20 for (n =3D interval_tree_iter_first(&cpu->watchpoints, addr, last); n; n =3D interval_tree_iter_next(n, addr, last)) { - CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + CPUBreakpoint *wp =3D container_of(n, CPUBreakpoint, itree); ret |=3D wp->flags; } return ret; @@ -52,7 +52,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vadd= r len, { vaddr last =3D addr + len - 1; IntervalTreeNode *n; - CPUWatchpoint *found_wp =3D NULL; + CPUBreakpoint *found_wp =3D NULL; bool have_cpu_wp =3D false; =20 assert(tcg_enabled()); @@ -78,7 +78,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vadd= r len, =20 for (n =3D interval_tree_iter_first(&cpu->watchpoints, addr, last); n; n =3D interval_tree_iter_next(n, addr, last)) { - CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + CPUBreakpoint *wp =3D container_of(n, CPUBreakpoint, itree); =20 if (wp->flags & flags) { /* @@ -104,7 +104,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, =20 for (n =3D interval_tree_iter_first(&cpu->watchpoints, addr, last)= ; n; n =3D interval_tree_iter_next(n, addr, last)) { - CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + CPUBreakpoint *wp =3D container_of(n, CPUBreakpoint, itree); =20 if ((wp->flags & BP_CPU) && (wp->flags & flags)) { wp->flags &=3D ~BP_WATCHPOINT_HIT; diff --git a/system/watchpoint.c b/system/watchpoint.c index fbaebba7cf..35cb3bdaec 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -24,10 +24,10 @@ #include "hw/core/cpu.h" =20 /* Add a watchpoint. */ -CPUWatchpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, +CPUBreakpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, BreakpointFlags flags, unsigned id) { - CPUWatchpoint *wp; + CPUBreakpoint *wp; vaddr last =3D addr + len - 1; vaddr in_page; =20 @@ -37,7 +37,7 @@ CPUWatchpoint *cpu_watchpoint_insert(CPUState *cpu, vaddr= addr, vaddr len, assert(ctpop32(flags & BP_ANY) =3D=3D 1); assert(!(flags & ~(BP_ANY | BP_MEM_ACCESS | BP_STOP_BEFORE_ACCESS))); =20 - wp =3D g_new0(CPUWatchpoint, 1); + wp =3D g_new0(CPUBreakpoint, 1); =20 wp->itree.start =3D addr; wp->itree.last =3D last; @@ -63,7 +63,7 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vadd= r len, =20 for (n =3D interval_tree_iter_first(&cpu->watchpoints, addr, addr); n; n =3D interval_tree_iter_next(n, addr, addr)) { - CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + CPUBreakpoint *wp =3D container_of(n, CPUBreakpoint, itree); =20 if (addr =3D=3D wp->itree.start && last =3D=3D wp->itree.last && @@ -76,7 +76,7 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vadd= r len, } =20 /* Remove a specific watchpoint by reference. */ -void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *watchpoint) { interval_tree_remove(&watchpoint->itree, &cpu->watchpoints); tlb_flush_page(cpu, watchpoint->itree.start); @@ -89,7 +89,7 @@ void cpu_watchpoint_remove_all(CPUState *cpu, BreakpointF= lags mask) IntervalTreeNode *n =3D interval_tree_iter_first(&cpu->watchpoints, 0,= -1); =20 while (n) { - CPUWatchpoint *wp =3D container_of(n, CPUWatchpoint, itree); + CPUBreakpoint *wp =3D container_of(n, CPUBreakpoint, itree); =20 n =3D interval_tree_iter_next(n, 0, -1); if (wp->flags & mask) { diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 0a383b9295..48c2a02bfb 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -2372,7 +2372,7 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcp= u_exit_exception_t *excp) =20 cpu_synchronize_state(cpu); =20 - CPUWatchpoint *wp =3D + CPUBreakpoint *wp =3D find_hw_watchpoint(cpu, excp->virtual_address); if (!wp) { error_report("EXCP_DEBUG but unknown hw watchpoint"); diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c index 5ecc0939e9..fc02415829 100644 --- a/target/arm/hyp_gdbstub.c +++ b/target/arm/hyp_gdbstub.c @@ -240,7 +240,7 @@ bool find_hw_breakpoint(CPUState *cpu, vaddr pc) return false; } =20 -CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr) +CPUBreakpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr) { int i; =20 diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 72a53bd7c3..7670041423 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1517,7 +1517,7 @@ static bool kvm_arm_handle_debug(ARMCPU *cpu, break; case EC_WATCHPOINT: { - CPUWatchpoint *wp =3D find_hw_watchpoint(cs, debug_exit->far); + CPUBreakpoint *wp =3D find_hw_watchpoint(cs, debug_exit->far); if (wp) { wp->hitaddr =3D debug_exit->far; cs->watchpoint_hit =3D wp; diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index e75fd39fb6..293907fdaf 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -365,7 +365,7 @@ bool arm_debug_check_breakpoint(CPUState *cs, CPUBreakp= oint *bp) return bp_wp_matches(cpu, env->cp15.dbgbcr[bp->id], arm_current_el(env= )); } =20 -bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +bool arm_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp) { /* * Called by core code when a CPU watchpoint fires; need to check if t= his @@ -422,7 +422,7 @@ void arm_debug_excp_handler(CPUState *cs) */ ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - CPUWatchpoint *wp_hit =3D cs->watchpoint_hit; + CPUBreakpoint *wp_hit =3D cs->watchpoint_hit; =20 if (wp_hit) { if (wp_hit->flags & BP_CPU) { diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 8c9304ddaf..3cc941cf00 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -6237,7 +6237,7 @@ void kvm_arch_remove_all_hw_breakpoints(void) nb_hw_breakpoint =3D 0; } =20 -static CPUWatchpoint hw_watchpoint; +static CPUBreakpoint hw_watchpoint; =20 static int kvm_handle_debug(X86CPU *cpu, struct kvm_debug_exit_arch *arch_info) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 82c1396970..8f9c16fcef 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -459,7 +459,7 @@ static struct HWBreakpoint { int type; } hw_debug_points[MAX_HW_BKPTS]; =20 -static CPUWatchpoint hw_watchpoint; +static CPUBreakpoint hw_watchpoint; =20 /* Default there is no breakpoint and watchpoint supported */ static int max_hw_breakpoint; diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index eb78a6a104..12785dc161 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -358,7 +358,7 @@ bool ppc_cpu_debug_check_breakpoint(CPUState *cs, CPUBr= eakpoint *bp) return false; } =20 -bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp) { #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 6777f1a905..958c534f4f 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -945,7 +945,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPU= Breakpoint *bp) return false; } =20 -bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; @@ -970,7 +970,7 @@ void riscv_trigger_realize(CPURISCVState *env) env->tdata2 =3D g_new0(uint64_t, env->num_triggers); env->tdata3 =3D g_new0(uint64_t, env->num_triggers); env->cpu_breakpoint =3D g_new0(CPUBreakpoint *, env->num_triggers); - env->cpu_watchpoint =3D g_new0(CPUWatchpoint *, env->num_triggers); + env->cpu_watchpoint =3D g_new0(CPUBreakpoint *, env->num_triggers); env->itrigger_timer =3D g_new0(QEMUTimer *, env->num_triggers); =20 for (i =3D 0; i < env->num_triggers; i++) { diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 7cd199578b..aff4d26096 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -130,7 +130,7 @@ */ #define KVM_SLOT_MAX_BYTES (4UL * TiB) =20 -static CPUWatchpoint hw_watchpoint; +static CPUBreakpoint hw_watchpoint; /* * We don't use a list because this structure is also used to transmit the * hardware breakpoints to the kernel. diff --git a/target/s390x/tcg/debug.c b/target/s390x/tcg/debug.c index bd30b85ada..9e724bb262 100644 --- a/target/s390x/tcg/debug.c +++ b/target/s390x/tcg/debug.c @@ -52,7 +52,7 @@ void s390_cpu_recompute_watchpoints(CPUState *cs) void s390x_cpu_debug_excp_handler(CPUState *cs) { CPUS390XState *env =3D cpu_env(cs); - CPUWatchpoint *wp_hit =3D cs->watchpoint_hit; + CPUBreakpoint *wp_hit =3D cs->watchpoint_hit; =20 if (wp_hit && wp_hit->flags & BP_CPU) { /* --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Unused so far. Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 2 +- target/arm/internals.h | 2 +- target/i386/tcg/helper-tcg.h | 2 +- target/ppc/internal.h | 2 +- target/riscv/debug.h | 2 +- target/s390x/tcg/tcg_s390x.h | 2 +- target/xtensa/cpu.h | 2 +- accel/tcg/cpu-exec.c | 2 +- target/arm/tcg/debug.c | 2 +- target/i386/tcg/system/bpt_helper.c | 2 +- target/ppc/tcg-excp_helper.c | 2 +- target/riscv/debug.c | 2 +- target/s390x/tcg/debug.c | 2 +- target/xtensa/helper.c | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 2dde42cf29..734bcd537b 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -99,7 +99,7 @@ struct TCGCPUOps { /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); /** @debug_excp_handler: Callback for handling debug exceptions */ - void (*debug_excp_handler)(CPUState *cpu); + void (*debug_excp_handler)(CPUState *cpu, CPUBreakpoint *hit); =20 /** @mmu_index: Callback for choosing softmmu mmu index */ int (*mmu_index)(CPUState *cpu, bool ifetch); diff --git a/target/arm/internals.h b/target/arm/internals.h index 5ef31aea50..51804963f9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -691,7 +691,7 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUBreakp= oint *wp); vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); =20 /* Callback function for when a watchpoint or breakpoint triggers. */ -void arm_debug_excp_handler(CPUState *cs); +void arm_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); =20 #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index f4b2ff740d..01f4a8bcd0 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -42,7 +42,7 @@ bool x86_need_replay_interrupt(int interrupt_request); bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif =20 -void breakpoint_handler(CPUState *cs); +void breakpoint_handler(CPUState *cs, CPUBreakpoint *hit); =20 /* n must be a constant to be efficient */ static inline target_long lshift(target_long x, int n) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 80f4195378..5d7346a03d 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -303,7 +303,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr= ); -void ppc_cpu_debug_excp_handler(CPUState *cs); +void ppc_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); bool ppc_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp); =20 diff --git a/target/riscv/debug.h b/target/riscv/debug.h index f5234ff763..540835f2d0 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -143,7 +143,7 @@ void tdata_csr_write(CPURISCVState *env, int tdata_inde= x, target_ulong val); =20 target_ulong tinfo_csr_read(CPURISCVState *env); =20 -void riscv_cpu_debug_excp_handler(CPUState *cs); +void riscv_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp); =20 diff --git a/target/s390x/tcg/tcg_s390x.h b/target/s390x/tcg/tcg_s390x.h index 975f60085a..61db0c0b53 100644 --- a/target/s390x/tcg/tcg_s390x.h +++ b/target/s390x/tcg/tcg_s390x.h @@ -26,7 +26,7 @@ G_NORETURN void tcg_s390_vector_exception(CPUS390XState *= env, uint32_t vxc, =20 #ifndef CONFIG_USER_ONLY void s390_cpu_recompute_watchpoints(CPUState *cs); -void s390x_cpu_debug_excp_handler(CPUState *cs); +void s390x_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); #endif =20 #endif /* TCG_S390X_H */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c256ab3cc8..663ee23dc4 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -621,7 +621,7 @@ void xtensa_translate_init(void); void xtensa_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); -void xtensa_breakpoint_handler(CPUState *cs); +void xtensa_breakpoint_handler(CPUState *cs, CPUBreakpoint *hit); void xtensa_register_core(XtensaConfigList *node); void xtensa_sim_open_console(Chardev *chr); void check_interrupts(CPUXtensaState *s); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c4ee6afe13..cca403ad62 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -693,7 +693,7 @@ static inline void cpu_handle_debug_exception(CPUState = *cpu) } =20 if (tcg_ops->debug_excp_handler) { - tcg_ops->debug_excp_handler(cpu); + tcg_ops->debug_excp_handler(cpu, cpu->watchpoint_hit); } } =20 diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 293907fdaf..fe8513a5de 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -414,7 +414,7 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *en= v) } } =20 -void arm_debug_excp_handler(CPUState *cs) +void arm_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { /* * Called by core code when a watchpoint or breakpoint fires; diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index c0c63e3e89..8ba5dfcfc1 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -202,7 +202,7 @@ bool check_hw_breakpoints(CPUX86State *env, bool force_= dr6_update) return hit_enabled; } =20 -void breakpoint_handler(CPUState *cs) +void breakpoint_handler(CPUState *cs, CPUBreakpoint *hit) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 12785dc161..51358c901f 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -309,7 +309,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, cpu_loop_exit_restore(cs, retaddr); } =20 -void ppc_cpu_debug_excp_handler(CPUState *cs) +void ppc_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 958c534f4f..a8429778f6 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -914,7 +914,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env) BIT(TRIGGER_TYPE_AD_MATCH6); } =20 -void riscv_cpu_debug_excp_handler(CPUState *cs) +void riscv_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; diff --git a/target/s390x/tcg/debug.c b/target/s390x/tcg/debug.c index 9e724bb262..58d9cc6e79 100644 --- a/target/s390x/tcg/debug.c +++ b/target/s390x/tcg/debug.c @@ -49,7 +49,7 @@ void s390_cpu_recompute_watchpoints(CPUState *cs) } } =20 -void s390x_cpu_debug_excp_handler(CPUState *cs) +void s390x_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { CPUS390XState *env =3D cpu_env(cs); CPUBreakpoint *wp_hit =3D cs->watchpoint_hit; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 0db5502287..02627ada7c 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -219,7 +219,7 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *en= v) return 0; } =20 -void xtensa_breakpoint_handler(CPUState *cs) +void xtensa_breakpoint_handler(CPUState *cs, CPUBreakpoint *hit) { CPUXtensaState *env =3D cpu_env(cs); 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226273; x=1783831073; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cP494Rw8f0vgO7hsG8GqjbbSorQrWAAshXUTXMQVwCM=; b=RoAQjyoiTAQIyAY1GI2sbDqJW8IGrYPJQ/k6+xwMdgSCOo3hOVR/Y56bim/adckbcj 2FexexQgfACaHOk9AbL6y+KbXRNTZ6rXI2uKbdTphM7xq2xHMoNWS8bOICpIegumicE4 IV1w1UzquFxyfcfVT5MII/drmPYBS0VGwdbAW9Uqlg0rxi6y3rr5BrcO9srT4/BAR9SU vr260SRnyV10QUvd6t3pv4RFlK4NREa4OHDJYVfj/Um15PF8g8Ri+a1PO1eGuBLKtWZ7 +L0an8K/NrTKXviq3L7IsAYQrRCAKrprcuRPN9IwXt8E1s3XQb+O8cT+25dckDqSY/hz kJiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226273; x=1783831073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=cP494Rw8f0vgO7hsG8GqjbbSorQrWAAshXUTXMQVwCM=; b=qgmpYfiabFZAKmerRwdR/Vvd8ntFKGj+Pt5vif4TZXc2DKw5DxMMPx3dj2poElE6pf vH2BVx0auJpcMn4amCANUczPSlTkc98SrBwPasMBwsj/RhIo/EYj2fcPr/hwFgBf+0Yi qdjlPKFM6nm21gIzXclI8LPsQBcXJU+d0cq5QA/lRFgwhzZrb2ABQWeK1fwxGIpxFFXL TWEeuYa/9+7DL+MEC6gVUONyLhX2D3bkDXKHBGbqBxMmudX8jwoZwq4KL5XmF4ABD2oy 3odBXtfaL4+E+dr3xRW+eCatWG3i03ITCra1e959+aM6bKbgSkfeqnVBB56IwGUGYj+t 9smQ== X-Gm-Message-State: AOJu0YxDlYhB/MbRPgM0f/JaeRIFE4h9eufYakhwNJDx4nlioSNxue9T sz44HsiiWJGUL47h359OjSYW3ok84rBBysYKFnzzRhwvghpdRmP5aflo/akE2+0DAm3dAeA6v6V pvLrj X-Gm-Gg: AfdE7clLue53RLk9VdxkRfn0avR+uWv72KYN/tDCBqfYVjspIPw8tN/GwfmMZwa6TJB BBm9h/fmtKKVBSei40ZbEUwzujLCHFd6MvVvodsyKPrTurwnuCLqt/cVZu11Ylgibkb8UgozcVC B1HvSyupgjsd+92Bips37HFeAdtr/GlIBYf6QPb4H8pQRd/O3do6f5SDzaAvUPjYuN6Bjr+d305 ET8P0uAy87rSpZj92SSXoWiWL+rd9q+tCjNacQ+isQQWeArRx0zGSlcIalcqTM+LeuEmSqAkdUb I2p5Pmd92UU7g14qgkpIFWDsUb8q8x4rZQp7grfmhTWPe7WEI3rM7QMXDex74DK496xXgCzCsus 7EIsB4VLbOf0VjQF69ISP3zIY5cJvfNbZMi7S+kfDGjfiTlWvZnESdtMuViJy/P0UcENCbIoCL+ ufjwuOJ5sIjC6ZuWgmt5kNrCcjTa+3c5bQovEcjYeAS765XRI= X-Received: by 2002:a17:902:e786:b0:2c9:ff83:41fa with SMTP id d9443c01a7336-2cbb9ebb50dmr50629105ad.24.1783226273331; Sat, 04 Jul 2026 21:37:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 31/46] accel/tcg: Pass breakpoint hit to debug_excp_handler Date: Sat, 4 Jul 2026 21:37:10 -0700 Message-ID: <20260705043725.1373137-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226814218158500 Content-Type: text/plain; charset="utf-8" Record the CPUBreakpoint in check_for_breakpoints_slow, into a new CPUState field, so that the as-yet unconverted target debug_excp_handler functions won't see it. Only call debug_excp_handler for BP_CPU, and clear the CPUState fields after the call. This will allow these actions to be dropped from the target hook. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 + accel/tcg/cpu-exec.c | 32 +++++++++++++++++++++++--------- 2 files changed, 24 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8d24aaff44..dc1c634258 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -526,6 +526,7 @@ struct CPUState { /* ice debug support */ IntervalTreeRoot breakpoints; IntervalTreeRoot watchpoints; + CPUBreakpoint *breakpoint_hit; CPUBreakpoint *watchpoint_hit; =20 void *opaque; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index cca403ad62..bda6dd9e46 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -363,6 +363,10 @@ static bool check_for_breakpoints_slow(CPUState *cpu, = vaddr pc, return false; =20 found: + bp->hitaddr =3D pc; + bp->hitlast =3D pc; + bp->hitattrs =3D MEMTXATTRS_UNSPECIFIED; + cpu->breakpoint_hit =3D bp; cpu->exception_index =3D EXCP_DEBUG; return true; } @@ -681,19 +685,29 @@ static inline bool cpu_handle_halt(CPUState *cpu) =20 static inline void cpu_handle_debug_exception(CPUState *cpu) { - const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; - IntervalTreeNode *n; + CPUBreakpoint *hit =3D cpu->watchpoint_hit; =20 - for (n =3D interval_tree_iter_first(&cpu->watchpoints, 0, -1); n; - n =3D interval_tree_iter_next(n, 0, -1)) { - CPUBreakpoint *wp =3D container_of(n, CPUBreakpoint, itree); - if (wp !=3D cpu->watchpoint_hit) { - wp->flags &=3D ~BP_WATCHPOINT_HIT; + if (hit) { + IntervalTreeNode *n; + + for (n =3D interval_tree_iter_first(&cpu->watchpoints, 0, -1); n; + n =3D interval_tree_iter_next(n, 0, -1)) { + CPUBreakpoint *wp =3D container_of(n, CPUBreakpoint, itree); + if (wp !=3D hit) { + wp->flags &=3D ~BP_WATCHPOINT_HIT; + } + } + } else { + hit =3D cpu->breakpoint_hit; + if (!hit) { + return; } } =20 - if (tcg_ops->debug_excp_handler) { - tcg_ops->debug_excp_handler(cpu, cpu->watchpoint_hit); + if (hit->flags & BP_CPU) { + cpu->cc->tcg_ops->debug_excp_handler(cpu, hit); + cpu->watchpoint_hit =3D NULL; + cpu->breakpoint_hit =3D NULL; } } =20 --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226909; cv=none; d=zohomail.com; s=zohoarc; b=anOmxujGr/1NyAG2suiFCMGyPTejcxdSo7/Kt/vOkDf4KvQ43g6ovKcun8JGsB/9mN7pwGDWfhv5Wd3WPJB/VFU8zIA+M0bBfEu1c3nbxFBKC6NOv1QrPi4D4J2GgGRzrT9aZds2ZebBynbqLOZefUF2/JVC4NEhNq18I14ZT70= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226909; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mes9xDUQ0Ck2g/+WTnUtzsbUXNthtYb/ogAdhSHGYlY=; b=jbrHAFYKd+S0cK2BCxvnlSyIkegOIe41ezGNvdLkEFhWSSoexa6tQ7d7xcXM5kbtcjbGd61t693kybdPapb0DTA/SS/ybctEMbDfLpyX5xU41CSbtYUM1/WZkUqEgIcZE1nBrR1vsLgAh1PCZvEe4mppg5rxhXYXIFRCclVTCHY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226908995312.073726306582; Sat, 4 Jul 2026 21:48:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEee-0001Lx-VX; Sun, 05 Jul 2026 00:40:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcb-0005Mr-4l for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:25 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEcH-0004NI-LS for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:24 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2cacf197759so28987515ad.2 for ; Sat, 04 Jul 2026 21:37:55 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226274; x=1783831074; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mes9xDUQ0Ck2g/+WTnUtzsbUXNthtYb/ogAdhSHGYlY=; b=RRqaEcfxaiRmjYVBkmGKhQJuCxjQtQQtWZTgqI5vcn6nZae0SmFcOxaxGQehREDzuP DOiXOTedxpkYZIu4l2CVSkiy0e7aFrcB3pb6JPoPH0xpyyxqtMhsQR+LlJNso/d7qenG PHfe1YQ9IYL5R+xp8klfaQaGjBrGoNmkvWuqHWkUEl3LeBYZTgxJmpvc0TgOhmAPDGM7 M6gyFxqh7kphZcevXZgAnGzzs+pZ2xj8ypY7hSfV3/md2e8xsYGNk8owtO9nnkQkjRQt lOsbN2Vcmc9J7WEncn1iLyAmwdPCBHrLIQgGk0I7Souir8NSf1ji+rAKNhmV8MmT9bKU ZHmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226274; x=1783831074; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=mes9xDUQ0Ck2g/+WTnUtzsbUXNthtYb/ogAdhSHGYlY=; b=ACOFN1+BL40Ml+xnLBTBE8CPaxkNudeuMkfn+z7MNU6WyRijdDbyldxmG/OIkq4Gz+ 2n8VLwkN7eOp3tmJOcSQ7lI6F/Arvs/F5aGXKf1jF8KaNXc8Oxr8H5kGIkMGzyX4rxTU 9GC+tfVz19a4YsUyEYpyVA1wzcVeZVSVnRegyxC8Dqryj7cOMLLYiVNXzdkJNvTICg6b w4vl59yer3OjOGWuC9znle3JReSeMdQuTtus9Be8WWwDdVxiGsSQHQNJgRDs5hLzBiaB Jnzts43f+zqIRHkMlkda7IaxEdpokIg67hDyYOvbmb3phCf6K3vJXTdk9Z+yx6Y1Dbz0 +8IA== X-Gm-Message-State: AOJu0Yz+q05IjAVj6PQuD0V0QXv7fg8uV1F08/dB2cfCrNretvqi2TFV VuGrrXWFFGE8941T941nArSFAnWhsWXAORU4B5Y+2eXFubE32ObAFaDU2+0f5EpBcvJ3AurXwk3 3vtsl X-Gm-Gg: AfdE7cmGe54E7/qWEO7qTZMV6dUCJzfqr4U++Mf3SYi3sZvl2IJB7s5VXjbZMJ/mtQz 9ujhQb8+EdC7+EShKor2USKd5WQDWkOkV8vWoegRrtkCObpGJKJBJrQhZn68xGHCUkhB8W2SK98 anGyjuQkWMP/U8GoI8DdUMuXHnoYwUgviYt690EQj2UtJoO+cEmMNZYKuSl2u79LzYYs6LufPVL 0cDxoiNTgiENmSrlH02XB0omeh0Ov8H2K/ftVuf9texAbLXHyqEuzBpDrz1gjv06j2a1SZp/LpX RMissn2uQ3Dp6tIkb7grPFUR8cGIKia2sCHNdJ1WhL/31czPBlYyzvfyMla0WzNmaYzTlQR/Sco b9NUR7qdid2AoTsJiJYHKi7GmMWJw5hXw9ZjTgodGVOwkR6TmkbOfJfL5ARsjpA4QxRdSJ3Ivga Dqs1pItuARlhPQbQZVn6stFvszyQTlqkr5ZEijYtkJCUETjq0= X-Received: by 2002:a17:903:b8f:b0:2c9:97a9:2097 with SMTP id d9443c01a7336-2cbb9efe254mr56878805ad.43.1783226274109; Sat, 04 Jul 2026 21:37:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 32/46] target/arm: Use CPUBreakpoint arg in arm_debug_excp_handler Date: Sat, 4 Jul 2026 21:37:11 -0700 Message-ID: <20260705043725.1373137-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226910368158500 Content-Type: text/plain; charset="utf-8" We no longer need to search for a matched breakpoint, test for BP_CPU, or clear watchpoint_hit. Signed-off-by: Richard Henderson --- target/arm/tcg/debug.c | 35 ++++++++++------------------------- 1 file changed, 10 insertions(+), 25 deletions(-) diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index fe8513a5de..d705f7aef2 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -422,42 +422,27 @@ void arm_debug_excp_handler(CPUState *cs, CPUBreakpoi= nt *hit) */ ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - CPUBreakpoint *wp_hit =3D cs->watchpoint_hit; + uint32_t excp, syndrome; =20 - if (wp_hit) { - if (wp_hit->flags & BP_CPU) { - bool wnr =3D (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) !=3D 0; + if (hit->flags & BP_MEM_ACCESS) { + bool wnr =3D hit->flags & BP_WATCHPOINT_HIT_WRITE; + syndrome =3D syn_watchpoint(0, 0, wnr); + excp =3D EXCP_DATA_ABORT; =20 - cs->watchpoint_hit =3D NULL; - - env->exception.fsr =3D arm_debug_exception_fsr(env); - env->exception.vaddress =3D wp_hit->hitaddr; - raise_exception_debug(env, EXCP_DATA_ABORT, - syn_watchpoint(0, 0, wnr)); - } + env->exception.vaddress =3D hit->hitaddr; } else { - uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; + syndrome =3D syn_breakpoint(0); + excp =3D EXCP_PREFETCH_ABORT; =20 - /* - * (1) GDB breakpoints should be handled first. - * (2) Do not raise a CPU exception if no CPU breakpoint has fired, - * since singlestep is also done by generating a debug internal - * exception. - */ - if (cpu_breakpoint_test(cs, pc, BP_GDB) - || !cpu_breakpoint_test(cs, pc, BP_CPU)) { - return; - } - - env->exception.fsr =3D arm_debug_exception_fsr(env); /* * FAR is UNKNOWN: clear vaddress to avoid potentially exposing * values to the guest that it shouldn't be able to see at its * exception/security level. */ env->exception.vaddress =3D 0; - raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); } + env->exception.fsr =3D arm_debug_exception_fsr(env); + raise_exception_debug(env, excp, syndrome); } =20 /* --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226519; cv=none; d=zohomail.com; s=zohoarc; b=lcMIFmcYxIswjbOQCY15wjwyP/MZj2r5hNqlQDapOixZOpnl4IlyYhi18+phrg2fcC1Q+pBpvMH4qpMe0y02g4U+ZP+3+rphDBY3zjreNUeS7CFYMW4TiA37HdybLGqZbwSVblv24Fw6d6e3jicirxbVqVaJdqHOLdwTqJWUfhk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226519; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aii0dYUlzhh0daweMydBIrcsyG896sPYULsiw+pFWxo=; b=L6u/yJk5gjUX2rlHj0KOsMemhumct7/df2RhyZ9VxH7y/RNidGv1WMYm3hZiyvqCgxJ3/zzl/ImCwmhLlZJEob3iABIOuYtJWHb/m7cMToUtsHiuLdQe2Rv4cdhaJrfFhgc4uPwI/UHHX1Nebq3bVBsGmAsjrg2UfA3uX2WzlDw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226519822893.8439038390418; Sat, 4 Jul 2026 21:41:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdw-0008Tw-6w; Sun, 05 Jul 2026 00:39:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcU-0005Fw-7S for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:18 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEc8-0004P3-Ny for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:17 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2caed617615so12732785ad.3 for ; Sat, 04 Jul 2026 21:37:56 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226275; x=1783831075; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aii0dYUlzhh0daweMydBIrcsyG896sPYULsiw+pFWxo=; b=WOsf7BRMRpviamxd1MF4I06kPwLbZ0QrQIvnf7ySwHZzDzk0NSZO/4JLoMF0c0JU9X GBcRLmwfDvmDFQc3nAzDdt7q97vbAXTRLs3Eq7+L+z8d/4mm7sy+NRcoPZ09zZnWQiMM yE9wI3Y7HYvJH2bmeWoMF6P3jzL08L5JAc03sZU+Cr71VjfuPJTFcaLYWJbRlELmKNlH GW8bZSEBxrDXk28X+SZfNQltyKZElv9eMUbzyZC3x4gvbncXEeIqcpSeBOmPpbJ9MA/h eHrVVlrbaxzbk33ZwNFE13nlnM1vJf/jcfeZaZQ2iuBvaaLN64hORMvtlJJOfQ2AgFIw xPbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226275; x=1783831075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=aii0dYUlzhh0daweMydBIrcsyG896sPYULsiw+pFWxo=; b=BTJlE1dubik5y7MrJJvVvZPJ2dZi/wWgt7Pn/kXjQz9Gr9jfLL8V4UNLMLqvPcQa/U WHyNFxoDAvwhH7490ek1+HfE7XSJ2F9tjIbROCsYvvx2AW6hKNV2ig7C/LTnOIzFuEAt Sjnatg+Ww/VIP2MwKEuWvGmhiUPfG5oniZOKFS9f/aFH/uKiczx/oj1Db9s1go16qVWx GUfs38RRTudVmDPAx/GKaaVg/uy3QqDFUbDTgxLXdO57JoYLS1Sw21f+3AA4sdXh1faE sB8u+6t0TqcIJYcMMIOr4gs4IQWZjjbAR6p+ggRub/DGWW+KRdqtmP9P8L5I0pD1CKvH tneQ== X-Gm-Message-State: AOJu0YzkQCP6do+HkstH6yEy9ajakpIzLPZWXEIgcXIC0OhtzKgLnOLz KyFdB3n5t7w1kNZT5m4UJCM8yfglN9NJWsapb53Lxukp7eyxm2W7JpIyxfQelVVT8ptuC6twEHi zrdTI X-Gm-Gg: AfdE7clcVPDV6FDd8XBWigi4/9yQXlVQANv46lB4DD6Bhy8c/djXrOk2qICz6liJ5gp 52yrWNNwf3Q0LkYaXMCbzfiUBtNvXeMjxQ7I7DEHyqPOQ/MiYQYSL1lejKQIlGlcUuXCp9bfb9l 2jomp0j7NKBuoqm5JAu1vLlqX2ej4edMrpJMRe113lkT/t4EZF8vako6mvJ0mnmMgYn1iF9JXi2 bkAjFN8TgIrGpbAL8S1tCGZ1SpeZ/axTRvgcD9XckTV6ZEgJwiEHcj1enDrZn94sfUDZto5+pMa N9Fy9mS8r+HkrnfgCW22Tu2lbSVycq+jVKsdFFtIao6eWi1LSuMwLjSVzE597N/O8p8sM0ysGRx nlyxuCBYiunTtvxIcnMVFO9MGQTDfk/Sseza9ARD77eFVqumH7kq1CQFvjZy+3avHhwWN4PEdW3 dy9JO44N53mWnbEML0LDGG3x4GuKY75qbRQGj1Z3f/oanQ+weZaTOLGNlfvQ== X-Received: by 2002:a17:902:ce12:b0:2ca:6d87:e684 with SMTP id d9443c01a7336-2cbb9ec3218mr50101035ad.32.1783226275000; Sat, 04 Jul 2026 21:37:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 33/46] target/i386: Pass wp_hit to check_hw_breakpoints Date: Sat, 4 Jul 2026 21:37:12 -0700 Message-ID: <20260705043725.1373137-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226521178158500 Content-Type: text/plain; charset="utf-8" Since force_dr6_update is set exclusively for breakpoints, replace force_dr6_update with wp_hit =3D=3D NULL. Use the value of wp_hit to notice which watchpoint is hit. Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 2 +- target/i386/tcg/bpt_helper.c | 2 +- target/i386/tcg/system/bpt_helper.c | 32 ++++++++++++----------------- 3 files changed, 15 insertions(+), 21 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 01f4a8bcd0..2227712e2e 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -114,7 +114,7 @@ int exception_has_error_code(int intno); void do_smm_enter(X86CPU *cpu); =20 /* system/bpt_helper.c */ -bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update); +bool check_hw_breakpoints(CPUX86State *env, CPUBreakpoint *wp_hit); =20 /* * Do the tasks usually performed by gen_eob(). Callers of this function diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c index bc34ac27fe..bcb9869c86 100644 --- a/target/i386/tcg/bpt_helper.c +++ b/target/i386/tcg/bpt_helper.c @@ -25,7 +25,7 @@ G_NORETURN void helper_single_step(CPUX86State *env) { #ifndef CONFIG_USER_ONLY - check_hw_breakpoints(env, true); + check_hw_breakpoints(env, NULL); env->dr[6] |=3D DR6_BS; #endif raise_exception(env, EXCP01_DB); diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index 8ba5dfcfc1..5dab77b2c4 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -160,34 +160,27 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t ne= w_dr7) env->hflags =3D (env->hflags & ~HF_IOBPT_MASK) | iobpt; } =20 -bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update) +bool check_hw_breakpoints(CPUX86State *env, CPUBreakpoint *wp_hit) { - target_ulong dr6; - int reg; + target_ulong dr6 =3D env->dr[6] & ~0xf; + bool force_dr6_update =3D wp_hit =3D=3D NULL; bool hit_enabled =3D false; =20 - dr6 =3D env->dr[6] & ~0xf; - for (reg =3D 0; reg < DR7_MAX_BP; reg++) { - bool bp_match =3D false; - bool wp_match =3D false; + for (int reg =3D 0; reg < DR7_MAX_BP; reg++) { + bool match =3D false; =20 switch (hw_breakpoint_type(env->dr[7], reg)) { case DR7_TYPE_BP_INST: - if (env->dr[reg] =3D=3D env->eip) { - bp_match =3D true; - } + match =3D env->dr[reg] =3D=3D env->eip; break; case DR7_TYPE_DATA_WR: case DR7_TYPE_DATA_RW: - if (env->cpu_watchpoint[reg] && - env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT) { - wp_match =3D true; - } + match =3D wp_hit =3D=3D env->cpu_watchpoint[reg]; break; case DR7_TYPE_IO_RW: break; } - if (bp_match || wp_match) { + if (match) { dr6 |=3D 1 << reg; if (hw_breakpoint_enabled(env->dr[7], reg)) { hit_enabled =3D true; @@ -207,10 +200,11 @@ void breakpoint_handler(CPUState *cs, CPUBreakpoint *= hit) X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; =20 - if (cs->watchpoint_hit) { - if (cs->watchpoint_hit->flags & BP_CPU) { + hit =3D cs->watchpoint_hit; + if (hit) { + if (hit->flags & BP_CPU) { cs->watchpoint_hit =3D NULL; - if (check_hw_breakpoints(env, false)) { + if (check_hw_breakpoints(env, hit)) { /* * FIXME: #DB should be delayed by one instruction if * INHIBIT_IRQ is set (STI cannot trigger a watchpoint). @@ -224,7 +218,7 @@ void breakpoint_handler(CPUState *cs, CPUBreakpoint *hi= t) } } else { if (cpu_breakpoint_test(cs, env->eip, BP_CPU)) { - check_hw_breakpoints(env, true); + check_hw_breakpoints(env, NULL); raise_exception(env, EXCP01_DB); } } --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226623; cv=none; d=zohomail.com; s=zohoarc; b=JxmrYj4NlZDYDp8P2+xrGn45PTKFuf71OTpVNpBu/fc8dmjHxl21UkdbefxVfmL4/cHestuNsP+CnqXmvTjXcT1j6cvIbqr9hIDQhs1Q8N43lUH1VCT/yuv7hB6ZbI4I8hXd1Af5/Viwnjh3BBRUgSkLcO8Fil+/ye2u44H8VLg= ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson --- target/i386/tcg/system/bpt_helper.c | 32 ++++++++++++----------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index 5dab77b2c4..86562fc946 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -200,28 +200,22 @@ void breakpoint_handler(CPUState *cs, CPUBreakpoint *= hit) X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; =20 - hit =3D cs->watchpoint_hit; - if (hit) { - if (hit->flags & BP_CPU) { - cs->watchpoint_hit =3D NULL; - if (check_hw_breakpoints(env, hit)) { - /* - * FIXME: #DB should be delayed by one instruction if - * INHIBIT_IRQ is set (STI cannot trigger a watchpoint). - * The delayed #DB should also fuse with one generated - * by ICEBP (aka INT1). - */ - raise_exception(env, EXCP01_DB); - } else { - cpu_loop_exit_noexc(cs); - } + if (hit->flags & BP_MEM_ACCESS) { + /* watchpoint */ + if (!check_hw_breakpoints(env, hit)) { + cpu_loop_exit_noexc(cs); } + /* + * FIXME: #DB should be delayed by one instruction if + * INHIBIT_IRQ is set (STI cannot trigger a watchpoint). + * The delayed #DB should also fuse with one generated + * by ICEBP (aka INT1). + */ } else { - if (cpu_breakpoint_test(cs, env->eip, BP_CPU)) { - check_hw_breakpoints(env, NULL); - raise_exception(env, EXCP01_DB); - } + /* breakpoint */ + check_hw_breakpoints(env, NULL); } + raise_exception(env, EXCP01_DB); } =20 target_ulong helper_get_dr(CPUX86State *env, int reg) --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226899; cv=none; d=zohomail.com; s=zohoarc; b=irANfP1CDJuhpriNFon5qMirjmGEY13cQyGLInt1MqQGBMoWu3SRBgJRRfu2XC3hKn0iGMWTbk/t+dX2Q+Jwq3JZqS66kPHcZOdouyR8oXzsvQzSPVEV8vg5gnsim1XWHjapzUl3n6FLm4TCOJdbRBKoQnsLHlNosGhJyqGlpBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226899; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HlU1WJhs/EKnxRmtpuuBgS8HV9oUIdhQMc6Ge3RayaI=; b=Rp8WRWLkXojPd9K4tbe1fkEbUD7jFlnt6gV/Mj5v85UFUovxaEzMV59GL/nqeRMUeonXGWUYh0zR/xqjgxdpnvdJD8BM4I4p88vapQ/6hi2idYMBMNh1Z+PuQa8N88DXUtDkENOhl3PvmT+32JZ9VBlLkp9cs3jNGfhefAGyV5E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226899656635.5963855162307; Sat, 4 Jul 2026 21:48:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdx-0008WP-K9; Sun, 05 Jul 2026 00:39:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcV-0005Hk-BN for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:21 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEc9-0004Rj-Ub for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:19 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2cc7e86e7aeso3366875ad.2 for ; Sat, 04 Jul 2026 21:37:57 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226277; x=1783831077; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=HlU1WJhs/EKnxRmtpuuBgS8HV9oUIdhQMc6Ge3RayaI=; b=Dg8EUxH7r7kK1S7o1tH96qSvwjj8v83i5UzPuPZy650+p93amflzk6AqO9XBGLug5W OpDXVQ4c7mYRm9g5qvedOWiemcQCQY9lbkepnirREP9l2FC1rgNbrOYgOL0IVnkb6q2s 6GMWsiVkT6M7mSVrIqb+yOfdotr1wLOPDoqQJzjTzVyOe66T1oVd7zpo4gvhitY1y72R pOKgVbuba9+2Cf5iCzXwMnqVzCuaNhPbZYGAHm5J92EXQcTWQy1Fe/G5lNvBoIYaWXre bqnnqkYNNspNk0MkQ9BaG3az/2piJ7IxIrPXuwdFZGt1o8th3vbcN3/xAXhWclX6s8jW 7CCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226277; x=1783831077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=HlU1WJhs/EKnxRmtpuuBgS8HV9oUIdhQMc6Ge3RayaI=; b=B6oRi2vmMxXF1zX+hy9ImsO/Bed/HGhMv4Veb+jpmO5YUrNedBqjKhY474Ri2TDPgO adPVggNewg2WOnHE4wrG8NbNlMpXjooRJ0BV7ri5c4I35esVSoqvuEoPA9J4ttdPSRnC cQ7Ssp+K2qbwxj7ilIF07x9O6bURkDVOq65sgEtHGh4Q+VrfLWlKJT/MCedO/jRVpuKM E+EQHm18lYylzk45+UsFNHJx+YrUQJ4uTWdXqUIIaTYm9FDwIvT3Zen8bYkR4GAbUu7U JXDu4+REMvxHpeXxwYbKsA94+5Dz3+0FXlUpJhprHuceO0f6DWe0pn7VCYGBOrkb+XZG RmYg== X-Gm-Message-State: AOJu0YxAlfRSYzkrunrfROR4NpuCmcs/KoNT9T+3hbUzZE4w1iBgBHeR PciBn8mOZySgF4wg3itK18xs16JDZgmiGEktECSBIs+Cc8RXLpoFoUdArkoRjlul3+gc/26jAF9 nQF7F X-Gm-Gg: AfdE7cl1u6lI3lS0lPGVLS1PJncpVNuYzUM5Ap8wSUz5Ppa+h8627BDgQxzM26a1S9e KsTu7huQ7W50k9ILQkPhnIat9jtMSofEyW5Goycz+m88efjs9xsKBHxLrbxKGN8HWqKXqhdO5jx ExZ1xwZIkBjJkiyzyWzPySgQHzjzoOlkcsyBMEtvRQkYB+AE6/RDryFJ/h2Ji6xzr/xJELmNW0j jQJmEyFLUH/5kmam3XvhGYMx9zVjGgAFj2/yo7Y9DkVHGFmkAVia13RZwoPagIRNVMEhvDuunaw 32aIapA1AAgyVmlOVU5qMrUTpFOEQ0dSX2uNwe4yvMMkBIxtEenOw6Z8dbnOv5KPLnxegZGiSuI q/AHWVr8hD3iRyukYPQKJtnzhPZTCBpKxzmr1a5xOXq/CFxX9MPnLHvMpyfY83J+buoIscJW3sL H2QWPcN/rujZWMB6qsU6+FY8WZ319XNyujxsYAQ7xXSdu6pak= X-Received: by 2002:a17:903:26d0:b0:2c9:c083:cd50 with SMTP id d9443c01a7336-2cbb9e2e2admr50526815ad.17.1783226276557; Sat, 04 Jul 2026 21:37:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 35/46] target/ppc: Use CPUBreakpoint arg in breakpoint_handler Date: Sat, 4 Jul 2026 21:37:14 -0700 Message-ID: <20260705043725.1373137-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226900366158500 Content-Type: text/plain; charset="utf-8" We don't need to check PPC_ISA207S, because that's already done starting with register_book3s_207_dbg_sprs(). We no longer need to check BP_CPU or clear watchpoint_hit. Signed-off-by: Richard Henderson --- target/ppc/tcg-excp_helper.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 51358c901f..56ca66e7b5 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -314,19 +314,14 @@ void ppc_cpu_debug_excp_handler(CPUState *cs, CPUBrea= kpoint *hit) #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); =20 - if (env->insns_flags2 & PPC2_ISA207S) { - if (cs->watchpoint_hit) { - if (cs->watchpoint_hit->flags & BP_CPU) { - env->spr[SPR_DAR] =3D cs->watchpoint_hit->hitaddr; - env->spr[SPR_DSISR] =3D PPC_BIT(41); - cs->watchpoint_hit =3D NULL; - raise_exception(env, POWERPC_EXCP_DSI); - } - cs->watchpoint_hit =3D NULL; - } else if (cpu_breakpoint_test(cs, env->nip, BP_CPU)) { - raise_exception_err(env, POWERPC_EXCP_TRACE, - PPC_BIT(33) | PPC_BIT(43)); - } + if (hit->flags & BP_MEM_ACCESS) { + /* watchpoint */ + env->spr[SPR_DAR] =3D hit->hitaddr; + env->spr[SPR_DSISR] =3D PPC_BIT(41); + raise_exception(env, POWERPC_EXCP_DSI); + } else { + /* breakpoint */ + raise_exception_err(env, POWERPC_EXCP_TRACE, PPC_BIT(33) | PPC_BIT= (43)); } #endif } --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226982; cv=none; d=zohomail.com; s=zohoarc; b=CamlQ4zTE0qfJKRcoF+kS5+FL6OoIcTXxr1GXf8V6cwGnmoNW3YQ1BkO06YO7pUQZgcm7IV/SV5rHNQR+23uqp+Ct03CsG0rogvc7e7TncfWlFGfzENHYEEAXxGcTYmD/sYHiSuX4T+9v7xe0ugs8u8Z3L3bNKVFUAxQYJyV9hQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226982; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GnP83ngqbzOCaEyHZuWHVT2DEUxtaEIT/kVQUZ1VwBM=; b=CXlWwnpdD/2Pqgwb6HPe9FAuj3C41fxHyOIUN9XwNK7S2yHHuAU31D8kjRz/gkcR3vrPK9564Is1rVhUGru4uY7oKTj5OzD4ezK3eLtT38W+QjYUdtkmuWfBIKdYNZ9XoctTM8/EQs2zKSUK80YSKhcGozEEdReXKPrx2bsZd6o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226981997179.25838836978517; Sat, 4 Jul 2026 21:49:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdu-0008Oh-A7; Sun, 05 Jul 2026 00:39:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcV-0005Hn-RP for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:21 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEcA-0004UC-Rk for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:19 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-2ca64c3ce5fso19728565ad.3 for ; Sat, 04 Jul 2026 21:37:58 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226277; x=1783831077; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GnP83ngqbzOCaEyHZuWHVT2DEUxtaEIT/kVQUZ1VwBM=; b=dClL0i5RWjVq+7cOca0wARGvOA9Kk5oFOvfmeOYw5cM1R6WGROgthgQUZbFwDnNc6L oP8SxrSlQINySR+/d87LXJ+jJR5j7QdnpqbH7W62tP27pC0urNVoJKhzWcgpgfuiIpPH /vPMtSybsdASdCNBa5EINsYbalMwR+o++lhYeIIWSFC0zSQy5gLImTxDQfD6YpPkVCmU 8lY34bctbZIInmpMl3Y87FtvBAv5kFEfvZO1Z1lUUoohPTkn1sysPaYyIRGXWd5KZFq7 vjVY+lQLDAi7nPMs7GFl6xKKV1EplhFCyTrjIDXJRR1fTxXb8by6IwznQ+h2qLmm2NuT cYJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226277; x=1783831077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=GnP83ngqbzOCaEyHZuWHVT2DEUxtaEIT/kVQUZ1VwBM=; b=ce+FzzpXhP7bV+KAsJ3Mf4qB/6+QocmD/4we7L4IC7xvMjQpLIVac8aB83/5xCA5MK 5E+AxJRuOkjfxg3J93UlxSkkgZEu3SPA79NtQckVnyiN3EzSr/gx/SSie0deniOyEHlh wD4RGnJvhdhPG6cznkHSyFiYGjAI4Ze0ZwKeG+NwSPty/GGXgyoFJUV0XGq8p8HiyGoF ZkP4f4kvtb2Q6I5d33W5VLjyHRZF2+VKCW8k6J3TCWkVWSOfark3yooAZ2KX5WioInlh bxt6eBSLcuSI0epG4S7CxvLN3eTEGqgOek1PiqjpvmqsZg7ttYi02Wbbxa1hT4wmI9W7 tktA== X-Gm-Message-State: AOJu0YyeVZvIEoCK4j8ypGQ9c9qdl6ZWACoeqWEptAAv8bGDswFj8G4D /aVot/E1S4GD+OfPuOHC+7FTof86c5JWVwP1IvGOCf37BdxKYK32k3kfbGPSg2xIrbtrD07Rhg8 yIWzy X-Gm-Gg: AfdE7clzz7zPBNehkpkdDRedd4Fd55SIQ2Kk9mXXviieQIRYYsg9kMAfCqpdWUXaU4L ubi6FYLy0JomcrSxD3F+CiUas/PI+CGhpimgt+o+1ot+HB3oXWq2NpN39/m0rXzD88Dvk+ZD18k CuzT4J1trESfiKT47IpwyOUQYQB8WWBz9ZM9cQTeYsosKcgaBtKbydoMcsVYiwOhRJS2YbqNuvT deIeUVcTo8KDJ0blAq/BroP/SPZJNFmgmEl1IOrDoa24KdO7ZS57b6kSc0ro3aFg2oifZZQyhS9 1DB5Af7Lugxz8sQNjxnFx2FSB+l56ZSKJdq9TjJt2u5wBVPoGIVTpY5KmP/NThHARGWRidFsSiN /XPwMoadO16IHcrDOBYoVtdXrgF2ii3MyKKLOxe2jJxKjXdFtgvFSTyOAiUmPj9+urExW+NGbcd X9NwNKEFsc088v6VCNWUJisw6LzuDGMnjKmSPDyWbpvGDHSDc= X-Received: by 2002:a17:903:b8f:b0:2c9:97a8:8c1b with SMTP id d9443c01a7336-2cbb9f086e7mr52110315ad.46.1783226277370; Sat, 04 Jul 2026 21:37:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 36/46] target/ppc: Simplify ppc_cpu_debug_check_breakpoint Date: Sat, 4 Jul 2026 21:37:15 -0700 Message-ID: <20260705043725.1373137-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226982617158500 Content-Type: text/plain; charset="utf-8" We don't need to check PPC_ISA207S, because that's already done starting with register_book3s_207_dbg_sprs(). Replace target_ulong with uint64_t, as we're under TARGET_PPC64. Signed-off-by: Richard Henderson --- target/ppc/tcg-excp_helper.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 56ca66e7b5..99ffe4a820 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -330,23 +330,19 @@ bool ppc_cpu_debug_check_breakpoint(CPUState *cs, CPU= Breakpoint *bp) { #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); + uint64_t priv =3D env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); =20 - if (env->insns_flags2 & PPC2_ISA207S) { - target_ulong priv; - - priv =3D env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); - switch (priv) { - case 0x1: /* problem */ - return env->msr & ((target_ulong)1 << MSR_PR); - case 0x2: /* supervisor */ - return (!(env->msr & ((target_ulong)1 << MSR_PR)) && - !(env->msr & ((target_ulong)1 << MSR_HV))); - case 0x3: /* hypervisor */ - return (!(env->msr & ((target_ulong)1 << MSR_PR)) && - (env->msr & ((target_ulong)1 << MSR_HV))); - default: - g_assert_not_reached(); - } + switch (priv) { + case 0x1: /* problem */ + return env->msr & (1ull << MSR_PR); + case 0x2: /* supervisor */ + return (!(env->msr & (1ull << MSR_PR)) && + !(env->msr & (1ull << MSR_HV))); + case 0x3: /* hypervisor */ + return (!(env->msr & (1ull << MSR_PR)) && + (env->msr & (1ull << MSR_HV))); + default: + g_assert_not_reached(); } #endif =20 --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226974; cv=none; d=zohomail.com; s=zohoarc; b=Wabdx0spas89AUmJqrPiH3daQvefwglR4OqJtsXS1NPEhdv/gxKvnW4bLiLW2NwX1Hh9s9uC+LA7GYtnENDNVIZX/v2e++6FEZj4W3+VajFNg9upQ3WHgBTsmgGnX9p5m87gkRbjYhu/BIFA+uIiGdAhEum9O5GOe0kp4DC1rcU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226974; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Gu1/Z4NGRci2zl7OUGsQFq715jKZAcS9WoRfcTkKu9k=; b=Cqd5+pdj21oeBtqVe9p1xvJgBQ1I+to86VtRJ0w1+dbfUUSUPZ0Om2mxTWknsH3wTTscICtSCgX1473eA9U90WVMQ86hF9epi26j4wSKxr1BwPZYEDKdqtngaXiQDMlKU3sQxwP+iLb4yRuJIYKZAqQNIRqVldaMbpb+NOtOFD8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226974936643.3815677464801; Sat, 4 Jul 2026 21:49:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdv-0008TT-Sc; Sun, 05 Jul 2026 00:39:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcX-0005J4-CR for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:21 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEcC-0004Vw-3q for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:20 -0400 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-ca12086c06eso1129656a12.0 for ; Sat, 04 Jul 2026 21:37:59 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226278; x=1783831078; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Gu1/Z4NGRci2zl7OUGsQFq715jKZAcS9WoRfcTkKu9k=; b=Su/JF5JrKq1V8q1V/FaNCvHr4pcFgGbupwdxgqCAVKJMC9YzCrUrHykerA2mkDwYha LfdoegNXxtMptpEisy0bBC+drwMGYAA3A3Ew4BZOa5I/N06zmxhwqBqogci+xngUBOjr 4r8TyfwfDNsxZIbnrziwZcypZcSd63ohASa0KH7qYpvjIWWqFMzHWWTTL/6nIY4DxTnC d1ZA+9wsVl4r1J+Z/h00weZTQP2fRnWUMR2KiRFixq6W0WT3ZzCSDvCKGMNpAUCTQFnS zvd+xMGd106RC5XArwFYi54bL3CUKfsPBdKs/BOfNiaB870lDH7Olt3nvnFlqdIwK21l 6euw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226278; x=1783831078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=Gu1/Z4NGRci2zl7OUGsQFq715jKZAcS9WoRfcTkKu9k=; b=Xr6FZyTb0X3nekNll/88RgOFbOyBeklM8g0/5nwrdOiPL3kwbyxbtR3mSBw9Ia106Y VKcHKB+E10L1u+Bk2jgqykwEI6bvCTMrdXE+yxPW6s0vvyfmfRao1BK6wmZkV+PgfBmQ xwNuAZHAyVR/B+TfO/gRRICHhiVWmWacB9QGFkSag/7AS2y817CGy70NS1A9FbpFoGmd 48KRuv9p++PBd6vNZhNuAgtAjJ8MzuDk5IcmTNEhtMh2UB69TQ8toO2KmRvN8Ha5tL87 5tMwnjeO/X0FWtD9V34Saq6AL1ED1vDadQs8v6lZIHY0qTCVOBG9CviIZYGlfVrCSJcE 6hVA== X-Gm-Message-State: AOJu0Yx++8arwZ6mZtURbsLCBhVWB8Za414JOuKzgXRB9q+v1JUwB7Q6 ko39lBhLlFXu60CfA9G6tjlHHSMJtpbuBIa/hJtNtN7lAyRVyMMsLlFvzEovLJB/n8fOGbp47em JLAhs X-Gm-Gg: AfdE7cmvTsVGuZMRYHhbuF9y2VYGzEFwPEdVEnTnsZqi1UgpsN5pbRKrSRSFOqK/sJx Yv1g8KOcr3naBWkJDXH6t3JsOwin0VQV3xVAmPFD2zbZFVgKrnn4wfanmomlv38eF5+n6ArX0jb 1ZDMNDGPg+3bGcwnXB58ot27IQ3GoEL5FWwiKHFBktT3Ibd6gF+mF5B3J5DCPsZcUN4PD0v3B04 sC0khgPKY45DdMg/DtFV6xz9msPa0oVSv9WV/y+BVKMu7y76lGv7PWQHRXyYdMIdUK5xCG3TVVQ QAt6RL8/r/QRdnkq4wJGCa8dPAo3MOmzOEihl6opMppCCGjEkKqgO6qw1dKsPoUH/pBZQ54j1Bk 57JWtJ2mgb71qjDf+BnD82JJ8kqpe3IztdyF3HLm3MnBrv2/dY0UBzq0MuKcQDfaU5XttmUi3ID UIoZ9482mN2uhf93d9k1rHf1dPly5wrNleSejssg7gkMP+uE0= X-Received: by 2002:a17:903:198e:b0:2c6:9f14:c50c with SMTP id d9443c01a7336-2cbb7cba325mr55750965ad.13.1783226278227; Sat, 04 Jul 2026 21:37:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 37/46] target/ppc: Simplify ppc_cpu_debug_check_watchpoint Date: Sat, 4 Jul 2026 21:37:16 -0700 Message-ID: <20260705043725.1373137-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226976634158500 Content-Type: text/plain; charset="utf-8" We don't need to check either ISA bit, because that's already done starting with SPR registration. Replace target_ulong with uint64_t, as we're under TARGET_PPC64. Signed-off-by: Richard Henderson --- target/ppc/tcg-excp_helper.c | 30 +++++++++--------------------- 1 file changed, 9 insertions(+), 21 deletions(-) diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 99ffe4a820..4065440949 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -353,35 +353,23 @@ bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPU= Breakpoint *wp) { #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); - bool wt, wti, hv, sv, pr; - uint32_t dawrx; + uint32_t dawrx =3D env->spr[wp->id ? SPR_DAWRX1 : SPR_DAWRX0]; + bool wt =3D extract32(dawrx, PPC_BIT_NR(59), 1); + bool wti =3D extract32(dawrx, PPC_BIT_NR(60), 1); + bool hv =3D extract32(dawrx, PPC_BIT_NR(61), 1); + bool sv =3D extract32(dawrx, PPC_BIT_NR(62), 1); + bool pr =3D extract32(dawrx, PPC_BIT_NR(62), 1); =20 - if ((env->insns_flags2 & PPC2_ISA207S) && - (wp =3D=3D env->dawr_watchpoint[0])) { - dawrx =3D env->spr[SPR_DAWRX0]; - } else if ((env->insns_flags2 & PPC2_ISA310) && - (wp =3D=3D env->dawr_watchpoint[1])) { - dawrx =3D env->spr[SPR_DAWRX1]; - } else { + if ((env->msr & (1ull << MSR_PR)) && !pr) { return false; - } - - wt =3D extract32(dawrx, PPC_BIT_NR(59), 1); - wti =3D extract32(dawrx, PPC_BIT_NR(60), 1); - hv =3D extract32(dawrx, PPC_BIT_NR(61), 1); - sv =3D extract32(dawrx, PPC_BIT_NR(62), 1); - pr =3D extract32(dawrx, PPC_BIT_NR(62), 1); - - if ((env->msr & ((target_ulong)1 << MSR_PR)) && !pr) { - return false; - } else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) { + } else if ((env->msr & (1ull << MSR_HV)) && !hv) { return false; } else if (!sv) { return false; } =20 if (!wti) { - if (env->msr & ((target_ulong)1 << MSR_DR)) { + if (env->msr & (1ull << MSR_DR)) { return wt; } else { return !wt; --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226896; cv=none; d=zohomail.com; s=zohoarc; b=aBIFOYS5QufxUQmQ2EpkwMcoCbp8kUxpPPhtjsEDzqRpYS3qBOHufNG0qrfk2qQQPhny7d2zk8QKx8+3PPRtZwkyfpyZas0KTlSOyktAkN6EYDTclkCHQQmWR/98AHRk4MMDHKI/Ydpj+kVExFaxbYH0RKd63wa2M+uWggu0/8I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226896; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AwlXkf93TRyaeETrOdNkI4UVA8dItVhEvL4JieLFr/A=; b=RcYyUWaiqeA7mOLZuiDcewyxx+y9an7O+4b41jwpCL1vEAmHoBRNh5EaipqI1GeQfWz98GlG70edc5ZLNMkltGEKbFAOEn35qOQuIBLfnlfUlcQBRPl9u6ZBtmUyL7hf6NH7ruFEB68c0vjKdIZvmGQWSja7HsyddexGt3FTdEs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226896857934.9155831714636; Sat, 4 Jul 2026 21:48:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEdx-0008VY-56; Sun, 05 Jul 2026 00:39:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcX-0005JN-Gl for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:21 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEcC-0004WY-HQ for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:21 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-2cab973140bso22118855ad.3 for ; Sat, 04 Jul 2026 21:38:00 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226279; x=1783831079; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AwlXkf93TRyaeETrOdNkI4UVA8dItVhEvL4JieLFr/A=; b=W/ykrwiGXni3xxFNh35T8d89iIZHIVSz0F2bzQChGkhmpTaE2ipQBqRbi8/YKgV904 hZft/glp3B7EHRCNyK2u4B/wO9V7E5TiC9EjTpVXLKLYM+pLI4Wm5TRdYN8Nzc7nIC5g /3wfJXlaarJih6mezMARmoB+Z2u6rF55lRwpRAZj2Z5FedIYW93gsKTX5RT+tMejVJ8K ANKbb82X0gkj0xwEAwUQ434e1imrARse1MDgYJMe3w4Kj0UtftoZeUSsdFLrV++qpQqf Kk1SLAr3xHsm9utMWNf0R4pp6sQ1uPJJstiQJIdABvAcNbsbGODDV0/lTjQzwunBrGjT 2EAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226279; x=1783831079; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=AwlXkf93TRyaeETrOdNkI4UVA8dItVhEvL4JieLFr/A=; b=Le47LeDzB/e+aItQqtl09iRrmtyKbGheoCFEaTSL4Scr3EP7ck8o9X9vrtebVpk7VJ j5Jd25Z7oaBsUsRsOLHO35kwuuEcMIwn8fgOQV2hG29vJb/zY5nHWbKGwt/CobVilFjQ tDutY+03ZSVPwDdbvEwtKINWzVv/PZ9hpr3edEfoBGIBP5caoqiiqNFyA2KapKujccl/ MDIrWDwu9CMCzqH/SmyPaVO3aZVfdBDVduTaY0AlXPUIC0/HtQ1ETdQWmVSfhHRl+Xap kZgp2GJiQKeJD5nSbIJkPBws8OlhRtAbLAkHtmYcGePqc5E/zlDZSwexqEPZ8ebqj8Hv 3Zbw== X-Gm-Message-State: AOJu0YzZYZp130JOI84YOD6H1kJdeGUPKt4MICcVZx+ZxrBjQSEydQ8I CNz6HpR69SJAVdKb98IJ/UbSZLoFk9nqBl2O5KYYQib7LAYYhzxJK3o1BzxDr7inF5OrXxuu+e7 QUsAO X-Gm-Gg: AfdE7ckQsHrhhzCPo0YH41MeCpKezodywGgEnf1sNQC/gBfMfAkOu0qmq8+AcD5qm8V /rrJlzOSya2Cd+OCj0OQsdP4kZ3L9oJu7DxDCfoGi5glaxfGq1mUGKflSbqBfBysMTrnN1mv3AK 4bpxiEQ/PogeHN2AYiUs5bgIXJ8a8AfVRz0tadN33GiHfXRHThKKru3/yQziTflUdegQAG3/Fme +W4efESDN6t6ErPfWg7RdZsBBCTHC03QIe4DNjDPDb56V0ajQbBHEaBh+yaNF7hWGLguuYQzipe p/sdQm3BDSiQCoVicMwVy1DPdXFmOc/fddvxasHRJt/QpyMvWWm87b9R+kqJs9o60G+QdPi9OsW +DblRyAiwVZkj4WfANxjSOhwbwjw90qq5JiGFCfIU4JLaaCmqw5Y2nRqAnEUkx6kuHMF/SqWu6G Mf5WQzfRq4HNCQD6kBGngCW8IvKpNckPtpz6B0rL4JcdY6IGo= X-Received: by 2002:a17:903:3c45:b0:2ca:64d3:f0da with SMTP id d9443c01a7336-2cbb9ee00cdmr54702325ad.32.1783226279046; Sat, 04 Jul 2026 21:37:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 38/46] target/s390x: Use CPUBreakpoint arg in breakpoint_handler Date: Sat, 4 Jul 2026 21:37:17 -0700 Message-ID: <20260705043725.1373137-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226898311158500 Content-Type: text/plain; charset="utf-8" We no longer need to test for BP_CPU, or clear watchpoint_hit. Signed-off-by: Richard Henderson --- target/s390x/tcg/debug.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/s390x/tcg/debug.c b/target/s390x/tcg/debug.c index 58d9cc6e79..ef0d953e01 100644 --- a/target/s390x/tcg/debug.c +++ b/target/s390x/tcg/debug.c @@ -52,9 +52,9 @@ void s390_cpu_recompute_watchpoints(CPUState *cs) void s390x_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { CPUS390XState *env =3D cpu_env(cs); - CPUBreakpoint *wp_hit =3D cs->watchpoint_hit; =20 - if (wp_hit && wp_hit->flags & BP_CPU) { + if (hit->flags & BP_MEM_ACCESS) { + /* watchpoint */ /* * FIXME: When the storage-alteration-space control bit is set, * the exception should only be triggered if the memory access @@ -62,7 +62,6 @@ void s390x_cpu_debug_excp_handler(CPUState *cs, CPUBreakp= oint *hit) * bit set. We have no way to detect that with the current * watchpoint code. */ - cs->watchpoint_hit =3D NULL; =20 env->per_address =3D env->psw.addr; env->per_perc_atmid |=3D PER_CODE_EVENT_STORE | get_per_atmid(env); --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226867; cv=none; d=zohomail.com; s=zohoarc; b=GWC6OZec7ICld/JRF+CQ3FIoN33knK92u9Cv95mCDX4gZQW7gkot/zhTirdGFHCZ1KjsZgLYraugGJLlI+7vWTkubPXRwKdCeaxh4P91NcqUwL/zJ22+pb0PBQpfbANpwhOk0/4WR2mjGDKxheuRJm1YWaR+xofScBYe+i7i62Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226867; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zEoEbldckN16OhTsR6Zaa+zbm5X/cyDm4W7LiW18RHY=; b=JwQNdaxtM/iZ0vioTYU1qA5byYStw3I5WJ6WXjGE5ytadfFZIBlWb3XNYffL+s+ziXd1MtKKCjvMVheDjs+AdqwErJ0hnrJp8m/TDw8UO1CWNOc2V2PiLDwJNZnu6AlHQTo+9gXoik+hFOMg1JmTxGlc3kVk2y3mDr2tffeSJw8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226867499690.7163800876435; Sat, 4 Jul 2026 21:47:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEed-0001B3-FE; Sun, 05 Jul 2026 00:40:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEcZ-0005Li-1i for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:24 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEcD-0004X9-M0 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:38:22 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2c7c61b5292so26371715ad.0 for ; Sat, 04 Jul 2026 21:38:01 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cad712ca17sm29863785ad.28.2026.07.04.21.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:37:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226280; x=1783831080; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zEoEbldckN16OhTsR6Zaa+zbm5X/cyDm4W7LiW18RHY=; b=VPEstlgkTS8voriYzOBdFJd/hJRHkMe8kIs6gxkbY7TA2KEpEI7R0OsLhvSZ0izB+/ eZQbpMgKvImcadSY984sQrWl5AZ+7PrLQHpUl2sdtnVz9JX0GO6O10HFQLqs6eX0IApx PhNf24XwXm8uKdrl0ZGcVpWdYzhnnWht1G/xiWMU1DhlG9GJElSYDpPUxP3RNg7wYPHR uKMO4eSz7ea/QNl+O4g2d5g2y1n9g1VMP7orOJ1b++VqAWGOiJpGdV57V8jB5ZpAteFq hXmxEP9c/HWzRsYcdUi76Gc9Gpj52Aktcb5sYat9wi7Cx+12i7rl6cjjTpmdqpRjUROC yvrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226280; x=1783831080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=zEoEbldckN16OhTsR6Zaa+zbm5X/cyDm4W7LiW18RHY=; b=rsWzA9o0/I2jawGh6u3o5HTab7zVnIgoQQN/YYRi5B8Tos54lBayVoNuBGS/0O3RoS NHFL6PI4xGIM9kzw5R2CRmKp9BPAn8muKtpB8EQ8XIXQLCl851iiu9pkykv1PAwqozoC VKccUkQ7PNRagqcjYeE395UJP8KsKIfxgJ9bpvov9hi81Th3dqaWk/pPVSkIqMtWOy1A N0AxIg7zhm7qkve0ypWsb1wlilOm3eQNEfZdKO3jMdAJlVm0MWxZa67uku4PuglkC4eC EFALSBP4YQH+WYaqCpoHnAerOwlDGU1AWh8HgR88WFCSkgBp/0jGh+Xwsy6urdP7VT19 hf3g== X-Gm-Message-State: AOJu0YwMkTpdFs8DJaagJOq5JJd/RCjWEs7VoOO18fNKxRvqw7O4E7z/ zj+QNAhjJ1ucApvUJcPR9zSITeld3f7XeIRgIzpSgbL/mfddaQvoJsEQBCJlg4ez8AXAzwjzEyi Mws3J X-Gm-Gg: AfdE7ckMyDGNrnOQ0m3PHrEjq4chpSuQqPN2+4Uqg1h9gkQeV3z2Pn8fO7dVpsiLZIL kfJEvZQhpTIcaKqPg1YAgxpfEbPZJbP1ER9meMjGfpHJ3uFMOij87AdWGXxWbRqAS7iTbE3f/h5 upzsNJslbbIUWws2p35gdznvXcuwwkRyvZdYtRtWXUyjnPDgpat61JyhGqSoL1yCC/MbtcQUjNv GVDUnMX4Y27TZeVo5QXulYXtSQXKNI4/kLfzojxcdNBazVVNK7H77ebwUaWMz6PvwgV5zRTKiFA 56X2Ega+EkyRahuqQfdCOk64IprtoVEakzdSe9yP9R2P2AFAa5QuxZnagBw3PHTOleRssVhpz0m WASLn8UDkv2QQL481FW4CM77icUSBjXedhUqXH8iF7zgcyjj19jONXDnh6mt02QnpkifXYoIZ+0 vWwilI/jPuXMBt3Kzq0Zf+9zu53/OoekHKFl6JOZvVeXmuVpQ= X-Received: by 2002:a17:903:b8f:b0:2c9:97a9:2098 with SMTP id d9443c01a7336-2cbb9f008dcmr55689425ad.44.1783226280287; Sat, 04 Jul 2026 21:38:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 39/46] target/riscv: Simplify riscv_cpu_debug_excp_handler Date: Sat, 4 Jul 2026 21:37:18 -0700 Message-ID: <20260705043725.1373137-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226868217158500 Content-Type: text/plain; charset="utf-8" We no longer need to test for BP_CPU. Signed-off-by: Richard Henderson --- target/riscv/debug.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index a8429778f6..994a77fd31 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -919,15 +919,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs, CPUBre= akpoint *hit) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; =20 - if (cs->watchpoint_hit) { - if (cs->watchpoint_hit->flags & BP_CPU) { - do_trigger_action(env, DBG_ACTION_BP); - } - } else { - if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { - do_trigger_action(env, DBG_ACTION_BP); - } - } + do_trigger_action(env, DBG_ACTION_BP); } =20 bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp) --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226971; cv=none; d=zohomail.com; s=zohoarc; b=D12TB7KnIA3ZVeHNvKV8UcJpUJw7g3GBG8RGIDbxx0NsDCZkTYqqUhIO5owj3QIY5oBouH5J2p/a7Jdt1Ed1wm/UUIwjipozmzCo56L1a5shJtAZzIrZvLkT2J72kPZ2uVr6Z7LCmetzVogu25BGVhe5nZkanwDzaVGNZ6+wTXc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226971; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Lp+19HN1hDJRD/nyQTZDKaLa3PwvYZGSdAI5w9aXD2A=; b=K/7TdDLjko6wQtY1A92jzj3pgstyQUJ39YDXyk3TS31tblbxzf9Zw3JknVscuYZOqSX8OM3ByAR9pGVy/R+Wzig8kxy4ZcVZiMQrWhbOdQnM8oJ7+lmiL5ydgXd2QJVT4sweVxnPlrpQyagUPGK7XmlKnd14pN3V0BdkHHbC6PM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226971642368.2809199295391; Sat, 4 Jul 2026 21:49:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEfE-0003bB-80; Sun, 05 Jul 2026 00:41:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEfC-0003R4-6p for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:06 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEf9-0006KJ-8x for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:05 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-8479f1a86ecso1096202b3a.1 for ; Sat, 04 Jul 2026 21:41:02 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 4 ---- target/riscv/debug.c | 8 ++------ 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c318dcd633..f9556c04a5 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -2373,10 +2373,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) break; case RISCV_EXCP_BREAKPOINT: tval =3D env->badaddr; - if (cs->watchpoint_hit) { - tval =3D cs->watchpoint_hit->hitaddr; - cs->watchpoint_hit =3D NULL; - } break; case RISCV_EXCP_SW_CHECK: tval =3D env->sw_check_code; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 994a77fd31..f4689519d8 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -919,6 +919,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs, CPUBrea= kpoint *hit) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; =20 + env->badaddr =3D hit->hitaddr; do_trigger_action(env, DBG_ACTION_BP); } =20 @@ -929,12 +930,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CP= UBreakpoint *bp) int i =3D bp->id; trigger_type_t trigger_type =3D get_trigger_type(env, i); =20 - if (trigger_common_match(env, trigger_type, i)) { - env->badaddr =3D env->tdata2[i]; - return true; - } - - return false; + return trigger_common_match(env, trigger_type, i); } =20 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp) --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226900496312.871702175357; Sat, 4 Jul 2026 21:48:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEfE-0003cq-FP; Sun, 05 Jul 2026 00:41:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEfC-0003UC-GP for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:06 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEfA-0006MX-Ef for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:06 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-845b6d9bf39so1505795b3a.1 for ; Sat, 04 Jul 2026 21:41:04 -0700 (PDT) Received: from stoup.. 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Rename to riscv_cpu_debug_check_bp_wp and install in both target hooks. Signed-off-by: Richard Henderson --- target/riscv/debug.h | 3 +-- target/riscv/debug.c | 12 +----------- target/riscv/tcg/tcg-cpu.c | 4 ++-- 3 files changed, 4 insertions(+), 15 deletions(-) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 540835f2d0..fbe6898718 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -144,8 +144,7 @@ void tdata_csr_write(CPURISCVState *env, int tdata_inde= x, target_ulong val); target_ulong tinfo_csr_read(CPURISCVState *env); =20 void riscv_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); -bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); -bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp); +bool riscv_cpu_debug_check_bp_wp(CPUState *cs, CPUBreakpoint *bp); =20 void riscv_trigger_realize(CPURISCVState *env); void riscv_trigger_unrealize(CPURISCVState *env); diff --git a/target/riscv/debug.c b/target/riscv/debug.c index f4689519d8..803418f390 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -923,7 +923,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs, CPUBrea= kpoint *hit) do_trigger_action(env, DBG_ACTION_BP); } =20 -bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp) +bool riscv_cpu_debug_check_bp_wp(CPUState *cs, CPUBreakpoint *bp) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; @@ -933,16 +933,6 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs, CP= UBreakpoint *bp) return trigger_common_match(env, trigger_type, i); } =20 -bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUBreakpoint *wp) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - int i =3D wp->id; - trigger_type_t trigger_type =3D get_trigger_type(env, i); - - return trigger_common_match(env, trigger_type, i); -} - void riscv_trigger_realize(CPURISCVState *env) { int i; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b73e3e9dd4..3701aa6c94 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -292,8 +292,8 @@ const TCGCPUOps riscv_tcg_ops =3D { .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, .debug_excp_handler =3D riscv_cpu_debug_excp_handler, - .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, - .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, + .debug_check_breakpoint =3D riscv_cpu_debug_check_bp_wp, + .debug_check_watchpoint =3D riscv_cpu_debug_check_bp_wp, #endif /* !CONFIG_USER_ONLY */ }; =20 --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226889; cv=none; d=zohomail.com; s=zohoarc; b=bDVphG7r4gGCS5AIJEBqUVbWcOBqEtOkZyeT5dHfM6hD51bPF6yxPVVdIyLYKMtaT3ioszbfxjwclD0z8dm43zTYkOkjZoIjBrZldsGouHYc1hnlv+6zw/G1cDnjdGhtDX7tpQsHr/dzUFE8YoOTIPojs0dDEswWN6KjnRwU1m8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226889; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Oi77c4t6mTRvDij0KOLon4zdhMhjLviMYDkRz5tIy7Q=; b=RWCrwWRwG89LWd83kcHqUvpeFHw1ipFZN5ABW+OhTyQk0xZijW4d6B8/JClZTX1/2EQo3fXZ88ujX2+6wBMtWHfheMtOZ0KtiHYmhT1OEqBfm28nlFTaGBvEm/7u8/g7ejtvLQtjw/fHJWr0lUYebGDZCYQ0VqnIjPL01k8BlfY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226889131176.21137022753214; Sat, 4 Jul 2026 21:48:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEfH-0003nF-7Y; Sun, 05 Jul 2026 00:41:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEfE-0003bv-8q for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:08 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEfC-0006NH-Ar for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:07 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-845e363246aso2027621b3a.1 for ; Sat, 04 Jul 2026 21:41:05 -0700 (PDT) Received: from stoup.. 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Sat, 04 Jul 2026 21:41:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 42/46] target/xtensa: Restrict xtensa_breakpoint_handler to system mode Date: Sat, 4 Jul 2026 21:37:21 -0700 Message-ID: <20260705043725.1373137-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226890249158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 663ee23dc4..119a0b8187 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -592,6 +592,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, vaddr addr, MemTxResult response, uintptr_t reta= ddr); hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); bool xtensa_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); +void xtensa_breakpoint_handler(CPUState *cs, CPUBreakpoint *hit); #endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void xtensa_count_regs(const XtensaConfig *config, @@ -621,7 +622,6 @@ void xtensa_translate_init(void); void xtensa_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); -void xtensa_breakpoint_handler(CPUState *cs, CPUBreakpoint *hit); void xtensa_register_core(XtensaConfigList *node); void xtensa_sim_open_console(Chardev *chr); void check_interrupts(CPUXtensaState *s); diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 2015a4e3d0..eb6758b694 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -316,7 +316,6 @@ static const TCGCPUOps xtensa_tcg_ops =3D { =20 .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, - .debug_excp_handler =3D xtensa_breakpoint_handler, .get_tb_cpu_state =3D xtensa_get_tb_cpu_state, .restore_state_to_opc =3D xtensa_restore_state_to_opc, .mmu_index =3D xtensa_cpu_mmu_index, @@ -331,6 +330,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, .debug_check_breakpoint =3D xtensa_debug_check_breakpoint, + .debug_excp_handler =3D xtensa_breakpoint_handler, #endif /* !CONFIG_USER_ONLY */ }; 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Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 +- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 119a0b8187..928d300772 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -592,7 +592,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, vaddr addr, MemTxResult response, uintptr_t reta= ddr); hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); bool xtensa_debug_check_breakpoint(CPUState *cs, CPUBreakpoint *bp); -void xtensa_breakpoint_handler(CPUState *cs, CPUBreakpoint *hit); +void xtensa_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit); #endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void xtensa_count_regs(const XtensaConfig *config, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index eb6758b694..82b7493ff4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -330,7 +330,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, .debug_check_breakpoint =3D xtensa_debug_check_breakpoint, - .debug_excp_handler =3D xtensa_breakpoint_handler, + .debug_excp_handler =3D xtensa_cpu_debug_excp_handler, #endif /* !CONFIG_USER_ONLY */ }; =20 diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index aa012068de..7643e97b2c 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -220,7 +220,7 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *en= v) return 0; } =20 -void xtensa_breakpoint_handler(CPUState *cs, CPUBreakpoint *hit) +void xtensa_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { CPUXtensaState *env =3D cpu_env(cs); =20 --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226676; cv=none; d=zohomail.com; s=zohoarc; b=ewwPGHHwayP6jSteh5p1hcyyMA5iNpJqJAM0lLNLHltmnfijfrsG+MBZKlzLDQkIENRKOn+CusFKmJuB4Tcceary25U1q+5BFZOXeWKEKDPKrVhQin4p/UokvDGDReh3VHw7l4iFjoMGkM0E7s/ICSLpzFejZkNvTv9HQudfNtQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226676; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9Z8VyrlNOS3AtUzlV7fFAEANc3KY/TwCjUicBVUQopA=; b=nPlUPYHogtHXmfWtCi6KVbK0MNJFJCyURNGjb3FEfUUsM9sY+scYjsnV4ttxqxsJDLVPVUo6oSbBnOPLZnaqTjQPHmmvVwNadCziT9sFulS3FRwzr2NeviKTqEw9DfHyQwmvBOZD+DdRZaVBiUdOnCNNhHD3JHldKJFnbCQ8/nY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226676550998.8116345435282; Sat, 4 Jul 2026 21:44:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEfK-0003wl-9o; Sun, 05 Jul 2026 00:41:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEfH-0003nq-9u for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:11 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEfD-0006OR-W4 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:11 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-845e363246aso2027639b3a.1 for ; Sat, 04 Jul 2026 21:41:07 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-847f6952a0dsm1952615b3a.0.2026.07.04.21.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:41:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226466; x=1783831266; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Z8VyrlNOS3AtUzlV7fFAEANc3KY/TwCjUicBVUQopA=; b=ppNF5PuNpbI8QeSD5r/vRERadsbJnmQ++YpSiaeFHTizbfigZHQqXX8Hd58KeWME/Y xOSshh9Vx6GktctbktWSbk8Nra8NvqHRqZwVQdOzwN8gLwoXnGQWMy8hE0Qf5CIPyOHB dZrzsCAVabaYYmqMxW8KmdXjYK07X4X9OKiEu9NqPMiCByWSz8Q7F86cE+O3y/XKX6zY SQXQk98XZms5UaSIF9qZaDTjLs8F12vPKkAPnNsPOMziO2e0SZRLcMP703IfiAzHWvII zJynTZN1R6a7i+hgod6z1ZBIyg0YjkTJh9NX3YWMlQOt3l5BB/Fnu3iv4/vnGeAO3kW8 A0QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226466; x=1783831266; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=9Z8VyrlNOS3AtUzlV7fFAEANc3KY/TwCjUicBVUQopA=; b=aBG24HaxlCYhh6vu3Y+VsSLnK4J/KBOftwKXbPfQXSRSLSbiEqmyKFVxj8ivQQJzG0 GbOh0XnffppxsNXVi01PF/KtHs8px8QHC61fg0PUbSB8lqF4exjRqWB8hLaWAUPoWNQs IFjQYuvP3Y7lxYmkSiSITOVK44vRvKoyR4N2+fkWC694X47tr/4yioiOHC8e6FJwlHBh zY71DjKHepTTbDdWhS5qVeVUXxOCRXYhxRwSEgfwvm4AHWmKZV1vmYnDLKkX83Bysk5a y3sBI0+XwqFyyIeiL0rJ+o7L695fUDOwOoYeoO+UkPYePz4taWH2uWqXEDqi+RZqiFBM UsOw== X-Gm-Message-State: AOJu0Yyq7crEf2OZpG3qkMvYkU77+pVQ/s1Z96pVZWtkD0FQpXTZDehn IMkz4m6KRGPHxBDwu/wOnB49gm8utB6dnpcRQaaYZaMQyeRyfN4Id7JPcqPdZSskHVaovyCybO6 Ql24Y X-Gm-Gg: AfdE7cm11KhTQo8wxtEKRo57QUheaKit007J4f0UCMwvyQQJ/v/PUZZc5CrEIPU6C3f y6iPdPrs5qUWyV5j6Yb0S8QJQMmimwtsE6ZEug+AX1ebdCdYaTgn7Y9VR8Lxr+yMljiee0C5jI/ AWnpQF5T+XjEEs7KpSiZ/HrfTMmJTBkOnKx70WMSbhRV7EbT1cRnf0oQ68FtWMCrOGwlYdl2Lpf HAzAm2EntTfXkKHGdmEujL22v8BrGPxZVdxmJLDcOa8t7WhUCKTTiVwnlPdJIGA33ueIS4vbgIp SVmSyZTeTHJtfWXfaHF3+iLluIqwXFYdGxdP0+7aS+Ul2+eMcnBTdsHsYQH7RDX8p1Ttj6VctcM Wy3vZmVAdZ0Gkk+pUvWb5gorCQDYROotp4sQ2oiFoH0IM6BjAGOWoDjK5yFEOa2Po+SpSNoLxay JorwByrJFjMm1q6Sp2zLf4OuBRwIJuu+6ntftbcTg8AuIHX6o= X-Received: by 2002:a05:6a00:2d99:b0:847:871a:94ca with SMTP id d2e1a72fcca58-847f6f3d63cmr4784193b3a.41.1783226466338; Sat, 04 Jul 2026 21:41:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 44/46] target/xtensa: Simplify xtensa_cpu_debug_excp_handler Date: Sat, 4 Jul 2026 21:37:23 -0700 Message-ID: <20260705043725.1373137-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226677800158501 Content-Type: text/plain; charset="utf-8" No longer need to check BP_CPU. Use hit->id instead of a search over ndbreak. Unify the raising of the exception. Signed-off-by: Richard Henderson --- target/xtensa/helper.c | 41 ++++++++++------------------------------- 1 file changed, 10 insertions(+), 31 deletions(-) diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 7643e97b2c..f66d0bff04 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -207,47 +207,26 @@ void xtensa_register_core(XtensaConfigList *node) } =20 #ifndef CONFIG_USER_ONLY -static uint32_t check_hw_breakpoints(CPUXtensaState *env) -{ - unsigned i; - - for (i =3D 0; i < env->config->ndbreak; ++i) { - if (env->cpu_watchpoint[i] && - env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) { - return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT); - } - } - return 0; -} - void xtensa_cpu_debug_excp_handler(CPUState *cs, CPUBreakpoint *hit) { CPUXtensaState *env =3D cpu_env(cs); + uint32_t cause; =20 - if (cs->watchpoint_hit) { - if (cs->watchpoint_hit->flags & BP_CPU) { - uint32_t cause; - - cs->watchpoint_hit =3D NULL; - cause =3D check_hw_breakpoints(env); - if (cause) { - debug_exception_env(env, cause); - } - cpu_loop_exit_noexc(cs); - } + if (hit->flags & BP_MEM_ACCESS) { + /* watchpoint */ + cause =3D DEBUGCAUSE_DB | (hit->id << DEBUGCAUSE_DBNUM_SHIFT); } else { - if (cpu_breakpoint_test(cs, env->pc, BP_GDB) - || !cpu_breakpoint_test(cs, env->pc, BP_CPU)) { - return; - } + /* breakpoint */ if (env->sregs[ICOUNT] =3D=3D 0xffffffff && xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - debug_exception_env(env, DEBUGCAUSE_IC); + cause =3D DEBUGCAUSE_IC; } else { - debug_exception_env(env, DEBUGCAUSE_IB); + cause =3D DEBUGCAUSE_IB; } - cpu_loop_exit_noexc(cs); } + + debug_exception_env(env, cause); + cpu_loop_exit_noexc(cs); } =20 void xtensa_cpu_do_unaligned_access(CPUState *cs, --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226546; cv=none; d=zohomail.com; s=zohoarc; b=PmbuQchrOnTV6O3sqQ5Oqd7GB6XrTJSXgqVA9S6K5k7Lb2LsyR0oRug6t00st71lEVNStP4ueKUU4qsJN9EfdDiUKOfOemSBiGAkhXPiHbnEkGRv/lPT7EVHBk4THvm5kLP9eIMUugvZXeQnF3JqIHcoFTnIEvJUIzLm8nyhtCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226546; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NSQn5AB1CNws1Obey85q6NalNpdc96132v00m/ICH9U=; b=NGCw4PZJeFpLpSwCph1SkqB4+OBOJkJ5kHHRJ5gmzmHbo8LFcKyU4BAecWHCkIVk4UrOlSrG5NWesJj9WX+g3GWM0tmzkTycn+YBtqvXbu4zLOWFE0uX/WbJf2wkSyctFYIlIyjsfaiqcXn+b/pWbZj9FPnHyT96g/bGGWn2tCM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226546963154.17895431481554; Sat, 4 Jul 2026 21:42:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEfM-00042A-HU; Sun, 05 Jul 2026 00:41:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEfI-0003sH-Gn for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:12 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEfE-0006Ox-Iy for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:12 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-84592b55832so1646694b3a.3 for ; Sat, 04 Jul 2026 21:41:08 -0700 (PDT) Received: from stoup.. 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This avoids a loop over all watchpoints. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 23 ++++------------------- gdbstub/system.c | 2 ++ 2 files changed, 6 insertions(+), 19 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index bda6dd9e46..c1e4cdbc19 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -685,27 +685,12 @@ static inline bool cpu_handle_halt(CPUState *cpu) =20 static inline void cpu_handle_debug_exception(CPUState *cpu) { - CPUBreakpoint *hit =3D cpu->watchpoint_hit; + CPUBreakpoint *hit =3D cpu->watchpoint_hit ? : cpu->breakpoint_hit; =20 - if (hit) { - IntervalTreeNode *n; - - for (n =3D interval_tree_iter_first(&cpu->watchpoints, 0, -1); n; - n =3D interval_tree_iter_next(n, 0, -1)) { - CPUBreakpoint *wp =3D container_of(n, CPUBreakpoint, itree); - if (wp !=3D hit) { - wp->flags &=3D ~BP_WATCHPOINT_HIT; - } - } - } else { - hit =3D cpu->breakpoint_hit; - if (!hit) { - return; - } - } - - if (hit->flags & BP_CPU) { + if (hit && hit->flags & BP_CPU) { cpu->cc->tcg_ops->debug_excp_handler(cpu, hit); + + hit->flags &=3D ~BP_WATCHPOINT_HIT; cpu->watchpoint_hit =3D NULL; cpu->breakpoint_hit =3D NULL; } diff --git a/gdbstub/system.c b/gdbstub/system.c index 017585187f..cbb72be33b 100644 --- a/gdbstub/system.c +++ b/gdbstub/system.c @@ -169,6 +169,8 @@ static void gdb_vm_state_change(void *opaque, bool runn= ing, RunState state) g_string_printf(buf, "T%02xthread:%s;%swatch:%" VADDR_PRIx ";", GDB_SIGNAL_TRAP, tid->str, type, cpu->watchpoint_hit->hitaddr); + + cpu->watchpoint_hit->flags &=3D ~BP_WATCHPOINT_HIT; cpu->watchpoint_hit =3D NULL; goto send_packet; } else { --=20 2.43.0 From nobody Sun Jul 26 11:03:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1783226889; cv=none; d=zohomail.com; s=zohoarc; b=CgtuWt5BQK5Img0IHXpAHnKb3yA2KdtkimTTroDuawrv6Ww777CtiWVipFxaoaRRAYG6ZIVOtd2h09RlZuFDCkGyovzqQjbhxnLyD+ZTMC+uacRmpcISDbUZSrtRErmLYjN81VLl9okmz4mKo+KgVgZG84QSEUyknV/Y1sj8Uz0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783226889; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gI8TJyVj//txxRRFeEfE8QbpaSNpGX4bw5i0vl11MXk=; b=jYcdY/s3EfVxoW0HBGgumbaw4vk/6avbcpummeoU7/DaSWmK4tKpG+lddPXRCJ2MptPxiZVeUxwIMHNkblQVR6QpEUXMFTuyzWC2IYLvi12MtxOUO//o603X+81IV20SFUONg3Z7SKRjwcokBBvMolOwdb1GIVZyebYB36vy26k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1783226889253444.83794080503856; Sat, 4 Jul 2026 21:48:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wgEfL-00040m-Qi; Sun, 05 Jul 2026 00:41:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wgEfJ-0003v9-H1 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:13 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wgEfF-0006PW-88 for qemu-devel@nongnu.org; Sun, 05 Jul 2026 00:41:13 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-84592b55832so1646703b3a.3 for ; Sat, 04 Jul 2026 21:41:08 -0700 (PDT) Received: from stoup.. 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[71.212.39.188]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-847f6952a0dsm1952615b3a.0.2026.07.04.21.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 21:41:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1783226468; x=1783831268; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gI8TJyVj//txxRRFeEfE8QbpaSNpGX4bw5i0vl11MXk=; b=l/mcXxbViPdpyYG2Z442l0785fzu/Kg/8sys0O6nEyqVk2SZAjUQEXE/ITolPTW0tu TGi35J0lBrkdYACkCA723cq5NyfOjRMXR5p+uOPaAX56IWS2Yw8vzS+K2q8jKajJ8zAU AaWgSEi7KpFN1XafV6dwotQxYiPdRICn4a7uyWVbwUaL2TXBH/dbfQmjoLkfjKXxlKNr TUKBJa3YuO9gTi5Cz4oWlzRfOfPrZ3WikKqMPcev6haAKUMlIUqMETwpD7GqikDG1a3y BhQjqc2EMWXgzy97ZpJHBMu6BLFRRjh/l0ckH284L/URuDx84sF2tMdhzFhzrOdLpAq+ JE0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783226468; x=1783831268; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=gI8TJyVj//txxRRFeEfE8QbpaSNpGX4bw5i0vl11MXk=; b=q30WntbGEdyruu/9g8w2m4roWJEOUDkHAcf7vK6/Vh7sWMHgn2gqx5Aawt7ff2/VKu hudkAfmnEMZwga2ttEd7uEdhV7ja9bCp7QKQUw72Rbc9eSOT477jaL+R1Tm2yt/++WNz CStTg/6KWW//s9YNQUf57XSFQUTOdVfvf5GoAVnAazS7woe+ZxpqbUWkC/vMnwT0zKOf B3AF7YUsq/WET3yoeT81Rp51UeB4H4lSKrdCUFmpy5ZYjggRvFYYrGcyJyPxFPIZYu7c xuENfC3C+krMkAegwLUlKVg49VeCB95xrtMk6nD0LQNl4XlFmVUkjvW8sOUXXV1wUoMk JDaQ== X-Gm-Message-State: AOJu0Ywk8Nt/UVryBVurVdNsbFMyGrxQcLqOw5Rt7up6hEeiAMw130eh wlaMvabdw8g6QYegRRb8zv3bJpBq/gK4NinTFOIDwqEdCRIeQck7Nj/wdJpLjUYa+YUG5XsdzYC hktiG X-Gm-Gg: AfdE7cnhUP2UpEFsFSQRUP9Wybpja4G/YOjALMoQS/XGkE6CvnKdvIspYc+2lNEe8f8 Vi3m8G9VBtVb2r7hIa8GJlZB2RtDLvJsiEZZ07/tOg21LgT0zuIEMQOV+arKQn6IEuvuux1Ke9w 9vmPJ13jyRQ+MtwYBr42Be5a2bIV9dRZ7/M+Vza0ZMFoGTmzrjLrXew+rlHbY1YWy7rle6RhZIi nOVktNnU3snNWcjTDc6319N3StrUTsOWAMFjWaR0HzvvLMyrsMV8lK5UY18RANq1h/5G0EF/tUi CTYunPeTaxHjykN1yPhgKlK1k5BF1hLeP1V8gUNKyq7QcVBhEAQk0eNeORuiYklC61SpZ9kl4OT 7DK0jurBh1iIMauR6Ep/vCCENqdKxct/RXg3peihq8TGbmAj5CV0nfSF9v1fSWn+q7y9Yy7T1FQ wuR/hWCAag1vMOn/i0ycBmJ3z1sYFxThI6PNrxnibeaGAY3fs= X-Received: by 2002:a05:6a00:2914:b0:847:8f8a:a055 with SMTP id d2e1a72fcca58-847f6dd6d35mr5137805b3a.17.1783226467780; Sat, 04 Jul 2026 21:41:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, philmd@oss.qualcomm.com Subject: [PATCH v2 46/46] accel/tcg: Merge CPUState.{break,watch}point_hit Date: Sat, 4 Jul 2026 21:37:25 -0700 Message-ID: <20260705043725.1373137-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260705043725.1373137-1-richard.henderson@linaro.org> References: <20260705043725.1373137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1783226890404158500 Content-Type: text/plain; charset="utf-8" Merge and name bp_wp_hit. Now that all targets have been converted to use debug_excp_handler hit argument, we only need one pointer to an outstanding debug event. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +-- accel/tcg/cpu-exec.c | 7 +++--- accel/tcg/watchpoint.c | 4 ++-- gdbstub/system.c | 51 ++++++++++++++++++++++-------------------- target/arm/hvf/hvf.c | 5 ++--- target/arm/kvm.c | 2 +- target/i386/kvm/kvm.c | 4 ++-- target/ppc/kvm.c | 2 +- target/s390x/kvm/kvm.c | 2 +- 9 files changed, 40 insertions(+), 40 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index dc1c634258..34f2850879 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -526,8 +526,7 @@ struct CPUState { /* ice debug support */ IntervalTreeRoot breakpoints; IntervalTreeRoot watchpoints; - CPUBreakpoint *breakpoint_hit; - CPUBreakpoint *watchpoint_hit; + CPUBreakpoint *bp_wp_hit; =20 void *opaque; =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c1e4cdbc19..f1dc130bfa 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -366,7 +366,7 @@ static bool check_for_breakpoints_slow(CPUState *cpu, v= addr pc, bp->hitaddr =3D pc; bp->hitlast =3D pc; bp->hitattrs =3D MEMTXATTRS_UNSPECIFIED; - cpu->breakpoint_hit =3D bp; + cpu->bp_wp_hit =3D bp; cpu->exception_index =3D EXCP_DEBUG; return true; } @@ -685,14 +685,13 @@ static inline bool cpu_handle_halt(CPUState *cpu) =20 static inline void cpu_handle_debug_exception(CPUState *cpu) { - CPUBreakpoint *hit =3D cpu->watchpoint_hit ? : cpu->breakpoint_hit; + CPUBreakpoint *hit =3D cpu->bp_wp_hit; =20 if (hit && hit->flags & BP_CPU) { cpu->cc->tcg_ops->debug_excp_handler(cpu, hit); =20 hit->flags &=3D ~BP_WATCHPOINT_HIT; - cpu->watchpoint_hit =3D NULL; - cpu->breakpoint_hit =3D NULL; + cpu->bp_wp_hit =3D NULL; } } =20 diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index bf4c46c393..f96ffc018d 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -56,7 +56,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vadd= r len, bool have_cpu_wp =3D false; =20 assert(tcg_enabled()); - if (cpu->watchpoint_hit) { + if (cpu->bp_wp_hit) { /* * We re-entered the check after replacing the TB. * Now raise the debug interrupt so that it will @@ -146,7 +146,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, return; } =20 - cpu->watchpoint_hit =3D found_wp; + cpu->bp_wp_hit =3D found_wp; =20 /* This call also restores vCPU state */ tb_check_watchpoint(cpu, ra); diff --git a/gdbstub/system.c b/gdbstub/system.c index cbb72be33b..f7d6df5e77 100644 --- a/gdbstub/system.c +++ b/gdbstub/system.c @@ -126,7 +126,6 @@ static void gdb_vm_state_change(void *opaque, bool runn= ing, RunState state) CPUState *cpu =3D gdbserver_state.c_cpu; g_autoptr(GString) buf =3D g_string_new(NULL); g_autoptr(GString) tid =3D g_string_new(NULL); - const char *type; int ret; =20 if (running || gdbserver_state.state =3D=3D RS_INACTIVE) { @@ -151,32 +150,36 @@ static void gdb_vm_state_change(void *opaque, bool ru= nning, RunState state) =20 switch (state) { case RUN_STATE_DEBUG: - if (cpu->watchpoint_hit) { - switch (cpu->watchpoint_hit->flags & BP_MEM_ACCESS) { - case BP_MEM_READ: - type =3D "r"; - break; - case BP_MEM_ACCESS: - type =3D "a"; - break; - default: - type =3D ""; - break; - } - trace_gdbstub_hit_watchpoint(type, - gdb_get_cpu_index(cpu), - cpu->watchpoint_hit->hitaddr); - g_string_printf(buf, "T%02xthread:%s;%swatch:%" VADDR_PRIx ";", - GDB_SIGNAL_TRAP, tid->str, type, - cpu->watchpoint_hit->hitaddr); + { + CPUBreakpoint *hit =3D cpu->bp_wp_hit; =20 - cpu->watchpoint_hit->flags &=3D ~BP_WATCHPOINT_HIT; - cpu->watchpoint_hit =3D NULL; - goto send_packet; - } else { + if (hit) { + unsigned watch =3D hit->flags & BP_MEM_ACCESS; + + hit->flags &=3D ~BP_WATCHPOINT_HIT; + cpu->bp_wp_hit =3D NULL; + + if (watch) { + static const char hit_type[4][2] =3D { + [BP_MEM_READ] =3D "r", + [BP_MEM_WRITE] =3D "", + [BP_MEM_ACCESS] =3D "a", + }; + const char *type =3D hit_type[watch]; + + trace_gdbstub_hit_watchpoint(type, gdb_get_cpu_index(c= pu), + hit->hitaddr); + g_string_printf(buf, "T%02xthread:%s;%swatch:%" + VADDR_PRIx ";", + GDB_SIGNAL_TRAP, tid->str, type, + hit->hitaddr); + goto send_packet; + } + /* else breakpoint */ + } trace_gdbstub_hit_break(); + ret =3D GDB_SIGNAL_TRAP; } - ret =3D GDB_SIGNAL_TRAP; break; case RUN_STATE_PAUSED: trace_gdbstub_hit_paused(); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 48c2a02bfb..10d707a452 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -2372,13 +2372,12 @@ static int hvf_handle_exception(CPUState *cpu, hv_v= cpu_exit_exception_t *excp) =20 cpu_synchronize_state(cpu); =20 - CPUBreakpoint *wp =3D - find_hw_watchpoint(cpu, excp->virtual_address); + CPUBreakpoint *wp =3D find_hw_watchpoint(cpu, excp->virtual_addres= s); if (!wp) { error_report("EXCP_DEBUG but unknown hw watchpoint"); } wp->hitaddr =3D excp->virtual_address; - cpu->watchpoint_hit =3D wp; + cpu->bp_wp_hit =3D wp; break; } case EC_DATAABORT: { diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7670041423..20c9631ccb 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1520,7 +1520,7 @@ static bool kvm_arm_handle_debug(ARMCPU *cpu, CPUBreakpoint *wp =3D find_hw_watchpoint(cs, debug_exit->far); if (wp) { wp->hitaddr =3D debug_exit->far; - cs->watchpoint_hit =3D wp; + cs->bp_wp_hit =3D wp; return true; } break; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 3cc941cf00..c7a326e560 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -6261,13 +6261,13 @@ static int kvm_handle_debug(X86CPU *cpu, break; case 0x1: ret =3D EXCP_DEBUG; - cs->watchpoint_hit =3D &hw_watchpoint; + cs->bp_wp_hit =3D &hw_watchpoint; hw_watchpoint.hitaddr =3D hw_breakpoint[n].addr; hw_watchpoint.flags =3D BP_MEM_WRITE; break; case 0x3: ret =3D EXCP_DEBUG; - cs->watchpoint_hit =3D &hw_watchpoint; + cs->bp_wp_hit =3D &hw_watchpoint; hw_watchpoint.hitaddr =3D hw_breakpoint[n].addr; hw_watchpoint.flags =3D BP_MEM_ACCESS; break; diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 8f9c16fcef..0050bd7648 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1590,7 +1590,7 @@ static int kvm_handle_hw_breakpoint(CPUState *cs, n =3D find_hw_watchpoint(arch_info->address, &flag); if (n >=3D 0) { handle =3D DEBUG_RETURN_GDB; - cs->watchpoint_hit =3D &hw_watchpoint; + cs->bp_wp_hit =3D &hw_watchpoint; hw_watchpoint.hitaddr =3D arch_info->address; hw_watchpoint.flags =3D flag; } diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index aff4d26096..8c56074304 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -1861,7 +1861,7 @@ static int kvm_arch_handle_debug_exit(S390CPU *cpu) switch (arch_info->type) { case KVM_HW_WP_WRITE: if (find_hw_breakpoint(arch_info->addr, -1, arch_info->type)) { - cs->watchpoint_hit =3D &hw_watchpoint; + cs->bp_wp_hit =3D &hw_watchpoint; hw_watchpoint.hitaddr =3D arch_info->addr; hw_watchpoint.flags =3D BP_MEM_WRITE; ret =3D EXCP_DEBUG; --=20 2.43.0