From nobody Sun Jul 26 11:06:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1782870751; cv=none; d=zohomail.com; s=zohoarc; b=UFZ9zuMpmU4Kooog3J8TOjff3IrUqygrkxpJh69uvOQkM/jYdVvls1zeDAwN8EaDOj+17Iem+ZiyVVRBvTxvDvP4XLZfnfzquHfuhNvoG2zPkVL/vn3ab9tQOoH4T6SDgIQ6McVVNUY/dj/k3HOxeBzEbu5lxMamvdUwUph9PaE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782870751; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cFVSdKRxBxbWRYZb04r06GB3+hYX03AMc5Cn5Wd3z24=; b=QpBWzRPZDAOfiax7NQp8SgiCths0h9vqIL+RTZx9OSNO90Msm9kt+iw038xpUvgCxbMANsHbR/ZlKcVZhCOfNh+FbIINfmbZ+fr1WyxAg+EJVooL64vZ8H/XenGWuWit0DgK+Lxa22Y0PBhPueYE+/Ey/6e5JSSd6ZMz+4BOoIQ= ARC-Authentication-Results: i=1; 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Wed, 01 Jul 2026 09:51:45 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1782870706; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To; bh=cFVSdKRxBxbWRYZb04r06GB3+hYX03AMc5Cn5Wd3z24=; b=XIZqtS0Ma4MHwm68Jinvy00c3q/w9+O/p06OjNaAmZIDu4WyU1Yp6QJXrgIqkK/WTOJi38s+ZkHgbykEKapL2FXS6iHddjG5X2xwe5ftV95YMIvK8viEnYbAFlAp2ZCgi96uYh2QrYcPDmcMIW8bG+lgIMvJqsWwOlhX21XcLng= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R161e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045098064; MF=lyndra@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0X61Frsz_1782870705; From: TANG Tiancheng Date: Wed, 01 Jul 2026 09:51:31 +0800 Subject: [PATCH v2 1/5] disas/riscv: Fix th.srri decoding MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-b4-disas-xthead-fix-riscv-next-v2-1-e6e4ff5a7847@linux.alibaba.com> References: <20260701-b4-disas-xthead-fix-riscv-next-v2-0-e6e4ff5a7847@linux.alibaba.com> In-Reply-To: <20260701-b4-disas-xthead-fix-riscv-next-v2-0-e6e4ff5a7847@linux.alibaba.com> To: qemu-devel@nongnu.org Cc: Christoph Muellner , LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza , Richard Henderson , qemu-riscv@nongnu.org, TANG Tiancheng X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782870704; l=1506; i=lyndra@linux.alibaba.com; s=20250909; h=from:subject:message-id; bh=m/WPwWNlaTg0Hlf4CSq6Gcr7JvCTsC5AbG3EU9dKV6w=; b=JOl9TldfeuhQWS2DbMG2TUx0isP4efkMSQcw9tVYpv1CqJ8rWrt9lKGUzioLcaItXLK4GbqLL gZYqUmrs6avBEvKsqCmnM9woSOvSSy9INJMNJTZCbuAScQCoFuogalu X-Developer-Key: i=lyndra@linux.alibaba.com; a=ed25519; pk=GQh4uOSLVucXGkaZfEuQ956CrYS14cn1TA3N8AiIjBw= X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.119 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.30.119; envelope-from=lyndra@linux.alibaba.com; helo=out30-119.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1782870754200158500 target/riscv/xthead.decode defines th.srri as funct6=3D000100 in bits 31:26, with the 6-bit immediate in bits 25:20. decode_xtheadbb() switches on bits 31:25, i.e. funct6 plus imm[5]. Therefore valid th.srri encodings are 0001000 and 0001001. The current 0000100 and 0000101 cases use the wrong funct6 value and decode valid th.srri instructions as illegal. Fix the cases to match funct6=3D000100 with both imm[5] values. Fixes: 318df7238b9f ("disas/riscv: Add support for XThead* instructions") Signed-off-by: TANG Tiancheng Reviewed-by: LIU Zhiwei Reviewed-by: Daniel Henrique Barboza --- disas/riscv-xthead.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c index fcca326d1c398a6745984b9f5d90fc5f7d54dfd9..2f2ddb8dd9a13e17a28539b4179= cd10fa93c5941 100644 --- a/disas/riscv-xthead.c +++ b/disas/riscv-xthead.c @@ -315,8 +315,10 @@ void decode_xtheadbb(rv_decode *dec, rv_isa isa) op =3D rv_op_th_revw; } break; - case 0b0000100: - case 0b0000101: op =3D rv_op_th_srri; break; + case 0b0001000: + case 0b0001001: + op =3D rv_op_th_srri; + break; } break; case 2: op =3D rv_op_th_ext; break; --=20 2.43.0 From nobody Sun Jul 26 11:06:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782870761282435.4909553473399; Tue, 30 Jun 2026 18:52:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wek7g-0003AI-Ee; Tue, 30 Jun 2026 21:52:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wek7d-00037c-GN; Tue, 30 Jun 2026 21:52:17 -0400 Received: from [115.124.30.101] (helo=out30-101.freemail.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wek7U-0004aH-He; Tue, 30 Jun 2026 21:52:17 -0400 Received: from ea134-sw06.eng.xrvm.cn(mailfrom:lyndra@linux.alibaba.com fp:SMTPD_---0X61FrtD_1782870705 cluster:ay36) by smtp.aliyun-inc.com; Wed, 01 Jul 2026 09:51:46 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1782870707; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To; bh=jtbdk5iG5WqPu5oOXDmCOt9/eRNGNPDbyea6/KJsfeE=; b=G0L5Ar5vITXgMlVGPVXJWz2FhyUY4vasI2c+jbFixnEUhkZZfQhBAToQD2cISQqIV1jLFcewf3cx0ilG3S9ZCRu1512xMgaUuUXIcWKEgvvMgA6mSzv693RhRBtxTRac3uCy3EYgHqdXTn6wJ9ggAqIhhAzXY4nbpV4hFbK11cE= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R131e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam011083073210; MF=lyndra@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0X61FrtD_1782870705; From: TANG Tiancheng Date: Wed, 01 Jul 2026 09:51:32 +0800 Subject: [PATCH v2 2/5] disas/riscv: Fix 6-bit immediate extraction MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-b4-disas-xthead-fix-riscv-next-v2-2-e6e4ff5a7847@linux.alibaba.com> References: <20260701-b4-disas-xthead-fix-riscv-next-v2-0-e6e4ff5a7847@linux.alibaba.com> In-Reply-To: <20260701-b4-disas-xthead-fix-riscv-next-v2-0-e6e4ff5a7847@linux.alibaba.com> To: qemu-devel@nongnu.org Cc: Christoph Muellner , LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza , Richard Henderson , qemu-riscv@nongnu.org, TANG Tiancheng X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782870704; l=1154; i=lyndra@linux.alibaba.com; s=20250909; h=from:subject:message-id; bh=fECxabHVg6J3QPrge6wP3Wo05THZjnLRqrtTjO6bXmk=; b=eYJ1vf/j5dWhHlJpGfhKNiCvroeN2VJ806O1TJj0OgeBPBX6GGgO/YNssP4OZAQKfCfNbTmPT EfJYe1GhRPTAc9PdZKH/ZScEF+5cKTGxbuSIw07Pim91I7PeSTLPJqh X-Developer-Key: i=lyndra@linux.alibaba.com; a=ed25519; pk=GQh4uOSLVucXGkaZfEuQ956CrYS14cn1TA3N8AiIjBw= X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.101 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.30.101; envelope-from=lyndra@linux.alibaba.com; helo=out30-101.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1782870762203158500 rv_codec_r2_imm6 is used for XThead instructions whose 6-bit immediate field is encoded in bits 25:20. The old expression left-shifted by 38 and then right-shifted by 60, so it kept only bits 25:22. Shift right by 58 instead, keeping the existing extraction style while retaining the full bits 25:20 field. This fixes the immediate printed for th.srri and th.tst. Fixes: 318df7238b9f ("disas/riscv: Add support for XThead* instructions") Signed-off-by: TANG Tiancheng Reviewed-by: LIU Zhiwei Reviewed-by: Daniel Henrique Barboza --- disas/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 7f1b26277378c225c963d8f435cc7a2fc6e4a0b8..400a57083f90be18ccd12415797= bce0df974784b 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -4546,7 +4546,7 @@ static uint32_t operand_zcmp_rlist(rv_inst inst) =20 static uint32_t operand_imm6(rv_inst inst) { - return (inst << 38) >> 60; + return (inst << 38) >> 58; } =20 static uint32_t operand_imm2(rv_inst inst) --=20 2.43.0 From nobody Sun Jul 26 11:06:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1782870707; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To; bh=SXjVdCGN0cA5Jj+IrBWQWgnMneXp9emPga8+CP/p0a4=; b=JuoaoB/cQhryem1PHKKIQZ6qItrDkc/Skr05D9DYrr6+u1l0DjWwGL13AtA7XLjqVNTBkiimDKAmJ28ZGmNRP+Zi9DT0Aq32RVamDFDQOxL/CLtvXNOhoW7UiEyLtYmjcdnkF7nsrtJOO7Cf4KakcPJYEHsufOrLai5bp7bpqJ8= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R481e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037026112; MF=lyndra@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0X61FrtT_1782870706; From: TANG Tiancheng Date: Wed, 01 Jul 2026 09:51:33 +0800 Subject: [PATCH v2 3/5] disas/riscv: Use signed type for vector immediates MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-b4-disas-xthead-fix-riscv-next-v2-3-e6e4ff5a7847@linux.alibaba.com> References: <20260701-b4-disas-xthead-fix-riscv-next-v2-0-e6e4ff5a7847@linux.alibaba.com> In-Reply-To: <20260701-b4-disas-xthead-fix-riscv-next-v2-0-e6e4ff5a7847@linux.alibaba.com> To: qemu-devel@nongnu.org Cc: Christoph Muellner , LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza , Richard Henderson , qemu-riscv@nongnu.org, TANG Tiancheng X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This sends negative immediates through an unsigned type before they are assigned to rv_decode.imm. Return int32_t to match the signed value extracted by the helper. Signed-off-by: TANG Tiancheng Reviewed-by: LIU Zhiwei --- disas/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 400a57083f90be18ccd12415797bce0df974784b..e9dcc173d8fa2f89d85b76595a7= 6931c4dddb462 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -4487,7 +4487,7 @@ static uint32_t operand_cimmq(rv_inst inst) ((inst << 57) >> 62) << 6; } =20 -static uint32_t operand_vimm(rv_inst inst) +static int32_t operand_vimm(rv_inst inst) { return (int64_t)(inst << 44) >> 59; } --=20 2.43.0 From nobody Sun Jul 26 11:06:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1782870745; cv=none; d=zohomail.com; s=zohoarc; b=jobGQu5U/zpn0P0ll8PFR5GmDuvWYvnhj2JDrIIi29CJzb8kd2L+R+psFpyWWhQ0dkIkD8MaSHH2NcT3PY5M30s0hTrnrJxvzJu6kbM/jMO0DNUwDdkDMz/enJceK3JBggKF1ir2KPu2UbOa0tlEs+MU/csm2lPwfQaP+DPuaO8= ARC-Message-Signature: i=1; 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BC=-1|-1; BR=01201311R891e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037026112; MF=lyndra@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0X61Frtn_1782870706; From: TANG Tiancheng Date: Wed, 01 Jul 2026 09:51:34 +0800 Subject: [PATCH v2 4/5] disas/riscv: Decode unsigned vector immediates as unsigned MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-b4-disas-xthead-fix-riscv-next-v2-4-e6e4ff5a7847@linux.alibaba.com> References: <20260701-b4-disas-xthead-fix-riscv-next-v2-0-e6e4ff5a7847@linux.alibaba.com> In-Reply-To: <20260701-b4-disas-xthead-fix-riscv-next-v2-0-e6e4ff5a7847@linux.alibaba.com> To: qemu-devel@nongnu.org Cc: Christoph Muellner , LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza , Richard Henderson , qemu-riscv@nongnu.org, TANG Tiancheng X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782870704; l=9235; i=lyndra@linux.alibaba.com; s=20250909; h=from:subject:message-id; bh=tImFSjPmU33K6q3EkmJwGTaBYcGu4Ak+aNy0XMBBkqg=; b=npeV81SzyREjx1q0bGtMvKXzrNeMNcMUej2PTC5bjh//TC9DuhYZiQqYGZd/07ZtqR+5Ic3V1 tQfb1Q09QRGAL3+zb4gx7O6k2JvUqA0TJKWQBbmLaZoc1uuG4AWU+xp X-Developer-Key: i=lyndra@linux.alibaba.com; a=ed25519; pk=GQh4uOSLVucXGkaZfEuQ956CrYS14cn1TA3N8AiIjBw= X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.124 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.30.124; envelope-from=lyndra@linux.alibaba.com; helo=out30-124.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1782870746525158500 rv_codec_v_i decodes all .vi operands with operand_vimm(), which sign-extends bits 19:15. That matches spec operands named imm, but not the .vi forms whose operand is uimm; uimm=3D31 is decoded as -1 and printed by the shared 6-bit 'u' formatter as 63. Add rv_codec_v_i_u/operand_vuimm() for the 5-bit uimm forms: vsll.vi, vsrl.vi, vsra.vi, vnsrl.wi, vnsra.wi, vssrl.vi, vssra.vi, vnclipu.wi, vnclip.wi, vslideup.vi, vslidedown.vi, vrgather.vi, vaeskf1.vi, vaeskf2.vi, vsm3c.vi, vsm4k.vi and vwsll.vi. The remaining rv_codec_v_i entries are the signed imm forms. Fixes: 07f4964d1785 ("disas/riscv.c: rvv: Add disas support for vector inst= ructions") Fixes: 9d92f56d4a44 ("disas/riscv: Add support for vector crypto extensions= ") Signed-off-by: TANG Tiancheng Reviewed-by: LIU Zhiwei --- disas/riscv.c | 45 ++++++++++++++++++++++++++++----------------- disas/riscv.h | 1 + 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index e9dcc173d8fa2f89d85b76595a76931c4dddb462..4b3f90418f8f17dd3fcb71f70c3= 9607fa293eb0e 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1803,19 +1803,19 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, @@ -1909,16 +1909,16 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, @@ -2048,15 +2048,15 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 }, { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 = }, { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 = }, + { "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, = 0 }, { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 = }, { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0= }, { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 = }, { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, @@ -2144,8 +2144,8 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, - { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, - { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, @@ -2169,14 +2169,14 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, - { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, - { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, - { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, @@ -4492,6 +4492,11 @@ static int32_t operand_vimm(rv_inst inst) return (int64_t)(inst << 44) >> 59; } =20 +static uint32_t operand_vuimm(rv_inst inst) +{ + return extract32(inst, 15, 5); +} + static uint32_t operand_vzimm11(rv_inst inst) { return (inst << 33) >> 53; @@ -4895,6 +4900,12 @@ static void decode_inst_operands(rv_decode *dec, rv_= isa isa) dec->imm =3D operand_vimm(inst); dec->vm =3D operand_vm(inst); break; + case rv_codec_v_i_u: + dec->rd =3D operand_rd(inst); + dec->rs2 =3D operand_rs2(inst); + dec->imm =3D operand_vuimm(inst); + dec->vm =3D operand_vm(inst); + break; case rv_codec_vror_vi: dec->rd =3D operand_rd(inst); dec->rs2 =3D operand_rs2(inst); diff --git a/disas/riscv.h b/disas/riscv.h index 379e642ec84e2da12ffd7905b590cdcee7bf215f..91ada8b531eb9a03bae49d8d36f= c42c497f277ed 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -149,6 +149,7 @@ typedef enum { rv_codec_v_r, rv_codec_v_ldst, rv_codec_v_i, + rv_codec_v_i_u, rv_codec_vsetvli, rv_codec_vsetivli, rv_codec_vror_vi, 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TI=SMTPD_---0X61FruA_1782870707; From: TANG Tiancheng Date: Wed, 01 Jul 2026 09:51:35 +0800 Subject: [PATCH v2 5/5] disas/riscv: Use extract helpers for operand fields MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-b4-disas-xthead-fix-riscv-next-v2-5-e6e4ff5a7847@linux.alibaba.com> References: <20260701-b4-disas-xthead-fix-riscv-next-v2-0-e6e4ff5a7847@linux.alibaba.com> In-Reply-To: <20260701-b4-disas-xthead-fix-riscv-next-v2-0-e6e4ff5a7847@linux.alibaba.com> To: qemu-devel@nongnu.org Cc: Christoph Muellner , LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza , Richard Henderson , qemu-riscv@nongnu.org, TANG Tiancheng X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782870704; l=14108; i=lyndra@linux.alibaba.com; s=20250909; h=from:subject:message-id; bh=jOr9Sdl++43Izfi/yLbK0gqXxWNHt8f8AzRfR5qfi1I=; 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USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1782870752333158500 Replace shift-based operand extraction with extract32() and sextract32(). For split immediates, build the unsigned value from explicit extract32() fields before applying sextract32() where a signed result is needed. The RISC-V disassembler currently follows target/riscv/internals.h: insn_len() and decodes only 16-bit or 32-bit instruction lengths, so the converted fields are all in the low 32 bits of rv_inst. Suggested-by: Richard Henderson Signed-off-by: TANG Tiancheng Reviewed-by: LIU Zhiwei --- disas/riscv.c | 232 +++++++++++++++++++++++++++++++-----------------------= ---- 1 file changed, 124 insertions(+), 108 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 4b3f90418f8f17dd3fcb71f70c39607fa293eb0e..234d45517cb682ce926024d39b5= da4e07d580bd2 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -4202,82 +4202,82 @@ static void decode_inst_opcode(rv_decode *dec, rv_i= sa isa) =20 static uint32_t operand_rd(rv_inst inst) { - return (inst << 52) >> 59; + return extract32(inst, 7, 5); } =20 static uint32_t operand_rs1(rv_inst inst) { - return (inst << 44) >> 59; + return extract32(inst, 15, 5); } =20 static uint32_t operand_rs2(rv_inst inst) { - return (inst << 39) >> 59; + return extract32(inst, 20, 5); } =20 static uint32_t operand_rs3(rv_inst inst) { - return (inst << 32) >> 59; + return extract32(inst, 27, 5); } =20 static uint32_t operand_aq(rv_inst inst) { - return (inst << 37) >> 63; + return extract32(inst, 26, 1); } =20 static uint32_t operand_rl(rv_inst inst) { - return (inst << 38) >> 63; + return extract32(inst, 25, 1); } =20 static uint32_t operand_pred(rv_inst inst) { - return (inst << 36) >> 60; + return extract32(inst, 24, 4); } =20 static uint32_t operand_succ(rv_inst inst) { - return (inst << 40) >> 60; + return extract32(inst, 20, 4); } =20 static uint32_t operand_rm(rv_inst inst) { - return (inst << 49) >> 61; + return extract32(inst, 12, 3); } =20 static uint32_t operand_shamt5(rv_inst inst) { - return (inst << 39) >> 59; + return extract32(inst, 20, 5); } =20 static uint32_t operand_shamt6(rv_inst inst) { - return (inst << 38) >> 58; + return extract32(inst, 20, 6); } =20 static uint32_t operand_shamt7(rv_inst inst) { - return (inst << 37) >> 57; + return extract32(inst, 20, 7); } =20 static uint32_t operand_crdq(rv_inst inst) { - return (inst << 59) >> 61; + return extract32(inst, 2, 3); } =20 static uint32_t operand_crs1q(rv_inst inst) { - return (inst << 54) >> 61; + return extract32(inst, 7, 3); } =20 static uint32_t operand_crs1rdq(rv_inst inst) { - return (inst << 54) >> 61; + return extract32(inst, 7, 3); } =20 static uint32_t operand_crs2q(rv_inst inst) { - return (inst << 59) >> 61; + return extract32(inst, 2, 3); } =20 static uint32_t calculate_xreg(uint32_t sreg) @@ -4287,80 +4287,86 @@ static uint32_t calculate_xreg(uint32_t sreg) =20 static uint32_t operand_sreg1(rv_inst inst) { - return calculate_xreg((inst << 54) >> 61); + return calculate_xreg(extract32(inst, 7, 3)); } =20 static uint32_t operand_sreg2(rv_inst inst) { - return calculate_xreg((inst << 59) >> 61); + return calculate_xreg(extract32(inst, 2, 3)); } =20 static uint32_t operand_crd(rv_inst inst) { - return (inst << 52) >> 59; + return extract32(inst, 7, 5); } =20 static uint32_t operand_crs1(rv_inst inst) { - return (inst << 52) >> 59; + return extract32(inst, 7, 5); } =20 static uint32_t operand_crs1rd(rv_inst inst) { - return (inst << 52) >> 59; + return extract32(inst, 7, 5); } =20 static uint32_t operand_crs2(rv_inst inst) { - return (inst << 57) >> 59; + return extract32(inst, 2, 5); } =20 static uint32_t operand_cimmsh5(rv_inst inst) { - return (inst << 57) >> 59; + return extract32(inst, 2, 5); } =20 static uint32_t operand_csr12(rv_inst inst) { - return (inst << 32) >> 52; + return extract32(inst, 20, 12); } =20 static int32_t operand_imm12(rv_inst inst) { - return ((int64_t)inst << 32) >> 52; + return sextract32(inst, 20, 12); } =20 static int32_t operand_imm20(rv_inst inst) { - return (((int64_t)inst << 32) >> 44) << 12; + return extract32(inst, 12, 20) << 12; } =20 static int32_t operand_jimm20(rv_inst inst) { - return (((int64_t)inst << 32) >> 63) << 20 | - ((inst << 33) >> 54) << 1 | - ((inst << 43) >> 63) << 11 | - ((inst << 44) >> 56) << 12; + uint32_t imm =3D extract32(inst, 31, 1) << 20 | + extract32(inst, 21, 10) << 1 | + extract32(inst, 20, 1) << 11 | + extract32(inst, 12, 8) << 12; + + return sextract32(imm, 0, 21); } =20 static int32_t operand_simm12(rv_inst inst) { - return (((int64_t)inst << 32) >> 57) << 5 | - (inst << 52) >> 59; + uint32_t imm =3D extract32(inst, 25, 7) << 5 | + extract32(inst, 7, 5); + + return sextract32(imm, 0, 12); } =20 static int32_t operand_sbimm12(rv_inst inst) { - return (((int64_t)inst << 32) >> 63) << 12 | - ((inst << 33) >> 58) << 5 | - ((inst << 52) >> 60) << 1 | - ((inst << 56) >> 63) << 11; + uint32_t imm =3D extract32(inst, 31, 1) << 12 | + extract32(inst, 25, 6) << 5 | + extract32(inst, 8, 4) << 1 | + extract32(inst, 7, 1) << 11; + + return sextract32(imm, 0, 13); } =20 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) { - int imm =3D ((inst << 51) >> 63) << 5 | - (inst << 57) >> 59; + int imm =3D extract32(inst, 12, 1) << 5 | + extract32(inst, 2, 5); if (isa =3D=3D rv128) { imm =3D imm ? imm : 64; } @@ -4369,8 +4375,8 @@ static uint32_t operand_cimmshl6(rv_inst inst, rv_isa= isa) =20 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) { - int imm =3D ((inst << 51) >> 63) << 5 | - (inst << 57) >> 59; + int imm =3D extract32(inst, 12, 1) << 5 | + extract32(inst, 2, 5); if (isa =3D=3D rv128) { imm =3D imm | (imm & 32) << 1; imm =3D imm ? imm : 64; @@ -4380,116 +4386,126 @@ static uint32_t operand_cimmshr6(rv_inst inst, rv= _isa isa) =20 static int32_t operand_cimmi(rv_inst inst) { - return (((int64_t)inst << 51) >> 63) << 5 | - (inst << 57) >> 59; + uint32_t imm =3D extract32(inst, 12, 1) << 5 | + extract32(inst, 2, 5); + + return sextract32(imm, 0, 6); } =20 static int32_t operand_cimmui(rv_inst inst) { - return (((int64_t)inst << 51) >> 63) << 17 | - ((inst << 57) >> 59) << 12; + uint32_t imm =3D extract32(inst, 12, 1) << 17 | + extract32(inst, 2, 5) << 12; + + return sextract32(imm, 0, 18); } =20 static uint32_t operand_cimmlwsp(rv_inst inst) { - return ((inst << 51) >> 63) << 5 | - ((inst << 57) >> 61) << 2 | - ((inst << 60) >> 62) << 6; + return extract32(inst, 12, 1) << 5 | + extract32(inst, 4, 3) << 2 | + extract32(inst, 2, 2) << 6; } =20 static uint32_t operand_cimmldsp(rv_inst inst) { - return ((inst << 51) >> 63) << 5 | - ((inst << 57) >> 62) << 3 | - ((inst << 59) >> 61) << 6; + return extract32(inst, 12, 1) << 5 | + extract32(inst, 5, 2) << 3 | + extract32(inst, 2, 3) << 6; } =20 static uint32_t operand_cimmlqsp(rv_inst inst) { - return ((inst << 51) >> 63) << 5 | - ((inst << 57) >> 63) << 4 | - ((inst << 58) >> 60) << 6; + return extract32(inst, 12, 1) << 5 | + extract32(inst, 6, 1) << 4 | + extract32(inst, 2, 4) << 6; } =20 static int32_t operand_cimm16sp(rv_inst inst) { - return (((int64_t)inst << 51) >> 63) << 9 | - ((inst << 57) >> 63) << 4 | - ((inst << 58) >> 63) << 6 | - ((inst << 59) >> 62) << 7 | - ((inst << 61) >> 63) << 5; + uint32_t imm =3D extract32(inst, 12, 1) << 9 | + extract32(inst, 6, 1) << 4 | + extract32(inst, 5, 1) << 6 | + extract32(inst, 3, 2) << 7 | + extract32(inst, 2, 1) << 5; + + return sextract32(imm, 0, 10); } =20 static int32_t operand_cimmj(rv_inst inst) { - return (((int64_t)inst << 51) >> 63) << 11 | - ((inst << 52) >> 63) << 4 | - ((inst << 53) >> 62) << 8 | - ((inst << 55) >> 63) << 10 | - ((inst << 56) >> 63) << 6 | - ((inst << 57) >> 63) << 7 | - ((inst << 58) >> 61) << 1 | - ((inst << 61) >> 63) << 5; + uint32_t imm =3D extract32(inst, 12, 1) << 11 | + extract32(inst, 11, 1) << 4 | + extract32(inst, 9, 2) << 8 | + extract32(inst, 8, 1) << 10 | + extract32(inst, 7, 1) << 6 | + extract32(inst, 6, 1) << 7 | + extract32(inst, 3, 3) << 1 | + extract32(inst, 2, 1) << 5; + + return sextract32(imm, 0, 12); } =20 static int32_t operand_cimmb(rv_inst inst) { - return (((int64_t)inst << 51) >> 63) << 8 | - ((inst << 52) >> 62) << 3 | - ((inst << 57) >> 62) << 6 | - ((inst << 59) >> 62) << 1 | - ((inst << 61) >> 63) << 5; + uint32_t imm =3D extract32(inst, 12, 1) << 8 | + extract32(inst, 10, 2) << 3 | + extract32(inst, 5, 2) << 6 | + extract32(inst, 3, 2) << 1 | + extract32(inst, 2, 1) << 5; + + return sextract32(imm, 0, 9); } =20 static uint32_t operand_cimmswsp(rv_inst inst) { - return ((inst << 51) >> 60) << 2 | - ((inst << 55) >> 62) << 6; + return extract32(inst, 9, 4) << 2 | + extract32(inst, 7, 2) << 6; } =20 static uint32_t operand_cimmsdsp(rv_inst inst) { - return ((inst << 51) >> 61) << 3 | - ((inst << 54) >> 61) << 6; + return extract32(inst, 10, 3) << 3 | + extract32(inst, 7, 3) << 6; } =20 static uint32_t operand_cimmsqsp(rv_inst inst) { - return ((inst << 51) >> 62) << 4 | - ((inst << 53) >> 60) << 6; + return extract32(inst, 11, 2) << 4 | + extract32(inst, 7, 4) << 6; } =20 static uint32_t operand_cimm4spn(rv_inst inst) { - return ((inst << 51) >> 62) << 4 | - ((inst << 53) >> 60) << 6 | - ((inst << 57) >> 63) << 2 | - ((inst << 58) >> 63) << 3; + return extract32(inst, 11, 2) << 4 | + extract32(inst, 7, 4) << 6 | + extract32(inst, 6, 1) << 2 | + extract32(inst, 5, 1) << 3; } =20 static uint32_t operand_cimmw(rv_inst inst) { - return ((inst << 51) >> 61) << 3 | - ((inst << 57) >> 63) << 2 | - ((inst << 58) >> 63) << 6; + return extract32(inst, 10, 3) << 3 | + extract32(inst, 6, 1) << 2 | + extract32(inst, 5, 1) << 6; } =20 static uint32_t operand_cimmd(rv_inst inst) { - return ((inst << 51) >> 61) << 3 | - ((inst << 57) >> 62) << 6; + return extract32(inst, 10, 3) << 3 | + extract32(inst, 5, 2) << 6; } =20 static uint32_t operand_cimmq(rv_inst inst) { - return ((inst << 51) >> 62) << 4 | - ((inst << 53) >> 63) << 8 | - ((inst << 57) >> 62) << 6; + return extract32(inst, 11, 2) << 4 | + extract32(inst, 10, 1) << 8 | + extract32(inst, 5, 2) << 6; } =20 static int32_t operand_vimm(rv_inst inst) { - return (int64_t)(inst << 44) >> 59; + return sextract32(inst, 15, 5); } =20 static uint32_t operand_vuimm(rv_inst inst) @@ -4499,74 +4515,74 @@ static uint32_t operand_vuimm(rv_inst inst) =20 static uint32_t operand_vzimm11(rv_inst inst) { - return (inst << 33) >> 53; + return extract32(inst, 20, 11); } =20 static uint32_t operand_vzimm10(rv_inst inst) { - return (inst << 34) >> 54; + return extract32(inst, 20, 10); } =20 static uint32_t operand_vzimm6(rv_inst inst) { - return ((inst << 37) >> 63) << 5 | - ((inst << 44) >> 59); + return extract32(inst, 26, 1) << 5 | + extract32(inst, 15, 5); } =20 static uint32_t operand_bs(rv_inst inst) { - return (inst << 32) >> 62; + return extract32(inst, 30, 2); } =20 static uint32_t operand_rnum(rv_inst inst) { - return (inst << 40) >> 60; + return extract32(inst, 20, 4); } =20 static uint32_t operand_vm(rv_inst inst) { - return (inst << 38) >> 63; + return extract32(inst, 25, 1); } =20 static uint32_t operand_uimm_c_lb(rv_inst inst) { - return (((inst << 58) >> 63) << 1) | - ((inst << 57) >> 63); + return extract32(inst, 5, 1) << 1 | + extract32(inst, 6, 1); } =20 static uint32_t operand_uimm_c_lh(rv_inst inst) { - return (((inst << 58) >> 63) << 1); + return extract32(inst, 5, 1) << 1; } =20 static uint32_t operand_zcmp_spimm(rv_inst inst) { - return ((inst << 60) >> 62) << 4; + return extract32(inst, 2, 2) << 4; } =20 static uint32_t operand_zcmp_rlist(rv_inst inst) { - return ((inst << 56) >> 60); + return extract32(inst, 4, 4); } =20 static uint32_t operand_imm6(rv_inst inst) { - return (inst << 38) >> 58; + return extract32(inst, 20, 6); } =20 static uint32_t operand_imm2(rv_inst inst) { - return (inst << 37) >> 62; + return extract32(inst, 25, 2); } =20 static uint32_t operand_immh(rv_inst inst) { - return (inst << 32) >> 58; + return extract32(inst, 26, 6); } =20 static uint32_t operand_imml(rv_inst inst) { - return (inst << 38) >> 58; + return extract32(inst, 20, 6); } =20 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t s= pimm) @@ -4585,12 +4601,12 @@ static uint32_t operand_zcmp_stack_adj(rv_inst inst= , rv_isa isa) =20 static uint32_t operand_tbl_index(rv_inst inst) { - return ((inst << 54) >> 56); + return extract32(inst, 2, 8); } =20 static uint32_t operand_lpl(rv_inst inst) { - return inst >> 12; + return extract32(inst, 12, 20); } =20 /* decode operands */ --=20 2.43.0