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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=alejandro.j.jimenez@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1782857370208158500 Content-Type: text/plain; charset="utf-8" From: David Hoppenbrouwers According to the AMD I/O Virtualization Technology (IOMMU) Specification (Rev 3.10), Section 2.4 Commands, the Generic Command Buffer Entry Format encodes the opcode in bits [63:60] of the command buffer. When handling illegal opcodes, the traces for unhandled commands and event log info extract the opcode from an incorrect offset in the command buffer. Fix this issue to avoid potential confusion with mismatched opcodes in traces and unlikely errors in guest event processing. Fixes: d29a09ca68428 ("hw/i386: Introduce AMD IOMMU") Signed-off-by: David Hoppenbrouwers Reviewed-by: Sairaj Kodilkar Acked-by: Igor Mammedov Signed-off-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 79216fb305..05b7c638f4 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1509,9 +1509,9 @@ static void amdvi_cmdbuf_exec(AMDVIState *s) amdvi_inval_all(s, cmd); break; default: - trace_amdvi_unhandled_command(extract64(cmd[1], 60, 4)); + trace_amdvi_unhandled_command(extract64(cmd[0], 60, 4)); /* log illegal command */ - amdvi_log_illegalcom_error(s, extract64(cmd[1], 60, 4), + amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), s->cmdbuf + s->cmdbuf_head); } } --=20 2.47.3 From nobody Sun Jul 26 11:03:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.165.32; envelope-from=alejandro.j.jimenez@oracle.com; helo=mx0a-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1782857376152158500 Content-Type: text/plain; charset="utf-8" fetch_pte() returns a status code 0 on success, and (small) negative values on failure. The PTE value itself is returned via an output parameter. amdvi_get_top_pt_level_and_perms() follows the same return convention. Both functions currently return uint64_t, which means any negative error values are returned as unsigned and then converted back to int by the callers. This does not cause any issues in the current implementation, but Coverity flags the type mismatch and potential overflow. Make both helpers return int, so the type matches what the return variable is (0 on success, small negative value on failure), and also the type used by all callers to store their return values. No functional changes are intended. Fixes: a1c97c395729 ("amd_iommu: Sync shadow page tables on page invalidati= on") Fixes: 786550e2d38a ("amd_iommu: Follow root pointer before page walk and u= se 1-based levels") Reported-by: Peter Maydell Suggested-by: Peter Maydell Signed-off-by: Alejandro Jimenez Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/amd_iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 05b7c638f4..a0835a20d7 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -659,7 +659,7 @@ static uint64_t large_pte_page_size(uint64_t pte) * - IOVA exceeds the address width supported by DTE[Mode] * In all such cases a page walk must be aborted. */ -static uint64_t amdvi_get_top_pt_level_and_perms(hwaddr address, uint64_t = dte, +static int amdvi_get_top_pt_level_and_perms(hwaddr address, uint64_t dte, uint8_t *top_level, IOMMUAccessFlags *dte_per= ms) { @@ -702,7 +702,7 @@ static uint64_t amdvi_get_top_pt_level_and_perms(hwaddr= address, uint64_t dte, * page table walk. This means that the DTE has valid data, but one o= f the * lower level entries in the Page Table could not be read. */ -static uint64_t fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64_t = dte, +static int fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64_t dte, uint64_t *pte, hwaddr *page_size) { uint64_t pte_addr; --=20 2.47.3 From nobody Sun Jul 26 11:03:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1782857368; cv=none; d=zohomail.com; s=zohoarc; b=N2D5/xGK7NRGf3XUShi3ENFwn83LvTEb35YZe8Hhc/sK2xvK/rib9o70gptCo/SGKIxxs+oxllBuSP/bbhB+0UgwP4z4IRGTJXoP+Hpt07O3Pc89sEplzuqB9iYEMk3Ihu1tPe/Xy0iVrnir5MXrq8fyB7IA1tFFgqrN+dBy2VI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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bh=YoGNWqIt3taWHOcRI4+ESM6QPZJyvW1F4VfAVHhMdL8=; b= Tw4Ohi7T8HOoUdYteAyhOb5lI9g2+vWsAF2A5rsf+7LqQCxtezr3QCt7Y6/ivaLZ YTuz+kz/sLneRHJkFkTgEhLMqXf3hQXk09ZDa5AJrOmXoceFfCG9tzf8+HdLW7Bb BeROhyTPszILO1ZUjbVkT7ncImHLp7twT0/zAoofArIrqixl//GpuhrnQwLjFB3Z n3WdXtpXLMDD84QPL20XIcpDCUFKA1D78rDxCrrdT8pTOHSneRIm7SYxwgxi4kgG qfzd1X/31oh7xkvEc1R5/YrLXwkRXDz3QMeAOtIamhVrYWWf8IO+riKV9Owcow80 slPakE1ec1yXvmlLh+3aCA== From: Alejandro Jimenez To: mst@redhat.com, qemu-devel@nongnu.org Cc: sarunkod@amd.com, qemu@demindiro.com, imammedo@redhat.com, peter.maydell@linaro.org, philmd@oss.qualcomm.com, alejandro.j.jimenez@oracle.com Subject: [PATCH 3/5] amd_iommu: Decode XT interrupt control register without bitfields Date: Tue, 30 Jun 2026 22:08:04 +0000 Message-ID: <20260630220806.1758748-4-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260630220806.1758748-1-alejandro.j.jimenez@oracle.com> References: <20260630220806.1758748-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.165.32; envelope-from=alejandro.j.jimenez@oracle.com; helo=mx0a-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1782857370247158500 The XT IOMMU General Interrupt Control Register is a guest-visible MMIO register. Decoding it with bitfields depends on host bitfield layout and is not portable to big-endian hosts. Fix this by removing union mmio_xt_intr and explicitly extracting fields with FIELD_EX64() from the full register value returned by amdvi_readq(), which has already been converted to host endianness. Using a designated initializer for X86IOMMUIrq also ensures fields not provided by the XT register (e.g. msi_addr_last_bits) are initialized before x86_iommu_irq_to_msi_message() uses them. CID: 1660056 Fixes: cf0210df65aa ("amd_iommu: Generate XT interrupts when xt support is = enabled") Reported-by: Peter Maydell Suggested-by: Peter Maydell Signed-off-by: Alejandro Jimenez Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/i386/amd_iommu.c | 28 ++++++++++++++++++---------- hw/i386/amd_iommu.h | 14 -------------- 2 files changed, 18 insertions(+), 24 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index a0835a20d7..291cb368a9 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -34,6 +34,7 @@ #include "hw/core/qdev-properties.h" #include "kvm/kvm_i386.h" #include "qemu/iova-tree.h" +#include "hw/core/registerfields.h" =20 struct AMDVIAddressSpace { PCIBus *bus; /* PCIBus (for bus number) */ @@ -88,6 +89,13 @@ typedef struct AMDVIIOTLBKey { uint16_t devid; } AMDVIIOTLBKey; =20 +/* XT IOMMU General Interrupt Control Register layout */ +FIELD(AMDVI_XT_GEN_INTR, DEST_MODE, 2, 1) +FIELD(AMDVI_XT_GEN_INTR, DEST_LO, 8, 24) +FIELD(AMDVI_XT_GEN_INTR, VECTOR, 32, 8) +FIELD(AMDVI_XT_GEN_INTR, DELIVERY_MODE, 40, 1) +FIELD(AMDVI_XT_GEN_INTR, DEST_HI, 56, 8) + uint64_t amdvi_extended_feature_register(AMDVIState *s) { uint64_t feature =3D AMDVI_DEFAULT_EXT_FEATURES; @@ -194,17 +202,17 @@ static void amdvi_assign_andq(AMDVIState *s, hwaddr a= ddr, uint64_t val) =20 static void amdvi_build_xt_msi_msg(AMDVIState *s, MSIMessage *msg) { - union mmio_xt_intr xt_reg; - struct X86IOMMUIrq irq; - - xt_reg.val =3D amdvi_readq(s, AMDVI_MMIO_XT_GEN_INTR); + uint64_t xt_reg =3D amdvi_readq(s, AMDVI_MMIO_XT_GEN_INTR); =20 - irq.vector =3D xt_reg.vector; - irq.delivery_mode =3D xt_reg.delivery_mode; - irq.dest_mode =3D xt_reg.destination_mode; - irq.dest =3D (xt_reg.destination_hi << 24) | xt_reg.destination_lo; - irq.trigger_mode =3D 0; - irq.redir_hint =3D 0; + X86IOMMUIrq irq =3D { + .vector =3D FIELD_EX64(xt_reg, AMDVI_XT_GEN_INTR, VECTOR), + .delivery_mode =3D FIELD_EX64(xt_reg, AMDVI_XT_GEN_INTR, DELIVERY_= MODE), + .dest_mode =3D FIELD_EX64(xt_reg, AMDVI_XT_GEN_INTR, DEST_MODE), + .dest =3D (FIELD_EX64(xt_reg, AMDVI_XT_GEN_INTR, DEST_HI) << 24) | + FIELD_EX64(xt_reg, AMDVI_XT_GEN_INTR, DEST_LO), + .trigger_mode =3D 0, + .redir_hint =3D 0, + }; =20 x86_iommu_irq_to_msi_message(&irq, msg); } diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 3cab04a6d4..ca4440a4c1 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -340,20 +340,6 @@ struct irte_ga { union irte_ga_hi hi; }; =20 -union mmio_xt_intr { - uint64_t val; - struct { - uint64_t rsvd_1:2, - destination_mode:1, - rsvd_2:5, - destination_lo:24, - vector:8, - delivery_mode:1, - rsvd_3:15, - destination_hi:8; - }; -}; - #define TYPE_AMD_IOMMU_DEVICE "amd-iommu" OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE) =20 --=20 2.47.3 From nobody Sun Jul 26 11:03:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1782857378; cv=none; d=zohomail.com; s=zohoarc; b=TMMEgOCAiiPgbQ3RYlmxx2tJt+Sq+nrRRO1XhQER1kkQLpTE+AlCHh3MzUKbBp5CCPyAywashF8mp7AMXSr7d2+8EUXZgIg9Y7+uiXwHK3rWd3KY4xZfyTtD7b3OUOeFfH/z6RIf6FNcV+M1TJxfjwJPJphe/AXUpPqJrUPQSRM= ARC-Message-Signature: i=1; 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bh=645Tf vzesUp3Di2aVWeUFo+Xd5Fg6DnwGsMTXCF/Mrs=; b=jpKaHkrqWkgvxGwaeuRvh YB+EQz+LUh18E/mwlrl84HyfLNlE5bwbyz5epo4flX9mZeZeSO4IJFajoBy+S4Gj UWS3FFEUI9bUW/5Tmm6LchWw8wDDzp1tESXmIZf2l8iKpw6UasW+F7ymjeVMgQk0 lZzpZICKoeTILQhg3bpi0kWYdmzR9l9fQvQHPZJ3ULvpHSYmvJOJ8wcL4EKwuXJA H7daTKCKfGI1/Tw1ex2sDTWipp63zv1mBiK1WYLvepCtwhdf/nhTnNqEFGRGd4Cr MoGlz9KqDaimuruXTxSMPShkXHjYPawTehw4ESzItwYGvz/aMJKUn4Qinm1dnl0H A== From: Alejandro Jimenez To: mst@redhat.com, qemu-devel@nongnu.org Cc: sarunkod@amd.com, qemu@demindiro.com, imammedo@redhat.com, peter.maydell@linaro.org, philmd@oss.qualcomm.com, alejandro.j.jimenez@oracle.com Subject: [PATCH 4/5] amd_iommu: Decode IRTEs without bitfields Date: Tue, 30 Jun 2026 22:08:05 +0000 Message-ID: <20260630220806.1758748-5-alejandro.j.jimenez@oracle.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260630220806.1758748-1-alejandro.j.jimenez@oracle.com> References: <20260630220806.1758748-1-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-30_05,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 bulkscore=0 mlxlogscore=927 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2606160000 definitions=main-2606300215 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjMwMDIxNSBTYWx0ZWRfXwupzoWUUkgw6 o4AS7m11xS6SjD4ql2UuUP4BXlEHN5UPtbTh77ERO4l8E8MBt8Z5MQbdJT1oHtJG6TnvSD9YB45 HNU832PJOu+XVjzuWSlcwypFeArzx3HlebogBfgpSbu0POEMni/R X-Proofpoint-GUID: kTkTa2l1tr4Cu6vtgC2Jd3UVR6JE9i6Z X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjMwMDIxNSBTYWx0ZWRfX4le8XeNqOPFt BxyiF+UM2nZ4V8xFILmHwFfetiqojM6oa3OKa/Sg0WSDN4zJIEJkAqXi4wKGsWIJtdWHfmevaYA +rm6XkXscZ4Gej/8vECEVsAanxii1a5s5Odi4gyDxMalHLWbVYEvegZ452l/CdMMo2pi8/IWYha oUkU9QOAlTsuAbzMJ9Ww93lLh3B49ZyQPWwpArjvj+ne1NwzX3tqArFw+y6np4oNxh3bwzMd1h0 kFgPmC6hxEpreGX7lhilfyhty7wt02b0+XymPD4xZyqv1eSjQegKhFYP8B6zc+MfO2q2tbve3ux pYlOopRNP3MnQwjdXw5HYwfQ0RjJsuzCNHeVsOkmHU0k/Md+WiP7Yh1VL9QoIzjxTdVANgRYl+v PZL6/9uJ5tdCr92fZOqS59rW67nyYZxFtiq0ZHOROk+rfW2Yg+P9wGMQ6z/6Hu/msXgCiJ8xxHS 4b7CdcFC3dZrS+jSfoiekHRXmQslBfSBJn7wKj18= X-Proofpoint-ORIG-GUID: kTkTa2l1tr4Cu6vtgC2Jd3UVR6JE9i6Z X-Authority-Analysis: v=2.4 cv=D5N37PRj c=1 sm=1 tr=0 ts=6a443e49 b=1 cx=c_pps a=qoll8+KPOyaMroiJ2sR5sw==:117 a=qoll8+KPOyaMroiJ2sR5sw==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=jiCTI4zE5U7BLdzWsZGv:22 a=BqU2WV_vvsyTyxaotp0D:22 a=KKAkSRfTAAAA:8 a=yPCof4ZbAAAA:8 a=iN8GYCbXJNbl4wqCgcoA:9 a=cvBusfyB2V15izCimMoJ:22 a=5yU3S35YU4bGjq-dph-N:22 a=Bho9c0fBagfJEIQBS7DQ:22 cc=ntf awl=host:12313 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=alejandro.j.jimenez@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1782857380236158500 Content-Type: text/plain; charset="utf-8" Interrupt remapping table entries are data stored in guest memory in little-endian format. Decoding them with bitfields depends on host bitfield layout and the value returned from dma_memory_read() is not portable to big-endian hosts. Replace the legacy and GA IRTE bitfield definitions with explicit FIELD() definitions. Convert the guest memory values returned from dma_memory_read() with le32_to_cpu() or le64_to_cpu(), then extract relevant fields using FIELD_EX32() or FIELD_EX64() as appropriate to match the IRTE format. Fixes: b44159fe0078 ("x86_iommu/amd: Add interrupt remap support when VAPIC= is not enabled") Fixes: 135f866e609c ("x86_iommu/amd: Add interrupt remap support when VAPIC= is enabled") Reported-by: Peter Maydell Suggested-by: Peter Maydell Signed-off-by: Alejandro Jimenez Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/amd_iommu.c | 93 +++++++++++++++++++++++++++++++++------------ hw/i386/amd_iommu.h | 49 ------------------------ 2 files changed, 69 insertions(+), 73 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 291cb368a9..c7bf21b762 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -89,6 +89,11 @@ typedef struct AMDVIIOTLBKey { uint16_t devid; } AMDVIIOTLBKey; =20 +typedef struct AMDVIIrteGA { + uint64_t ga_lo; + uint64_t ga_hi; +} AMDVIIrteGA; + /* XT IOMMU General Interrupt Control Register layout */ FIELD(AMDVI_XT_GEN_INTR, DEST_MODE, 2, 1) FIELD(AMDVI_XT_GEN_INTR, DEST_LO, 8, 24) @@ -96,6 +101,37 @@ FIELD(AMDVI_XT_GEN_INTR, VECTOR, 32, 8) FIELD(AMDVI_XT_GEN_INTR, DELIVERY_MODE, 40, 1) FIELD(AMDVI_XT_GEN_INTR, DEST_HI, 56, 8) =20 +/* Interrupt Remapping Table Fields Formats */ + +/* Basic 32-bit IRTE layout (GAEn=3D0) */ +FIELD(AMDVI_IRTE, VALID, 0, 1) +FIELD(AMDVI_IRTE, SUP_IOPF, 1, 1) +FIELD(AMDVI_IRTE, INT_TYPE, 2, 3) +FIELD(AMDVI_IRTE, RQ_EOI, 5, 1) +FIELD(AMDVI_IRTE, DM, 6, 1) +FIELD(AMDVI_IRTE, GUEST_MODE, 7, 1) +FIELD(AMDVI_IRTE, DESTINATION, 8, 8) +FIELD(AMDVI_IRTE, VECTOR, 16, 8) + +/* 128-bit IRTE layout (GAEn=3D1) */ +FIELD(AMDVI_IRTE_GA_LO, VALID, 0, 1) +FIELD(AMDVI_IRTE_GA_LO, SUP_IOPF, 1, 1) +FIELD(AMDVI_IRTE_GA_LO, INT_TYPE, 2, 3) +FIELD(AMDVI_IRTE_GA_LO, RQ_EOI, 5, 1) +FIELD(AMDVI_IRTE_GA_LO, DM, 6, 1) +FIELD(AMDVI_IRTE_GA_LO, GUEST_MODE, 7, 1) +/* + * In the 128-bit IRTE format, XT mode uses IRTE_GA_LOW.Destination[23:0] + * together with IRTE_GA_HI.DestinationHi[7:0] to construct a 32-bit x2APIC + * destination. + * Without XTEn (i.e. when x2APIC support is not enabled), only + * IRTE_GA_LOW.Destination[7:0] is used. + */ +FIELD(AMDVI_IRTE_GA_LO, DESTINATION, 8, 24) + +FIELD(AMDVI_IRTE_GA_HI, VECTOR, 0, 8) +FIELD(AMDVI_IRTE_GA_HI, DESTINATION_HI, 56, 8) + uint64_t amdvi_extended_feature_register(AMDVIState *s) { uint64_t feature =3D AMDVI_DEFAULT_EXT_FEATURES; @@ -1983,7 +2019,7 @@ static IOMMUTLBEntry amdvi_translate(IOMMUMemoryRegio= n *iommu, hwaddr addr, } =20 static int amdvi_get_irte(AMDVIState *s, MSIMessage *origin, uint64_t *dte, - union irte *irte, uint16_t devid) + uint32_t *irte, uint16_t devid) { uint64_t irte_root, offset; =20 @@ -1998,7 +2034,8 @@ static int amdvi_get_irte(AMDVIState *s, MSIMessage *= origin, uint64_t *dte, return -AMDVI_IR_GET_IRTE; } =20 - trace_amdvi_ir_irte_val(irte->val); + *irte =3D le32_to_cpu(*irte); + trace_amdvi_ir_irte_val(*irte); =20 return 0; } @@ -2010,8 +2047,9 @@ static int amdvi_int_remap_legacy(AMDVIState *iommu, X86IOMMUIrq *irq, uint16_t sid) { + uint8_t int_type; + uint32_t irte; int ret; - union irte irte; =20 /* get interrupt remapping table */ ret =3D amdvi_get_irte(iommu, origin, dte, &irte, sid); @@ -2019,32 +2057,33 @@ static int amdvi_int_remap_legacy(AMDVIState *iommu, return ret; } =20 - if (!irte.fields.valid) { + if (!FIELD_EX32(irte, AMDVI_IRTE, VALID)) { trace_amdvi_ir_target_abort("RemapEn is disabled"); return -AMDVI_IR_TARGET_ABORT; } =20 - if (irte.fields.guest_mode) { + if (FIELD_EX32(irte, AMDVI_IRTE, GUEST_MODE)) { error_report_once("guest mode is not zero"); return -AMDVI_IR_ERR; } =20 - if (irte.fields.int_type > AMDVI_IOAPIC_INT_TYPE_ARBITRATED) { + int_type =3D FIELD_EX32(irte, AMDVI_IRTE, INT_TYPE); + if (int_type > AMDVI_IOAPIC_INT_TYPE_ARBITRATED) { error_report_once("reserved int_type"); return -AMDVI_IR_ERR; } =20 - irq->delivery_mode =3D irte.fields.int_type; - irq->vector =3D irte.fields.vector; - irq->dest_mode =3D irte.fields.dm; - irq->redir_hint =3D irte.fields.rq_eoi; - irq->dest =3D irte.fields.destination; + irq->delivery_mode =3D int_type; + irq->vector =3D FIELD_EX32(irte, AMDVI_IRTE, VECTOR); + irq->dest_mode =3D FIELD_EX32(irte, AMDVI_IRTE, DM); + irq->redir_hint =3D FIELD_EX32(irte, AMDVI_IRTE, RQ_EOI); + irq->dest =3D FIELD_EX32(irte, AMDVI_IRTE, DESTINATION); =20 return 0; } =20 static int amdvi_get_irte_ga(AMDVIState *s, MSIMessage *origin, uint64_t *= dte, - struct irte_ga *irte, uint16_t devid) + AMDVIIrteGA *irte, uint16_t devid) { uint64_t irte_root, offset; =20 @@ -2058,7 +2097,9 @@ static int amdvi_get_irte_ga(AMDVIState *s, MSIMessag= e *origin, uint64_t *dte, return -AMDVI_IR_GET_IRTE; } =20 - trace_amdvi_ir_irte_ga_val(irte->hi.val, irte->lo.val); + irte->ga_lo =3D le64_to_cpu(irte->ga_lo); + irte->ga_hi =3D le64_to_cpu(irte->ga_hi); + trace_amdvi_ir_irte_ga_val(irte->ga_hi, irte->ga_lo); return 0; } =20 @@ -2069,8 +2110,9 @@ static int amdvi_int_remap_ga(AMDVIState *iommu, X86IOMMUIrq *irq, uint16_t sid) { + AMDVIIrteGA irte; + uint8_t int_type; int ret; - struct irte_ga irte; =20 /* get interrupt remapping table */ ret =3D amdvi_get_irte_ga(iommu, origin, dte, &irte, sid); @@ -2078,30 +2120,33 @@ static int amdvi_int_remap_ga(AMDVIState *iommu, return ret; } =20 - if (!irte.lo.fields_remap.valid) { + if (!FIELD_EX64(irte.ga_lo, AMDVI_IRTE_GA_LO, VALID)) { trace_amdvi_ir_target_abort("RemapEn is disabled"); return -AMDVI_IR_TARGET_ABORT; } =20 - if (irte.lo.fields_remap.guest_mode) { + if (FIELD_EX64(irte.ga_lo, AMDVI_IRTE_GA_LO, GUEST_MODE)) { error_report_once("guest mode is not zero"); return -AMDVI_IR_ERR; } =20 - if (irte.lo.fields_remap.int_type > AMDVI_IOAPIC_INT_TYPE_ARBITRATED) { + int_type =3D FIELD_EX64(irte.ga_lo, AMDVI_IRTE_GA_LO, INT_TYPE); + if (int_type > AMDVI_IOAPIC_INT_TYPE_ARBITRATED) { error_report_once("reserved int_type is set"); return -AMDVI_IR_ERR; } =20 - irq->delivery_mode =3D irte.lo.fields_remap.int_type; - irq->vector =3D irte.hi.fields.vector; - irq->dest_mode =3D irte.lo.fields_remap.dm; - irq->redir_hint =3D irte.lo.fields_remap.rq_eoi; + irq->delivery_mode =3D int_type; + irq->vector =3D FIELD_EX64(irte.ga_hi, AMDVI_IRTE_GA_HI, VECTOR); + irq->dest_mode =3D FIELD_EX64(irte.ga_lo, AMDVI_IRTE_GA_LO, DM); + irq->redir_hint =3D FIELD_EX64(irte.ga_lo, AMDVI_IRTE_GA_LO, RQ_EOI); if (iommu->xten) { - irq->dest =3D irte.lo.fields_remap.destination | - (irte.hi.fields.destination_hi << 24); + irq->dest =3D FIELD_EX64(irte.ga_lo, AMDVI_IRTE_GA_LO, DESTINATION= ) | + (FIELD_EX64(irte.ga_hi, AMDVI_IRTE_GA_HI, DESTINATION_= HI) + << 24); } else { - irq->dest =3D irte.lo.fields_remap.destination & 0xff; + irq->dest =3D FIELD_EX64(irte.ga_lo, AMDVI_IRTE_GA_LO, DESTINATION= ) & + 0xff; } =20 return 0; diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index ca4440a4c1..687691ec1c 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -291,55 +291,6 @@ #define AMDVI_DEV_LINT0_PASS_MASK (1ULL << 62) #define AMDVI_DEV_LINT1_PASS_MASK (1ULL << 63) =20 -/* Interrupt remapping table fields (Guest VAPIC not enabled) */ -union irte { - uint32_t val; - struct { - uint32_t valid:1, - no_fault:1, - int_type:3, - rq_eoi:1, - dm:1, - guest_mode:1, - destination:8, - vector:8, - rsvd:8; - } fields; -}; - -/* Interrupt remapping table fields (Guest VAPIC is enabled) */ -union irte_ga_lo { - uint64_t val; - - /* For int remapping */ - struct { - uint64_t valid:1, - no_fault:1, - /* ------ */ - int_type:3, - rq_eoi:1, - dm:1, - /* ------ */ - guest_mode:1, - destination:24, - rsvd_1:32; - } fields_remap; -}; - -union irte_ga_hi { - uint64_t val; - struct { - uint64_t vector:8, - rsvd_2:48, - destination_hi:8; - } fields; -}; - -struct irte_ga { - union irte_ga_lo lo; - union irte_ga_hi hi; -}; - #define TYPE_AMD_IOMMU_DEVICE "amd-iommu" OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE) =20 --=20 2.47.3 From nobody Sun Jul 26 11:03:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1782857343; cv=none; d=zohomail.com; s=zohoarc; b=RtmD8S8hFw+QxCMxUy84N1PBJxHzM7NiQOs9UYbsOlsCVa313MLyeKOYHOvq/Hohgz7xzULmyTwD3JEoQ3h5eo+u/tTwD9/y8IKpfAqG8C5dev8+6gPPGKE0kWGw7pC5HY268gM/HiozBwE/0CosARnxhfAUU24BPzYoq2N/1sU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782857343; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=alejandro.j.jimenez@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1782857344138158500 Content-Type: text/plain; charset="utf-8" AMD IOMMU command buffer entries are stored in guest memory in little-endian format. Convert command buffer with le64_to_cpu() after dma_memory_read(), so that command handlers can all operate using host native endianness. Remove the cpu_to_le*() conversions from command handlers, since the values are used internally by device emulation and do not need translation. Conversion is only necessary when reading or writing to guest memory e.g. writing completion-wait data and event log entries. The flow for command buffer handling is: - Retrieve command buffer (cmd[]) from guest memory (via dma_memory_read()) - Convert command buffer to host endianness (via le64_to_cpu()) - All handlers decode fields from cmd[] in host-endian format - All emulation code uses decoded values in host-endian format - Use cpu_to_le*() when writing back data to guest memory Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU") Signed-off-by: Alejandro Jimenez Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/amd_iommu.c | 39 +++++++++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 10 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index c7bf21b762..90252c52af 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -278,6 +278,7 @@ static uint32_t get_next_eventlog_entry(AMDVIState *s) =20 static void amdvi_log_event(AMDVIState *s, uint64_t *evt) { + uint64_t le_evt[2]; uint32_t evtlog_tail_next; =20 /* event logging not enabled */ @@ -298,8 +299,14 @@ static void amdvi_log_event(AMDVIState *s, uint64_t *e= vt) return; } =20 + /* + * Convert event buffer to little-endian before writing it to guest me= mory. + */ + le_evt[0] =3D cpu_to_le64(evt[0]); + le_evt[1] =3D cpu_to_le64(evt[1]); + if (dma_memory_write(&address_space_memory, s->evtlog + s->evtlog_tail, - evt, AMDVI_EVENT_LEN, MEMTXATTRS_UNSPECIFIED)) { + le_evt, AMDVI_EVENT_LEN, MEMTXATTRS_UNSPECIFIED))= { trace_amdvi_evntlog_fail(s->evtlog, s->evtlog_tail); } =20 @@ -545,15 +552,18 @@ static void amdvi_update_iotlb(AMDVIState *s, uint16_= t devid, static void amdvi_completion_wait(AMDVIState *s, uint64_t *cmd) { /* pad the last 3 bits */ - hwaddr addr =3D cpu_to_le64(extract64(cmd[0], 3, 49)) << 3; - uint64_t data =3D cpu_to_le64(cmd[1]); + hwaddr addr =3D extract64(cmd[0], 3, 49) << 3; + uint64_t data =3D cmd[1]; + + /* Format the data to be written to guest memory as little-endian */ + uint64_t le_data =3D cpu_to_le64(data); =20 if (extract64(cmd[0], 52, 8)) { amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), s->cmdbuf + s->cmdbuf_head); } if (extract64(cmd[0], 0, 1)) { - if (dma_memory_write(&address_space_memory, addr, &data, + if (dma_memory_write(&address_space_memory, addr, &le_data, AMDVI_COMPLETION_DATA_SIZE, MEMTXATTRS_UNSPECIFIED)) { trace_amdvi_completion_wait_fail(addr); @@ -1281,7 +1291,7 @@ static void amdvi_update_addr_translation_mode(AMDVIS= tate *s, uint16_t devid) /* log error without aborting since linux seems to be using reserved bits = */ static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd) { - uint16_t devid =3D cpu_to_le16((uint16_t)extract64(cmd[0], 0, 16)); + uint16_t devid =3D extract64(cmd[0], 0, 16); =20 trace_amdvi_devtab_inval(PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid)); @@ -1448,9 +1458,9 @@ static void amdvi_sync_domain(AMDVIState *s, uint16_t= domid, uint64_t addr, /* we don't have devid - we can't remove pages by address */ static void amdvi_inval_pages(AMDVIState *s, uint64_t *cmd) { - uint16_t domid =3D cpu_to_le16((uint16_t)extract64(cmd[0], 32, 16)); - uint64_t addr =3D cpu_to_le64(extract64(cmd[1], 12, 52)) << 12; - uint16_t flags =3D cpu_to_le16((uint16_t)extract64(cmd[1], 0, 3)); + uint16_t domid =3D extract64(cmd[0], 32, 16); + uint64_t addr =3D extract64(cmd[1], 12, 52) << 12; + uint16_t flags =3D extract64(cmd[1], 0, 3); =20 if (extract64(cmd[0], 20, 12) || extract64(cmd[0], 48, 12) || extract64(cmd[1], 3, 9)) { @@ -1497,7 +1507,7 @@ static void amdvi_inval_inttable(AMDVIState *s, uint6= 4_t *cmd) static void iommu_inval_iotlb(AMDVIState *s, uint64_t *cmd) { =20 - uint16_t devid =3D cpu_to_le16(extract64(cmd[0], 0, 16)); + uint16_t devid =3D extract64(cmd[0], 0, 16); if (extract64(cmd[1], 1, 1) || extract64(cmd[1], 3, 1) || extract64(cmd[1], 6, 6)) { amdvi_log_illegalcom_error(s, extract64(cmd[0], 60, 4), @@ -1509,7 +1519,7 @@ static void iommu_inval_iotlb(AMDVIState *s, uint64_t= *cmd) g_hash_table_foreach_remove(s->iotlb, amdvi_iotlb_remove_by_devid, &devid); } else { - amdvi_iotlb_remove_page(s, cpu_to_le64(extract64(cmd[1], 12, 52)) = << 12, + amdvi_iotlb_remove_page(s, extract64(cmd[1], 12, 52) << 12, devid); } trace_amdvi_iotlb_inval(); @@ -1527,6 +1537,15 @@ static void amdvi_cmdbuf_exec(AMDVIState *s) return; } =20 + /* + * Commands in guest memory are little-endian. Convert once after read= ing + * so that command handlers can decode values in host native endiannes= s. + * Convert back to little-endian only when writing data to guest memor= y via + * dma_memory_write(). + */ + cmd[0] =3D le64_to_cpu(cmd[0]); + cmd[1] =3D le64_to_cpu(cmd[1]); + switch (extract64(cmd[0], 60, 4)) { case AMDVI_CMD_COMPLETION_WAIT: amdvi_completion_wait(s, cmd); --=20 2.47.3