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Mon, 29 Jun 2026 18:09:46 -0700 (PDT) X-Received: by 2002:a05:6214:248a:b0:8e6:23ab:a055 with SMTP id 6a1803df08f44-8f1bd21e19bmr29000256d6.33.1782781785414; Mon, 29 Jun 2026 18:09:45 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, andrew.jones@oss.qualcomm.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH] hw/riscv/riscv-iommu.c: fix read fault being recorded as write Date: Mon, 29 Jun 2026 22:09:38 -0300 Message-ID: <20260630010938.1331641-1-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwNjMwMDAwNyBTYWx0ZWRfX3aGGh2nlHQ9q ziT7sBrGZfTEvov4kRXmtt8zCOr92POV3B8KEV+nuhLkqDEXL907oGU84iEfhj9zu6ayBv7L8XD sUzuUs9yRml3TygFL5EcERDl5SLFP3A= X-Proofpoint-ORIG-GUID: WnjCVsSMUFAfm31wcLBkKLWcRgHPdEXu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjMwMDAwNyBTYWx0ZWRfX/ZafW0KX6Awb sOX8FALVCC/ofXDiAtlQ+BXoV6nxnbyAzcgnUoMBExYCpqr1L5jyjdYEXRfjjWJ7g/8lZ0stduB GcqvTw7obrShjipVpVBZsyiY4iNRT8VDv19gh9tTlVzxIKiKRXSDkmkSxg6zQf+DsjVzrIfdzZ3 eP3+F6WLVBsrl2mJud68m0YcUKJSxQdVYempLVs0BPqDfKhq3Cs0QOzBPb2mUxqppfJP8AFKQdq oYVcGR+vdd8oMwba/3TpyiinZTbpqPE8KqiFLebDQ96GO5yastoxDJKm9NOd+Oi8YjvTU0Y10t4 +LJNUozfRA0eKqeTTr1H8ch/ml0uQZuvKGphp3yGRy08uvQ+xOGh+wyuoJ9dUtBLYdhF+xuLQzg fBmR23E5pGjJn9bIRfEYmGseT9MGZuATyms7dsDeFqg9CMxFSVRS2wYcX9FhKukeN8HiF3bg4Uf YgpQk4mev5fF24H3OEQ== X-Authority-Analysis: v=2.4 cv=NZzWEWD4 c=1 sm=1 tr=0 ts=6a43175b cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=sHJf4AwOIoU3qjeHFPlg6Q==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=p0WdMEafAAAA:8 a=EUspDBNiAAAA:8 a=2kUl_4CQJ_2POlUL4sAA:9 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-GUID: WnjCVsSMUFAfm31wcLBkKLWcRgHPdEXu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_05,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 spamscore=0 adultscore=0 suspectscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606300007 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1782781852148158500 Content-Type: text/plain; charset="utf-8" Under certain circunstances, like the one described in [1], a read operation that faults will be logged as a write fault instead if it happens after the translation phase in riscv_iommu_spa_fetch(). The first problem is that we're overwriting iotlb->perm with PTE flags, so an IOMMU_RO access flag can be overwritten by whatever flags the PTE has. This will cause the wrong fault type to be thrown at the end of the function in case a fault happens. To solve the iotlb->perm overwrite we'll bit_and the original iotlb->perm access flags with the PTE access flags, preserving the original access type. So a IOMMU_RO access in a R+W PTE will result in a IOMMU_RO perm. Second, the resulting fault is received by riscv_iommu_translate(), which will then report the fault. To do that we require a transaction type (ttype). We're prioritizing checking "perm & IOMMU_RW" to set a UADDR_WR ttype, and then checking "perm & IOMMU_RO" to set UADDR_RD ttype. The issue with that is IOMMU_RO=3D1 and IOMMU_RW=3D3, thus checking "perm & IOMMU_RW" for a write then "perm & IOMMU_RO" for a read will cause the read fault to always be diagnosed as write. Make the iotlb->perm matches more strict: "perm & IOMMU_RW" must be exactly IOMMU_RW, ensuring that 'perm' has both flags. Then we can check perm & IOMMU_WO and perm & IOMMU_RO without worrying about overlapping with the RW flag. [1] https://gitlab.com/qemu-project/qemu/-/work_items/3577 Fixes: 69a9ae4836 ("hw/riscv/riscv-iommu: add ATS support") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3577 Signed-off-by: Daniel Henrique Barboza --- hw/riscv/riscv-iommu.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index c9687e01a8..e1ff5eb864 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -282,6 +282,7 @@ static hwaddr riscv_iommu_napot_page_mask(hwaddr ppn, h= waddr addr, hwaddr *out) static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ct= x, IOMMUTLBEntry *iotlb) { + IOMMUAccessFlags pte_perm; dma_addr_t addr, base; uint64_t satp, gatp, pte; bool en_s, en_g; @@ -509,8 +510,16 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, R= ISCVIOMMUContext *ctx, } /* Translation phase completed (GPA or SPA) */ iotlb->translated_addr =3D base; - iotlb->perm =3D (pte & PTE_W) ? ((pte & PTE_R) ? IOMMU_RW : IO= MMU_WO) - : IOMMU_RO; + + /* + * Do a bit_and between the PTE bits and the original + * request flags to determine the exact permission we + * need, i.e. if the original request is RO and the + * PTE has RW flags the actual perm is RO. + */ + pte_perm =3D (pte & PTE_W) ? ((pte & PTE_R) ? IOMMU_RW : IOMMU= _WO) + : IOMMU_RO; + iotlb->perm &=3D pte_perm; =20 /* Check MSI GPA address match */ if (pass =3D=3D S_STAGE && (iotlb->perm & IOMMU_WO) && @@ -1704,7 +1713,8 @@ done: if (fault) { unsigned ttype =3D RISCV_IOMMU_FQ_TTYPE_PCIE_ATS_REQ; =20 - if (iotlb->perm & IOMMU_RW) { + if ((iotlb->perm & IOMMU_RW) =3D=3D IOMMU_RW + || iotlb->perm & IOMMU_WO) { ttype =3D RISCV_IOMMU_FQ_TTYPE_UADDR_WR; } else if (iotlb->perm & IOMMU_RO) { ttype =3D RISCV_IOMMU_FQ_TTYPE_UADDR_RD; --=20 2.43.0