From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735252; cv=none; d=zohomail.com; s=zohoarc; b=WEN/EOdWhiRdNQCMvZlzj7kiTgtVfErUoKYsXTlF4uLIPw6bHpdMrR4bv2g/NEIx9jGolEdmmRyS00B266u/EVw/Z70GEWbLCKP+GoPYNZSK6QpiKWIdv3GCjb3sAJvM4ifjdl8InfzC7onUDPvEys9GgtFzROhwRed80alo1Lw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735252; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=LyhKlDdDcEZAv6sqTUFEF9PTo3TL06w67QzpnS1/n9k=; b=Wk+CxR4VE57IDwUeQAudHY3Ne8IQutBgC8fdwhbqO9SaNI3UA3Ok4+E7+eNSJ+w63+gXoa6XRTkVhidH8ooqhE7A8+HcF6zV1y0zI9s+uCjzLb7vOB71ZmHJqQWUMC2pezruh4Hzgsb23rhf5ZabhGeWgUEWeszQWi8kWn7BOJA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735252846505.0455831324301; Mon, 29 Jun 2026 05:14:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAfx-00071V-5n; Mon, 29 Jun 2026 08:01:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfI-0006pR-Px for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:47 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfF-0007Gk-HU for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:39 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-46cbe01d4b6so1874336f8f.2 for ; Mon, 29 Jun 2026 05:00:37 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-473dddcb295sm8753061f8f.35.2026.06.29.05.00.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 05:00:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1782734436; x=1783339236; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=LyhKlDdDcEZAv6sqTUFEF9PTo3TL06w67QzpnS1/n9k=; b=yeaH4pZpAPYIH96HztRd7Z4tWL0KKYjA35JWYekdQ3NBk0yO9DjsdFwXMq9dnlO1Xl RPBrNZxaBuZsUrmGjHi8B9hXK94oZiD8TYsLt5Ib1nc+mUGkgNyzTBes99hcJsdhoNgN VH01nXBCt2W9KpEejfTf6EZr5CoGlhaunVl+JC5NCY1bdx3Q5s3lQd6DuWgUAkLbtqG2 EsDGNvFsuyB4MfsWlmvRI1VLdO8YbLsBBixEFl4ROrkCfKPqIldVr8aTROt/z8znQC26 P9xPTuedBKRwp7a7obLNLeTUhmoBSP2Hgll6U19intTQ/jNDpgZNO3ka7YLsDmtXr0gN n57Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782734436; x=1783339236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=LyhKlDdDcEZAv6sqTUFEF9PTo3TL06w67QzpnS1/n9k=; b=NUejq6nlBcKDy6WGnRJY6p4EWKZG80LOO3VHrDsbmAjZ6fGIRfmeFUSr1UaGa6hyfD vlFtHi7/Yh8wY+FoDw1hbb5L0EKbK7Q88pkkDFRN3Fgi6/iGEsOpvncm9ig8qmsfl2xk 8mPrkvcXJ1EjHegs4gxHFCGfa6z6pJ8nSCTPLeyq3YNyXCGPYq5a5UnwSf+30jsqP6Dq 1/lg8aJqIzsuM81b/C7NTUMf5GfkVJ2tqTOm2Pqo5khiyhRnhykscrimmTRA1Pr8DNd2 6Oh4IV6oyChIdMC8zsv0RJ7s8SAakJXXo1Y0fXZNtkcjLjt9Dfsbzo/qJS+7ghqFPIyx I7wg== X-Gm-Message-State: AOJu0YynfIU3yCGuKkjzrf98gDw1wHE7vW2i5YnwprLo9eIQwQbisFDU Qc2StI60mT5VKmvsiGQZMXUQJH5iJB67JCQc38g9vVnwWyEJKgWm+qYzsHCef7ecEaxa3QLkiY3 8Mc2Q X-Gm-Gg: AfdE7ckocnr8QglbEI/chhdQsbCD62YP4iUK300PjpO/Oxrq4LLj+KXhBYkKYYGAanO YKKZr40gTLUCWVxOsPHvmnrJf3uZFhZQD/MtiR/7evTm198uJkmW51m4Opdei05bAf/MvoL8UQN G/jb9/8Z1sfCDXixzoKaU5bvi8ZRL9Qwkz/Mgys43mjMjFNEs9VzSpoZnsR5a/PTJ0wOrkqrGvQ jos9EmVetuTz/UgQUljsHc/7SzgssaDTXIXZITBfe/cg8dGbnzaPXcCAg8Q+TQTpOszZQyFkZHO X9/mFqGOiKhg/kWm6f4OKeGSkB0ZrYfJVX8mGLvt8ETw8QAa4zXc2PhAM5NoPDyK6VSqN34H74V E1QnkBORQpuf8yDZ+9yvPv1I6LRdqJ8+wgyT0pXrVJDH5+9WY6sPjiDW+erZnxc3AoCedb12pJ8 MO6yzuwNZi6FSY7QSqSHVPzewpGRD95nOBaCEB21Wz+nXoe2rvvKdSxIO5k3bSX999cJ7PYcfO/ 9raPmjNXOWE3epr+3HJ9w== X-Received: by 2002:a05:600c:46d5:b0:492:4667:8c40 with SMTP id 5b1f17b1804b1-493b718fb6emr8183305e9.8.1782734435766; Mon, 29 Jun 2026 05:00:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/54] hw/timer/imx_epit: Replace DPRINTF with trace events Date: Mon, 29 Jun 2026 12:59:39 +0100 Message-ID: <20260629120032.1645265-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735255095158500 From: jack wang <163wangjack@gmail.com> Clean up the codebase by removing the outdated DEBUG_IMX_EPIT and DPRINTF macros, replacing them with modern QEMU trace events. This also removes an empty and meaningless DPRINTF("\n") in the imx_epit_realize function. Signed-off-by: jack wang <163wangjack@gmail.com> Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260617161406.14705-1-163wangjack@gmail.com [PMM: remove stray blank lines from bottom of trace-events file] Signed-off-by: Peter Maydell --- hw/timer/imx_epit.c | 25 +++++-------------------- hw/timer/trace-events | 6 ++++++ 2 files changed, 11 insertions(+), 20 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index c67a39f10c..374ec7d324 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -20,18 +20,7 @@ #include "hw/misc/imx_ccm.h" #include "qemu/module.h" #include "qemu/log.h" - -#ifndef DEBUG_IMX_EPIT -#define DEBUG_IMX_EPIT 0 -#endif - -#define DPRINTF(fmt, args...) \ - do { \ - if (DEBUG_IMX_EPIT) { \ - fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_EPIT, \ - __func__, ##args); \ - } \ - } while (0) +#include "trace.h" =20 static const char *imx_epit_reg_name(uint32_t reg) { @@ -80,7 +69,7 @@ static uint32_t imx_epit_get_freq(IMXEPITState *s) uint32_t prescaler =3D 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRES= CALE_BITS); uint32_t f_in =3D imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[= clksrc]); uint32_t freq =3D f_in / prescaler; - DPRINTF("ptimer frequency is %u\n", freq); + trace_imx_epit_get_freq(freq); return freq; } =20 @@ -146,8 +135,7 @@ static uint64_t imx_epit_read(void *opaque, hwaddr offs= et, unsigned size) HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); break; } - - DPRINTF("(%s) =3D 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value= ); + trace_imx_epit_read(imx_epit_reg_name(offset >> 2), reg_value); =20 return reg_value; } @@ -328,8 +316,7 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, { IMXEPITState *s =3D IMX_EPIT(opaque); =20 - DPRINTF("(%s, value =3D 0x%08x)\n", imx_epit_reg_name(offset >> 2), - (uint32_t)value); + trace_imx_epit_write(imx_epit_reg_name(offset >> 2), value); =20 switch (offset >> 2) { case 0: /* CR */ @@ -362,7 +349,7 @@ static void imx_epit_cmp(void *opaque) /* The cmp ptimer can't be running when the peripheral is disabled */ assert(s->cr & CR_EN); =20 - DPRINTF("sr was %d\n", s->sr); + trace_imx_epit_cmp(s->sr); /* Set interrupt status bit SR.OCIF and update the interrupt state */ s->sr |=3D SR_OCIF; imx_epit_update_int(s); @@ -399,8 +386,6 @@ static void imx_epit_realize(DeviceState *dev, Error **= errp) IMXEPITState *s =3D IMX_EPIT(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); =20 - DPRINTF("\n"); - sysbus_init_irq(sbd, &s->irq); memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX= _EPIT, 0x00001000); diff --git a/hw/timer/trace-events b/hw/timer/trace-events index ac5afe84e8..634ba1da27 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -122,3 +122,9 @@ hpet_ram_write_tn_cmp(uint8_t reg_off) "hpet_ram_writel= HPET_TN_CMP + %" PRIu8 hpet_ram_write_invalid_tn_cmp(void) "invalid HPET_TN_CMP + 4 write" hpet_ram_write_invalid(void) "invalid hpet_ram_writel" hpet_ram_write_counter_write_while_enabled(void) "Writing counter while HP= ET enabled!" + +# imx_epit.c +imx_epit_get_freq(uint32_t freq) "ptimer frequency is %u" +imx_epit_read(const char *name, uint32_t value) "(%s) =3D 0x%08x" +imx_epit_write(const char *name, uint64_t value) "(%s, value =3D 0x%08" PR= Ix64 ")" +imx_epit_cmp(uint32_t sr) "sr was %d" --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fixes: 2430d49a17c9 ("target/arm: Enable FEAT_FPMR for -cpu max") Reported-by: Dillon Sharlet Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260618040718.572950-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 86aae36ae5..128c78f6cf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -421,6 +421,10 @@ static void arm_cpu_reset_hold(Object *obj, ResetType = type) env->cp15.mdscr_el1 |=3D 1 << 12; /* Enable FEAT_MOPS */ env->cp15.sctlr_el[1] |=3D SCTLR_MSCEN; + /* Enable FEAT_FPMR */ + if (cpu_isar_feature(aa64_fpmr, cpu)) { + env->cp15.sctlr_el[1] |=3D SCTLR_EnFPM; + } /* For Linux, GCSPR_EL0 is always readable. */ if (cpu_isar_feature(aa64_gcs, cpu)) { env->cp15.gcscr_el[0] =3D GCSCRE0_NTR; --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735122; cv=none; d=zohomail.com; s=zohoarc; b=U0s5N6ry3KB+1/+yQyHhTOraPleqLYraUWHy2NxwpXlJYIukI3Eswe8zY9yE7r2KWJNdJk7qcWMHRAoIHZw0yfSG+o8ZWK9buNWZ2z7bxojd86qnQg5Uv0yiPZmUhjNd9whu+HKOYp4Zvr9HOkDxvPFd6L/0LkWZWMvyU5yZnow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735122; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=zzb+ngrcMV7t/VoMg3XUGX/7GW0Bksnjz6fJmHX6u5A=; b=H6cpvvwCRGYFokrAfhpf10iPLl/bKPBUFsDLD4cGMvOST2vtnjte7OWazlJKkm8qdguT8Lg9WBhGKM8maVnjF+w2et4VNBOPyrbEBZZL7NldEWB422RdWQTV+iNlC8QQ2ncPP65DRf5Sk7kETKSVpsxVHQ7JbMDNNaZWcu/EhGc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735122267445.1393029287185; Mon, 29 Jun 2026 05:12:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAg7-00075W-Vl; Mon, 29 Jun 2026 08:01:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfK-0006pZ-Eo for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:47 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfI-0007J1-IJ for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:42 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-47231f1f8f3so2283305f8f.1 for ; Mon, 29 Jun 2026 05:00:39 -0700 (PDT) Received: from lanath.. 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Mon, 29 Jun 2026 05:00:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/54] target/arm: Implement EXPAND Date: Mon, 29 Jun 2026 12:59:41 +0100 Message-ID: <20260629120032.1645265-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735124220158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260618040718.572950-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve-defs.h | 5 +++++ target/arm/tcg/sve.decode | 2 ++ target/arm/tcg/sve_helper.c | 26 ++++++++++++++++++++++++++ target/arm/tcg/translate-sve.c | 7 +++++++ 4 files changed, 40 insertions(+) diff --git a/target/arm/tcg/helper-sve-defs.h b/target/arm/tcg/helper-sve-d= efs.h index de2254bb19..1d9066dcbb 100644 --- a/target/arm/tcg/helper-sve-defs.h +++ b/target/arm/tcg/helper-sve-defs.h @@ -3203,3 +3203,8 @@ DEF_HELPER_FLAGS_6(sve2_famin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_6(sve2_famin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(sve_expand_b, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_expand_h, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_expand_s, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_expand_d, TCG_CALL_NO_WG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 2795c2ec7f..5ec1d420c2 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -742,6 +742,8 @@ SPLICE 00000101 .. 101 100 100 ... ..... .....= @rdn_pg_rm # SVE2 vector splice (predicated, constructive) SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn =20 +EXPAND 00000101 .. 110 001 100 ... ..... ..... @rd_pg_rn + ### SVE Select Vectors Group =20 # SVE select vector elements (predicated) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index a0a189eb1e..2517362189 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -3671,6 +3671,32 @@ void HELPER(sve_compact_d)(void *vd, void *vn, void = *vg, uint32_t desc) } } =20 +#define DO_EXPAND(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \ +{ \ + intptr_t oprsz =3D simd_oprsz(desc); \ + ARMVectorReg tmp_n =3D *(ARMVectorReg *)vn; \ + for (intptr_t i =3D 0, j =3D 0; i < oprsz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + TYPE nn =3D 0; \ + if (pg & 1) { \ + nn =3D *(TYPE *)((void *)&tmp_n + H(j)); \ + j +=3D sizeof(TYPE); \ + } \ + *(TYPE *)(vd + H(i)) =3D nn; \ + i +=3D sizeof(TYPE); \ + pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +DO_EXPAND(sve_expand_b, uint8_t, H1) +DO_EXPAND(sve_expand_h, uint16_t, H1_2) +DO_EXPAND(sve_expand_s, uint32_t, H1_4) +DO_EXPAND(sve_expand_d, uint64_t, H1_8) + +#undef DO_EXPAND /* Similar to the ARM LastActiveElement pseudocode function, except the * result is multiplied by the element size. This includes the not found * indication; e.g. not found for esz=3D3 is -8. diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 9a72e03513..57c21a13e8 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -6956,6 +6956,13 @@ static gen_helper_gvec_3 * const sqneg_fns[4] =3D { TRANS_FEAT(SQNEG_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->e= sz], a, 0) TRANS_FEAT(SQNEG_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, sqneg_fns= [a->esz], a, 1) =20 +static gen_helper_gvec_3 * const expand_fns[4] =3D { + gen_helper_sve_expand_b, gen_helper_sve_expand_h, + gen_helper_sve_expand_s, gen_helper_sve_expand_d, +}; +TRANS_FEAT_STREAMING_IF(EXPAND, aa64_sme2p2_or_sve2p2, aa64_sme2p2, + gen_gvec_ool_arg_zpz, expand_fns[a->esz], a, 0) + DO_ZPZZ(SQSHL, aa64_sme_or_sve2, sve2_sqshl) DO_ZPZZ(SQRSHL, aa64_sme_or_sve2, sve2_sqrshl) DO_ZPZZ(SRSHL, aa64_sme_or_sve2, sve2_srshl) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735124; cv=none; d=zohomail.com; s=zohoarc; b=Kcy304EBZJF6MIy9OwybWem2dhBI6YsuiiTVZCsSVlWhtkU17z50yIHnY+4zmX6CGd7V8cW5R6Qp+Tbh/DEmnGM1LFugQebxS+Bhmb8qlhSnO4QcYAUtw1UNDdd2nOOEUyH1Qr5MlTxGDrgUSiQ+Fp5o2YcJ700o+zrdqE6nm+Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735124; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=YqFJCC+KvfJZ0ogi6P9IwtcgoHH7mCUbydKh3+PQeEg=; b=fPh+P08D/u9OT2SBWWNdQewmqei26l0jbYmzsjnylXoSHLUuMh9SuCxBfwvjaT3g3zDWbUwDmz73wUfzmBgfzoiyKKeYCJ9f0oWbasvcwvNHt3o33TweXzkyyaMqYyRApLA+flRPEuuh/nlfz0RDzOHL8O3SFWvmpzLvCglIQys= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735124122556.5865311775273; Mon, 29 Jun 2026 05:12:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAg3-00074J-PD; Mon, 29 Jun 2026 08:01:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfK-0006pY-7o for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:46 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfI-0007JI-J7 for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:41 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-493a7bd27c2so11481885e9.3 for ; Mon, 29 Jun 2026 05:00:40 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260618040718.572950-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_helper.c | 51 +++++++++++++++---------------------- 1 file changed, 21 insertions(+), 30 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 2517362189..9b45b0d331 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -3637,39 +3637,30 @@ DO_TRN(sve2_trn_q, Int128, ) #undef DO_UZP #undef DO_TRN =20 -void HELPER(sve_compact_s)(void *vd, void *vn, void *vg, uint32_t desc) -{ - intptr_t i, j, opr_sz =3D simd_oprsz(desc) / 4; - uint32_t *d =3D vd, *n =3D vn; - uint8_t *pg =3D vg; - - for (i =3D j =3D 0; i < opr_sz; i++) { - if (pg[H1(i / 2)] & (i & 1 ? 0x10 : 0x01)) { - d[H4(j)] =3D n[H4(i)]; - j++; - } - } - for (; j < opr_sz; j++) { - d[H4(j)] =3D 0; - } +#define DO_COMPACT(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \ +{ \ + intptr_t j =3D 0, oprsz =3D simd_oprsz(desc); \ + for (intptr_t i =3D 0; i < oprsz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)(vd + H(j)) =3D *(TYPE *)(vn + H(i)); \ + j +=3D sizeof(TYPE); \ + } \ + i +=3D sizeof(TYPE); \ + pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ + for (; j < oprsz; j +=3D sizeof(TYPE)) { \ + *(TYPE *)(vd + H(j)) =3D 0; \ + } \ } =20 -void HELPER(sve_compact_d)(void *vd, void *vn, void *vg, uint32_t desc) -{ - intptr_t i, j, opr_sz =3D simd_oprsz(desc) / 8; - uint64_t *d =3D vd, *n =3D vn; - uint8_t *pg =3D vg; +DO_COMPACT(sve_compact_s, uint32_t, H1_4) +DO_COMPACT(sve_compact_d, uint64_t, H1_8) =20 - for (i =3D j =3D 0; i < opr_sz; i++) { - if (pg[H1(i)] & 1) { - d[j] =3D n[i]; - j++; - } - } - for (; j < opr_sz; j++) { - d[j] =3D 0; - } -} +#undef DO_COMPACT =20 #define DO_EXPAND(NAME, TYPE, H) \ void HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \ --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734575; cv=none; d=zohomail.com; s=zohoarc; b=bttnu9YqtLxEPRSm9WYUX6fVVQAEtiqrw4VYv8rB+pHnYwU5119u3s6GDHjOsndGHtfIhUzn72CqdY4GLulvOrCOXnoH06gTnq+1fL/iULv2+1h85AnwBrdzSmgb7oxyEaa4QGOdBPtYdkem2qm/3xWRguMdWkCewD5wgHBGkmw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734575; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=GcrC4AtoY+vXqBjgHK/kJhXaOE665auUSmXZjlmsf0s=; b=PrTZctlcsuIeAc4jBRLgrIklyop21VealwL18HqLmdRwgGxdgz6wUPCm/MIwwiTnsrx8+64w68VIQLvNVP3zHl0/ES5lBdl+Wk9o2hi6liGiZP/57S8wlbdlZFPnrsTu+iMCZ5yF7E0sAThjmJz96qZP2qcgbLt6o009fm7WGL0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734575319586.2944060044018; Mon, 29 Jun 2026 05:02:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAfm-0006yS-FS; Mon, 29 Jun 2026 08:01:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfL-0006pe-Hg for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:47 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfJ-0007JR-E6 for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:43 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-47122683cf3so839662f8f.0 for ; Mon, 29 Jun 2026 05:00:41 -0700 (PDT) Received: from lanath.. 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Mon, 29 Jun 2026 05:00:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/54] target/arm: Implement COMPACT for byte/halfword Date: Mon, 29 Jun 2026 12:59:43 +0100 Message-ID: <20260629120032.1645265-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734577300158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260618040718.572950-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve-defs.h | 2 ++ target/arm/tcg/sve.decode | 1 - target/arm/tcg/sve_helper.c | 2 ++ target/arm/tcg/translate-sve.c | 22 +++++++++++++++++----- 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/helper-sve-defs.h b/target/arm/tcg/helper-sve-d= efs.h index 1d9066dcbb..b64a0faa19 100644 --- a/target/arm/tcg/helper-sve-defs.h +++ b/target/arm/tcg/helper-sve-defs.h @@ -733,6 +733,8 @@ DEF_HELPER_FLAGS_4(sve_trn_s, TCG_CALL_NO_RWG, void, pt= r, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_trn_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve2_trn_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sve_compact_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sve_compact_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(sve_compact_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(sve_compact_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) =20 diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 5ec1d420c2..a3eefd60e5 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -693,7 +693,6 @@ TBXQ 00000101 .. 1 ..... 001 101 ..... .....= @rd_rn_rm ### SVE Permute - Predicated Group =20 # SVE compress active elements -# Note esz >=3D 2 COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn =20 # SVE conditionally broadcast element to vector diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 9b45b0d331..bd8fa2da7e 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -3657,6 +3657,8 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, uint3= 2_t desc) \ } \ } =20 +DO_COMPACT(sve_compact_b, uint8_t, H1) +DO_COMPACT(sve_compact_h, uint16_t, H1_2) DO_COMPACT(sve_compact_s, uint32_t, H1_4) DO_COMPACT(sve_compact_d, uint64_t, H1_8) =20 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 57c21a13e8..01199dbd78 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -2769,11 +2769,23 @@ TRANS_FEAT_NONSTREAMING(TRN2_q, aa64_sve_f64mm, do_= interleave_q, *** SVE Permute Vector - Predicated Group */ =20 -static gen_helper_gvec_3 * const compact_fns[4] =3D { - NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d -}; -TRANS_FEAT_NONSTREAMING(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, - compact_fns[a->esz], a, 0) +static bool trans_COMPACT(DisasContext *s, arg_COMPACT *a) +{ + static gen_helper_gvec_3 * const fns[4] =3D { + gen_helper_sve_compact_b, gen_helper_sve_compact_h, + gen_helper_sve_compact_s, gen_helper_sve_compact_d + }; + + if (!dc_isar_feature(aa64_sme2p2, s)) { + if (!(a->esz >=3D MO_32 + ? dc_isar_feature(aa64_sve, s) + : dc_isar_feature(aa64_sve2p2, s))) { + return false; + } + s->is_nonstreaming =3D true; + } + return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0); +} =20 /* Call the helper that computes the ARM LastActiveElement pseudocode * function, scaled by the element size. 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Mon, 29 Jun 2026 05:00:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/54] target/arm: Implement FIRSTP, LASTP Date: Mon, 29 Jun 2026 12:59:44 +0100 Message-ID: <20260629120032.1645265-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735252888158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260618040718.572950-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve-defs.h | 3 ++ target/arm/tcg/sve.decode | 3 ++ target/arm/tcg/sve_helper.c | 30 +++++++++++++++++ target/arm/tcg/translate-sve.c | 56 ++++++++++++++++++++++++++++++++ 4 files changed, 92 insertions(+) diff --git a/target/arm/tcg/helper-sve-defs.h b/target/arm/tcg/helper-sve-d= efs.h index b64a0faa19..19bd936f6e 100644 --- a/target/arm/tcg/helper-sve-defs.h +++ b/target/arm/tcg/helper-sve-defs.h @@ -961,6 +961,9 @@ DEF_HELPER_FLAGS_4(sve_brkns, TCG_CALL_NO_RWG, i32, ptr= , ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_cntp, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) DEF_HELPER_FLAGS_2(sve2p1_cntp_c, TCG_CALL_NO_RWG_SE, i64, i32, i32) =20 +DEF_HELPER_FLAGS_3(sve_firstp, TCG_CALL_NO_RWG_SE, i64, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sve_lastp, TCG_CALL_NO_RWG_SE, i64, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(sve_whilel, TCG_CALL_NO_RWG, i32, ptr, i32, i32) DEF_HELPER_FLAGS_3(sve_whileg, TCG_CALL_NO_RWG, i32, ptr, i32, i32) =20 diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index a3eefd60e5..bdc2b7f0c0 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -852,6 +852,9 @@ BRKN 00100101 0. 01100001 .... 0 .... 0 ....= @pd_pg_pn_s CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn CNTP_c 00100101 esz:2 100 000 10 000 vl:1 1 rn:4 rd:5 =20 +FIRSTP 00100101 .. 100 001 10 .... 0 .... ..... @rd_pg4_pn +LASTP 00100101 .. 100 010 10 .... 0 .... ..... @rd_pg4_pn + # SVE inc/dec register by predicate count INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred= u=3D1 =20 diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index bd8fa2da7e..b2875a559b 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -4328,6 +4328,36 @@ uint64_t HELPER(sve2p1_cntp_c)(uint32_t png, uint32_= t desc) return count >> p.lg2_stride; } =20 +uint64_t HELPER(sve_firstp)(void *vn, void *vg, uint32_t pred_desc) +{ + intptr_t words =3D DIV_ROUND_UP(FIELD_EX32(pred_desc, PREDDESC, OPRSZ)= , 8); + intptr_t esz =3D FIELD_EX32(pred_desc, PREDDESC, ESZ); + uint64_t *n =3D vn, *g =3D vg, mask =3D pred_esz_masks[esz]; + + for (intptr_t i =3D 0; i < words; ++i) { + uint64_t t =3D n[i] & g[i] & mask; + if (t) { + return (i * 64 + ctz64(t)) >> esz; + } + } + return -1; +} + +uint64_t HELPER(sve_lastp)(void *vn, void *vg, uint32_t pred_desc) +{ + intptr_t words =3D DIV_ROUND_UP(FIELD_EX32(pred_desc, PREDDESC, OPRSZ)= , 8); + intptr_t esz =3D FIELD_EX32(pred_desc, PREDDESC, ESZ); + uint64_t *n =3D vn, *g =3D vg, mask =3D pred_esz_masks[esz]; + + for (intptr_t i =3D words - 1; i >=3D 0; --i) { + uint64_t t =3D n[i] & g[i] & mask; + if (t) { + return (i * 64 + (63 - clz64(t))) >> esz; + } + } + return -1; +} + /* C.f. Arm pseudocode EncodePredCount */ static uint64_t encode_pred_count(uint32_t elements, uint32_t count, uint32_t esz, bool invert) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 01199dbd78..63f64796e5 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3481,6 +3481,62 @@ static bool trans_SINCDECP_z(DisasContext *s, arg_in= cdec2_pred *a) return true; } =20 +static bool do_firstp_lastp(DisasContext *s, arg_rpr_esz *a, bool firstp) +{ + if (sve_access_check(s)) { + unsigned psz =3D pred_full_reg_size(s); + TCGv_i64 v =3D cpu_reg(s, a->rd); + + if (psz <=3D 8) { + uint64_t psz_mask; + + tcg_gen_ld_i64(v, tcg_env, pred_full_reg_offset(s, a->rn)); + if (a->rn !=3D a->pg) { + TCGv_i64 g =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(g, tcg_env, pred_full_reg_offset(s, a->pg)); + tcg_gen_and_i64(v, v, g); + } + + /* + * Reduce the pred_esz_masks value simply to reduce the + * size of the code generated here. + */ + psz_mask =3D MAKE_64BIT_MASK(0, psz * 8); + tcg_gen_andi_i64(v, v, pred_esz_masks[a->esz] & psz_mask); + + if (firstp) { + tcg_gen_ctzi_i64(v, v, -1); + } else { + tcg_gen_clzi_i64(v, v, 64); + tcg_gen_subfi_i64(v, 63, v); + } + tcg_gen_sari_i64(v, v, a->esz); + } else { + TCGv_ptr t_pn =3D tcg_temp_new_ptr(); + TCGv_ptr t_pg =3D tcg_temp_new_ptr(); + unsigned desc =3D 0; + TCGv_i32 t_desc; + + desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, psz); + desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); + + tcg_gen_addi_ptr(t_pn, tcg_env, pred_full_reg_offset(s, a->rn)= ); + tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg)= ); + t_desc =3D tcg_constant_i32(desc); + + if (firstp) { + gen_helper_sve_firstp(v, t_pn, t_pg, t_desc); + } else { + gen_helper_sve_lastp(v, t_pn, t_pg, t_desc); + } + } + } + return true; +} + +TRANS_FEAT(FIRSTP, aa64_sme2p2_or_sve2p2, do_firstp_lastp, a, true) +TRANS_FEAT(LASTP, aa64_sme2p2_or_sve2p2, do_firstp_lastp, a, false) + /* *** SVE Integer Compare Scalars Group */ --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734645; cv=none; d=zohomail.com; s=zohoarc; b=f1UbaTDyOrPqeLwgnVZiNoyMThm9uetiaqMBQk/es7bCa4z1quAZUue2/S2+0ZQ8lIflBixZG9fL8htuhHSWWmDj/KWqVDgjB94iOL+/vDv784LNx1Yrw2WfwLpSqgLlceee06GuTuoorT2YhcYHnIkmEh1kjm6TyIHwapIgOdc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734645; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=+eAs302DE7f4GmSyP0JJV9n2j02SGwYGE/QqXwuEST8=; b=mEujx4AK8ujfR15R0m6Z+xd5rqdTAlFvZzEdUT2hT4s4/6hFkyfo8o2nGLSZWw8bEZt962tRnR/p7JIARVF841Ohb/5jyAxQhaccPl5NOthviC/8PJQjt/KIW5wlneFTia8zkONnapn7YoQB8r6kTSODsVl8pK3JVYnBt/BTyEI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734645496949.3524960252872; Mon, 29 Jun 2026 05:04:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAfo-00070V-51; Mon, 29 Jun 2026 08:01:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfa-0006tH-Og for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:03 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfV-0007NE-7j for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:56 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-474303f3c72so434821f8f.0 for ; Mon, 29 Jun 2026 05:00:51 -0700 (PDT) Received: from lanath.. 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Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260618040718.572950-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- bsd-user/aarch64/target_arch_elf.h | 2 +- linux-user/aarch64/elfload.c | 2 +- target/arm/cpu-features.h | 2 +- target/arm/tcg/translate-sve.c | 8 ++++---- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_a= rch_elf.h index 5ea5232a57..2fb7dcd778 100644 --- a/bsd-user/aarch64/target_arch_elf.h +++ b/bsd-user/aarch64/target_arch_elf.h @@ -126,7 +126,7 @@ static uint32_t get_elf_hwcap2(void) =20 GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); - GET_FEATURE_ID(aa64_sve2_aes, ARM_HWCAP2_A64_SVEAES); + GET_FEATURE_ID(aa64_sve_aes, ARM_HWCAP2_A64_SVEAES); GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL); GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM); GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 4887a3a7b7..3479e61a12 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -184,7 +184,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) =20 GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); - GET_FEATURE_ID(aa64_sve2_aes, ARM_HWCAP2_A64_SVEAES); + GET_FEATURE_ID(aa64_sve_aes, ARM_HWCAP2_A64_SVEAES); GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL); GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM); GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index a80b251589..af843b32d3 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1524,7 +1524,7 @@ static inline bool isar_feature_aa64_sve2p2(const ARM= ISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >=3D 3; } =20 -static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) +static inline bool isar_feature_aa64_sve_aes(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) !=3D 0; } diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 63f64796e5..9f0f0e0e12 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -8174,14 +8174,14 @@ TRANS_FEAT(SDOT_zzzz_2s, aa64_sme2_or_sve2p1, gen_g= vec_ool_arg_zzzz, TRANS_FEAT(UDOT_zzzz_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzzz, gen_helper_gvec_udot_2h, a, 0) =20 -TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, +TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve_aes, gen_gvec_ool_zz, gen_helper_crypto_aesmc, a->rd, a->rd, 0) -TRANS_FEAT_NONSTREAMING(AESIMC, aa64_sve2_aes, gen_gvec_ool_zz, +TRANS_FEAT_NONSTREAMING(AESIMC, aa64_sve_aes, gen_gvec_ool_zz, gen_helper_crypto_aesimc, a->rd, a->rd, 0) =20 -TRANS_FEAT_NONSTREAMING(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, +TRANS_FEAT_NONSTREAMING(AESE, aa64_sve_aes, gen_gvec_ool_arg_zzz, gen_helper_crypto_aese, a, 0) -TRANS_FEAT_NONSTREAMING(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, +TRANS_FEAT_NONSTREAMING(AESD, aa64_sve_aes, gen_gvec_ool_arg_zzz, gen_helper_crypto_aesd, a, 0) =20 TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260618040718.572950-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + linux-user/aarch64/elfload.c | 1 + target/arm/cpu-features.h | 5 +++++ target/arm/tcg/cpu64.c | 1 + target/arm/tcg/translate-sve.c | 20 +++++++++++--------- 5 files changed, 19 insertions(+), 9 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index a8072ddb67..0b4623139a 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -171,6 +171,7 @@ the following architecture extensions: - FEAT_SME_F64F64 (Double-precision floating-point outer product instructi= ons) - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instruc= tions) - FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit e= lements) +- FEAT_SSVE_AES (Streaming SVE Mode Advanced Encryption Standard and 128-b= it polynomial multiply long instructions) - FEAT_SSVE_FP8DOT2 (SVE2 FP8 2-way dot product to half-precision instruct= ions in Streaming SVE mode) - FEAT_SSVE_FP8DOT4 (SVE2 FP8 4-way dot product to single-precision instru= ctions in Streaming SVE mode) - FEAT_SSVE_FP8FMA (SVE2 FP8 multiply-accumulate to half-precision and sin= gle-precision instructions in Streaming SVE mode) diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 3479e61a12..0f96bbe70b 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -173,6 +173,7 @@ abi_ulong get_elf_hwcap(CPUState *cs) GET_FEATURE_ID(aa64_cmpbr, ARM_HWCAP_A64_CMPBR); GET_FEATURE_ID(aa64_f8mm8, ARM_HWCAP_A64_F8MM8); GET_FEATURE_ID(aa64_f8mm4, ARM_HWCAP_A64_F8MM4); + GET_FEATURE_ID(aa64_ssve_aes, ARM_HWCAP_A64_SME_AES); =20 return hwcaps; } diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index af843b32d3..c07bcb0a73 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1575,6 +1575,11 @@ static inline bool isar_feature_aa64_sve_b16b16(cons= t ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16); } =20 +static inline bool isar_feature_aa64_ssve_aes(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, AES); +} + static inline bool isar_feature_aa64_ssve_f8fma(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index f7a920a202..e4a8d7a2f6 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1383,6 +1383,7 @@ void aarch64_max_tcg_initfn(Object *obj) SET_IDREG(isar, ID_AA64DFR0, t); =20 t =3D GET_IDREG(isar, ID_AA64SMFR0); + t =3D FIELD_DP64(t, ID_AA64SMFR0, AES, 1); /* FEAT_SSVE_AES */ t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP2, 1); /* FEAT_SSVE_FP8DOT2 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8DP4, 1); /* FEAT_SSVE_FP8DOT4 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* FEAT_SSVE_FP8FMA */ diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 9f0f0e0e12..79e8e16b24 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -7169,7 +7169,7 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_e= sz *a, bool sel) if (!dc_isar_feature(aa64_sve2_pmull128, s)) { return false; } - s->is_nonstreaming =3D true; + s->is_nonstreaming =3D !dc_isar_feature(aa64_ssve_aes, s); } return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); } @@ -8174,15 +8174,17 @@ TRANS_FEAT(SDOT_zzzz_2s, aa64_sme2_or_sve2p1, gen_g= vec_ool_arg_zzzz, TRANS_FEAT(UDOT_zzzz_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzzz, gen_helper_gvec_udot_2h, a, 0) =20 -TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve_aes, gen_gvec_ool_zz, - gen_helper_crypto_aesmc, a->rd, a->rd, 0) -TRANS_FEAT_NONSTREAMING(AESIMC, aa64_sve_aes, gen_gvec_ool_zz, - gen_helper_crypto_aesimc, a->rd, a->rd, 0) +TRANS_FEAT_STREAMING_IF(AESMC, aa64_sve_aes, aa64_ssve_aes, + gen_gvec_ool_zz, gen_helper_crypto_aesmc, + a->rd, a->rd, 0) +TRANS_FEAT_STREAMING_IF(AESIMC, aa64_sve_aes, aa64_ssve_aes, + gen_gvec_ool_zz, gen_helper_crypto_aesimc, + a->rd, a->rd, 0) =20 -TRANS_FEAT_NONSTREAMING(AESE, aa64_sve_aes, gen_gvec_ool_arg_zzz, - gen_helper_crypto_aese, a, 0) -TRANS_FEAT_NONSTREAMING(AESD, aa64_sve_aes, gen_gvec_ool_arg_zzz, - gen_helper_crypto_aesd, a, 0) +TRANS_FEAT_STREAMING_IF(AESE, aa64_sve_aes, aa64_ssve_aes, + gen_gvec_ool_arg_zzz, gen_helper_crypto_aese, a, 0) +TRANS_FEAT_STREAMING_IF(AESD, aa64_sve_aes, aa64_ssve_aes, + gen_gvec_ool_arg_zzz, gen_helper_crypto_aesd, a, 0) =20 TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, gen_helper_crypto_sm4e, a, 0) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260618040718.572950-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_helper.c | 43 ++++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index b2875a559b..ac96b18784 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -917,12 +917,45 @@ DO_ZPZ(sve_ah_fneg_h, uint16_t, H1_2, DO_AH_FNEG_H) DO_ZPZ(sve_ah_fneg_s, uint32_t, H1_4, DO_AH_FNEG_S) DO_ZPZ_D(sve_ah_fneg_d, uint64_t, DO_AH_FNEG_D) =20 -#define DO_NOT(N) (~N) +static inline void +sve_not_zpz(uint64_t *d, uint64_t *n, uint8_t *pg, uint32_t desc, + uint64_t (*expand)(uint8_t)) +{ + intptr_t opr_sz =3D simd_oprsz(desc) / 8; + bool zeroing =3D simd_data(desc) & 1; =20 -DO_ZPZ(sve_not_zpz_b, uint8_t, H1, DO_NOT) -DO_ZPZ(sve_not_zpz_h, uint16_t, H1_2, DO_NOT) -DO_ZPZ(sve_not_zpz_s, uint32_t, H1_4, DO_NOT) -DO_ZPZ_D(sve_not_zpz_d, uint64_t, DO_NOT) + if (zeroing) { + for (intptr_t i =3D 0; i < opr_sz; ++i) { + uint64_t p =3D expand(pg[H1(i)]); + d[i] =3D ~n[i] & p; + } + } else { + for (intptr_t i =3D 0; i < opr_sz; ++i) { + uint64_t p =3D expand(pg[H1(i)]); + d[i] =3D (~n[i] & p) | (d[i] & ~p); + } + } +} + +void HELPER(sve_not_zpz_b)(void *vd, void *vn, void *pg, uint32_t desc) +{ + sve_not_zpz(vd, vn, pg, desc, expand_pred_b); +} + +void HELPER(sve_not_zpz_h)(void *vd, void *vn, void *pg, uint32_t desc) +{ + sve_not_zpz(vd, vn, pg, desc, expand_pred_h); +} + +void HELPER(sve_not_zpz_s)(void *vd, void *vn, void *pg, uint32_t desc) +{ + sve_not_zpz(vd, vn, pg, desc, expand_pred_s); +} + +void HELPER(sve_not_zpz_d)(void *vd, void *vn, void *pg, uint32_t desc) +{ + sve_not_zpz(vd, vn, pg, desc, expand_pred_d); +} =20 #define DO_SXTB(N) ((int8_t)N) #define DO_SXTH(N) ((int16_t)N) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734498; cv=none; d=zohomail.com; s=zohoarc; b=VWofkVHcuUUROHa7X/itzDwxLj7ieCod1Kpt42HobxdzuYjxAEqVImUZi2wYvweMtyItNuC4P5njJxcOQgeotfVrqupRiIwFbGSMxnbZ14inz0gCXL8vmES65gX+/VLLBITkaToJSBDXuIMkPhMa3GJNT40pM/Mt/8N+H8q+tzk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734498; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7lR7Tonf1+bbpt3Sq4KZxZhoKMSzg6FEvdecxKcxMM8=; b=GXAgW2UX6ZPyDwGNTdAKff5t+Yr7jjVnPGIWjckHqo834wtmuuh7in32DITnNZKWYvmire+dx4GD38zXzlGeprGy4+6QOOXi6lUvHoB9dzkRzjBYHdt7jhuNQEC3pMM1hQIxOT/emKMORQZaw8miqkJkZhcN6d/8dfMMnSdBJnI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734498865237.551339195487; Mon, 29 Jun 2026 05:01:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAg9-000767-8H; Mon, 29 Jun 2026 08:01:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfQ-0006qq-Uv for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:50 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfP-0007LZ-9V for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:48 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-47122683cf3so839794f8f.0 for ; Mon, 29 Jun 2026 05:00:46 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260618041517.573469-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme_helper.c | 33 --------------------------------- target/arm/tcg/vec_internal.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 33 deletions(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 8e8e6c00ca..685b6b46be 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -64,39 +64,6 @@ void helper_sme_zero(CPUARMState *env, uint32_t imm, uin= t32_t svl) } } =20 - -/* - * When considering the ZA storage as an array of elements of - * type T, the index within that array of the Nth element of - * a vertical slice of a tile can be calculated like this, - * regardless of the size of type T. This is because the tiles - * are interleaved, so if type T is size N bytes then row 1 of - * the tile is N rows away from row 0. The division by N to - * convert a byte offset into an array index and the multiplication - * by N to convert from vslice-index-within-the-tile to - * the index within the ZA storage cancel out. - */ -#define tile_vslice_index(i) ((i) * sizeof(ARMVectorReg)) - -/* - * When doing byte arithmetic on the ZA storage, the element - * byteoff bytes away in a tile vertical slice is always this - * many bytes away in the ZA storage, regardless of the - * size of the tile element, assuming that byteoff is a multiple - * of the element size. Again this is because of the interleaving - * of the tiles. For instance if we have 1 byte per element then - * each row of the ZA storage has one byte of the vslice data, - * and (counting from 0) byte 8 goes in row 8 of the storage - * at offset (8 * row-size-in-bytes). - * If we have 8 bytes per element then each row of the ZA storage - * has 8 bytes of the data, but there are 8 interleaved tiles and - * so byte 8 of the data goes into row 1 of the tile, - * which is again row 8 of the storage, so the offset is still - * (8 * row-size-in-bytes). Similarly for other element sizes. - */ -#define tile_vslice_offset(byteoff) ((byteoff) * sizeof(ARMVectorReg)) - - /* * Move Zreg vector to ZArray column. */ diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index 06fef2a209..77e5b01550 100644 --- a/target/arm/tcg/vec_internal.h +++ b/target/arm/tcg/vec_internal.h @@ -55,6 +55,37 @@ typedef struct CPUArchState CPUARMState; #define H8(x) (x) #define H1_8(x) (x) =20 +/* + * When considering the ZA storage as an array of elements of + * type T, the index within that array of the Nth element of + * a vertical slice of a tile can be calculated like this, + * regardless of the size of type T. This is because the tiles + * are interleaved, so if type T is size N bytes then row 1 of + * the tile is N rows away from row 0. The division by N to + * convert a byte offset into an array index and the multiplication + * by N to convert from vslice-index-within-the-tile to + * the index within the ZA storage cancel out. + */ +#define tile_vslice_index(i) ((i) * sizeof(ARMVectorReg)) + +/* + * When doing byte arithmetic on the ZA storage, the element + * byteoff bytes away in a tile vertical slice is always this + * many bytes away in the ZA storage, regardless of the + * size of the tile element, assuming that byteoff is a multiple + * of the element size. Again this is because of the interleaving + * of the tiles. For instance if we have 1 byte per element then + * each row of the ZA storage has one byte of the vslice data, + * and (counting from 0) byte 8 goes in row 8 of the storage + * at offset (8 * row-size-in-bytes). + * If we have 8 bytes per element then each row of the ZA storage + * has 8 bytes of the data, but there are 8 interleaved tiles and + * so byte 8 of the data goes into row 1 of the tile, + * which is again row 8 of the storage, so the offset is still + * (8 * row-size-in-bytes). Similarly for other element sizes. + */ +#define tile_vslice_offset(byteoff) ((byteoff) * sizeof(ARMVectorReg)) + /* * Expand active predicate bits to bytes, for byte elements. */ --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735119; cv=none; d=zohomail.com; s=zohoarc; b=CBQv+RZ58yIR2jRyIuUXAmj7WH/KAbIM9Lnh1zqm7APac2sljn+LsiTRWCvUDTQZ540OH/KqilVSZA2jGZcede50Em9P+chbvX5i8Z+gK+UKTClJJQ/IAuqsP8+rRdgQXPPQ0bRpKZQqcetHvE+zgG1NSCfgI1nWqZthkTr+xlw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735119; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=EgCSUfF3fVYqj1i+7Q5vqzIEq5SCrDOg8aKzKrq3nhY=; b=PJpw58KBWlXWuWcd2Ex5jB/S2FekNucNIWRshxPdvrWhdY4IophU3jv6bfrelrdd8cwIs+i0CNuFVH0QKpeKvpeFDW0JCD58JBq9nL05Q3t39o1EpLQQC98eOIVZCOs4y2dYr3jUyjzKMgGlahCGGCRy53Qle51SD7y6Is5d5c4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735119466680.5316942529024; Mon, 29 Jun 2026 05:11:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgI-0007MR-ME; Mon, 29 Jun 2026 08:01:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfc-0006uJ-Q3 for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:03 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfW-0007NT-LJ for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:00:58 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-461edb387ddso3087460f8f.3 for ; Mon, 29 Jun 2026 05:00:51 -0700 (PDT) Received: from lanath.. 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Mon, 29 Jun 2026 05:00:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/54] target/arm: Implement FMOPA (widening, 4-way fp8 to fp32) Date: Mon, 29 Jun 2026 12:59:49 +0100 Message-ID: <20260629120032.1645265-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735119872158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260618041517.573469-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 5 +++++ target/arm/tcg/fp8_helper.c | 35 ++++++++++++++++++++++++++++++++ target/arm/tcg/helper-fp8-defs.h | 2 ++ target/arm/tcg/sme.decode | 2 ++ target/arm/tcg/translate-sme.c | 19 +++++++++++++++++ 5 files changed, 63 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index c07bcb0a73..45213f71ab 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1600,6 +1600,11 @@ static inline bool isar_feature_aa64_sme_b16b16(cons= t ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16); } =20 +static inline bool isar_feature_aa64_sme_f8f32(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F8F32); +} + static inline bool isar_feature_aa64_sme_f16f16(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F16F16); diff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c index bd0877071b..08e04364fa 100644 --- a/target/arm/tcg/fp8_helper.c +++ b/target/arm/tcg/fp8_helper.c @@ -857,3 +857,38 @@ void HELPER(gvec_fmmla_hb)(void *vd, void *vn, void *v= m, =20 clear_tail(vd, oprsz, simd_maxsz(desc)); } + +void HELPER(sme_fmopa_sb)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, CPUARMState *env, uint32_t desc) +{ + FP8MulContext ctx =3D fp8_mul_start(env, -1); + intptr_t oprsz =3D simd_maxsz(desc); + uint16_t *pn =3D vpn, *pm =3D vpm; + + for (intptr_t row =3D 0; row < oprsz; ) { + uint16_t prow =3D pn[H2(row >> 4)]; + do { + void *vza_row =3D vza + tile_vslice_offset(row); + uint32_t n =3D *(uint32_t *)(vzn + H1_4(row)); + + n &=3D expand_pred_b(prow & 0xf); + + for (intptr_t col =3D 0; col < oprsz; ) { + uint16_t pcol =3D pm[H2(col >> 4)]; + do { + if (prow & pcol & 0xf) { + uint32_t *a =3D vza_row + H1_4(col); + uint32_t m =3D *(uint32_t *)(vzm + H1_4(col)); + + m &=3D expand_pred_b(pcol & 0xf); + *a =3D f8dotadd_s(n, m, 4, *a, &ctx); + } + col +=3D 4; + pcol >>=3D 4; + } while (col & 15); + } + row +=3D 4; + prow >>=3D 4; + } while (row & 15); + } +} diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-d= efs.h index e942308af4..7c090ccad6 100644 --- a/target/arm/tcg/helper-fp8-defs.h +++ b/target/arm/tcg/helper-fp8-defs.h @@ -38,3 +38,5 @@ DEF_HELPER_FLAGS_5(gvec_fdot_idx_hb, TCG_CALL_NO_RWG, voi= d, ptr, ptr, ptr, env, =20 DEF_HELPER_FLAGS_5(gvec_fmmla_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) DEF_HELPER_FLAGS_5(gvec_fmmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) + +DEF_HELPER_FLAGS_7(sme_fmopa_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , ptr, env, i32) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 495330aed7..e668293efd 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -198,6 +198,8 @@ BFMOPA 10000001 101 ..... ... ... ..... . 100 = . @op_16 BFMOPA_w 10000001 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_w_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 =20 +FMOPA_sb 10000000 101 zm:5 pm:3 pn:3 zn:5 0 00 zad:2 &op sub=3D0 + SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32 SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32 USMOPA_s 1010000 1 10 0 ..... ... ... ..... . 00 .. @op_32 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 98d3d18791..63c6e2c9b1 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -616,6 +616,25 @@ TRANS_FEAT(BFMOPA_w, aa64_sme, do_outprod_env, a, MO_3= 2, : !s->fpcr_ah ? gen_helper_sme_bfmops_w : gen_helper_sme_ah_bfmops_w) =20 +static bool trans_FMOPA_sb(DisasContext *s, arg_op *a) +{ + if (!dc_isar_feature(aa64_sme_f8f32, s)) { + return false; + } + if (fpmr_access_check(s) && sme_smza_enabled_check(s)) { + int svl =3D streaming_vec_reg_size(s); + uint32_t desc =3D simd_desc(svl, svl, 0); + + gen_helper_sme_fmopa_sb(get_tile(s, MO_32, a->zad), + vec_full_reg_ptr(s, a->zn), + vec_full_reg_ptr(s, a->zm), + pred_full_reg_ptr(s, a->pn), + pred_full_reg_ptr(s, a->pm), + tcg_env, tcg_constant_i32(desc)); + } + return true; +} + TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s) TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s) TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa= _s) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734571; 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Mon, 29 Jun 2026 05:00:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/54] target/arm: Implement FMLALL (multiple and single vector) Date: Mon, 29 Jun 2026 12:59:50 +0100 Message-ID: <20260629120032.1645265-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734573201158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260618041517.573469-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 4 +++ target/arm/tcg/translate-sme.c | 49 ++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index e668293efd..4956995924 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -445,6 +445,10 @@ FMLS_n1_h 11000001 001 1 .... 0 .. 111 ..... 01 = ... @azz_nx1_o3 n=3D4 FMLS_n1_s 11000001 001 1 .... 0 .. 110 ..... 01 ... @azz_nx1_o3 n= =3D4 FMLS_n1_d 11000001 011 1 .... 0 .. 110 ..... 01 ... @azz_nx1_o3 n= =3D4 =20 +FMLALL_n1_b 11000001 001 1 .... 0 .. 001 ..... 000 .. @azz_nx1_o2x4 = n=3D1 +FMLALL_n1_b 11000001 001 0 .... 0 .. 000 ..... 0001 . @azz_nx1_o1x4 = n=3D2 +FMLALL_n1_b 11000001 001 1 .... 0 .. 000 ..... 0001 . @azz_nx1_o1x4 = n=3D4 + ### SME2 Multi-vector Multiple Array Vectors =20 %zn_ax2 6:4 !function=3Dtimes_2 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 63c6e2c9b1..30487c34a0 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1059,6 +1059,47 @@ static bool do_azz_acc_fp(DisasContext *s, int nreg,= int nsel, return true; } =20 +static bool do_azz_acc_fp8(DisasContext *s, int nreg, int nsel, + int rv, int off, int zn, int zm, + int data, int shsel, bool multi, + gen_helper_gvec_3_ptr *fn) +{ + /* + * TODO: Could plausibly reuse do_azz_acc_fp, after the fpmr check, + * but the fp8 helpers were written without a separate addend operand. + */ + if (fpmr_access_check(s) && sme_smza_enabled_check(s)) { + int svl =3D streaming_vec_reg_size(s); + int vstride =3D svl / nreg; + TCGv_ptr t_za =3D get_zarray(s, rv, off, nreg, nsel); + TCGv_ptr t; + + t =3D tcg_temp_new_ptr(); + + for (int r =3D 0; r < nreg; ++r) { + TCGv_ptr t_zn =3D vec_full_reg_ptr(s, zn); + TCGv_ptr t_zm =3D vec_full_reg_ptr(s, zm); + + for (int i =3D 0; i < nsel; ++i) { + int o_za =3D (r * vstride + i) * sizeof(ARMVectorReg); + int desc =3D simd_desc(svl, svl, data | (i << shsel)); + + tcg_gen_addi_ptr(t, t_za, o_za); + fn(t, t_zn, t_zm, tcg_env, tcg_constant_i32(desc)); + } + + /* + * For multiple-and-single vectors, Zn may wrap. + * For multiple vectors, both Zn and Zm are aligned. + */ + zn =3D (zn + 1) % 32; + zm +=3D multi; + } + } + return true; +} + + static bool do_fmlal(DisasContext *s, arg_azz_n *a, bool sub, bool multi) { return do_azz_acc_fp(s, a->n, 2, a->rv, a->off, a->zn, a->zm, @@ -1071,6 +1112,14 @@ TRANS_FEAT(FMLSL_n1, aa64_sme2, do_fmlal, a, true, f= alse) TRANS_FEAT(FMLAL_nn, aa64_sme2, do_fmlal, a, false, true) TRANS_FEAT(FMLSL_nn, aa64_sme2, do_fmlal, a, true, true) =20 +static bool do_fmlall_fp8(DisasContext *s, arg_azz_n *a, bool multi) +{ + return do_azz_acc_fp8(s, a->n, 4, a->rv, a->off, a->zn, a->zm, + 0, 0, multi, gen_helper_gvec_fmla_sb); +} + +TRANS_FEAT(FMLALL_n1_b, aa64_sme_f8f32, do_fmlall_fp8, a, false) + static bool do_fmlal_nx(DisasContext *s, arg_azx_n *a, bool sub) { return do_azz_acc_fp(s, a->n, 2, a->rv, a->off, a->zn, a->zm, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 29 Jun 2026 05:00:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/54] target/arm: Implement FMLALL (multiple vector) Date: Mon, 29 Jun 2026 12:59:51 +0100 Message-ID: <20260629120032.1645265-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735131968158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260618041517.573469-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 3 +++ target/arm/tcg/translate-sme.c | 1 + 2 files changed, 4 insertions(+) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 4956995924..ccc33463c2 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -569,6 +569,9 @@ FMLS_nn_h 11000001 101 ...01 0 .. 100 ...00 11 ..= . @azz_4x4_o3 FMLS_nn_s 11000001 101 ...01 0 .. 110 ...00 01 ... @azz_4x4_o3 FMLS_nn_d 11000001 111 ...01 0 .. 110 ...00 01 ... @azz_4x4_o3 =20 +FMLALL_nn_b 11000001 101 ....0 0 .. 000 ....1 0000 . @azz_2x2_o1x4 +FMLALL_nn_b 11000001 101 ...01 0 .. 000 ...01 0000 . @azz_4x4_o1x4 + &az_n n off rv zm @az_2x2_o3 ........ ... ..... . .. ... ..... .. off:3 \ &az_n n=3D2 rv=3D%mova_rv zm=3D%zn_ax2 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 30487c34a0..ae1dbd0528 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1119,6 +1119,7 @@ static bool do_fmlall_fp8(DisasContext *s, arg_azz_n = *a, bool multi) } =20 TRANS_FEAT(FMLALL_n1_b, aa64_sme_f8f32, do_fmlall_fp8, a, false) +TRANS_FEAT(FMLALL_nn_b, aa64_sme_f8f32, do_fmlall_fp8, a, true) =20 static bool do_fmlal_nx(DisasContext *s, arg_azx_n *a, bool sub) { --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jun 2026 05:00:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/54] target/arm: Implement FMLALL (multiple and indexed vector) Date: Mon, 29 Jun 2026 12:59:52 +0100 Message-ID: <20260629120032.1645265-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734647973158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260618041517.573469-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 4 ++++ target/arm/tcg/translate-sme.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index ccc33463c2..80ad674cf2 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -771,6 +771,10 @@ FMLS_nx_h 11000001 0001 .... 1 .. 1.. ...00 1 ..= .. @azx_4x1_i3_o3 FMLS_nx_s 11000001 0101 .... 1 .. 0.. ...00 10 ... @azx_4x1_i2_o3 FMLS_nx_d 11000001 1101 .... 1 .. 00. ...00 10 ... @azx_4x1_i1_o3 =20 +FMLALL_nx_b 11000001 0100 .... . .. ... ..... 000 .. @azx_1x1_i4_o2 +FMLALL_nx_b 11000001 1001 .... 0 .. 0.. ....1 00.. . @azx_2x1_i4_o1 +FMLALL_nx_b 11000001 0001 .... 1 .. 0.. ...10 00.. . @azx_4x1_i4_o1 + ### SME2 Add / Sub array accumulators =20 ADD_aaz_s 11000001 101 000000 .. 111 ....0 10 ... @az_2x2_o3 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index ae1dbd0528..cc85c6d6e0 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1157,6 +1157,10 @@ static bool do_bfmlal_nx(DisasContext *s, arg_azx_n = *a, bool sub) TRANS_FEAT(BFMLAL_nx, aa64_sme2, do_bfmlal_nx, a, false) TRANS_FEAT(BFMLSL_nx, aa64_sme2, do_bfmlal_nx, a, true) =20 +TRANS_FEAT(FMLALL_nx_b, aa64_sme_f8f32, do_azz_acc_fp8, + a->n, 4, a->rv, a->off, a->zn, a->zm, + a->idx << 2, 0, false, gen_helper_gvec_fmla_idx_sb) + static bool do_fdot(DisasContext *s, arg_azz_n *a, bool multi) { return do_azz_acc_fp(s, a->n, 1, a->rv, a->off, a->zn, a->zm, 1, 0, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jun 2026 05:00:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/54] target/arm: Implement FDOT (multiple and single vector) Date: Mon, 29 Jun 2026 12:59:53 +0100 Message-ID: <20260629120032.1645265-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734803670158501 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20260618041517.573469-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 3 +++ target/arm/tcg/translate-sme.c | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 80ad674cf2..3c7caf8bdb 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -449,6 +449,9 @@ FMLALL_n1_b 11000001 001 1 .... 0 .. 001 ..... 000 = .. @azz_nx1_o2x4 n=3D1 FMLALL_n1_b 11000001 001 0 .... 0 .. 000 ..... 0001 . @azz_nx1_o1x4 = n=3D2 FMLALL_n1_b 11000001 001 1 .... 0 .. 000 ..... 0001 . @azz_nx1_o1x4 = n=3D4 =20 +FDOT_n1_sb 11000001 001 0 .... 0 .. 100 ..... 11 ... @azz_nx1_o3 n= =3D2 +FDOT_n1_sb 11000001 001 1 .... 0 .. 100 ..... 11 ... @azz_nx1_o3 n= =3D4 + ### SME2 Multi-vector Multiple Array Vectors =20 %zn_ax2 6:4 !function=3Dtimes_2 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index cc85c6d6e0..8fea451089 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1170,6 +1170,14 @@ static bool do_fdot(DisasContext *s, arg_azz_n *a, b= ool multi) TRANS_FEAT(FDOT_n1, aa64_sme2, do_fdot, a, false) TRANS_FEAT(FDOT_nn, aa64_sme2, do_fdot, a, true) =20 +static bool do_fdot_fp8(DisasContext *s, arg_azz_n *a, bool multi) +{ + return do_azz_acc_fp8(s, a->n, 1, a->rv, a->off, a->zn, a->zm, + 0, 0, multi, gen_helper_gvec_fdot_sb); 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Mon, 29 Jun 2026 05:00:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/54] target/arm: Implement FDOT (multiple vector) Date: Mon, 29 Jun 2026 12:59:54 +0100 Message-ID: <20260629120032.1645265-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734649974158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20260618041517.573469-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 3 +++ target/arm/tcg/translate-sme.c | 1 + 2 files changed, 4 insertions(+) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 3c7caf8bdb..04dd0e6df0 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -575,6 +575,9 @@ FMLS_nn_d 11000001 111 ...01 0 .. 110 ...00 01 ..= . @azz_4x4_o3 FMLALL_nn_b 11000001 101 ....0 0 .. 000 ....1 0000 . @azz_2x2_o1x4 FMLALL_nn_b 11000001 101 ...01 0 .. 000 ...01 0000 . @azz_4x4_o1x4 =20 +FDOT_nn_sb 11000001 101 ....0 0 .. 100 ....1 10 ... @azz_2x2_o3 +FDOT_nn_sb 11000001 101 ...01 0 .. 100 ...01 10 ... @azz_4x4_o3 + &az_n n off rv zm @az_2x2_o3 ........ ... ..... . .. ... ..... .. off:3 \ &az_n n=3D2 rv=3D%mova_rv zm=3D%zn_ax2 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 8fea451089..467b44e832 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1177,6 +1177,7 @@ static bool do_fdot_fp8(DisasContext *s, arg_azz_n *a= , bool multi) } =20 TRANS_FEAT(FDOT_n1_sb, aa64_sme_f8f32, do_fdot_fp8, a, false) +TRANS_FEAT(FDOT_nn_sb, aa64_sme_f8f32, do_fdot_fp8, a, true) =20 static bool do_fdot_nx(DisasContext *s, arg_azx_n *a) { --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jun 2026 05:00:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/54] target/arm: Implement FDOT (multiple and indexed vector) Date: Mon, 29 Jun 2026 12:59:55 +0100 Message-ID: <20260629120032.1645265-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734500624158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20260618041517.573469-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 3 +++ target/arm/tcg/translate-sme.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 04dd0e6df0..7324ccddac 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -781,6 +781,9 @@ FMLALL_nx_b 11000001 0100 .... . .. ... ..... 000 .= . @azx_1x1_i4_o2 FMLALL_nx_b 11000001 1001 .... 0 .. 0.. ....1 00.. . @azx_2x1_i4_o1 FMLALL_nx_b 11000001 0001 .... 1 .. 0.. ...10 00.. . @azx_4x1_i4_o1 =20 +FDOT_nx_b 11000001 0101 .... 0 .. 0.. ....1 11 ... @azx_2x1_i2_o3 +FDOT_nx_b 11000001 0101 .... 1 .. 0.. ...00 01 ... @azx_4x1_i2_o3 + ### SME2 Add / Sub array accumulators =20 ADD_aaz_s 11000001 101 000000 .. 111 ....0 10 ... @az_2x2_o3 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 467b44e832..a9adaa02bd 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1161,6 +1161,10 @@ TRANS_FEAT(FMLALL_nx_b, aa64_sme_f8f32, do_azz_acc_f= p8, a->n, 4, a->rv, a->off, a->zn, a->zm, a->idx << 2, 0, false, gen_helper_gvec_fmla_idx_sb) =20 +TRANS_FEAT(FDOT_nx_b, aa64_sme_f8f32, do_azz_acc_fp8, + a->n, 1, a->rv, a->off, a->zn, a->zm, + a->idx, 0, false, gen_helper_gvec_fdot_idx_sb) + static bool do_fdot(DisasContext *s, arg_azz_n *a, bool multi) { return do_azz_acc_fp(s, a->n, 1, a->rv, a->off, a->zn, a->zm, 1, 0, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jun 2026 05:00:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/54] target/arm: Implement FVDOTB, FVDOTT Date: Mon, 29 Jun 2026 12:59:56 +0100 Message-ID: <20260629120032.1645265-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734658045158501 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20260618041517.573469-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/fp8_helper.c | 23 +++++++++++++++++++++++ target/arm/tcg/helper-fp8-defs.h | 2 ++ target/arm/tcg/sme.decode | 7 +++++++ target/arm/tcg/translate-sme.c | 10 ++++++++++ 4 files changed, 42 insertions(+) diff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c index 08e04364fa..3c2d959099 100644 --- a/target/arm/tcg/fp8_helper.c +++ b/target/arm/tcg/fp8_helper.c @@ -892,3 +892,26 @@ void HELPER(sme_fmopa_sb)(void *vza, void *vzn, void *= vzm, void *vpn, } while (row & 15); } } + +void HELPER(sme_fvdot_idx_sb)(void *vd, void *vn, void *vm, + CPUARMState *env, uint32_t desc) +{ + FP8MulContext ctx =3D fp8_mul_start(env, -1); + intptr_t oprsz =3D simd_maxsz(desc); + intptr_t elements =3D oprsz / sizeof(float32); + int idx_n =3D extract32(desc, SIMD_DATA_SHIFT, 2); + int idx_m =3D extract32(desc, SIMD_DATA_SHIFT + 2, 3); + float32 *d =3D vd; + uint8_t *n0 =3D vn; + uint8_t *n1 =3D vn + sizeof(ARMVectorReg); + uint16_t *m =3D vm; + intptr_t i =3D 0; + + do { + uint16_t mm =3D m[H2(2 * i + idx_m)]; + do { + uint16_t nn =3D n0[H1(4 * i + idx_n)] | (n1[H1(4 * i + idx_n)]= << 8); + d[H4(i)] =3D f8dotadd_s(nn, mm, 2, d[H4(i)], &ctx); + } while (++i & 3); + } while (i < elements); +} diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-d= efs.h index 7c090ccad6..ef1375fea7 100644 --- a/target/arm/tcg/helper-fp8-defs.h +++ b/target/arm/tcg/helper-fp8-defs.h @@ -40,3 +40,5 @@ DEF_HELPER_FLAGS_5(gvec_fmmla_sb, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, env, i32 DEF_HELPER_FLAGS_5(gvec_fmmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) =20 DEF_HELPER_FLAGS_7(sme_fmopa_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , ptr, env, i32) + +DEF_HELPER_FLAGS_5(sme_fvdot_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,= env, i32) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 7324ccddac..1de5f341ef 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -784,6 +784,13 @@ FMLALL_nx_b 11000001 0001 .... 1 .. 0.. ...10 00..= . @azx_4x1_i4_o1 FDOT_nx_b 11000001 0101 .... 0 .. 0.. ....1 11 ... @azx_2x1_i2_o3 FDOT_nx_b 11000001 0101 .... 1 .. 0.. ...00 01 ... @azx_4x1_i2_o3 =20 +%idx2_10_3 10:1 3:1 +@azx_4x2_i2_o3 ........ .... zm:4 . .. ... .... ... off:3 \ + &azx_n n=3D4 rv=3D%mova_rv zn=3D%zn_ax2 idx=3D%idx2_10_3 + +FVDOTB_sb 11000001 1101 .... 0 .. 01. ....0 0. ... @azx_4x2_i2_o3 +FVDOTT_sb 11000001 1101 .... 0 .. 01. ....0 1. ... @azx_4x2_i2_o3 + ### SME2 Add / Sub array accumulators =20 ADD_aaz_s 11000001 101 000000 .. 111 ....0 10 ... @az_2x2_o3 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index a9adaa02bd..a79b0a9b80 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1233,6 +1233,16 @@ static bool do_vdot(DisasContext *s, arg_azx_n *a, g= en_helper_gvec_4_ptr *fn) TRANS_FEAT(FVDOT, aa64_sme, do_vdot, a, gen_helper_sme2_fvdot_idx_h) TRANS_FEAT(BFVDOT, aa64_sme, do_vdot, a, gen_helper_sme2_bfvdot_idx) =20 +static bool do_fvdot_sb(DisasContext *s, arg_azx_n *a, bool top) +{ + return do_azz_acc_fp8(s, a->n, 1, a->rv, a->off, a->zn, a->zm, + (2 * a->idx + top) << 2, 0, false, + gen_helper_sme_fvdot_idx_sb); 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Mon, 29 Jun 2026 05:00:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/54] target/arm: Enable FEAT_SME_F8F32 for -cpu max Date: Mon, 29 Jun 2026 12:59:57 +0100 Message-ID: <20260629120032.1645265-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734605588158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20260618041517.573469-11-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + linux-user/aarch64/elfload.c | 1 + target/arm/tcg/cpu64.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 0b4623139a..a3a1607ff9 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -169,6 +169,7 @@ the following architecture extensions: - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) - FEAT_SME_F16F16 (Non-widening half-precision FP16 arithmetic for SME2) - FEAT_SME_F64F64 (Double-precision floating-point outer product instructi= ons) +- FEAT_SME_F8F32 (SME2 ZA-targeting FP8 multiply-accumulate, dot product, = and outer product to single-precision instructions) - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instruc= tions) - FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit e= lements) - FEAT_SSVE_AES (Streaming SVE Mode Advanced Encryption Standard and 128-b= it polynomial multiply long instructions) diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 0f96bbe70b..20b9838520 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -235,6 +235,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) GET_FEATURE_ID(aa64_ssve_f8fma, ARM_HWCAP2_A64_SME_SF8FMA); GET_FEATURE_ID(aa64_ssve_f8dp4, ARM_HWCAP2_A64_SME_SF8DP4); GET_FEATURE_ID(aa64_ssve_f8dp2, ARM_HWCAP2_A64_SME_SF8DP2); + GET_FEATURE_ID(aa64_sme_f8f32, ARM_HWCAP2_A64_SME_F8F32); =20 return hwcaps; } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index e4a8d7a2f6..e9eda8fbf1 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1392,6 +1392,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F32, 1); /* FEAT_SME_F8F32 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F16, 1); /* FEAT_SME_F16F16 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, B16B16, 1); /* FEAT_SME_B16B16 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* FEAT_SME2 */ --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-473dddcb295sm8753061f8f.35.2026.06.29.05.00.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 05:00:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1782734455; x=1783339255; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2jGVng5hkuTjGzBl0GQQyq5EosBoiD4hMICnM+T1qsU=; b=J4UqL9jUBJktvDTWTV7K3csc5P3RHv9w05WH60lCLKr0U5IDylhJ8ZdVjOJ1OwIh70 MRA/nI80su6YaCXknfeuoZEAzMXA9JwmRa3Woi0r9f7LXpYk3uXsf2q99oC/CkR+ealt RzI42w+UrQbNd0QrWY6XLJ4c57wXeEPc8Js00C++LVJFaPGNIzA6+2YEoYLwXO9RaLxH SJNEKjkF1E5i7tTvrfrBfE4SoUp5J75fX2xMAYQ9lVJObCWI8QCy5Wit5LKYKwt5rToT ZlQzQlEU0oIaGKmIMMQSUrnkiSgSOYmra8KU9Prie7rTkH09DgQim6EO3RvnbXp6jDkn 6P7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782734455; x=1783339255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2jGVng5hkuTjGzBl0GQQyq5EosBoiD4hMICnM+T1qsU=; b=d3G+QwHYFwFZ+E3Qkjazg0mAfzEpnnKhapEzLAj5D55Mhkpla8W3JYDhqryG5Ul8b3 of2JiuJRLdI+9Wq51UkFWTxCZECPqzku27iP9XZOjoEq9Ivglpy2jGVuaLg1zqbpF0z6 esXReXdW+zpvtDZkT1khAVfmlR01FYLv61ZnPkoG/rzqiFT2k7Psbrd2gcZJzzwSAjx4 RrHz7v9Kl123lCb/F/DV0cm46ieBs3PJgEXq+6DelRVc12r+0kf+n4E4sbbs5u2VP9UJ EPIgmBb6Aa0YYcTgBWANz51hrtKHWXw/hdxsmgaZ2FeUn4VVNSFAPZwuO8G629vWZ3oO Zppg== X-Gm-Message-State: AOJu0Yz4ERowtrK72nIWntAJwaPNi+pYDbhCQ1/FA9dJIRfzPq1gDlhl nDdVtHMwmnC5XlRdC4kamV0psqL65GXnBtp8E7qojLPQFrZPw5H3pxEM4wn3RPRjRMM13osjZiX KTZBJ X-Gm-Gg: AfdE7clw0bgbEo4BIe1RLkGneOUHJb/oo7JLl+19RjJG/nDVSGn1dSvHvBzd4nz5SRl wEMa5LjWclxVITb47cupWH7SbcI9eYH+Gn1C4N0aBZjZSYw3m1Z6FPTy0PEiduvT1isglxxEQx4 EGuCI0fhOO5j7TnFP61ztCX1f//bQGv3dPpF/mBYbg8oetPGLTYw4MIWShKjrSS6lXI8bL3j/dI 9luA5/s6ivEO0Rn3WQBGnOZ8LOQjCcTJ2LcxcR1ZRmFG5qSr0ctYXtaMsy8hunzzJ0f0vBbAd0E +4dJge1aBJfLcqCjT9lIYyJzY2JvwVe2VNwQ1kZYMcGM3/zE6SCD2WznlJuOKwJ+ELwcRojCAf8 fKsmI+Vh6ce3GSyDvvD08biA3ZhK/CSeaAGg429g7i9mjWJHZ6f5a21ORoLu/BrxOkQoEdcGqRK SXWfBx8iSMmvq4/u0Qe8NeZwwH8GeRfCLdIF/p+Q9G4nZ4FbsvRytgYrKP1Sn2VOtEzpgkxjWS5 z90hKOcqioFFCQa/xfFIQ== X-Received: by 2002:a5d:588b:0:b0:45d:4a00:b927 with SMTP id ffacd0b85a97d-46dc12df9eemr26459636f8f.31.1782734455328; Mon, 29 Jun 2026 05:00:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/54] arm/gicv5: Add URL to GICv5 specification Date: Mon, 29 Jun 2026 12:59:58 +0100 Message-ID: <20260629120032.1645265-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735019177158500 The GICv5 specification has now been assigned its final document ID for a rev A.a spec version. This seems like a good point to add a pointer to the spec to the main source files. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260615105029.2898872-2-peter.maydell@linaro.org --- hw/intc/arm_gicv5.c | 5 +++++ target/arm/tcg/gicv5-cpuif.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 6b1dd04991..0fa3d6b601 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -4,6 +4,11 @@ * Copyright (c) 2025 Linaro Limited * * SPDX-License-Identifier: GPL-2.0-or-later + * + * The IRS is defined in IHI 111701 + * (ARM Generic Interrupt Controller Architecture Specification, + * GIC architecture version 5): + * https://developer.arm.com/documentation/111701/latest */ =20 #include "qemu/osdep.h" diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index dd2f696511..891cb2d3b7 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -4,6 +4,11 @@ * Copyright (c) 2025 Linaro Limited * * SPDX-License-Identifier: GPL-2.0-or-later + * + * The cpu interface is defined in IHI 111701 + * (ARM Generic Interrupt Controller Architecture Specification, + * GIC architecture version 5): + * https://developer.arm.com/documentation/111701/latest */ =20 #include "qemu/osdep.h" --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735167; cv=none; d=zohomail.com; s=zohoarc; b=LIAVQQluTJYaitRZMOIODNMrJXGyOKDFnEmIMDL23456vl3OvmtTqhJWIFO0Oih2u+ZHhnnB+bEIGoJbiPD5EVAB/ec8wp6uUD55uNOgs1Q5jwkR+oAZMfZx1IyC6pbSU7nk5bckAD7hGdQ34lT1XTLtLDXF3vPHvx8QhuD1TME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735167; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=rI+HS35xOsQlDFg64FvBF7DCHZ4OhMqSz1As1ax8qfU=; b=S4OJnP/LLAAYHvztr2nmm2h+7r+prxrbqJjbMgZBppC99h7qNOw6ufJqIjn9Wb94YhjHmVtzHN+RHw4JsdYp+mRBklpMbxVsc4Htbb/fKCRGVsMDeJ8RPsot6OLmQVN8P/7aY6h3ZUGYBB20eCpIEDbJLIhJg+CTlJabO8ojmMg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735167491917.5185754379306; Mon, 29 Jun 2026 05:12:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgE-0007Hg-Mw; Mon, 29 Jun 2026 08:01:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfi-0006vc-0M for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:07 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfa-0007P2-Fx for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:02 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-47231f1f8f3so2283921f8f.1 for ; Mon, 29 Jun 2026 05:00:57 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-473dddcb295sm8753061f8f.35.2026.06.29.05.00.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 05:00:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1782734456; x=1783339256; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rI+HS35xOsQlDFg64FvBF7DCHZ4OhMqSz1As1ax8qfU=; b=HGCFc0dfwJlke5eUvVeh//3LJaesjgd+S2PvaQSsmsWEOAW7mF8DGhpmg2bfXodrya 5reILBxglx9uzd2VqzZ+V7WaLT1wxT0B0P8HQAzWUv7w3BHBrZiZW9SLox0kECzxMFPu HZB7QG1DqBa8cc5ofzqIcEAaYNa54qWOJgzwVaheKxsM0WsfXQruncyNB+PTacUD7NEk 9wlYNMsiafik2xkcP8M1xf2BfwWz7n8vbA6i/7HroRUbY0H2yZaCIyvQKwTmRWogNEia n8MllrcLl5sNQDs8qiW7Ed+V83DnqI4M8rXfAPgjQOrNcJToQYNe4tIT7rWaxaFqHZmD TB/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782734456; x=1783339256; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=rI+HS35xOsQlDFg64FvBF7DCHZ4OhMqSz1As1ax8qfU=; b=qwNYHxkTO0TxPzlRO9FIIO3L72T/fAVih1IYotTzHwV06bJAZILzQHrYGO/VKSCejU kNUgTbDIIE8O+sL+D/crYkSauwqG+fqsQDOVcpLIUiPI2NWTemWU3awfNTZGijG1hm93 iiL2TqkuTR6QNgdGgxAzoMSIR4TgcxoEyJOwASbGWdN3lgZc1wy3YRxlzOHT5yGZmC6+ MG7OXXez1Mn6MoErLeG+amHIUJkuwTAg6ESc46Dox3Pkgwjm2PuDRObSQHsfGM9QELTD ofPWy736vb9GoGDyWXzkO4+uyL7kZQDoxN5iWBlCw7DMGu0TDUUBAyNQSrbqP0kKWkJg 0qsQ== X-Gm-Message-State: AOJu0Yxk4XZk95JbTHMTMKISJg4Skc+XwZYe+b485lW+nwt3XUvrXr80 uJzK2CqySlusb4Ob6uaC7x5RWWlj43xMgH4vhROOjc7eMBqSoeKGlf42N0KXXiA9GB6sC5wiKgr n6oYZ X-Gm-Gg: AfdE7cmS/BkTtNviHcQG6KrKFcyOrCVzlepxEWDATQDFyuXr5xinUjZrF00GHih7YYI ZRILqsKWC5USj/fEBLwPTKUUqKQocV/wEu4vB2fWJHOmO31tbpzSZQ5+R/gj+wDTw5iGKCyDMHc MZrMG5tKHItgYb7yBwaNi2vLyi2bm37WoDGAyIvCj3P1cAP+ZtJpgE18tgW8HNrUB02dLR3N2Uz E8cl7tW8CN/TmgI+yW/5Q7CsLt2a98pDSOLm7AGjdeGvd+QnFdfYU3xeqCyKG8XJDAJP8rJQ1nF PclS+rT4tWojUB+SZyITawCWc9cM6RCExVThLyXWINhKusqtgODwJLMBYUlhSPpoMgxINC/br69 A/7tQ3CQXijwiGyR5xjIi8ewL/bjeEo7QdwC65q/JeV9gMjOa/IDW5zwGLt94aMn570SICycqwR VEHk7n68W21p8bY5CcjRM9/uZtKu+mBec8P8ONjz4ErddG6h3krLBY3IBxe/To6TNL+iKI+6AD8 2/g2R2ARqo3YQautqmHQWj2Kv8eWADQ X-Received: by 2002:a05:6000:2512:b0:46f:f12b:e45a with SMTP id ffacd0b85a97d-46ff12be583mr14736952f8f.23.1782734456213; Mon, 29 Jun 2026 05:00:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/54] target/arm: GICv5 cpuif: Recalculate IRQ/FIQ on ICC_PCR_EL1 write Date: Mon, 29 Jun 2026 12:59:59 +0100 Message-ID: <20260629120032.1645265-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735168437158500 When the guest writes ICC_PCR_EL1 we should recheck whether we should be signalling IRQ or FIQ, because we use this priority mask value in determining whether the highest priority interrupt should be signalled or not. Fixes: 9bd90bddb79b ("target/arm: GICv5 cpuif: Signal IRQ or FIQ") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260615105029.2898872-3-peter.maydell@linaro.org --- target/arm/tcg/gicv5-cpuif.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 891cb2d3b7..09c3fdda61 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -565,6 +565,7 @@ static void gic_icc_pcr_el1_write(CPUARMState *env, con= st ARMCPRegInfo *ri, =20 value &=3D R_ICC_PCR_PRIORITY_MASK; env->gicv5_cpuif.icc_pcr[domain] =3D value; + gicv5_update_irq_fiq(env); } =20 static void gic_icc_pcr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734721; cv=none; d=zohomail.com; s=zohoarc; b=PpuQos4rIJ72ZH7aVFsnCArr+eGMFWYS397BL/fljrgXqAm9rJsh02Za9ZdgBmnsK+Ofu1k057uB6/bHbvM74BfDN9XOKqeXZufM96EngykoVSYmOl3KCIUOcuQVB5TIDamPPqnw5mJTVSKD2um8dMCIndejcuNc2bRLa86pFqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734721; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=zvLNc0vzKaBuvu31NLedVEX7bGRGAQf2IsYZSe4AZqo=; b=SOP+ClazzpQjwxb/8VyvsohTVGzu7sAF2hakLsiLbiLf49m8K2A69BMSIE0sT+UAzEaJ/28KDZWIhK7rpkC0rTSEKIySFg7x66xK0+fbiosKQkJo0c6jXjgZmKuYvEwB5U4rfTmvNXFsdS4AYLczCEcpy8vsqfXvJCQAkZkQLSw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734721083126.10450323100793; Mon, 29 Jun 2026 05:05:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgC-0007Af-0h; Mon, 29 Jun 2026 08:01:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfi-0006wS-3e for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:07 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfc-0007Pz-IZ for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:02 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-46ed4f66256so2707145f8f.3 for ; Mon, 29 Jun 2026 05:00:59 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-473dddcb295sm8753061f8f.35.2026.06.29.05.00.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 05:00:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1782734457; x=1783339257; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=zvLNc0vzKaBuvu31NLedVEX7bGRGAQf2IsYZSe4AZqo=; b=ts9CCARj2yoSJ4ps05ZryaMquWgtTyqesZFtHV2i+uyliXtfEjZ4N8maN1A1/hlzDv CsdxL63n5hvsg6rUxSUTaaZloQVe6+l2Vr7BeH5ldXRWi9ktPodUxlVoczYsRgBlQ2BU ekDX2nKTRw5BrWuIUn9+/t76bKtwMkaDCWK2NLFPcs/oK0SROhYjn7dHMhCSwRvXYYPV jQ5mljcGo5KCBx++nrOkrD9IE1H4njHLgNq1UhD5kbRVVmgbuf37RIhChxl9HJmHZnAJ ESKiTZBWNy+9lSyZF6AL1mI9Wxy+19IUXwP8ARcehDTETgG7NWCw3dBhUdux4QX4aRKn FyQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782734457; x=1783339257; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=zvLNc0vzKaBuvu31NLedVEX7bGRGAQf2IsYZSe4AZqo=; b=N8AaudhQ0s1CAm3go8shqelMw2jJOlzjdbKMqGsBm/Dsgp2mw3zNoAQHhWokHSCBI0 s3aoo/g0NumH//6+F/NCvzKSjBtxD42uG0AS62161uCEMmJAaF6i+xFoPLHqxfPZJGB/ 8nysPZsv/NdP+N8czVVevwJf86+goCy0q/NEU3otygKXcD7Axt5DrXRyOvJJViBfDVWA 5RI1xeZWcECDbCe8TIUzagM29AA4bjs5Am3b09VnN1a4TStuKtXmDxicvUfGjTJYFCNF aJPA2hkg8B6kjt5vhUL024B8fvjd5zYb+IJF1nG8d0KsA1i07NKAyRnd/1u6/0fhI6Iu ATxQ== X-Gm-Message-State: AOJu0Yy9mGAU259tjdgRjtzjo2o1nSsbD7fht2808k0sHLqQpJZQLvz6 gT03s3+13WDIWw0NlztNXddKJqsxx9II7jaqlft0Y3kelfSfeJeEPHqd9pOHwjQjGkHY6ikBaYj YbSki X-Gm-Gg: AfdE7cnffPr+pDRVzF+iKbIldXHm5nHG33I5MEkkdrskyiBvUOtGQ2BlWliMjaaV3DU eFJ0I/pNlXhl0i9Nkwc18OiCEe0VDnYbu7LSqUv18TLjhzTIOHyEm7N+ISZCTGRyfCNOSLHrnia FR+1cqiubR4Ijs/xSmYkQIkXCXX2rOxh5ComRftKQKdBz+dinROqvng16WaNFg1Xd0nSHd41aCk kiOrHFtENJzz3tVy6DG9LU4MPRtRbbHQCDa2wUT5CnYKCpyByiRjaFphnnVOouRgKxZUl+RHKM9 H3fwEs9s1zNt/VTwjh8JPjOBYR6LrDxRk1qBm4Fgxocu2/UW3iNc6iezqK6VuhkF33eh3nBxBz7 aiXKGBQx6AqL+6B4i5WKqDOK2n+Gl+nK7Ab6y4GmCdt0Nft4DPSgyxtjFCWNs98USHd75UHbHly kK+RzjsJ5GzdFd0xaj7LIBR0Hcvdb1sT3yUqxeCjBgdku6V0jSsvCCuNf98KJZLsaHtU8AScCqO B+03LCvbJt0MOC+TYyMyA== X-Received: by 2002:a05:6000:382:b0:471:e4fc:d881 with SMTP id ffacd0b85a97d-4750079f963mr234750f8f.30.1782734457256; Mon, 29 Jun 2026 05:00:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/54] target/arm: GICv5 cpuif: Tag ICC_PPI_PRIORITYR regs as ARM_CP_NO_RAW Date: Mon, 29 Jun 2026 13:00:00 +0100 Message-ID: <20260629120032.1645265-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_FILL_THIS_FORM_SHORT=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734722657158500 The GICv5 system registers are all tagged with ARM_CP_NO_RAW, because we don't want them to use the standard mechanisms for migration or KVM state synchronization. (GICv5 handling of both migration and KVM support is a "will be implemented later" feature.) We missed this tag on the ICC_PPI_PRIORITYR_EL1 registers; add it. Fixes: ef540c1d301 ("target/arm: GICv5 cpuif: Implement PPI priority regist= ers") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260615105029.2898872-4-peter.maydell@linaro.org --- target/arm/tcg/gicv5-cpuif.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 09c3fdda61..1aa4bde799 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -950,7 +950,7 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu) .name =3D name, .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 14 + (i >> 3), .opc2 =3D i & 7, - .access =3D PL1_RW, .type =3D ARM_CP_IO, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pri= ority[i]), .writefn =3D gic_ppi_priority_write, .raw_writefn =3D raw_= write, }; --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734794; cv=none; d=zohomail.com; s=zohoarc; b=UbjRzJpVxi/lAPG2fZVlHyfKKvfAdLiDSS5mgjX5dtH4mg3jOHkqj6Smzw8ht4JlY78ehS0HVOyyz75ZB1J1FWjbJxRs5hRjotMCBqH3KN3f4W8K+iIG/SH/pS75XZpMZ8pAJ65UEODKveyfZ3A1f6+zk8z8eIn71wbkjTOSBzc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734794; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7nxrNrYCopcurGkkgdYz5xeXgIeGKYV3dyMssD6Ea1k=; b=j6oRBKKvAWRptF6ltZZ005AUdwhbv6ghSt8P0OP7q2zQW52D/7a0X/b80JLZNWXXfaIxhQnG+5jzlOuzWFdABn/xVbgLRP8QmEdZvRJlK/M94tNRDclS2N+LbGkjiNtPvVEi6biZ6F9whi9+oQEkOUn/Tpeyov6/E9h0HVRq+hQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734794222210.4453257394273; Mon, 29 Jun 2026 05:06:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgJ-0007Mr-Bk; Mon, 29 Jun 2026 08:01:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfi-0006w6-3e for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:07 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfc-0007Py-Ic for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:03 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-47362928f65so860022f8f.2 for ; Mon, 29 Jun 2026 05:00:59 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-473dddcb295sm8753061f8f.35.2026.06.29.05.00.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 05:00:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1782734458; x=1783339258; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7nxrNrYCopcurGkkgdYz5xeXgIeGKYV3dyMssD6Ea1k=; b=JyCMYcKQItAzcpdILpTTgPqDdmaIigsugmU5NULG4u121w2vzpxtDBrdNX8To8/Zh3 Ap11zMKY3Y/Icxpi0Scr1IHRvVAvLAfaXueBCqmXaRkC0kDdZwD4NaDYBlaH2HtBQ+ZO qf3TVPY0ZmVCB0wSsln1KIhxT6fv9rq6G5vMXGBZsHBzu6B/6rV2HhlDEoxSVUuxLgPB TMpu73nzrH4AO2avWvkgbqJubxd7u399p2Soy2sOpX7CsYw92H28o3H52Y8oDEBCb6Hm CJUIg9KZ1IbsFbuT1JfySmEKSDnClEg586PKfccjSA0EWwyljls9oDNh2R1lGIZrOcS1 VIeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782734458; x=1783339258; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=7nxrNrYCopcurGkkgdYz5xeXgIeGKYV3dyMssD6Ea1k=; b=Xd8BbCpDVDhHDbXtEQnFeEidPPV3MJbHsOsMklNFAJCUA/hAYKvoOZs/SDpd5KzXP8 N8Y84qLF97L3QGENa2UsXttZkS8DuolJERI7mwVLvf4GGAzWkSfj0hdlOb6dsR/RvFfA ywoO0BG5nDh1ArX5vFpTs1km7LAIGpCJjOl/kEQy9hMQNaXWYLYEp82fsYZgLAO7hx+p /J3snM+iNFFWdck9rajC2HQeMddxt5dp8/DfoF/Ol3f324ZRR9FDyyZLRlbNm20ytNc9 4WHSQihmsnZg6f8t6PZ2216pbu3q1UcZhMAlpkwpFYLjCP4XgeoRDtA11i30c/0ltxuc ccmg== X-Gm-Message-State: AOJu0YzSKzKWppXtX85J9M2eB9bqIFvh6YzxyCKWsnpZB0XZMUxE2yG8 atrYYMXv3EoqZqhtVJn7wceHFCgwfzBWAQVKWnGU06AeFgKE5qI9Bs70q9qEaRDJiQwbPDYokUs HWrcY X-Gm-Gg: AfdE7cmGLx3avMkPOb1aTyqsWbzJCwSXP7fczUKhv37wVGFOCMLEbBQiAqGQDGaL8iT JWphO6M6hcrBnVLWGMqVB8mHBxw8o2ggmPupwbkPveZUuKuT3oqogFygQVoLTLZwrEhM3EvAqkj RkCU6p7ShPvPUlmVj2DitlHUDxaS+hwhBeliwF7Ym17rdGw+4QdY31KP4nHBgvL+8GEBMwssyUe Rq7R1/ymAho+tocMw3oV44gbtjiWvVX4RoN9msRNLETCqe6Im596DfkQlOvzUm2cYb9DZOHi0z+ a8y3NAalcp7+AD16WQaOr+B7yQ1X9kVst0p8cshg1BLbldK2WSv0isiZ2D/kxOQ0GzjCjxdhZrL jiBGlid7dJmkxUKYWi0UQwMRzsCvezm9GPVf4k4+YvbEPQRUNeg5drrhhQ3e96oexnghKIXWHhI UcuGGstybh8nbsmenKjC8iF2BxCWlZH6m5+4NTsKGck2QSRtjUqGFqSdfOAbMMcPASkO+CST3Px crvLdOg5955FXI/XI6dWo8xDXdowj1g X-Received: by 2002:a05:6000:2487:b0:474:6301:3e3d with SMTP id ffacd0b85a97d-474ff09be36mr258798f8f.11.1782734458213; Mon, 29 Jun 2026 05:00:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/54] target/arm: GICv5 cpuif: Remove ICC_HAPR_EL1 Date: Mon, 29 Jun 2026 13:00:01 +0100 Message-ID: <20260629120032.1645265-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734795375158500 The ICC_HAPR_EL1 register reported the current running priority of the CPU. However this can be easily calculated by reading the APR register, so it has been removed in the newly released A.a version of the GICv5 spec (IHI 111701). Remove QEMU's implementation of this register. (This is OK for us to do without warning because our GICv5 support is listed as "experimental"; we anticipated that this kind of spec change might happen.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260615105029.2898872-5-peter.maydell@linaro.org --- target/arm/tcg/gicv5-cpuif.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 1aa4bde799..a868adca66 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -511,15 +511,6 @@ static void gic_icc_apr_el1_reset(CPUARMState *env, co= nst ARMCPRegInfo *ri) } } =20 -static uint64_t gic_icc_hapr_el1_read(CPUARMState *env, const ARMCPRegInfo= *ri) -{ - /* - * ICC_HAPR_EL1 reports the current running priority, which can be - * calculated from the APR register. - */ - return gic_running_prio(env, gicv5_current_phys_domain(env)); -} - /* ICC_CR0_EL1 is also banked */ static uint64_t gic_icc_cr0_el1_read(CPUARMState *env, const ARMCPRegInfo = *ri) { @@ -928,11 +919,6 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .writefn =3D gic_icc_pcr_el1_write, .resetfn =3D gic_icc_pcr_el1_reset, }, - { .name =3D "ICC_HAPR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 12, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_R, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .readfn =3D gic_icc_hapr_el1_read, .raw_writefn =3D arm_cp_write_i= gnore, - }, }; =20 void define_gicv5_cpuif_regs(ARMCPU *cpu) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735114; cv=none; d=zohomail.com; s=zohoarc; b=Zslo/zcnkgAOtz8eTSRXiNedwOXHGTTDzMJ3nHAjQhbVHVb5veMxOmdQs0+u8PNGyCDhvmx1yUCLS2VzR3cbDhV58BwCg4y6bHhRdGc3ZVlJg0bdcXKA8d0cavlk3oAtnx29LMYwgSBs9a5zi6MFYwD5CUpBi00lcJGEpK6kda4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735114; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=NE0FUuP3qSW1y1JInNt898EU0WBaDbtQtzuimcKJcCA=; b=IBBb2X/uihk5kg/mFYx7IHuD2Cqzegg813H19WxhcUE4GJf9x4Joljbcrhg7tO+uSZY/tVQ5PLVdkhLN4w6Z+cg3oZHxrsylyVzfkOY/StTaf8sQFOlTVhRDDFUX/6tzdjZzfSRk4pDK9i5au70apRtSiJHhGAvIupv5XMb1Khg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735114082673.2273343068506; Mon, 29 Jun 2026 05:11:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgA-00079D-RT; Mon, 29 Jun 2026 08:01:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfj-0006wg-95 for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:08 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAff-0007QG-RY for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:07 -0400 Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-c0c15bd6b8fso327931666b.0 for ; Mon, 29 Jun 2026 05:01:00 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-473dddcb295sm8753061f8f.35.2026.06.29.05.00.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 05:00:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1782734459; x=1783339259; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NE0FUuP3qSW1y1JInNt898EU0WBaDbtQtzuimcKJcCA=; b=vCGUqz55TsXWaczdLEvpe5WBnhjv++Cbsr6VhNEQr32v5OI8/k18g2mJQwWWJ5LrM+ uAcAa2/ovrmsG64a3J8qSHiGF9fDMrSwd2NJQsH3LAz54ywhXy8TUf2iCPyIiEoNMtnx bfnpOub2mdXEN013ftRyU+1pMpjUnTsWGUC2dqlryyMF7K6cPUzlG5TDBICB1MRIuySs j9vThUsFgHUxAn9nWeNOMVqBWOEFRO6K2rhJ/tZoeewGMAGBeeCngKhFDzPuYlO1LB8V O3QFeglqDyEDfkjukqDykya4iUAdVdOSZ2hVxdGtphoavpLvmhlQWg5Bk/9Tlz0U5Mwc 1/ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782734459; x=1783339259; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=NE0FUuP3qSW1y1JInNt898EU0WBaDbtQtzuimcKJcCA=; b=ptnC0r2Yf2RaEsPGTgkZKE9YFNPAP34N6L5RgvLAJJdg1E+Q6C4EQHeCfZe+t4M84n UXra4DtpBioynEVLO780FOrX5KwYNr85EA94Par+OXl6K4TMnUSBIIaqwt5wbMySXc9V FnbYJJd6rkJfk8Ed87xyOLxfl74r+fM8J3gAI9LJo04a7/EObsOOLXyF+AWOU2+SrSUU yh407s1njeiYaaAghmT/norCIWOZCATAUlpqeGgSHeYNHrEwxd+EJuCyhph/+a7ArC97 DCqTA9rqBTOCLjns+ahAt6BwUkglaetnou0Z3aSZA/NqCWZQY8raTKimNofsXKDkkliD NRmA== X-Gm-Message-State: AOJu0YzQWzCRh0o14eKZeAO55JUP51GvD/3AO+TN3KbkaOVTRZHD9j92 adWVXYN7HHlXI8u20Tzni9PdiauzgWHhqtMkHp5c4CTNt2n1JdkeF1JXidly/pqiB40l3GcS55M BFsX5 X-Gm-Gg: AfdE7ckP4ODVZfJHmNmdIfW54FPBq/cCl/VuZD3K7LtK27xy03FYMYhkUGhTNE1Crk3 Dsn2C+YDf0mOPSWcXub2A54hvsdZZwx5of+6Y2lluPnfN/NLVT12z/UHJ/klENx8pPi3SteMWC3 YSuIsas8mkog9sdoQCCfDlKTP2cVGFEiwKFAr10ha90BSwpVqgz3ig7SZRGhHABvuqkKnSPUSqk 74ZEOqbEhKlUjvehi4SIzJ4yHA3Kssgjqvks4/e+BTreFoNNvsoAz1kVYXT/jUinhNNrUpmEViS zX2agVjC01Ui3nCs45R0tFSvjsofsPVDb/ByX86MZj0gIfqrQOpI1DwHz+zyQMNGNkbk+hX5W91 m8b8NVlqIGjMclvuGG68tfn91O4RNodIwHqZ+y1++BpAUPbzyQoynWPTJ57tI2hyY8anm3oLlA5 d1fWZ1DQetfYt1pxFBm8+3hQg7G+f92456iOt2E6esZQLWhczjl15Ydia4MxM4EwRJk6nMli2Ia NGpJHctskAW4ULTQQRfNA== X-Received: by 2002:a17:907:1c84:b0:c12:6f47:1d30 with SMTP id a640c23a62f3a-c126f471e3bmr108812166b.65.1782734459218; Mon, 29 Jun 2026 05:00:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/54] hw/intc/gicv5: Define and use GICV5_PENDING_IRQ_NONE Date: Mon, 29 Jun 2026 13:00:02 +0100 Message-ID: <20260629120032.1645265-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735115910158500 The GICv5PendingIrq struct representation of "there is no pending interrupt" sets the prio field to PRIO_IDLE, and generally to avoid confusion we also set the intid to 0. We want to return this value or initialize some variable to it in several places in the GICv5 implementation, and the support for the virtual interrupt domain introduces more. Define a convenience macro for this special-case struct value, and use it instead of opencoding either the structure initializer or explicit assignment to the two fields. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260615105029.2898872-6-peter.maydell@linaro.org --- hw/intc/arm_gicv5.c | 6 ++---- include/hw/intc/arm_gicv5_types.h | 4 ++++ target/arm/tcg/gicv5-cpuif.c | 7 +++---- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 0fa3d6b601..08878193df 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -429,8 +429,7 @@ static void irs_recalc_hppi(GICv5 *s, GICv5Domain domai= n, uint32_t iaffid) ARMCPU *cpu =3D cpuidx >=3D 0 ? cs->cpus[cpuidx] : NULL; GICv5PendingIrq best; =20 - best.intid =3D 0; - best.prio =3D PRIO_IDLE; + best =3D GICV5_PENDING_IRQ_NONE; =20 if (!cpu) { /* Nothing happens for iaffids targeting nonexistent CPUs */ @@ -526,8 +525,7 @@ static void irs_recall_hppis(GICv5 *s, GICv5Domain doma= in) GICv5Common *cs =3D ARM_GICV5_COMMON(s); =20 for (int i =3D 0; i < cs->num_cpus; i++) { - s->hppi[domain][i].intid =3D 0; - s->hppi[domain][i].prio =3D PRIO_IDLE; + s->hppi[domain][i] =3D GICV5_PENDING_IRQ_NONE; gicv5_forward_interrupt(cs->cpus[i], domain); } } diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_= types.h index de4f78a149..851286b1b5 100644 --- a/include/hw/intc/arm_gicv5_types.h +++ b/include/hw/intc/arm_gicv5_types.h @@ -105,6 +105,10 @@ typedef struct GICv5PendingIrq { uint8_t prio; } GICv5PendingIrq; =20 +/* A GICv5PendingIrq struct initializer for "no pending interrupt" */ +#define GICV5_PENDING_IRQ_NONE \ + ((GICv5PendingIrq) { .intid =3D 0, .prio =3D PRIO_IDLE }) + /* Fields in a generic 32-bit INTID, per R_TJPHS */ FIELD(INTID, ID, 0, 24) FIELD(INTID, TYPE, 29, 3) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index a868adca66..1cdd4103d0 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -144,7 +144,7 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5= Domain domain) =20 if (!(env->gicv5_cpuif.icc_cr0[domain] & R_ICC_CR0_EN_MASK)) { /* If cpuif is disabled there is no HPPI */ - return (GICv5PendingIrq) { .intid =3D 0, .prio =3D PRIO_IDLE }; + return GICV5_PENDING_IRQ_NONE; } =20 irs_hppi =3D gicv5_get_hppi(gic, domain, env->gicv5_iaffid); @@ -168,7 +168,7 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5= Domain domain) if (best.prio =3D=3D PRIO_IDLE || best.prio > env->gicv5_cpuif.icc_pcr[domain] || best.prio >=3D gic_running_prio(env, domain)) { - return (GICv5PendingIrq) { .intid =3D 0, .prio =3D PRIO_IDLE }; + return GICV5_PENDING_IRQ_NONE; } return best; } @@ -258,8 +258,7 @@ static void gic_recalc_ppi_hppi(CPUARMState *env) * enabled, pending and not active. */ for (int i =3D 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_hppi); i++) { - env->gicv5_cpuif.ppi_hppi[i].intid =3D 0; - env->gicv5_cpuif.ppi_hppi[i].prio =3D PRIO_IDLE; + env->gicv5_cpuif.ppi_hppi[i] =3D GICV5_PENDING_IRQ_NONE; }; =20 for (int i =3D 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_active); i++) { --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Date: Mon, 29 Jun 2026 13:00:03 +0100 Message-ID: <20260629120032.1645265-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734521205158500 Content-Type: text/plain; charset="utf-8" From: Jim MacArthur Reviewed-by: Richard Henderson Signed-off-by: Jim MacArthur Message-id: 20260618-jmac-gpc3b-v3-1-353e546067e7@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 45213f71ab..2e4f22f193 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1159,6 +1159,11 @@ static inline bool isar_feature_aa64_rme_gpc2(const = ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) >=3D 2; } =20 +static inline bool isar_feature_aa64_rme_gpc3(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) >=3D 3; +} + static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64PFR0, DIT) !=3D 0; --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734973; cv=none; d=zohomail.com; s=zohoarc; b=LF/653mFRjcghB63A1M6/RnrCdEqEIXLHrzgtUZnoJDz30Xaob8X7tR2spCXqmWYqcIP81mlsZJgELv74trBuq084uKxC32Qb/F5vOgM3/AkoxKZd1Z1qlOYpD0oug3amnR/5xX32QupHJ4iSC9RbtsqL2Vbgo5sI1ZWKvLDEDQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734973; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7RKjdoQN2UDq3Fu/0bG4dxPSqOTiQ2ZKnh7ijMCw0AY=; b=FX2KLUS7tSGK3PB0bkQSFSBMgjtPZmGAwntLnJXKxIboLAZeWegyfKoyZS8ooNKnP9usSozNMrGN5uhMxlugXegOHkdDHDiXmefEe353d8HJhBasL4U6YtvmKSLMhJF35og0NGX82IrYIBg+V65CHVG/BgoXaU8qlNNpmbYTx6s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734973766341.6623038036862; Mon, 29 Jun 2026 05:09:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAg8-00075x-Om; Mon, 29 Jun 2026 08:01:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfk-0006xe-QC for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:10 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfh-0007Rc-LR for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:08 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4936e85e0deso10237015e9.2 for ; Mon, 29 Jun 2026 05:01:03 -0700 (PDT) Received: from lanath.. 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A custom write function is necessary to flush TLBs when this register is written. Also allows write to the GPCBW bit of GPCCR_EL3. Reviewed-by: Richard Henderson Signed-off-by: Jim MacArthur Message-id: 20260618-jmac-gpc3b-v3-2-353e546067e7@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 +++++++ target/arm/helper.c | 19 +++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 31a5567c95..84d33e87dc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -559,6 +559,7 @@ typedef struct CPUArchState { /* RME registers */ uint64_t gpccr_el3; uint64_t gptbr_el3; + uint64_t gpcbw_el3; uint64_t mfar_el3; =20 /* NV2 register */ @@ -1244,6 +1245,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cpu); typedef struct ARMGranuleProtectionConfig { /* GPCCR_EL3 */ uint64_t gpccr; + /* GPCBW_EL3 */ + uint64_t gpcbw; /* GPTBR_EL3 */ uint64_t gptbr; /* ID_AA64MMFR0_EL1.PARange */ @@ -2116,6 +2119,10 @@ FIELD(GPCCR, NA6, 27, 1) FIELD(GPCCR, NA7, 28, 1) FIELD(GPCCR, GPCBW, 29, 1) =20 +FIELD(GPCBW, BWSIZE, 37, 2) +FIELD(GPCBW, BWSTRIDE, 32, 5) +FIELD(GPCBW, BWADDR, 0, 25) + FIELD(MFAR, FPA, 12, 40) FIELD(MFAR, NSE, 62, 1) FIELD(MFAR, NS, 63, 1) diff --git a/target/arm/helper.c b/target/arm/helper.c index a234aa031c..ddca634538 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5001,6 +5001,10 @@ static void gpccr_write(CPUARMState *env, const ARMC= PRegInfo *ri, R_GPCCR_SPAD_MASK | R_GPCCR_NSPAD_MASK | R_GPCCR_RLPAD_= MASK; } =20 + if (cpu_isar_feature(aa64_rme_gpc3, env_archcpu(env))) { + rw_mask |=3D R_GPCCR_GPCBW_MASK; + } + env->cp15.gpccr_el3 =3D (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw= _mask); } =20 @@ -5010,11 +5014,26 @@ static void gpccr_reset(CPUARMState *env, const ARM= CPRegInfo *ri) env_archcpu(env)->reset_l0gptsz); } =20 +static void gpcbw_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t rw_mask =3D R_GPCBW_BWADDR_MASK | R_GPCBW_BWSTRIDE_MASK | + R_GPCBW_BWSIZE_MASK; + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); + env->cp15.gpcbw_el3 =3D (value & rw_mask); +} + static const ARMCPRegInfo rme_reginfo[] =3D { { .name =3D "GPCCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 6, .access =3D PL3_RW, .writefn =3D gpccr_write, .resetfn =3D gpccr_res= et, .fieldoffset =3D offsetof(CPUARMState, cp15.gpccr_el3) }, + { .name =3D "GPCBW_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 5, + .access =3D PL3_RW, .writefn =3D gpcbw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.gpcbw_el3) }, { .name =3D "GPTBR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 4, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.gptb= r_el3) }, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jun 2026 05:01:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/54] target/arm/ptw.c: Add Granule Bypass Windows Date: Mon, 29 Jun 2026 13:00:05 +0100 Message-ID: <20260629120032.1645265-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734849927158500 Content-Type: text/plain; charset="utf-8" From: Jim MacArthur Signed-off-by: Jim MacArthur Reviewed-by: Richard Henderson Message-id: 20260618-jmac-gpc3b-v3-3-353e546067e7@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1470de3010..99295954a1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -343,11 +343,21 @@ bool arm_granule_protection_check(ARMGranuleProtectio= nConfig config, .space =3D ARMSS_Root, }; const uint64_t gpccr =3D config.gpccr; + const uint64_t gpcbw =3D config.gpcbw; unsigned pps, pgs, l0gptsz, level =3D 0; uint64_t tableaddr, pps_mask, align, entry, index; MemTxResult result; int gpi; =20 + const uint64_t BW_ADDR_SHIFT =3D 30; + const uint64_t BW_SIZE_SHIFT =3D 30; + const uint64_t BW_STRIDE_SHIFT =3D 40; + + uint64_t bw_size_field =3D FIELD_EX64(gpcbw, GPCBW, BWSIZE); + uint64_t bw_stride_field =3D FIELD_EX64(gpcbw, GPCBW, BWSTRIDE); + uint64_t bw_addr =3D FIELD_EX64(gpcbw, GPCBW, BWADDR) << BW_ADDR_SHIFT; + uint64_t bw_mask =3D 0; + /* * We assume Granule Protection Check is enabled when * calling this function (GPCCR.GPC =3D=3D 1). @@ -399,6 +409,58 @@ bool arm_granule_protection_check(ARMGranuleProtection= Config config, goto fault_walk; } =20 + /* At this point, GPCCR_EL3 is valid */ + + /* + * GPC Priority 1 (R_GMGRR): + * If GPCCR_EL3.GPCBW is 1 and the configuration GPCBW + * is invalid, the access fails as GPT walk fault at level 0. + */ + if (FIELD_EX64(gpccr, GPCCR, GPCBW)) { + uint64_t bw_size =3D 0; + uint64_t bw_stride =3D 0; + + /* BWSIZE, BWSTRIDE have a limited number of acceptable values. */ + switch (bw_size_field) { + case 0b000: + case 0b001: + case 0b010: + case 0b100: + case 0b110: + bw_size =3D 1ULL << (bw_size_field + BW_SIZE_SHIFT); + break; + default: /* Reserved value */ + goto fault_walk; + } + switch (bw_stride_field) { + case 0b00000: + case 0b00010: + case 0b00100: + case 0b00110: + case 0b00111: + case 0b01000: + case 0b01001: + case 0b01010: + case 0b10000: + bw_stride =3D 1ULL << (bw_stride_field + BW_STRIDE_SHIFT); + break; + default: /* Reserved value */ + goto fault_walk; + } + /* + * GPCBW is invalid if the base address is: + * not aligned to the size programmed in BWSIZE, or + * greater than or equal to the stride value configured by BWSTRID= E. + * We can make bw_mask which marks exactly which bits in bw_addr m= ay + * be set (gpcbwu:gpcbwl). + */ + bw_mask =3D bw_stride - bw_size; + + if (bw_addr & ~bw_mask) { + goto fault_walk; + } + } + /* Note this field is read-only and fixed at reset. */ l0gptsz =3D 30 + FIELD_EX64(gpccr, GPCCR, L0GPTSZ); =20 @@ -433,6 +495,20 @@ bool arm_granule_protection_check(ARMGranuleProtection= Config config, goto fault_fail; } =20 + /* + * Bypass window check. + * I_JJLRM: Granule Protection Table (GPT) lookups can be skipped + * in portions of the memory map by using GPC bypass windows. + * I_XNHTX: The GPC bypass window check (...) is performed + * immediately after priority 3. + * bw_mask from earlier makes this check for us. + */ + if (FIELD_EX64(gpccr, GPCCR, GPCBW)) { + if ((paddress & bw_mask) =3D=3D bw_addr) { + return true; + } + } + /* GPC Priority 4: the base address of GPTBR_EL3 exceeds PPS. */ tableaddr =3D config.gptbr << 12; if (tableaddr & ~pps_mask) { @@ -3879,6 +3955,7 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Tra= nslate *ptw, }; struct ARMGranuleProtectionConfig config =3D { .gpccr =3D env->cp15.gpccr_el3, + .gpcbw =3D env->cp15.gpcbw_el3, .gptbr =3D env->cp15.gptbr_el3, .parange =3D FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANG= E), .support_sel2 =3D cpu_isar_feature(aa64_sel2, cpu), --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734762; cv=none; d=zohomail.com; s=zohoarc; b=llHIMBzuWMt1CXfz4zFTkEVBSVLeoZt0vyhpfrHd4bHaoxmX7SJ3/9Z2+ZmFtqX/kEtFoMojwFUAiQ10H9VvnaiEwJ18n/VHBwFJfEYvLQbuL57iOONdCmPn5qMkNiVZFtwPjrkT+puBEm6RcR1M83rvwJ+PXEemT0QFaul9bZU= ARC-Message-Signature: i=1; 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2 : 0); + /* Enable FEAT_RME_GPC3 */ + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, RME, value ? 3 : 0); } =20 static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734531; cv=none; d=zohomail.com; s=zohoarc; b=PDvMXzYauBbZFgTex6BkVhVo14D1g148/ZKQrvPjm6IvOlvQLzZzS6z2h7cY7lJhuRhk5kThPZ0TVBsWboAedfgqSo1kNFy7euySwmNOUae6XMuyYCeO+cXUKTWn2u9eL2exFJ01Cxxzp6ltl9+29pAnGAJ2RhYcjSZP7Rg7IGU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734531; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=lN37vHzTAwH+qCtzUf9JtjJBEPMP/QIkkrtzMW9C0cA=; b=gJ0GOgZqrBU5B6MRwnN5KHoR/LxB/tY8hyIrHk+kS2822KnpixuOXMeYm41VnghZCiPfG5ROTU5IgC3xhtO9SMXVDGbNXXOgypNoA5aPlQDs39aTc+R18vLfYZ+30WNZUU6lOPicgFfs2H1OVFDjt9QmKFe9o53OrlVChgDDueg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178273453197627.903371809910823; Mon, 29 Jun 2026 05:02:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgD-0007EL-Np; Mon, 29 Jun 2026 08:01:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfl-0006xg-AQ for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:10 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfh-0007Sw-N6 for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:09 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-47248615e4dso1505097f8f.2 for ; Mon, 29 Jun 2026 05:01:05 -0700 (PDT) Received: from lanath.. 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LOGGING_VECTOR_TABLE is added to switch this on, and vec_logging_boot.o is built from boot.S with this flag. Since boot.o is created for multiple test targets, we have to build a separate object and selectively link this new vec_logging_boot.o into particular test binaries. Signed-off-by: Jim MacArthur Reviewed-by: Richard Henderson Message-id: 20260618-jmac-gpc3b-v3-5-353e546067e7@linaro.org Signed-off-by: Peter Maydell --- tests/tcg/aarch64/Makefile.softmmu-target | 11 ++-- tests/tcg/aarch64/system/boot.S | 65 +++++++++++++++++++++++ tests/tcg/aarch64/system/boot.h | 14 +++++ 3 files changed, 86 insertions(+), 4 deletions(-) create mode 100644 tests/tcg/aarch64/system/boot.h diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/= Makefile.softmmu-target index f7a7d2b800..c353b7f8d6 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -25,7 +25,7 @@ LDFLAGS=3D-Wl,-T$(LINK_SCRIPT) TESTS+=3D$(AARCH64_TESTS) $(MULTIARCH_TESTS) EXTRA_RUNS+=3D$(MULTIARCH_RUNS) CFLAGS+=3D-nostdlib -ggdb -O0 $(MINILIB_INC) -LDFLAGS+=3D-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc +LDFLAGS+=3D-static -nostdlib $(MINILIB_OBJS) -lgcc =20 config-cc.mak: Makefile $(quiet-@)( \ @@ -36,17 +36,20 @@ config-cc.mak: Makefile # building head blobs .PRECIOUS: $(CRT_OBJS) =20 +vector_log_boot.o: $(CRT_PATH)/boot.S + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -DLOGGING_VECTOR_TABLE -x assembler-with-= cpp -Wa,--noexecstack -c $< -o $@ + %.o: $(CRT_PATH)/%.S $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -Wa,--noexecstack -= c $< -o $@ =20 # Build and link the tests %: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o =20 memory: CFLAGS+=3D-DCHECK_UNALIGNED=3D1 =20 memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o =20 memory-sve: CFLAGS+=3D-DCHECK_UNALIGNED=3D1 -march=3Darmv8.1-a+sve -O3 =20 @@ -107,7 +110,7 @@ QEMU_MTE_ENABLED_MACHINE=3D-M virt,mte=3Don -cpu max -d= isplay none QEMU_OPTS_WITH_MTE_ON =3D $(QEMU_MTE_ENABLED_MACHINE) $(QEMU_BASE_ARGS) -k= ernel mte: CFLAGS+=3D-march=3Darmv8.5-a+memtag mte: mte.S $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o =20 run-mte: QEMU_OPTS=3D$(QEMU_OPTS_WITH_MTE_ON) run-mte: mte diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boo= t.S index 8bfa4e4efc..c6e5ad889b 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -60,6 +60,40 @@ curr_sp0_irq: curr_sp0_fiq: curr_sp0_serror: curr_spx_sync: +#ifdef LOGGING_VECTOR_TABLE + sub sp, sp, #16 + stp x0, x1, [sp, #0] + mrs x0, ESR_EL3 + lsr x0, x0, #26 + and x0, x0, #0x3f + cmp x0, #37 + beq data_fault + cmp x0, #30 + beq gpc_fault + b generic_exception + +data_fault: + mrs x0, FAR_EL3 + adrp x1, exception_log + str x0, [x1] + ldr x0, =3D0x1001 + str x0, [x1, #8] + b skip_return +gpc_fault: + mrs x0, FAR_EL3 + adrp x1, exception_log + str x0, [x1] + ldr x0, =3D0x1002 + str x0, [x1, #8] + /* Fall through */ +skip_return: + mrs x0, ELR_EL3 + add x0, x0, #4 /* Skip faulting instruction */ + msr ELR_EL3, x0 + ldp x0, x1, [sp, #0] + add sp, sp, #16 + eret +#endif curr_spx_irq: curr_spx_fiq: curr_spx_serror: @@ -71,6 +105,7 @@ lower_a32_sync: lower_a32_irq: lower_a32_fiq: lower_a32_serror: +generic_exception: adr x1, .unexp_excp exit_msg: mov x0, SYS_WRITE0 @@ -404,6 +439,36 @@ ttb_stage2: .space 4096, 0 =20 .align 12 + .global realms_gpt0 + /* GPT stage 0 table */ +realms_gpt0: + .space 4096, 0 + .align 17 + .global realms_gpt1 + /* GPT stage 1 table, initialised to all 0xFF (full access) */ +realms_gpt1: + .space 524288, 0xFF +#ifdef LOGGING_VECTOR_TABLE + .align 12 + .global exception_fault_address + .type exception_fault_address, @object + .size exception_fault_address, 8 + .global exception_type_code + .type exception_type_code, @object + .size exception_type_code, 8 + /* + * These fields record details of the last exception, if + * LOGGING_VECTOR_TABLE is defined. + */ +exception_log: +exception_fault_address: + /* The contents of FAR_EL3 when an exception is taken. */ + .space 8, 0 +exception_type_code: + /* A generic code indicating what type of exception occurred. */ + .space 8, 0 +#endif + .align 12 system_stack: .space 4096, 0 system_stack_end: diff --git a/tests/tcg/aarch64/system/boot.h b/tests/tcg/aarch64/system/boo= t.h new file mode 100644 index 0000000000..cb9ab6c1b9 --- /dev/null +++ b/tests/tcg/aarch64/system/boot.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * + * + * Copyright (c) 2026 Linaro Ltd + * + */ + + +/* Global variables exported in boot.S */ +extern volatile uint64_t exception_fault_address; /* Updated by ISR */ +extern volatile uint64_t exception_type_code; /* Updated by ISR */ +extern uint64_t realms_gpt0[]; +extern uint64_t realms_gpt1[]; --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734549; cv=none; d=zohomail.com; s=zohoarc; b=Fw7e8LMGmv8leefw1x2Dvp792zGGWz4k8hGoYCzgdBNUKP7QrA3yZoeAeocssLqu2wdao5MFezIhICjYcn2oXE7tGrbbu7uFhoFGOdM5Pg4q1j8jQe1wHmbbUXEUVTXsmVYQbC//4RR1ZbZhRAVThdhxnB5LbeV8FaqgZuUoQFA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734549; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-473dddcb295sm8753061f8f.35.2026.06.29.05.01.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 05:01:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1782734465; x=1783339265; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ppLpIKgj1iYNeAkqUQhnvLVdqr6JLUnnYruG7BwRYA0=; b=rkfbJi2/uQEsUBxK96WAXcWtFghoRlqIkTrjMlR9xt+Drc33CfZtRJmkPVqWB3izUa XNIPmgfGOzd6emYEn6NrPZwPPpto31fNMSElkOvX1OjFoubOVvdLUIA+IJNZAfMnqDvQ LcNYQSqvBi53JB1j7iAe1PrDzBqBrXM1ojS6FxhNWRZgmRXfeyB+u5W0H3gnpZneceR/ axIB2RutFmNpsEEIACkgbBbR6P/VPO12rmeetGcsOKPs5Og8IvQW4z5abGMlGzHbqpEu dfyA5LBSA4BYBT2nMb28lC7g7r9fyT77rc5ZxGYpmhCOBmWU5S11x7BW64S18UAJu4Ir nPYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782734465; x=1783339265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ppLpIKgj1iYNeAkqUQhnvLVdqr6JLUnnYruG7BwRYA0=; b=bDdnV6H5trZ53sv6P0TOCwhhpDrJJwEsAkbQXe9jxme5X3M2VvL4JJov3e0y20/1HG 4T/CDjw2U39NfRhYGTkFiCSa6P1FMy4dBQad8QmwWDTfiSCou7fgbjHlk+6Q9CMRy+eE yfOQuXuS80g4xv6GgJGaqF8REx3DopNHASn0jwhyd8C55nfPnWi3NdQlNUCmQWBlzbfl wSO9/i/3T2YEg4DBzW3BhMXqFDOTP+OdJbt2FpUdkP1to6u/oqJvnZCXA0t7V3ucmKI2 FN391P7XeJNBCSkpf8FENUpuwWTbBDprUoPkXbSCPpN7Tbh7p2OagoekgnXKpT+fFXHF t8ow== X-Gm-Message-State: AOJu0YxvJWloi66CHQe8g4kQRFuqcXImXhVC/Cu8rgyYRI3bJ0eqRQp0 eRujvTCKbDBBnLiAzt4kSSOjx+mPMhMvHk5EIGPy24Ul6d3/wrdqTtCHKFundX1qlYMhUf4zMuV xmSg3 X-Gm-Gg: AfdE7cnVw9uFNqHmxn0fqk7g2xJcr2+zGjEJTUUdaoe17SAanHtLT3Zr0Tg0AMhF68c 7RvbAx/O7LfG90J5+yQ9qzOmO+doHHfhclxta2Xq0zPR9GzVqwGafM5+O+RCigr0qZ8dCeTuCUt VUJi+dRtsTZ4EYvcJrxa458/wNufzilGtdp2NfiSfm61Q0zgfEB3+gyZmgNRd1yZ1KZTHwrDBHZ LdRXnX0dbcWYKamBUJ1lJCJzP8w8sXlfWFvaPkQV3wYrb+LvZEHGiDy4n36H1buKd345puTUDZA EDnHmRj1limp4h8Rknwf98niPEtEEkJ8L+T8vjHkn9wE5tBcKJxrK4evCOvazzO78EcsNgoPnRP eJmtUH9qgZyalF2qd4Orz5z9DBWlC/T8bYn0Y1zLAN9WIuZjm+v0ygwo8E6z1J5XmNduxehNo2E aQD4xyNWIWWBq3pUqh0QU5640rXUpT4MgIMakbTi6Ds0SNicmV3iiBUMtrscfVC4h81ybsCREHI 6sv8UGoBu/S6z191BbWJw== X-Received: by 2002:a05:600c:3052:b0:493:b6e4:fb2b with SMTP id 5b1f17b1804b1-493b6e4fbdemr6655885e9.25.1782734465092; Mon, 29 Jun 2026 05:01:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/54] tests/tcg/aarch64/system/gpc-test.c: Basic test for granule protection check Date: Mon, 29 Jun 2026 13:00:08 +0100 Message-ID: <20260629120032.1645265-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734551378158500 Content-Type: text/plain; charset="utf-8" From: Jim MacArthur * Sets up granule protection tables * Enables GPC and bypass windows * Performs memory accesses in the protected region to check for allowed and disallowed reads. Reviewed-by: Richard Henderson Signed-off-by: Jim MacArthur Message-id: 20260618-jmac-gpc3b-v3-6-353e546067e7@linaro.org Signed-off-by: Peter Maydell --- tests/tcg/aarch64/Makefile.softmmu-target | 11 +- tests/tcg/aarch64/system/gpc-test.c | 165 ++++++++++++++++++++++ 2 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/system/gpc-test.c diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/= Makefile.softmmu-target index c353b7f8d6..3f30be6c5d 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -53,7 +53,10 @@ memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILI= B_OBJS) =20 memory-sve: CFLAGS+=3D-DCHECK_UNALIGNED=3D1 -march=3Darmv8.1-a+sve -O3 =20 -TESTS+=3Dmemory-sve +gpc-test: gpc-test.c $(LINK_SCRIPT) vector_log_boot.o $(MINILIB_OBJS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) vector_log_boot.o + +TESTS+=3Dmemory-sve gpc-test =20 # Running QEMU_BASE_MACHINE=3D-M virt -cpu max -display none @@ -74,6 +77,12 @@ QEMU_EL2_MACHINE=3D-machine virt,virtualization=3Don,gic= -version=3D2 -cpu cortex-a57 - QEMU_EL2_BASE_ARGS=3D-semihosting-config enable=3Don,target=3Dnative,chard= ev=3Doutput,arg=3D"2" run-vtimer: QEMU_OPTS=3D$(QEMU_EL2_MACHINE) $(QEMU_EL2_BASE_ARGS) -kernel =20 +# gpc tests need EL3 and RME +QEMU_EL3_MACHINE=3D-machine virt,virtualization=3Don,secure=3Don,gic-versi= on=3D3 -cpu max,x-rme=3Don +QEMU_EL3_BASE_ARGS=3D-semihosting-config enable=3Don,target=3Dnative,chard= ev=3Doutput,arg=3D"3" +run-gpc-test: QEMU_OPTS=3D$(QEMU_EL3_MACHINE) $(QEMU_EL3_BASE_ARGS) -kern= el +run-gpc3-test: QEMU_OPTS=3D$(QEMU_EL3_MACHINE) $(QEMU_EL3_BASE_ARGS) -kern= el + # Simple Record/Replay Test .PHONY: memory-record run-memory-record: memory-record memory diff --git a/tests/tcg/aarch64/system/gpc-test.c b/tests/tcg/aarch64/system= /gpc-test.c new file mode 100644 index 0000000000..f26b23efaf --- /dev/null +++ b/tests/tcg/aarch64/system/gpc-test.c @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * + * + * Copyright (c) 2026 Linaro Ltd + * + */ + +#include +#include +#include +#include "boot.h" + +#define ID_AA64PFR0_EL1 "S3_0_C0_C4_0" + +#define GPTBR_EL3 "S3_6_C2_C1_4" +#define GPCBW_EL3 "S3_6_C2_C1_5" +#define GPCCR_EL3 "S3_6_C2_C1_6" +#define VBAR_EL3 "S3_6_C12_C0_0" + +#define get_sys_reg(register_name, dest) \ + asm("mrs %[reg], " register_name "\n\t" : [reg] "=3Dr" (dest)) +#define set_sys_reg(register_name, value) \ + asm("msr " register_name ", %[reg]\n\r" : : [reg] "r" (value)) + +const uint32_t gpc_granule_size =3D 4096; +const uint32_t gpis_per_64_bits =3D 16; + +int main(uint64_t sp) +{ + uint64_t out; + uint64_t pfr0; + uint64_t gpt_base; + uint64_t rme_status; + uint64_t currentel_raw; + uint64_t currentel; + uint64_t gpcbw; + uint64_t gpt_table0_addr =3D (uint64_t) realms_gpt0; + uint64_t gpt_table1_addr =3D (uint64_t) realms_gpt1; + + /* Mask is FNG1, FNG0, and A2 */ + const uint64_t feature_mask =3D (1ULL << 18 | 1ULL << 17 | 1ULL << 16); + const uint64_t in =3D feature_mask; + + get_sys_reg("CurrentEL", currentel_raw); + currentel =3D (currentel_raw >> 2) & 0x3; + + if (currentel < 3) { + ml_printf("FAIL: Test must be run at EL3 (it is %d)\n", currentel); + return 1; + } + + get_sys_reg(ID_AA64PFR0_EL1, pfr0); + + /* rme_status is 1 for RME, 2 for RME + GPC2, 3 for RME+GPC3 */ + rme_status =3D (pfr0 >> 52) & 0xF; + if (rme_status < 2) { + ml_printf("SKIP: System does not support RME (RME=3D%ld)\n", rme_s= tatus); + return 0; + } + + /* Configure the level 0 table for the first 4GB of memory */ + realms_gpt0[0] =3D gpt_table1_addr | 0x3; /* Covers GB 0; table descri= ptor */ + realms_gpt0[1] =3D 0xf1; /* Covers GB 1; full access */ + realms_gpt0[2] =3D 0xf1; /* Covers GB 2; full access */ + realms_gpt0[3] =3D 0xf1; /* Covers GB 3; full access */ + + /* Pick an artibtrary location to read inside the first 1GB. */ + uint64_t fault_location =3D 0x10202008; + uint32_t gpi_index =3D fault_location / gpc_granule_size; + realms_gpt1[gpi_index / gpis_per_64_bits] =3D 0; + + gpt_base =3D gpt_table0_addr >> 12; + set_sys_reg(GPTBR_EL3, gpt_base); + + /* + * Default values: + * PPS=3D0: GPC table 0 protects 4GB. + * RLPAD=3D0: Realm physical address spaces are normal + * NSPAD=3D0: Non-secure physical address spaces are normal + * SPAD=3D0: Secure physical address spaces are normal + * IRGN=3D0: Inner non-cacheable + * ORGN=3D0: Outer non-cacheable + * PGS=3D0: Physical granule size is 4KB. + * GPCP=3D0: All GPC faults reported + * TBGPCP=3D0: Trace buffer rejects trace + * L0GPTSZ=3D0: Each entry in table 0 protects 1GB. + * APPSAA=3D0: Accesses above 4GB must be to Non-secure PAs + * GPCBW=3D0: Bypass windows disabled. + * NA6, NA7, NSP, SA, NSO are all reserved values for GPI. + */ + uint64_t gpccr =3D 0; + + /* Switch on granule protection check */ + gpccr |=3D 1 << 16; /* GPC enabled. */ + gpccr |=3D 0b10 << 12; /* SH =3D Outer shareable */ + set_sys_reg(GPCCR_EL3, gpccr); + + /* Access some memory outside the GPC forbidden region */ + uint64_t x =3D *(unsigned int *) (fault_location + 4096 * 16); + ml_printf("Fault address: %lx\n", exception_fault_address); + if (exception_fault_address !=3D 0) { + ml_printf("FAIL: Memory access was blocked by GPC, " + "and should not have been\n"); + return 1; + } + + /* Access the GPC forbidden region */ + x =3D *(unsigned int *) fault_location; + + ml_printf("Fault address: %lx\n", exception_fault_address); + if (exception_fault_address !=3D fault_location) { + ml_printf("FAIL: Memory access was not blocked by GPC, " + "and should have been\n"); + return 1; + } + + rme_status =3D (pfr0 >> 52) & 0xF; + if (rme_status < 3) { + ml_printf("SKIP: System does not support GPC3 (RME=3D%ld)\n", rme_= status); + return 0; + } + + /* Clear the exception record */ + exception_fault_address =3D 0; + + /* Enable bypass windows */ + gpccr |=3D 1 << 29; /* GPC Bypass windows enabled */ + set_sys_reg(GPCCR_EL3, gpccr); + + gpcbw =3D 0; /* Base 0GB, Size 1GB, Stride 1TB */ + set_sys_reg(GPCBW_EL3, gpcbw); + ml_printf("GPCBW configured\n"); + + /* Access the GPC forbidden region again */ + x =3D *(unsigned int *) fault_location; + + ml_printf("Fault address: %lx\n", exception_fault_address); + if (exception_fault_address !=3D 0) { + ml_printf("FAIL: Memory access was blocked by GPC, " + "and should have been allowed by bypass window. code=3D%= lx\n", + exception_type_code); + return 1; + } + + /* Clear the exception record */ + exception_fault_address =3D 0; + /* Reconfigure GPCBW to 1GB start */ + gpcbw =3D 1; /* Base 1GB, Size 1GB, Stride 1TB */ + set_sys_reg(GPCBW_EL3, gpcbw); + ml_printf("GPCBW reconfigured for 1GB start\n"); + + /* Access the GPC forbidden region again */ + x =3D *(unsigned int *) fault_location; + + ml_printf("Fault address: %lx\n", exception_fault_address); + if (exception_fault_address !=3D fault_location) { + ml_printf("FAIL: Memory access was allowed by GPC, " + "and should not have been allowed by bypass window. code= =3D%lx\n", + exception_type_code); + return 1; + } + + return 0; +} --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734618; cv=none; d=zohomail.com; s=zohoarc; b=iJpT90c0CqbxESpSKDhlolTkbwMLUQjgllc6pInV6fOGPkyCe0CrGfIiL8E/GR5IC8txUQzJPoAVt8nYltg299sncuLBkkRERuAtH8G8OOnCs93Z4ljHmfThs4s+b7gDvjFhPPampryLN47jz8jhjnrGysyDGmB9S/n+nBJ+ROI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734618; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Kdr+B0IDw6BWJTk+TtoSalHMga33GbxHLgqk8sNq28g=; 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Signed-off-by: Maty=C3=A1=C5=A1 Bobek Signed-off-by: Pavel Pisa Tested-by: Pavel Pisa Reviewed-by: Bernhard Beschow Reviewed-by: Pavel Pisa Message-id: 629d00a1d8712dbf293fb13ac1a02bf80f6334ca.1782140438.git.matyas.= bobek@gmail.com Signed-off-by: Peter Maydell --- hw/arm/sabrelite.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index db5669c5c2..04484aaa14 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -104,8 +104,10 @@ static void sabrelite_init(MachineState *machine) } } =20 -static void sabrelite_machine_init(MachineClass *mc) +static void sabrelite_machine_class_init(ObjectClass *oc, const void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); + mc->desc =3D "Freescale i.MX6 Quad SABRE Lite Board (Cortex-A9)"; mc->init =3D sabrelite_init; mc->max_cpus =3D FSL_IMX6_NUM_CPUS; @@ -114,4 +116,18 @@ static void sabrelite_machine_init(MachineClass *mc) mc->auto_create_sdcard =3D true; } =20 -DEFINE_MACHINE_ARM("sabrelite", sabrelite_machine_init) +static const TypeInfo sabrelite_machine_init_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("sabrelite"), + .parent =3D TYPE_MACHINE, + .class_init =3D sabrelite_machine_class_init, + .instance_size =3D sizeof(MachineState), + .abstract =3D false, + .interfaces =3D arm_machine_interfaces, +}; + +static void sabrelite_machine_init_register_types(void) +{ + type_register_static(&sabrelite_machine_init_typeinfo); +} + +type_init(sabrelite_machine_init_register_types) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734652; cv=none; d=zohomail.com; s=zohoarc; b=LcImdimlDdDUBER9DVMHARRGZEZqKTff31+0FR8peHini8UNL2WCPEqzzUv1jKvG3iEjpKmYitUG/LCFh8Pv/4NuAL/jxOwmL77VzMnm4Tyuga4nwN/LJIg/OpnIflQwf3tbJ8cAsnrNypy/YC6LpAn7xvfwShskYO4vau2V1m4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734652; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=EDFZRou/PG3IEZxQk0bZnXFq3CToCUYmHAeKMV8JW0o=; b=R+qoLtBb3h/tYtLoIfKtytlZF3snXxi3oOlburngyznY1KSXO32ZeVFjGl7smFA6Vod8l35Xie8r0zvRZHU54PScdnYsIt59wabBjH/e0inwdyGOFwDq+319u7WYKXE8v/gfwTUjEBF0H3eaFaleVofXVn5rYRQuHOSMmjNncu0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734652827399.176598839916; Mon, 29 Jun 2026 05:04:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgG-0007LL-Vi; Mon, 29 Jun 2026 08:01:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfm-0006zj-JR for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:10 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfk-0007Vd-Q5 for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:10 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-46e4764ca48so3094189f8f.0 for ; Mon, 29 Jun 2026 05:01:08 -0700 (PDT) Received: from lanath.. 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Previously, Sabrelite board MachineState was declared indirectly by the DEFINE_MACHINE_ARM macro. FslIMX6State was only instantiated in the sabrelite_init function. For FlexCAN device, machine properties will be used to select QEMU CAN buses. A custom class is therefore required, so the CanBusState "connections" can then be added as fields. Signed-off-by: Maty=C3=A1=C5=A1 Bobek Signed-off-by: Pavel Pisa Tested-by: Pavel Pisa Reviewed-by: Bernhard Beschow Reviewed-by: Pavel Pisa Message-id: 115740db83cf2e5a5e7bb349130c9706934ec1f3.1782140438.git.matyas.= bobek@gmail.com Signed-off-by: Peter Maydell --- hw/arm/sabrelite.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 04484aaa14..7e036e6388 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -20,6 +20,15 @@ #include "qemu/error-report.h" #include "system/qtest.h" =20 +struct SabreliteMachineState { + MachineState parent_obj; + + FslIMX6State soc; +}; + +#define TYPE_SABRELITE_MACHINE MACHINE_TYPE_NAME("sabrelite") +OBJECT_DECLARE_SIMPLE_TYPE(SabreliteMachineState, SABRELITE_MACHINE) + static struct arm_boot_info sabrelite_binfo =3D { /* DDR memory start */ .loader_start =3D FSL_IMX6_MMDC_ADDR, @@ -41,7 +50,7 @@ static void sabrelite_reset_secondary(ARMCPU *cpu, =20 static void sabrelite_init(MachineState *machine) { - FslIMX6State *s; + SabreliteMachineState *s =3D SABRELITE_MACHINE(machine); =20 /* Check the amount of memory is compatible with the SOC */ if (machine->ram_size > FSL_IMX6_MMDC_SIZE) { @@ -50,13 +59,12 @@ static void sabrelite_init(MachineState *machine) exit(1); } =20 - s =3D FSL_IMX6(object_new(TYPE_FSL_IMX6)); - object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); + object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_FSL_IMX6= ); =20 /* Ethernet PHY address is 6 */ - object_property_set_int(OBJECT(s), "fec-phy-num", 6, &error_fatal); + object_property_set_int(OBJECT(&s->soc), "fec-phy-num", 6, &error_fata= l); =20 - qdev_realize(DEVICE(s), NULL, &error_fatal); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR, machine->ram); @@ -70,7 +78,7 @@ static void sabrelite_init(MachineState *machine) /* Add the sst25vf016b NOR FLASH memory to first SPI */ Object *spi_dev; =20 - spi_dev =3D object_resolve_path_component(OBJECT(s), "spi1"); + spi_dev =3D object_resolve_path_component(OBJECT(&s->soc), "spi1"); if (spi_dev) { SSIBus *spi_bus; =20 @@ -89,7 +97,7 @@ static void sabrelite_init(MachineState *machine) qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fat= al); =20 cs_line =3D qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS,= 0); - qdev_connect_gpio_out(DEVICE(&s->gpio[2]), 19, cs_line); + qdev_connect_gpio_out(DEVICE(&s->soc.gpio[2]), 19, cs_line= ); } } } @@ -100,7 +108,7 @@ static void sabrelite_init(MachineState *machine) sabrelite_binfo.secondary_cpu_reset_hook =3D sabrelite_reset_secondary; =20 if (!qtest_enabled()) { - arm_load_kernel(&s->cpu[0], machine, &sabrelite_binfo); + arm_load_kernel(&s->soc.cpu[0], machine, &sabrelite_binfo); } } =20 @@ -117,10 +125,10 @@ static void sabrelite_machine_class_init(ObjectClass = *oc, const void *data) } =20 static const TypeInfo sabrelite_machine_init_typeinfo =3D { - .name =3D MACHINE_TYPE_NAME("sabrelite"), + .name =3D TYPE_SABRELITE_MACHINE, .parent =3D TYPE_MACHINE, .class_init =3D sabrelite_machine_class_init, - .instance_size =3D sizeof(MachineState), + .instance_size =3D sizeof(SabreliteMachineState), .abstract =3D false, .interfaces =3D arm_machine_interfaces, }; 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The clock frequency will be used for computing timestamps in FlexCAN emulator. Signed-off-by: Maty=C3=A1=C5=A1 Bobek Signed-off-by: Pavel Pisa Tested-by: Pavel Pisa Reviewed-by: Bernhard Beschow Reviewed-by: Pavel Pisa Message-id: 95da33074f8b79842566d61e4e04448b1e622080.1782140438.git.matyas.= bobek@gmail.com Signed-off-by: Peter Maydell --- hw/misc/imx6_ccm.c | 24 ++++++++++++++++++++++++ hw/misc/trace-events | 2 ++ include/hw/misc/imx6_ccm.h | 4 ++++ include/hw/misc/imx_ccm.h | 1 + 4 files changed, 31 insertions(+) diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c index a10b67d396..45fdd0d5a8 100644 --- a/hw/misc/imx6_ccm.c +++ b/hw/misc/imx6_ccm.c @@ -257,6 +257,15 @@ static uint64_t imx6_analog_get_pll2_clk(IMX6CCMState = *dev) return freq; } =20 +static uint64_t imx6_analog_get_pll3_clk(IMX6CCMState *dev) +{ + uint64_t freq =3D 480000000; + + trace_imx6_analog_get_pll3_clk(freq); + + return freq; +} + static uint64_t imx6_analog_get_pll2_pfd0_clk(IMX6CCMState *dev) { uint64_t freq =3D 0; @@ -344,6 +353,18 @@ static uint64_t imx6_ccm_get_per_clk(IMX6CCMState *dev) return freq; } =20 +static uint64_t imx6_ccm_get_can_clk(IMX6CCMState *dev) +{ + uint64_t freq =3D 0; + + freq =3D imx6_analog_get_pll3_clk(dev) / 8; + freq /=3D (1 + EXTRACT(dev->ccm[CCM_CSCMR2], CAN_CLK_PODF)); + + trace_imx6_ccm_get_can_clk(freq); + + return freq; +} + static uint32_t imx6_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk cloc= k) { uint32_t freq =3D 0; @@ -358,6 +379,9 @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMStat= e *dev, IMXClk clock) case CLK_IPG_HIGH: freq =3D imx6_ccm_get_per_clk(s); break; + case CLK_CAN: + freq =3D imx6_ccm_get_can_clk(s); + break; case CLK_32k: freq =3D CKIL_FREQ; break; diff --git a/hw/misc/trace-events b/hw/misc/trace-events index b88accc437..99910fc068 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -242,11 +242,13 @@ imx6_analog_get_periph_clk(uint32_t freq) "freq =3D %= u Hz" imx6_analog_get_pll2_clk(uint32_t freq) "freq =3D %u Hz" imx6_analog_get_pll2_pfd0_clk(uint32_t freq) "freq =3D %u Hz" imx6_analog_get_pll2_pfd2_clk(uint32_t freq) "freq =3D %u Hz" +imx6_analog_get_pll3_clk(uint32_t freq) "freq =3D %u Hz" imx6_analog_read(const char *reg, uint32_t value) "reg[%s] =3D> 0x%" PRIx32 imx6_analog_write(const char *reg, uint32_t value) "reg[%s] <=3D 0x%" PRIx= 32 imx6_ccm_get_ahb_clk(uint32_t freq) "freq =3D %u Hz" imx6_ccm_get_ipg_clk(uint32_t freq) "freq =3D %u Hz" imx6_ccm_get_per_clk(uint32_t freq) "freq =3D %u Hz" +imx6_ccm_get_can_clk(uint32_t freq) "freq =3D %u Hz" imx6_ccm_get_clock_frequency(unsigned clock, uint32_t freq) "(Clock =3D %d= ) =3D %u" imx6_ccm_read(const char *reg, uint32_t value) "reg[%s] =3D> 0x%" PRIx32 imx6_ccm_reset(void) "" diff --git a/include/hw/misc/imx6_ccm.h b/include/hw/misc/imx6_ccm.h index ccf46d7353..a54b940686 100644 --- a/include/hw/misc/imx6_ccm.h +++ b/include/hw/misc/imx6_ccm.h @@ -164,6 +164,10 @@ #define PERCLK_PODF_SHIFT (0) #define PERCLK_PODF_LENGTH (6) =20 +/* CCM_CSCMR2 */ +#define CAN_CLK_PODF_SHIFT (2) +#define CAN_CLK_PODF_LENGTH (6) + /* CCM_ANALOG_PFD_528 */ #define PFD0_FRAC_SHIFT (0) #define PFD0_FRAC_LENGTH (6) diff --git a/include/hw/misc/imx_ccm.h b/include/hw/misc/imx_ccm.h index c4212d04ea..6839716ea3 100644 --- a/include/hw/misc/imx_ccm.h +++ b/include/hw/misc/imx_ccm.h @@ -46,6 +46,7 @@ typedef enum { CLK_EXT, CLK_HIGH_DIV, CLK_HIGH, + CLK_CAN, } IMXClk; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-473dddcb295sm8753061f8f.35.2026.06.29.05.01.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 05:01:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1782734470; x=1783339270; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BPouxIFJYi6K0Kg3sEqqWKKn7Ziph+VwZm6dT3aJqnA=; b=ds4GGopWG8RnX3ZL3BWeHdXPLxTvqnTrM74j3zcS3NPR1+DSczIA2IKZTb3z3shLbZ wXrV9CbG1pTi0wT/Hk2Mz+o0sNtfi3iAmwm9vMj/Xn9VU7gXVD0i6BBHFNw5ahNquOK8 aoghsBmvoLFbykmdoHim7Tn5oIl/Lx2vu5O1XcM4TDktOdniSfPO2pgfBV/WD6iM6hcQ PXXIOMo/G2y5tALBxt24MJDB9wRkqlAujld/crdRJNs6CsqcWQy7N6jdooQ1QYiZHAgB zTwjnVnqX9g123e/Mo3JXHAO1PNdLZWc4bA3uiLmxuacHgq3Oi77GJfhV3pgKPBf6oiy 1NbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782734470; x=1783339270; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=BPouxIFJYi6K0Kg3sEqqWKKn7Ziph+VwZm6dT3aJqnA=; b=FXQa7mHBClykOGSSwBT7eyy0Qu2u0yJZ5v88/4EGPMOV+yJaXM7HUtjXkbYR6XYUOg O47uM1JlyOGB51LsBnSbVe20baF3YrcVzFb0Iqf4rpFWFfKyaryctfZo7WPYWZNk/mQL jK4a7IO/BMUDSg9iYhewockzzOfHF6wM7Hzotfw+EWQeuYb79lVPNnzRk+OvTY2Xgk+w qQGnlx3JgTU7XN3A9P8IYOzQzijaC2ZIQHCN5fszRonyZ3YYCsC+4jYYo6/8tBW533G1 nY6ncMCKPcIYINYB3rKEh5Qo7LSZNcbrHQ8YO/ay/8FSHR3O9vJk0vw3jqKsHAiI/4Jy 0pbQ== X-Gm-Message-State: AOJu0YwCTdXuPQ9I4H4qCwoTlKzgYKrTGYV2vyZACRbN9Ed5JuvSaVx2 DObl6+hWvEEdML+Knnk6GgSrR8Xixyd7vYULtkv0LWLZ8jZYw/ijDx1XJHOpH4fSPV/r7/25sL6 PBIih X-Gm-Gg: AfdE7cmTtFu4gfeANlwXDayslJLt/9nWNAKt9Zu7vjj2hlbgrS5woXqWPn5DC+kvqQ2 wJTWohPAxdm5zSoplSlD8/viSk4zqrCRLe9e35X0+ID12Y1CxBVa+5UuLP6Nwb8BuJq8yHJ/gbB EXDu40JZGMIoFW40tMTOi36ri5sb84A10X0WPqktHwOU0sskhC4CFpBGDpW0pRvyfYRDvVQiCUO Mdrf7Z07l8LkxCUHloxn/yTs5FIZg2mh9cGkLT9R3ZxcQulVSUV+dl8mdwJSXaE4wlK6Xzlmlcj L6T6wA6KZheQ2Fi0f3MiamNlH+tSYXVqfI6DSSFfBT/ZIlnZEmLGd1FlmEYildtl6THYH8ma9Es jDyl8b3hWtyvgeYEGUASZx0rjbo/5eotfu8DLZvkuTMdqkAybS/c+ps/sv4c0RsFXfCsVbCsM8Q FLy0tYeJfR9vNEkJS6ugUrRNgob2gcuxKVSaDGOyTorwfJtOyMD+Vv+LpTlKf49S3DhBi4vQ6ar KCn+3fKd+g5H+pOIqDRGA== X-Received: by 2002:a05:6000:2c0b:b0:45d:4c30:81a6 with SMTP id ffacd0b85a97d-46da753faa0mr24961917f8f.5.1782734469419; Mon, 29 Jun 2026 05:01:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/54] hw/net/can/flexcan: NXP FlexCAN core emulation Date: Mon, 29 Jun 2026 13:00:12 +0100 Message-ID: <20260629120032.1645265-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735168536158500 From: Maty=C3=A1=C5=A1 Bobek Added the FlexCAN2 emulator implementation core, with CAN_FLEXCAN Kconfig flag and MAINTAINERS entry. FlexCAN2 version can be found in i.MX6 SoCs and others. More information about the implementation can be found in [1]. Some macro and struct defintions were borrowed from the Linux kernel. The original authors agreed with relicensing them to GPL-2.0-or-later on the qemu-devel mailing list. [1] http://dspace.cvut.cz/bitstream/handle/10467/122654/F3-BP-2025-Bobek-Ma= tyas-BP_Bobek_FlexCAN_final_4.pdf Signed-off-by: Maty=C3=A1=C5=A1 Bobek Signed-off-by: Pavel Pisa Tested-by: Pavel Pisa Reviewed-by: Bernhard Beschow Reviewed-by: Pavel Pisa Message-id: 03dc62ff8013bb946aab8f64e51638b810629529.1782140438.git.matyas.= bobek@gmail.com Signed-off-by: Peter Maydell --- MAINTAINERS | 8 + hw/net/Kconfig | 5 + hw/net/can/flexcan.c | 1396 +++++++++++++++++++++++++++++++++++++ hw/net/can/flexcan_regs.h | 197 ++++++ hw/net/can/meson.build | 1 + hw/net/can/trace-events | 18 + include/hw/net/flexcan.h | 145 ++++ 7 files changed, 1770 insertions(+) create mode 100644 hw/net/can/flexcan.c create mode 100644 hw/net/can/flexcan_regs.h create mode 100644 include/hw/net/flexcan.h diff --git a/MAINTAINERS b/MAINTAINERS index 72357df7c4..91317818bf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2107,6 +2107,14 @@ F: hw/net/can/xlnx-* F: include/hw/net/xlnx-* F: tests/qtest/xlnx-can*-test* =20 +FlexCAN +M: Matyas Bobek +M: Pavel Pisa +S: Maintained +F: hw/net/can/flexcan.c +F: hw/net/can/flexcan_regs.h +F: include/hw/net/flexcan.h + EDU M: Jiri Slaby S: Maintained diff --git a/hw/net/Kconfig b/hw/net/Kconfig index f9a1dfb80d..b56a173eed 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -157,3 +157,8 @@ config CAN_CTUCANFD_PCI default y if PCI_DEVICES depends on PCI && CAN_CTUCANFD select CAN_BUS + +config CAN_FLEXCAN + bool + depends on IMX + select CAN_BUS diff --git a/hw/net/can/flexcan.c b/hw/net/can/flexcan.c new file mode 100644 index 0000000000..1ea459d9f6 --- /dev/null +++ b/hw/net/can/flexcan.c @@ -0,0 +1,1396 @@ +/* + * QEMU model of the NXP FLEXCAN device. + * + * This implementation is based on the following reference manual: + * i.MX 6Dual/6Quad Applications Processor Reference Manual + * Document Number: IMX6DQRM, Rev. 6, 05/2020 + * + * Copyright (c) 2025 Matyas Bobek + * + * Based on CTU CAN FD emulation implemented by Jan Charvat. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/core/sysbus.h" +#include "qapi/error.h" +#include "hw/core/irq.h" +#include "migration/vmstate.h" +#include "net/can_emu.h" +#include "hw/core/qdev-properties.h" +#include "trace.h" + +#include "hw/net/flexcan.h" +#include "flexcan_regs.h" +#include "qemu/timer.h" + +/* + * Indicates MB w/ received frame has not been serviced yet + * This is an emulator-only flag in position of unused (reserved) bit + * of message buffer control register + */ +#define FLEXCAN_MB_CNT_NOT_SRV BIT(23) +/** + * if no MB is locked, FlexcanState.locked_mb + * is set to FLEXCAN_NO_MB_LOCKED + */ +#define FLEXCAN_NO_MB_LOCKED -1 +/** + * if no frame is waiting in the SMB, FlexcanState.smb_target_mbid + * is set to FLEXCAN_SMB_EMPTY + */ +#define FLEXCAN_SMB_EMPTY -1 +/** + * When the module is disabled or in freeze mode, + * the timer is not running. That is indicated by setting + * FlexcanState.timer_start to FLEXCAN_TIMER_STOPPED. + */ +#define FLEXCAN_TIMER_STOPPED -1 + +/* These constants are returned by flexcan_fifo_rx() and flexcan_mb_rx(), = */ +enum FlexcanRx { +/* Retry the other receiving mechanism (ie. message bufer or mailbox). */ + FLEXCAN_RX_SEARCH_RETRY, +/* The frame was received and stored. */ + FLEXCAN_RX_SEARCH_ACCEPT, +/* The frame was filtered out and dropped. */ + FLEXCAN_RX_SEARCH_DROPPED, +}; + +/* + * These constants are returned by flexcan_mb_rx_check_mb(). + * See flexcan_mb_rx_check_mb() kerneldoc for details. + */ +enum FlexcanCheck { + FLEXCAN_CHECK_MB_NIL =3D 0, + FLEXCAN_CHECK_MB_MATCH =3D 3, + FLEXCAN_CHECK_MB_MATCH_NON_FREE =3D 1, + FLEXCAN_CHECK_MB_MATCH_LOCKED =3D 5, +}; + +static const FlexcanRegs flexcan_regs_write_mask =3D { + .mcr =3D 0xF6EB337F, + .ctrl =3D 0xFFFFFFFF, + .timer =3D 0xFFFFFFFF, + .tcr =3D 0xFFFFFFFF, + .rxmgmask =3D 0xFFFFFFFF, + .rx14mask =3D 0xFFFFFFFF, + .rx15mask =3D 0xFFFFFFFF, + .ecr =3D 0xFFFFFFFF, + .esr =3D 0xFFFFFFFF, + .imask2 =3D 0xFFFFFFFF, + .imask1 =3D 0xFFFFFFFF, + .iflag2 =3D 0, + .iflag1 =3D 0, + .ctrl2 =3D 0xFFFFFFFF, + .esr2 =3D 0, + .imeur =3D 0, + .lrfr =3D 0, + .crcr =3D 0, + .rxfgmask =3D 0xFFFFFFFF, + .rxfir =3D 0, + .cbt =3D 0, + ._reserved2 =3D 0, + .dbg1 =3D 0, + .dbg2 =3D 0, + .mbs =3D { [0 ... 63] =3D { + .can_ctrl =3D 0xFFFFFFFF & ~FLEXCAN_MB_CNT_NOT_SRV, + .can_id =3D 0xFFFFFFFF, + .data =3D { 0xFFFFFFFF, 0xFFFFFFFF }, + } }, + ._reserved4 =3D {0}, + .rximr =3D { [0 ... 63] =3D 0xFFFFFFFF }, + ._reserved5 =3D {0}, + .gfwr_mx6 =3D 0xFFFFFFFF, + ._reserved6 =3D {0}, + ._reserved8 =3D {0}, + .rx_smb0_raw =3D {0, 0, 0, 0}, + .rx_smb1 =3D {0, 0, 0, 0}, +}; +static const FlexcanRegs flexcan_regs_reset_mask =3D { + .mcr =3D 0x80000000, + .ctrl =3D 0xFFFFFFFF, + .timer =3D 0, + .tcr =3D 0, + .rxmgmask =3D 0xFFFFFFFF, + .rx14mask =3D 0xFFFFFFFF, + .rx15mask =3D 0xFFFFFFFF, + .ecr =3D 0, + .esr =3D 0, + .imask2 =3D 0, + .imask1 =3D 0, + .iflag2 =3D 0, + .iflag1 =3D 0, + .ctrl2 =3D 0xFFFFFFFF, + .esr2 =3D 0, + .imeur =3D 0, + .lrfr =3D 0, + .crcr =3D 0, + .rxfgmask =3D 0xFFFFFFFF, + .rxfir =3D 0xFFFFFFFF, + .cbt =3D 0, + ._reserved2 =3D 0, + .dbg1 =3D 0, + .dbg2 =3D 0, + .mb =3D {0xFFFFFFFF}, + ._reserved4 =3D {0}, + .rximr =3D {0xFFFFFFFF}, + ._reserved5 =3D {0}, + .gfwr_mx6 =3D 0, + ._reserved6 =3D {0}, + ._reserved8 =3D {0}, + .rx_smb0_raw =3D {0, 0, 0, 0}, + .rx_smb1 =3D {0, 0, 0, 0}, +}; + +/* length of buffer used to format register names in trace output */ +#define FLEXCAN_DBG_BUF_LEN 16 + +/** + * flexcan_dbg_mb_code_strs - Readable names for CODE field codes + * + * Readable names for possible values of CODE field in message buffer + * control word. + */ +static const char *flexcan_dbg_mb_code_strs[16] =3D { + "INACTIVE_RX", + "FULL", + "EMPTY", + "OVERRUN", + "INACTIVE_TX", + "RANSWER", + "DATA", + "TANSWER" +}; + +/** + * flexcan_dbg_mb_code() - Get the string representation of a mailbox code + * @mb_ctrl: The mailbox control register value + * @buf: The buffer to store the string representation + * + * Return: Either constant string or string formatted into @buf + */ +static const char *flexcan_dbg_mb_code(uint32_t mb_ctrl, char *buf) +{ + uint32_t code =3D mb_ctrl & FLEXCAN_MB_CODE_MASK; + uint32_t code_idx =3D code >> 24; + if (code =3D=3D FLEXCAN_MB_CODE_TX_ABORT) { + return "ABORT"; + } else { + const char *code_str =3D flexcan_dbg_mb_code_strs[code_idx >> 1]; + if (code_idx & 1) { + g_snprintf(buf, FLEXCAN_DBG_BUF_LEN, "%s+BUSY", code_str); + return buf; + } + + return code_str; + } +} + +static const char *flexcan_dbg_reg_name_fixed(hwaddr addr) +{ + switch (addr) { + case offsetof(FlexcanRegs, mcr): + return "MCR"; + case offsetof(FlexcanRegs, ctrl): + return "CTRL"; + case offsetof(FlexcanRegs, timer): + return "TIMER"; + case offsetof(FlexcanRegs, esr): + return "ESR"; + case offsetof(FlexcanRegs, rxmgmask): + return "RXMGMASK"; + case offsetof(FlexcanRegs, rx14mask): + return "RX14MASK"; + case offsetof(FlexcanRegs, rx15mask): + return "RX15MASK"; + case offsetof(FlexcanRegs, rxfgmask): + return "RXFGMASK"; + case offsetof(FlexcanRegs, ecr): + return "ECR"; + case offsetof(FlexcanRegs, ctrl2): + return "CTRL2"; + case offsetof(FlexcanRegs, imask2): + return "IMASK2"; + case offsetof(FlexcanRegs, imask1): + return "IMASK1"; + case offsetof(FlexcanRegs, iflag2): + return "IFLAG2"; + case offsetof(FlexcanRegs, iflag1): + return "IFLAG1"; + } + return NULL; +} + +static inline void flexcan_trace_mem_op(FlexcanState *s, hwaddr addr, + uint32_t value, int size, bool is_= wr) +{ + if (trace_event_get_state_backends(TRACE_FLEXCAN_MEM_OP)) { + const char *reg_name =3D "unknown"; + char reg_name_buf[FLEXCAN_DBG_BUF_LEN] =3D { 0 }; + const char *reg_name_fixed =3D flexcan_dbg_reg_name_fixed(addr); + const char *op_string =3D is_wr ? "write" : "read"; + + if (reg_name_fixed) { + reg_name =3D reg_name_fixed; + } else if (addr >=3D 0x80 && addr < 0x480) { + int mbidx =3D (addr - 0x80) / 16; + g_snprintf(reg_name_buf, sizeof(reg_name_buf), "MB%i", mbidx); + reg_name =3D reg_name_buf; + } else if (addr >=3D 0x880 && addr < 0x9e0) { + int id =3D (addr - 0x880) / 4; + g_snprintf(reg_name_buf, sizeof(reg_name_buf), "RXIMR%i", id); + reg_name =3D reg_name_buf; + } + + trace_flexcan_mem_op(DEVICE(s)->canonical_path, op_string, value, = addr, + reg_name, size); + } +} + +static enum FlexcanRx flexcan_mb_rx(FlexcanState *s, + const qemu_can_frame *frame); +static void flexcan_mb_unlock(FlexcanState *s); + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Mailbox Utils =3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D */ + +/** + * flexcan_mailbox_count() - Get number of enabled mailboxes + * @s: FlexCAN device pointer + * + * Count is based on MCR[MAXMB] field. Note that some of those mailboxes + * might be part of queue or queue ID filters or ordinary message buffers. + */ +static inline int flexcan_enabled_mailbox_count(const FlexcanState *s) +{ + return MIN((s->regs.mcr & FLEXCAN_MCR_MAXMB(UINT32_MAX)) + 1, + FLEXCAN_MAILBOX_COUNT); +} + +/** + * flexcan_get_first_message_buffer() - Get pointer to first message buffer + * @s: FlexCAN device pointer + * + * In context of this function, message buffer means a mailbox which is not + * a queue element nor a queue filter. Note this function does not take + * MCR[MAXMB] into account, meaning that the returned mailbox + * might be disabled. + */ +static FlexcanRegsMessageBuffer *flexcan_get_first_message_buffer( + FlexcanState *s) +{ + if (s->regs.mcr & FLEXCAN_MCR_FEN) { + int rffn =3D (s->regs.ctrl2 & FLEXCAN_CTRL2_RFFN(UINT32_MAX)) >> 2= 4; + return s->regs.mbs + 8 + 2 * rffn; + } + + return s->regs.mbs; +} + +/** + * flexcan_get_last_enabled_mailbox() - Get pointer to last enabled mailbo= x. + * @s: FlexCAN device pointer + * + * When used with flexcan_get_first_message_buffer(), all mailboxes *ptr in + * range `first_message_buffer() <=3D ptr <=3D last_enabled_mailbox` are v= alid + * message buffer mailboxes. + * + * Return: Last enabled mailbox in MCR[MAXMB] sense. The mailbox might be + * of any type. + */ +static inline FlexcanRegsMessageBuffer *flexcan_get_last_enabled_mailbox( + FlexcanState *s) +{ + return s->regs.mbs + flexcan_enabled_mailbox_count(s); +} + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Free-running Timer =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D */ +static inline int64_t flexcan_get_time(void) +{ + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); +} + +/** + * flexcan_get_bitrate() - Calculate CAN bitrate (in Hz) + * @s: FlexCAN device pointer + * + * The bitrate is determined by FlexCAN configuration in CTRL1 register, + * and CCM co + */ +static uint32_t flexcan_get_bitrate(FlexcanState *s) +{ + uint32_t conf_presdiv =3D (s->regs.ctrl & FLEXCAN_CTRL_PRESDIV_MASK) >= > 24; + uint32_t conf_pseg1 =3D (s->regs.ctrl & FLEXCAN_CTRL_PSEG1_MASK) >> 19; + uint32_t conf_pseg2 =3D (s->regs.ctrl & FLEXCAN_CTRL_PSEG2_MASK) >> 16; + uint32_t conf_propseg =3D s->regs.ctrl & FLEXCAN_CTRL_PROPSEG_MASK; + + /* N of time quanta for segments */ + uint32_t tseg1 =3D 2 + conf_pseg1 + conf_propseg; + uint32_t tseg2 =3D 1 + conf_pseg2; + uint32_t total_qpb =3D 1 + tseg1 + tseg2; + + uint32_t pe_freq, s_freq, bitrate; + + assert(s->ccm); + + /* s_freq: CAN clock from CCM divided by the prescaler */ + pe_freq =3D imx_ccm_get_clock_frequency(s->ccm, CLK_CAN); + s_freq =3D pe_freq / (1 + conf_presdiv); + bitrate =3D s_freq / total_qpb; + + trace_flexcan_get_bitrate(DEVICE(s)->canonical_path, pe_freq, + 1 + conf_presdiv, s_freq, tseg1, tseg2, tota= l_qpb, + bitrate); + return bitrate; +} + +/** + * int128_mul_6464() - Multiply two 64-bit integers into a 128-bit one + */ +static Int128 int128_muls_6464(int64_t ai, int64_t bi) +{ + uint64_t l, h; + + muls64(&l, &h, ai, bi); + return int128_make128(l, h); +} + +/** + * flexcan_get_timestamp() - Get current value of the 16-bit free-running = timer + * @s: FlexCAN device pointer + * @mk_unique: if true, make the timestamp unique by incrementing it if ne= eded + */ +static uint32_t flexcan_get_timestamp(FlexcanState *s, bool mk_unique) +{ + const Int128 nanoseconds_in_second =3D int128_makes64((int64_t)1e9); + Int128 ncycles, cycles128; + int64_t current_time, elapsed_time_ns; + uint64_t cycles; + uint32_t rv, shift =3D 0; + + if (s->timer_start =3D=3D FLEXCAN_TIMER_STOPPED) { + /* timer is not running, return last value */ + trace_flexcan_get_timestamp(DEVICE(s)->canonical_path, -1, 0, 0, 0, + s->regs.timer); + return s->regs.timer; + } + + current_time =3D flexcan_get_time(); + elapsed_time_ns =3D current_time - s->timer_start; + if (elapsed_time_ns < 0) { + trace_flexcan_timer_overflow(DEVICE(s)->canonical_path, current_ti= me, + s->timer_start, elapsed_time_ns); + return 0xFFFF; + } + + ncycles =3D int128_muls_6464(s->timer_freq, elapsed_time_ns); + cycles128 =3D int128_divs(ncycles, nanoseconds_in_second); + /* 64 bits hold for over 50k years at 10MHz */ + cycles =3D int128_getlo(cycles128); + + if (mk_unique && cycles <=3D s->last_rx_timer_cycles) { + shift =3D 1; + cycles =3D s->last_rx_timer_cycles + shift; + } + + s->last_rx_timer_cycles =3D cycles; + rv =3D (uint32_t)cycles & 0xFFFF; + + trace_flexcan_get_timestamp(DEVICE(s)->canonical_path, + elapsed_time_ns / (uint32_t)1e6, + s->timer_freq, cycles, shift, rv); + return rv; +} + +/** + * flexcan_timer_start() - Start the free-running timer + * @s: FlexCAN device pointer + * + * This should be called when the module leaves freeze mode. + */ +static void flexcan_timer_start(FlexcanState *s) +{ + s->timer_freq =3D flexcan_get_bitrate(s); + s->timer_start =3D flexcan_get_time(); + s->last_rx_timer_cycles =3D 0; + + trace_flexcan_timer_start(DEVICE(s)->canonical_path, s->timer_freq, + s->regs.timer); +} + +/** + * flexcan_timer_stop() - Stop the free-running timer + * @s: FlexCAN device pointer + * + * This should be called when the module enters freeze mode. + * Stores the current timestamp in the TIMER register. + */ +static void flexcan_timer_stop(FlexcanState *s) +{ + s->regs.timer =3D flexcan_get_timestamp(s, false); + s->timer_start =3D FLEXCAN_TIMER_STOPPED; + + trace_flexcan_timer_stop(DEVICE(s)->canonical_path, s->timer_freq, + s->regs.timer); +} + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D IRQ handling =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D */ +/** + * flexcan_irq_update() - Update qemu_irq line based on interrupt registers + * @s: FlexCAN device pointer + */ +static void flexcan_irq_update(FlexcanState *s) +{ + uint32_t mb_irqs[2]; + int irq_pending; + /* these are all interrupt sources from FlexCAN */ + /* mailbox interrupt sources */ + mb_irqs[0] =3D s->regs.iflag1 & s->regs.imask1; + mb_irqs[1] =3D s->regs.iflag2 & s->regs.imask2; + + /** + * these interrupts aren't currently used and they can never be raised + * + * bool irq_wake_up =3D (s->regs.mcr & FLEXCAN_MCR_WAK_MSK) && + * (s->regs.ecr & FLEXCAN_ESR_WAK_INT); + * bool irq_bus_off =3D (s->regs.ctrl & FLEXCAN_CTRL_BOFF_MSK) && + * (s->regs.ecr & FLEXCAN_ESR_BOFF_INT); + * bool irq_error =3D (s->regs.ctrl & FLEXCAN_CTRL_ERR_MSK) && + * (s->regs.ecr & FLEXCAN_ESR_ERR_INT); + * bool irq_tx_warn =3D (s->regs.ctrl & FLEXCAN_CTRL_TWRN_MSK) && + * (s->regs.ecr & FLEXCAN_ESR_TWRN_INT); + * bool irq_rx_warn =3D (s->regs.ctrl & FLEXCAN_CTRL_RWRN_MSK) && + * (s->regs.ecr & FLEXCAN_ESR_RWRN_INT); + */ + + irq_pending =3D (mb_irqs[0] || mb_irqs[1]) ? 1 : 0; + trace_flexcan_irq_update(DEVICE(s)->canonical_path, mb_irqs[0], mb_irq= s[1], + irq_pending); + + qemu_set_irq(s->irq, irq_pending); +} + +/** + * flexcan_irq_iflag_set() - Set IFLAG bit corresponding to MB mbidx + * @s: FlexCAN device pointer + * @mbidx: mailbox index + */ +static void flexcan_irq_iflag_set(FlexcanState *s, int mbidx) +{ + if (mbidx < 32) { + s->regs.iflag1 |=3D BIT(mbidx); + } else { + s->regs.iflag2 |=3D BIT(mbidx - 32); + } +} + +/** + * flexcan_irq_iflag_clear() - Clear IFLAG bit corresponding to MB mbidx + * @s: FlexCAN device pointer + * @mbidx: mailbox index + */ +static void flexcan_irq_iflag_clear(FlexcanState *s, int mbidx) +{ + if (mbidx < 32) { + s->regs.iflag1 &=3D ~BIT(mbidx); + } else { + s->regs.iflag2 &=3D ~BIT(mbidx - 32); + } +} + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D RESET =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ +static void flexcan_reset_local_state(FlexcanState *s) +{ + uint32_t *reset_mask =3D (uint32_t *)&flexcan_regs_reset_mask; + for (int i =3D 0; i < (sizeof(FlexcanRegs) / 4); i++) { + s->regs_raw[i] &=3D reset_mask[i]; + } + + s->regs.mcr |=3D 0x5980000F; + s->locked_mbidx =3D FLEXCAN_NO_MB_LOCKED; + s->smb_target_mbidx =3D FLEXCAN_SMB_EMPTY; + s->timer_start =3D FLEXCAN_TIMER_STOPPED; + + trace_flexcan_reset(DEVICE(s)->canonical_path); +} + +static void flexcan_reset_enter(Object *obj, ResetType type) +{ + FlexcanState *s =3D CAN_FLEXCAN(obj); + + memset(&s->regs, 0, sizeof(s->regs)); + flexcan_reset_local_state(s); +} + +static void flexcan_reset_hold(Object *obj, ResetType type) +{ + FlexcanState *s =3D CAN_FLEXCAN(obj); + + flexcan_irq_update(s); +} + + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Operation mode control =3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D */ +/** + * flexcan_update_esr() - Update ESR based on mode and CAN bus connection = state + * @s: FlexCAN device pointer + */ +static void flexcan_update_esr(FlexcanState *s) +{ + bool is_running =3D (s->regs.mcr & FLEXCAN_MCR_NOT_RDY) =3D=3D 0; + /* potentially, there could be other influences on ESR[SYNCH] */ + + if (is_running && s->canbus) { + s->regs.esr |=3D FLEXCAN_ESR_SYNCH | FLEXCAN_ESR_IDLE; + } else { + s->regs.esr &=3D ~(FLEXCAN_ESR_SYNCH | FLEXCAN_ESR_IDLE); + } +} + +/** + * flexcan_update_esr() - Process MCR write + * @s: FlexCAN device pointer + * @pv: previously set MCR value + * + * This function expects the new MCR value to be already written in s->reg= s.mcr. + */ +static void flexcan_set_mcr(FlexcanState *s, const uint32_t pv) +{ + uint32_t cv =3D s->regs.mcr; + + /* -- module disable mode -- */ + if (!(pv & FLEXCAN_MCR_MDIS) && (cv & FLEXCAN_MCR_MDIS)) { + /* transition to Module Disable mode */ + cv |=3D FLEXCAN_MCR_LPM_ACK; + } else if ((pv & FLEXCAN_MCR_MDIS) && !(cv & FLEXCAN_MCR_MDIS)) { + /* transition from Module Disable mode */ + cv &=3D ~FLEXCAN_MCR_LPM_ACK; + } + + /* -- soft reset -- */ + if (!(cv & FLEXCAN_MCR_LPM_ACK) && (cv & FLEXCAN_MCR_SOFTRST)) { + if (s->regs.mcr & FLEXCAN_MCR_LPM_ACK) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid soft reset request in low-power mod= e", + DEVICE(s)->canonical_path); + } + + flexcan_reset_local_state(s); + cv =3D s->regs.mcr; + } + + /* -- freeze mode -- */ + if (!(cv & FLEXCAN_MCR_LPM_ACK) && + (cv & FLEXCAN_MCR_FRZ) && + (cv & FLEXCAN_MCR_HALT)) { + cv |=3D FLEXCAN_MCR_FRZ_ACK; + } else { + cv &=3D ~FLEXCAN_MCR_FRZ_ACK; + } + + /* -- fifo mode -- */ + if ( + ((pv & FLEXCAN_MCR_FEN) && !(cv & FLEXCAN_MCR_FEN)) || + (!(pv & FLEXCAN_MCR_FEN) && (cv & FLEXCAN_MCR_FEN)) + ) { + /* clear iflags used by fifo */ + s->regs.iflag1 &=3D ~( + FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | + FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | + FLEXCAN_IFLAG_RX_FIFO_WARN + ); + } + if (!(pv & FLEXCAN_MCR_FEN) && (cv & FLEXCAN_MCR_FEN)) { + /* zero out fifo region, we rely on zeroed can_ctrl for empty slot= s */ + memset(s->regs.mbs, 0, + FLEXCAN_FIFO_DEPTH * sizeof(FlexcanRegsMessageBuffer)); + } + + /* + * assert NOT_RDY bit if in disable, + * stop (not implemented) or freeze mode + */ + if ((cv & FLEXCAN_MCR_LPM_ACK) || (cv & FLEXCAN_MCR_FRZ_ACK)) { + cv |=3D FLEXCAN_MCR_NOT_RDY; + } else { + cv &=3D ~FLEXCAN_MCR_NOT_RDY; + } + + if ((pv & FLEXCAN_MCR_NOT_RDY) && !(cv & FLEXCAN_MCR_NOT_RDY)) { + /* module went up, start the timer */ + flexcan_timer_start(s); + } else if (!(pv & FLEXCAN_MCR_NOT_RDY) && (cv & FLEXCAN_MCR_NOT_RDY)) { + /* module went down, store the current timer value */ + flexcan_timer_stop(s); + } + + s->regs.mcr =3D cv; + flexcan_update_esr(s); + trace_flexcan_set_mcr( + DEVICE(s)->canonical_path, + cv & FLEXCAN_MCR_LPM_ACK ? "DISABLED" : "ENABLED", + (cv & FLEXCAN_MCR_FRZ_ACK || cv & FLEXCAN_MCR_LPM_ACK) ? + "FROZEN" : "RUNNING", + cv & FLEXCAN_MCR_FEN ? "FIFO" : "MAILBOX", + cv & FLEXCAN_MCR_NOT_RDY ? "NOT_RDY" : "RDY", + s->regs.esr & FLEXCAN_ESR_SYNCH ? "SYNC" : "NOSYNC" + ); +} + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D TX =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ +static void flexcan_transmit(FlexcanState *s, int mbidx) +{ + FlexcanRegsMessageBuffer *mb =3D &s->regs.mbs[mbidx]; + qemu_can_frame frame =3D { + .flags =3D 0, + }; + uint32_t *frame_data =3D (uint32_t *)&frame.data; + uint32_t timestamp =3D flexcan_get_timestamp(s, true); + + if ((s->regs.ctrl & FLEXCAN_CTRL_LOM) || + (s->regs.mcr & FLEXCAN_MCR_NOT_RDY)) { + /* no transmiting in listen-only, freeze or low-power mode */ + return; + } + + if (mb->can_ctrl & FLEXCAN_MB_CNT_IDE) { + /* 29b ID stored in bits [0, 29) */ + uint32_t id =3D mb->can_id & 0x1FFFFFFF; + frame.can_id =3D id | QEMU_CAN_EFF_FLAG; + } else { + /* 11b ID stored in bits [18, 29) */ + uint32_t id =3D (mb->can_id & (0x7FF << 18)) >> 18; + frame.can_id =3D id; + } + + frame.can_dlc =3D (mb->can_ctrl & (0xF << 16)) >> 16; + + for (int i =3D 0; i < 2; i++) { + stl_be_p(&frame_data[i], mb->data[i]); + } + + if (!(s->regs.mcr & FLEXCAN_MCR_SRX_DIS)) { + /* self-reception */ + flexcan_mb_rx(s, &frame); + } + if (!(s->regs.ctrl & FLEXCAN_CTRL_LPB)) { + /* send to bus if not in loopback mode */ + if (s->canbus) { + can_bus_client_send(&s->bus_client, &frame, 1); + } else { + /* todo: raise error (no ack) */ + } + } + + mb->can_ctrl &=3D ~(FLEXCAN_MB_CODE_MASK | FLEXCAN_MB_CNT_TIMESTAMP_MA= SK); + mb->can_ctrl |=3D FLEXCAN_MB_CODE_TX_INACTIVE | + FLEXCAN_MB_CNT_TIMESTAMP(timestamp); + + /* todo: compute the CRC */ + s->regs.crcr =3D FLEXCAN_CRCR_TXCRC(0) | FLEXCAN_CRCR_MBCRC(mbidx); + + flexcan_irq_iflag_set(s, mbidx); +} + +static void flexcan_mb_write(FlexcanState *s, int mbid) +{ + FlexcanRegsMessageBuffer *mb =3D &s->regs.mbs[mbid]; + + bool is_mailbox =3D (mb <=3D flexcan_get_last_enabled_mailbox(s)) && + (mb >=3D flexcan_get_first_message_buffer(s)); + + if (trace_event_get_state_backends(TRACE_FLEXCAN_MB_WRITE)) { + char code_str_buf[FLEXCAN_DBG_BUF_LEN] =3D { 0 }; + const char *code_str =3D flexcan_dbg_mb_code(mb->can_ctrl, code_st= r_buf); + trace_flexcan_mb_write(DEVICE(s)->canonical_path, mbid, code_str, + is_mailbox, mb->can_ctrl, mb->can_id); + } + + if (!is_mailbox) { + /** + * Disabled mailbox or mailbox in region of queue filters + * was updated. Either way there is nothing to do. + */ + return; + } + + /* any write to message buffer clears the not_serviced flag */ + mb->can_ctrl &=3D ~FLEXCAN_MB_CNT_NOT_SRV; + + /** + * todo: search for active tx mbs on transition from freeze/disable mo= de + */ + switch (mb->can_ctrl & FLEXCAN_MB_CODE_MASK) { + case FLEXCAN_MB_CODE_TX_INACTIVE: + QEMU_FALLTHROUGH; + case FLEXCAN_MB_CODE_RX_INACTIVE: + QEMU_FALLTHROUGH; + case FLEXCAN_MB_CODE_RX_EMPTY: + QEMU_FALLTHROUGH; + case FLEXCAN_MB_CODE_RX_FULL: + QEMU_FALLTHROUGH; + case FLEXCAN_MB_CODE_RX_RANSWER: + break; + + case FLEXCAN_MB_CODE_TX_DATA: + flexcan_transmit(s, mbid); + break; + case FLEXCAN_MB_CODE_TX_ABORT: + /* + * as transmission is instant, it can never be aborted + * we need to set CODE in C/S back to the previous code + */ + mb->can_ctrl &=3D ~FLEXCAN_MB_CODE(1); + break; + case FLEXCAN_MB_CODE_TX_TANSWER: + break; + default: + /* prevent setting the busy bit */ + mb->can_ctrl &=3D ~FLEXCAN_MB_CODE_RX_BUSY_BIT; + break; + } + +} + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D RX =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ +static void flexcan_mb_move_in(FlexcanState *s, const qemu_can_frame *fram= e, + FlexcanRegsMessageBuffer *target_mb) +{ + uint32_t frame_len =3D frame->can_dlc; + uint32_t *frame_data =3D (uint32_t *)&frame->data; + int timestamp =3D flexcan_get_timestamp(s, true); + uint32_t new_code =3D 0; + + memset(target_mb, 0, sizeof(FlexcanRegsMessageBuffer)); + + if (frame_len > 8) { + frame_len =3D 8; + } + for (int i =3D 0; i < 2; i++) { + target_mb->data[i] =3D ldl_be_p(&frame_data[i]); + } + + switch (target_mb->can_ctrl & FLEXCAN_MB_CODE_MASK) { + case FLEXCAN_MB_CODE_RX_FULL: + case FLEXCAN_MB_CODE_RX_OVERRUN: + if (target_mb->can_ctrl & FLEXCAN_MB_CNT_NOT_SRV) { + new_code =3D FLEXCAN_MB_CODE_RX_OVERRUN; + } else { + new_code =3D FLEXCAN_MB_CODE_RX_FULL; + } + break; + case FLEXCAN_MB_CODE_RX_RANSWER: + assert(s->regs.ctrl2 & FLEXCAN_CTRL2_RRS); + new_code =3D FLEXCAN_MB_CODE_TX_TANSWER; + break; + default: + new_code =3D FLEXCAN_MB_CODE_RX_FULL; + } + + target_mb->can_ctrl =3D new_code + | FLEXCAN_MB_CNT_TIMESTAMP(timestamp) + | FLEXCAN_MB_CNT_LENGTH(frame_len) + | FLEXCAN_MB_CNT_NOT_SRV + | FLEXCAN_MB_CNT_SRR; /* always set for received frames */ + if (frame->can_id & QEMU_CAN_RTR_FLAG) { + target_mb->can_ctrl |=3D FLEXCAN_MB_CNT_RTR; + } + + if (frame->can_id & QEMU_CAN_EFF_FLAG) { + target_mb->can_ctrl |=3D FLEXCAN_MB_CNT_IDE; + target_mb->can_id |=3D frame->can_id & QEMU_CAN_EFF_MASK; + } else { + target_mb->can_id |=3D (frame->can_id & QEMU_CAN_SFF_MASK) << 18; + } +} +static void flexcan_mb_lock(FlexcanState *s, int mbidx) +{ + FlexcanRegsMessageBuffer *mb =3D &s->regs.mbs[mbidx]; + if ((mb > flexcan_get_last_enabled_mailbox(s)) || + (mb < flexcan_get_first_message_buffer(s))) { + return; + } + switch (mb->can_ctrl & FLEXCAN_MB_CODE_MASK) { + case FLEXCAN_MB_CODE_RX_FULL: + QEMU_FALLTHROUGH; + case FLEXCAN_MB_CODE_RX_OVERRUN: + QEMU_FALLTHROUGH; + case FLEXCAN_MB_CODE_RX_RANSWER: + /* continue */ + trace_flexcan_mb_lock(DEVICE(s)->canonical_path, mbidx, 1); + break; + default: + trace_flexcan_mb_lock(DEVICE(s)->canonical_path, mbidx, 0); + return; + } + + s->locked_mbidx =3D mbidx; +} + +static void flexcan_mb_unlock(FlexcanState *s) +{ + int locked_mbidx =3D s->locked_mbidx; + bool has_pending_frame =3D locked_mbidx =3D=3D s->smb_target_mbidx; + + if (s->locked_mbidx =3D=3D FLEXCAN_NO_MB_LOCKED) { + return; + } + + assert(locked_mbidx >=3D 0 && locked_mbidx < FLEXCAN_MAILBOX_COUNT); + FlexcanRegsMessageBuffer *locked_mb =3D &s->regs.mbs[locked_mbidx]; + s->locked_mbidx =3D FLEXCAN_NO_MB_LOCKED; + + if (locked_mb >=3D flexcan_get_first_message_buffer(s) && + locked_mb <=3D flexcan_get_last_enabled_mailbox(s) + ) { + /* mark the message buffer as serviced */ + locked_mb->can_ctrl &=3D ~FLEXCAN_MB_CNT_NOT_SRV; + } + + /* try move in from SMB */ + trace_flexcan_mb_unlock(DEVICE(s)->canonical_path, locked_mbidx, + has_pending_frame ? " PENDING FRAME IN SMB" : = ""); + + /* todo: in low-power modes, this should be postponed until exit */ + if (has_pending_frame) { + FlexcanRegsMessageBuffer *target_mb =3D &s->regs.mbs[locked_mbidx]; + memcpy(target_mb, &s->regs.rx_smb0, sizeof(FlexcanRegsMessageBuffe= r)); + + memset(&s->regs.rx_smb0, 0, sizeof(FlexcanRegsMessageBuffer)); + s->locked_mbidx =3D FLEXCAN_SMB_EMPTY; + + flexcan_irq_iflag_set(s, locked_mbidx); + } +} + +static bool flexcan_can_receive(CanBusClientState *client) +{ + FlexcanState *s =3D container_of(client, FlexcanState, bus_client); + return !(s->regs.mcr & FLEXCAN_MCR_NOT_RDY); +} + +/* --------- RX FIFO ---------- */ + +/** + * flexcan_fifo_pop() - Pop message from FIFO and update IRQs + * @s: FlexCAN device pointer + * + * Does not require the queue to be non-empty. + */ +static void flexcan_fifo_pop(FlexcanState *s) +{ + if (s->regs.fifo.mb_back.can_ctrl !=3D 0) { + /* move queue elements forward */ + memmove(&s->regs.fifo.mb_back, &s->regs.fifo.mbs_queue[0], + sizeof(s->regs.fifo.mbs_queue)); + + /* clear the first-in slot */ + memset(&s->regs.mbs[FLEXCAN_FIFO_DEPTH - 1], 0, + sizeof(FlexcanRegsMessageBuffer)); + + trace_flexcan_fifo_pop(DEVICE(s)->canonical_path, 1, + s->regs.fifo.mb_back.can_ctrl !=3D 0); + } else { + trace_flexcan_fifo_pop(DEVICE(s)->canonical_path, 0, 0); + } + + if (s->regs.fifo.mb_back.can_ctrl !=3D 0) { + flexcan_irq_iflag_set(s, I_FIFO_AVAILABLE); + } else { + flexcan_irq_iflag_clear(s, I_FIFO_AVAILABLE); + } +} + +/** + * flexcan_fifo_find_free_slot() - Find the first free slot in the FIFO + * @s: FlexCAN device pointer + * + * Return: Pointer to the first free slot in the FIFO, + * or NULL if the queue is full. + */ +static FlexcanRegsMessageBuffer *flexcan_fifo_find_free_slot(FlexcanState = *s) +{ + for (int i =3D 0; i < FLEXCAN_FIFO_DEPTH; i++) { + FlexcanRegsMessageBuffer *mb =3D &s->regs.mbs[i]; + if (mb->can_ctrl =3D=3D 0) { + return mb; + } + } + return NULL; +} + +/** + * flexcan_fifo_push() - Update FIFO IRQs after frame move-in + * @s: FlexCAN device pointer + * @slot: Target FIFO slot + * + * The usage is as follows: + * 1. Get free slot pointer using flexcan_fifo_find_free_slot() + * 2. Move the frame in if not NULL + * 3. Call flexcan_fifo_push() regardless of the NULL pointer + */ +static void flexcan_fifo_push(FlexcanState *s, FlexcanRegsMessageBuffer *s= lot) +{ + if (slot) { + int n_occupied =3D slot - s->regs.mbs; + if (n_occupied =3D=3D 4) { /* 4 means the 5th slot was filled in */ + /* + * fifo occupancy increased from 4 to 5, + * raising FIFO_WARN interrupt + */ + flexcan_irq_iflag_set(s, I_FIFO_WARN); + } + flexcan_irq_iflag_set(s, I_FIFO_AVAILABLE); + + trace_flexcan_fifo_push(DEVICE(s)->canonical_path, n_occupied); + } else { + flexcan_irq_iflag_set(s, I_FIFO_OVERFLOW); + + trace_flexcan_fifo_push(DEVICE(s)->canonical_path, -1); + } +} + +static enum FlexcanRx flexcan_fifo_rx(FlexcanState *s, + const qemu_can_frame *buf) +{ + /* todo: filtering. return FLEXCAN_FIFO_RX_RETRY if filtered out */ + if ((s->regs.mcr & FLEXCAN_MCR_IDAM_MASK) =3D=3D FLEXCAN_MCR_IDAM_D) { + /* all frames rejected */ + return FLEXCAN_RX_SEARCH_RETRY; + } else { + /* push message to queue if not full */ + FlexcanRegsMessageBuffer *slot =3D flexcan_fifo_find_free_slot(s); + if (slot) { + flexcan_mb_move_in(s, buf, slot); + } + flexcan_fifo_push(s, slot); + + return slot ? FLEXCAN_RX_SEARCH_ACCEPT : FLEXCAN_RX_SEARCH_DROPPED; + } +} + +/* --------- RX message buffer ---------- */ + +/** + * flexcan_mb_rx_check_mb() - Check if a mb matches a received frame + * @s: FlexCAN device pointer + * @buf: Frame to be received from CAN subsystem + * @mbid: Target mailbox index. The mailbox must be a valid message buffer. + * + * Return: FLEXCAN_CHECK_MB_NIL if the message buffer does not match. + * FLEXCAN_CHECK_MB_MATCH if the message buffer matches the receiv= ed + * frame and is free-to-receive, + * FLEXCAN_CHECK_MB_MATCH_LOCKED if the message buffer matches, + * but is locked, + * FLEXCAN_CHECK_MB_MATCH_NON_FREE if the message buffer matches, + * but is not free-to-receive + * for some other reason. + */ +static enum FlexcanCheck flexcan_mb_rx_check_mb(FlexcanState *s, + const qemu_can_frame *buf, + int mbid) +{ + FlexcanRegsMessageBuffer *mb =3D &s->regs.mbs[mbid]; + const bool is_rtr =3D !!(buf->can_id & QEMU_CAN_RTR_FLAG); + const bool is_serviced =3D !(mb->can_ctrl & FLEXCAN_MB_CNT_NOT_SRV); + const bool is_locked =3D s->locked_mbidx =3D=3D mbid; + + bool is_free_to_receive =3D false; + bool is_matched =3D false; + + switch (mb->can_ctrl & FLEXCAN_MB_CODE_MASK) { + case FLEXCAN_MB_CODE_RX_RANSWER: + if (is_rtr && !(s->regs.ctrl2 & FLEXCAN_CTRL2_RRS)) { + /* todo: do the actual matching/filtering and RTR answer */ + is_matched =3D true; + } + break; + case FLEXCAN_MB_CODE_RX_FULL: + QEMU_FALLTHROUGH; + case FLEXCAN_MB_CODE_RX_OVERRUN: + is_free_to_receive =3D is_serviced; + /* todo: do the actual matching/filtering */ + is_matched =3D true; + break; + case FLEXCAN_MB_CODE_RX_EMPTY: + is_free_to_receive =3D true; + /* todo: do the actual matching/filtering */ + is_matched =3D true; + break; + default: + break; + } + + if (trace_event_get_state_backends(TRACE_FLEXCAN_MB_RX_CHECK_MB)) { + char code_str_buf[FLEXCAN_DBG_BUF_LEN] =3D { 0 }; + const char *code_str =3D flexcan_dbg_mb_code(mb->can_ctrl, code_st= r_buf); + trace_flexcan_mb_rx_check_mb(DEVICE(s)->canonical_path, mbid, code= _str, + is_matched, is_free_to_receive, + is_serviced, is_locked); + } + + if (!is_matched) { + return FLEXCAN_CHECK_MB_NIL; + } + + if (is_locked) { + return FLEXCAN_CHECK_MB_MATCH_LOCKED; + } + + if (is_free_to_receive) { + return FLEXCAN_CHECK_MB_MATCH; + } + + return FLEXCAN_CHECK_MB_MATCH_NON_FREE; +} + +static enum FlexcanRx flexcan_mb_rx(FlexcanState *s, const qemu_can_frame = *buf) +{ + int last_not_free_to_receive_mbid =3D -1; + bool last_not_free_to_receive_locked =3D false; + + FlexcanRegsMessageBuffer *first_mb =3D flexcan_get_first_message_buffe= r(s); + FlexcanRegsMessageBuffer *last_mb =3D flexcan_get_last_enabled_mailbox= (s); + + for (FlexcanRegsMessageBuffer *mb =3D first_mb; + mb <=3D last_mb; mb++) { + int mbid =3D mb - s->regs.mbs; + enum FlexcanCheck r =3D flexcan_mb_rx_check_mb(s, buf, mbid); + if (r =3D=3D FLEXCAN_CHECK_MB_MATCH) { + flexcan_mb_move_in(s, buf, mb); + flexcan_irq_iflag_set(s, mbid); + return FLEXCAN_RX_SEARCH_ACCEPT; + } + + if (r =3D=3D FLEXCAN_CHECK_MB_MATCH_NON_FREE) { + last_not_free_to_receive_mbid =3D mbid; + last_not_free_to_receive_locked =3D false; + } else if (r =3D=3D FLEXCAN_CHECK_MB_MATCH_LOCKED) { + /* + * message buffer is locked, + * we can move in the message after it's unlocked + */ + last_not_free_to_receive_mbid =3D mbid; + last_not_free_to_receive_locked =3D true; + } + } + + if (last_not_free_to_receive_mbid >=3D -1) { + if (last_not_free_to_receive_locked) { + /* + * copy to temporary mailbox (SMB) + * it will be moved in when the mailbox is unlocked + */ + s->regs.rx_smb0.can_ctrl =3D + s->regs.mbs[last_not_free_to_receive_mbid].can_id; + flexcan_mb_move_in(s, buf, &s->regs.rx_smb0); + s->smb_target_mbidx =3D last_not_free_to_receive_mbid; + return FLEXCAN_RX_SEARCH_ACCEPT; + } + + if (s->regs.mcr & FLEXCAN_MCR_IRMQ) { + flexcan_mb_move_in(s, buf, + &s->regs.mbs[last_not_free_to_receive_mbid]= ); + flexcan_irq_iflag_set(s, last_not_free_to_receive_mbid); + return FLEXCAN_RX_SEARCH_ACCEPT; + } + } + + return FLEXCAN_RX_SEARCH_RETRY; +} + +static ssize_t flexcan_receive(CanBusClientState *client, + const qemu_can_frame *frames, size_t frames= _cnt) +{ + FlexcanState *s =3D container_of(client, FlexcanState, bus_client); + trace_flexcan_receive(DEVICE(s)->canonical_path, frames_cnt); + + if (frames_cnt =3D=3D 0) { + return 0; + } + + /* clear the SMB, as it would be overriden in hardware */ + memset(&s->regs.rx_smb0, 0, sizeof(FlexcanRegsMessageBuffer)); + s->smb_target_mbidx =3D FLEXCAN_SMB_EMPTY; + + for (size_t i =3D 0; i < frames_cnt; i++) { + int r; + const qemu_can_frame *frame =3D &frames[i]; + if (frame->can_id & QEMU_CAN_ERR_FLAG) { + /* todo: error frame handling */ + continue; + } + if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) { + /* CAN FD supported only in later FlexCAN version */ + continue; + } + + /* todo: this order logic is not complete and needs further work */ + if (s->regs.mcr & FLEXCAN_MCR_FEN && + s->regs.ctrl2 & FLEXCAN_CTRL2_MRP) { + r =3D flexcan_mb_rx(s, frame); + if (r =3D=3D FLEXCAN_RX_SEARCH_RETRY) { + flexcan_fifo_rx(s, frame); + } + } else if (s->regs.mcr & FLEXCAN_MCR_FEN) { + r =3D flexcan_fifo_rx(s, frame); + if (r =3D=3D FLEXCAN_RX_SEARCH_RETRY) { + flexcan_mb_rx(s, frame); + } + } else { + flexcan_mb_rx(s, frame); + } + } + + flexcan_irq_update(s); + return 1; +} + +/* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D I/O handling =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D */ +static void flexcan_mem_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + FlexcanState *s =3D opaque; + uint32_t write_mask =3D ((const uint32_t *) + &flexcan_regs_write_mask)[addr / 4]; + uint32_t old_value =3D s->regs_raw[addr / 4]; + + /* + * 0 for bits that can "only be written in Freeze mode as it is blocked + * by hardware in other modes" + */ + const uint32_t freeze_mask_mcr =3D 0xDF54CC80; + const uint32_t freeze_mask_ctrl1 =3D 0x0000E740; + + flexcan_trace_mem_op(s, addr, val, size, true); + switch (addr) { + case offsetof(FlexcanRegs, mcr): + if (!(s->regs.mcr & FLEXCAN_MCR_FRZ_ACK)) { + write_mask &=3D freeze_mask_mcr; + } + s->regs.mcr =3D (val & write_mask) | (old_value & ~write_mask); + flexcan_set_mcr(s, old_value); + break; + case offsetof(FlexcanRegs, ctrl): + if (!(s->regs.mcr & FLEXCAN_MCR_FRZ_ACK)) { + write_mask &=3D freeze_mask_ctrl1; + } + s->regs.ctrl =3D (val & write_mask) | (old_value & ~write_mask); + break; + case offsetof(FlexcanRegs, iflag1): + s->regs.iflag1 &=3D ~val; + if ((s->regs.mcr & FLEXCAN_MCR_FEN) && + (val & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE)) { + flexcan_fifo_pop(s); + } + break; + case offsetof(FlexcanRegs, iflag2): + s->regs.iflag2 &=3D ~val; + break; + case offsetof(FlexcanRegs, ctrl2): + QEMU_FALLTHROUGH; + case offsetof(FlexcanRegs, ecr): + QEMU_FALLTHROUGH; + case offsetof(FlexcanRegs, rxmgmask): + QEMU_FALLTHROUGH; + case offsetof(FlexcanRegs, rx14mask): + QEMU_FALLTHROUGH; + case offsetof(FlexcanRegs, rx15mask): + QEMU_FALLTHROUGH; + case offsetof(FlexcanRegs, rxfgmask): + QEMU_FALLTHROUGH; + case offsetof(FlexcanRegs, rximr[0]) ... offsetof(FlexcanRegs, rximr[6= 3]): + /* these registers can only be written in freeze mode */ + if (!(s->regs.mcr & FLEXCAN_MCR_FRZ_ACK)) { + break; + } + QEMU_FALLTHROUGH; + default: + s->regs_raw[addr / 4] =3D (val & write_mask) | (old_value & ~write= _mask); + + if (addr >=3D offsetof(FlexcanRegs, mb) && + addr < offsetof(FlexcanRegs, _reserved4)) { + /* access to mailbox */ + int mbid =3D (addr - offsetof(FlexcanRegs, mb)) / + sizeof(FlexcanRegsMessageBuffer); + + if (s->locked_mbidx =3D=3D mbid) { + flexcan_mb_unlock(s); + } + + /* check for invalid writes into FIFO region */ + if (s->regs.mcr & FLEXCAN_MCR_FEN && mbid < FLEXCAN_FIFO_DEPTH= ) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid write to Rx-FIFO structure", + DEVICE(s)->canonical_path); + return; + } + + /* run mailbox processing function on write to control word */ + if ((addr & 0xF) =3D=3D 0) { + flexcan_mb_write(s, mbid); + } + } + break; + } + + flexcan_irq_update(s); +} + +static uint64_t flexcan_mem_read(void *opqaue, hwaddr addr, unsigned size) +{ + FlexcanState *s =3D opqaue; + uint32_t rv =3D s->regs_raw[addr >> 2]; + + if (addr >=3D offsetof(FlexcanRegs, mb) && + addr < offsetof(FlexcanRegs, _reserved4)) { + /* reading from mailbox */ + hwaddr offset =3D addr - offsetof(FlexcanRegs, mb); + int mbid =3D offset / sizeof(FlexcanRegsMessageBuffer); + + if (addr % 16 =3D=3D 0 && s->locked_mbidx !=3D mbid) { + /* reading control word locks the mailbox */ + flexcan_mb_unlock(s); + flexcan_mb_lock(s, mbid); + flexcan_irq_update(s); + rv =3D s->regs.mbs[mbid].can_ctrl & ~FLEXCAN_MB_CNT_NOT_SRV; + } + } else if (addr =3D=3D offsetof(FlexcanRegs, timer)) { + flexcan_mb_unlock(s); + flexcan_irq_update(s); + rv =3D flexcan_get_timestamp(s, false); + } + + flexcan_trace_mem_op(s, addr, rv, size, false); + return rv; +} + +static bool flexcan_mem_accepts(void *opaque, hwaddr addr, + unsigned size, bool is_write, + MemTxAttrs attrs) +{ + FlexcanState *s =3D opaque; + + if ((s->regs.ctrl2 & FLEXCAN_CTRL2_WRMFRZ) && + (s->regs.mcr & FLEXCAN_MCR_FRZ_ACK)) { + /* unrestricted access to FlexCAN memory in freeze mode */ + return true; + } else if (attrs.user && (s->regs.mcr & FLEXCAN_MCR_SUPV)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid user-mode access to restricted register= ", + DEVICE(s)->canonical_path); + return false; + } else if (attrs.user && is_write && addr < 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid user-mode access to MCR", + DEVICE(s)->canonical_path); + return false; + } + + return true; +} + +static const struct MemoryRegionOps flexcan_ops =3D { + .read =3D flexcan_mem_read, + .write =3D flexcan_mem_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + .unaligned =3D true, + .accepts =3D flexcan_mem_accepts + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false + }, +}; + +static CanBusClientInfo flexcan_bus_client_info =3D { + .can_receive =3D flexcan_can_receive, + .receive =3D flexcan_receive, +}; + +static int flexcan_connect_to_bus(FlexcanState *s, CanBusState *bus) +{ + s->bus_client.info =3D &flexcan_bus_client_info; + + if (can_bus_insert_client(bus, &s->bus_client) < 0) { + return -1; + } + return 0; +} + +static void flexcan_init(Object *obj) +{ + FlexcanState *s =3D CAN_FLEXCAN(obj); + + memory_region_init_io( + &s->iomem, obj, &flexcan_ops, s, TYPE_CAN_FLEXCAN, + offsetof(FlexcanRegs, _reserved6) + ); +} + +static void flexcan_realize(DeviceState *dev, Error **errp) +{ + FlexcanState *s =3D CAN_FLEXCAN(dev); + + if (s->canbus) { + if (flexcan_connect_to_bus(s, s->canbus) < 0) { + error_setg(errp, "%s: flexcan_connect_to_bus failed", + dev->canonical_path); + return; + } + } + + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(SYS_BUS_DEVICE(dev)), &s->irq); +} + +static const VMStateDescription vmstate_can =3D { + .name =3D TYPE_CAN_FLEXCAN, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_INT64(timer_start, FlexcanState), + VMSTATE_UINT32_ARRAY(regs_raw, FlexcanState, sizeof(FlexcanRegs) /= 4), + VMSTATE_INT32(locked_mbidx, FlexcanState), + VMSTATE_INT32(smb_target_mbidx, FlexcanState), + VMSTATE_END_OF_LIST(), + }, +}; + +static const Property flexcan_properties[] =3D { + DEFINE_PROP_LINK("canbus", FlexcanState, canbus, TYPE_CAN_BUS, + CanBusState *), +}; + +static void flexcan_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.enter =3D flexcan_reset_enter; + rc->phases.hold =3D flexcan_reset_hold; + dc->realize =3D flexcan_realize; + device_class_set_props(dc, flexcan_properties); + dc->vmsd =3D &vmstate_can; + dc->desc =3D "i.MX FLEXCAN Controller"; +} + +static const TypeInfo flexcan_info =3D { + .name =3D TYPE_CAN_FLEXCAN, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(FlexcanState), + .class_init =3D flexcan_class_init, + .instance_init =3D flexcan_init, +}; + +static void can_register_types(void) +{ + type_register_static(&flexcan_info); +} +type_init(can_register_types) diff --git a/hw/net/can/flexcan_regs.h b/hw/net/can/flexcan_regs.h new file mode 100644 index 0000000000..c18bc4736e --- /dev/null +++ b/hw/net/can/flexcan_regs.h @@ -0,0 +1,197 @@ +/* + * Field bitmasks and register structs definitions for FlexCAN + * + * This implementation is based on the following datasheet: + * i.MX 6Dual/6Quad Applications Processor Reference Manual + * Document Number: IMX6DQRM, Rev. 6, 05/2020 + * + * Copyright (c) 2025 Matyas Bobek + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/bitops.h" + +#ifndef HW_CAN_FLEXCAN_REGS_H +#define HW_CAN_FLEXCAN_REGS_H + +#define FLEXCAN_GENMASK(h, l) (((~(uint32_t)0) >> (31 - (h) + (l))) << (l)) + +/** + * The following macros were originally written for the Linux kernel by: + * Andrey Volkov + * Sascha Hauer + * Marc Kleine-Budde + * David Jander + * and they have agreed to license them under GPL-2.0-or-later. + */ + +/* FLEXCAN module configuration register (CANMCR) bits */ +#define FLEXCAN_MCR_MDIS BIT(31) +#define FLEXCAN_MCR_FRZ BIT(30) +#define FLEXCAN_MCR_FEN BIT(29) +#define FLEXCAN_MCR_HALT BIT(28) +#define FLEXCAN_MCR_NOT_RDY BIT(27) +#define FLEXCAN_MCR_WAK_MSK BIT(26) +#define FLEXCAN_MCR_SOFTRST BIT(25) +#define FLEXCAN_MCR_FRZ_ACK BIT(24) +#define FLEXCAN_MCR_SUPV BIT(23) +#define FLEXCAN_MCR_SLF_WAK BIT(22) +#define FLEXCAN_MCR_WRN_EN BIT(21) +#define FLEXCAN_MCR_LPM_ACK BIT(20) +#define FLEXCAN_MCR_WAK_SRC BIT(19) +#define FLEXCAN_MCR_DOZE BIT(18) +#define FLEXCAN_MCR_SRX_DIS BIT(17) +#define FLEXCAN_MCR_IRMQ BIT(16) +#define FLEXCAN_MCR_LPRIO_EN BIT(13) +#define FLEXCAN_MCR_AEN BIT(12) +#define FLEXCAN_MCR_FDEN BIT(11) +#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f) +#define FLEXCAN_MCR_IDAM_A (0x0 << 8) +#define FLEXCAN_MCR_IDAM_B (0x1 << 8) +#define FLEXCAN_MCR_IDAM_C (0x2 << 8) +#define FLEXCAN_MCR_IDAM_D (0x3 << 8) +#define FLEXCAN_MCR_IDAM_MASK (0x3 << 8) + +/* FLEXCAN control register (CANCTRL) bits */ +#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xFF) << 24) +#define FLEXCAN_CTRL_PRESDIV_MASK FLEXCAN_CTRL_PRESDIV(UINT32_MAX) +#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) +#define FLEXCAN_CTRL_RJW_MASK FLEXCAN_CTRL_RJW(UINT32_MAX) +#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) +#define FLEXCAN_CTRL_PSEG1_MASK FLEXCAN_CTRL_PSEG1(UINT32_MAX) +#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) +#define FLEXCAN_CTRL_PSEG2_MASK FLEXCAN_CTRL_PSEG2(UINT32_MAX) +#define FLEXCAN_CTRL_BOFF_MSK BIT(15) +#define FLEXCAN_CTRL_ERR_MSK BIT(14) +#define FLEXCAN_CTRL_CLK_SRC BIT(13) +#define FLEXCAN_CTRL_LPB BIT(12) +#define FLEXCAN_CTRL_TWRN_MSK BIT(11) +#define FLEXCAN_CTRL_RWRN_MSK BIT(10) +#define FLEXCAN_CTRL_SMP BIT(7) +#define FLEXCAN_CTRL_BOFF_REC BIT(6) +#define FLEXCAN_CTRL_TSYN BIT(5) +#define FLEXCAN_CTRL_LBUF BIT(4) +#define FLEXCAN_CTRL_LOM BIT(3) +#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) +#define FLEXCAN_CTRL_PROPSEG_MASK FLEXCAN_CTRL_PROPSEG(UINT32_MAX) +#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) +#define FLEXCAN_CTRL_ERR_STATE \ + (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ + FLEXCAN_CTRL_BOFF_MSK) +#define FLEXCAN_CTRL_ERR_ALL \ + (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) + +/* FLEXCAN control register 2 (CTRL2) bits */ +#define FLEXCAN_CTRL2_ECRWRE BIT(29) +#define FLEXCAN_CTRL2_WRMFRZ BIT(28) +#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24) +#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19) +#define FLEXCAN_CTRL2_MRP BIT(18) +#define FLEXCAN_CTRL2_RRS BIT(17) +#define FLEXCAN_CTRL2_EACEN BIT(16) +#define FLEXCAN_CTRL2_ISOCANFDEN BIT(12) + +/* FLEXCAN memory error control register (MECR) bits */ +#define FLEXCAN_MECR_ECRWRDIS BIT(31) +#define FLEXCAN_MECR_HANCEI_MSK BIT(19) +#define FLEXCAN_MECR_FANCEI_MSK BIT(18) +#define FLEXCAN_MECR_CEI_MSK BIT(16) +#define FLEXCAN_MECR_HAERRIE BIT(15) +#define FLEXCAN_MECR_FAERRIE BIT(14) +#define FLEXCAN_MECR_EXTERRIE BIT(13) +#define FLEXCAN_MECR_RERRDIS BIT(9) +#define FLEXCAN_MECR_ECCDIS BIT(8) +#define FLEXCAN_MECR_NCEFAFRZ BIT(7) + +/* FLEXCAN error and status register (ESR) bits */ +#define FLEXCAN_ESR_SYNCH BIT(18) +#define FLEXCAN_ESR_TWRN_INT BIT(17) +#define FLEXCAN_ESR_RWRN_INT BIT(16) +#define FLEXCAN_ESR_BIT1_ERR BIT(15) +#define FLEXCAN_ESR_BIT0_ERR BIT(14) +#define FLEXCAN_ESR_ACK_ERR BIT(13) +#define FLEXCAN_ESR_CRC_ERR BIT(12) +#define FLEXCAN_ESR_FRM_ERR BIT(11) +#define FLEXCAN_ESR_STF_ERR BIT(10) +#define FLEXCAN_ESR_TX_WRN BIT(9) +#define FLEXCAN_ESR_RX_WRN BIT(8) +#define FLEXCAN_ESR_IDLE BIT(7) +#define FLEXCAN_ESR_BOFF_INT BIT(2) +#define FLEXCAN_ESR_ERR_INT BIT(1) +#define FLEXCAN_ESR_WAK_INT BIT(0) + +/* FLEXCAN Bit Timing register (CBT) bits */ +#define FLEXCAN_CBT_BTF BIT(31) +#define FLEXCAN_CBT_EPRESDIV_MASK FLEXCAN_GENMASK(30, 21) +#define FLEXCAN_CBT_ERJW_MASK FLEXCAN_GENMASK(20, 16) +#define FLEXCAN_CBT_EPROPSEG_MASK FLEXCAN_GENMASK(15, 10) +#define FLEXCAN_CBT_EPSEG1_MASK FLEXCAN_GENMASK(9, 5) +#define FLEXCAN_CBT_EPSEG2_MASK FLEXCAN_GENMASK(4, 0) + +/* FLEXCAN FD control register (FDCTRL) bits */ +#define FLEXCAN_FDCTRL_FDRATE BIT(31) +#define FLEXCAN_FDCTRL_MBDSR1 FLEXCAN_GENMASK(20, 19) +#define FLEXCAN_FDCTRL_MBDSR0 FLEXCAN_GENMASK(17, 16) +#define FLEXCAN_FDCTRL_MBDSR_8 0x0 +#define FLEXCAN_FDCTRL_MBDSR_12 0x1 +#define FLEXCAN_FDCTRL_MBDSR_32 0x2 +#define FLEXCAN_FDCTRL_MBDSR_64 0x3 +#define FLEXCAN_FDCTRL_TDCEN BIT(15) +#define FLEXCAN_FDCTRL_TDCFAIL BIT(14) +#define FLEXCAN_FDCTRL_TDCOFF FLEXCAN_GENMASK(12, 8) +#define FLEXCAN_FDCTRL_TDCVAL FLEXCAN_GENMASK(5, 0) + +/* FLEXCAN FD Bit Timing register (FDCBT) bits */ +#define FLEXCAN_FDCBT_FPRESDIV_MASK FLEXCAN_GENMASK(29, 20) +#define FLEXCAN_FDCBT_FRJW_MASK FLEXCAN_GENMASK(18, 16) +#define FLEXCAN_FDCBT_FPROPSEG_MASK FLEXCAN_GENMASK(14, 10) +#define FLEXCAN_FDCBT_FPSEG1_MASK FLEXCAN_GENMASK(7, 5) +#define FLEXCAN_FDCBT_FPSEG2_MASK FLEXCAN_GENMASK(2, 0) + +/* FLEXCAN CRC Register (CRCR) bits */ +#define FLEXCAN_CRCR_MBCRC_MASK FLEXCAN_GENMASK(22, 16) +#define FLEXCAN_CRCR_MBCRC(x) (((x) & FLEXCAN_CRCR_MBCRC_MASK) <= < 16) +#define FLEXCAN_CRCR_TXCRC_MASK FLEXCAN_GENMASK(14, 0) +#define FLEXCAN_CRCR_TXCRC(x) ((x) & FLEXCAN_CRCR_TXCRC_MASK) + +/* FLEXCAN interrupt flag register (IFLAG) bits */ +/* Errata ERR005829 step7: Reserve first valid MB */ +#define I_FIFO_OVERFLOW 7 +#define I_FIFO_WARN 6 +#define I_FIFO_AVAILABLE 5 + +#define FLEXCAN_TX_MB_RESERVED_RX_FIFO 8 +#define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX 0 +#define FLEXCAN_RX_MB_RX_MAILBOX_FIRST (FLEXCAN_TX_MB_RESERVED_RX_MAILBOX= + 1) +#define FLEXCAN_IFLAG_MB(x) BIT_ULL(x) +#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(I_FIFO_OVERFLOW) +#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(I_FIFO_WARN) +#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(I_FIFO_AVAILABLE) + +/* FLEXCAN message buffers */ +#define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24) +#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24) +#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24) +#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24) +#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24) +#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24) + +#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24) +#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24) +#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24) +#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24) + +#define FLEXCAN_MB_CODE(x) (((x) & 0xF) << 24) +#define FLEXCAN_MB_CODE_MASK FLEXCAN_MB_CODE(UINT32_MAX) + +#define FLEXCAN_MB_CNT_EDL BIT(31) +#define FLEXCAN_MB_CNT_BRS BIT(30) +#define FLEXCAN_MB_CNT_ESI BIT(29) +#define FLEXCAN_MB_CNT_SRR BIT(22) +#define FLEXCAN_MB_CNT_IDE BIT(21) +#define FLEXCAN_MB_CNT_RTR BIT(20) +#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xF) << 16) +#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xFFFF) +#define FLEXCAN_MB_CNT_TIMESTAMP_MASK FLEXCAN_MB_CNT_TIMESTAMP(UINT32_MA= X) + +#endif diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build index 7382344628..401afde2e4 100644 --- a/hw/net/can/meson.build +++ b/hw/net/can/meson.build @@ -6,3 +6,4 @@ system_ss.add(when: 'CONFIG_CAN_CTUCANFD', if_true: files('= ctucan_core.c')) system_ss.add(when: 'CONFIG_CAN_CTUCANFD_PCI', if_true: files('ctucan_pci.= c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can.= c')) system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-canf= d.c')) +system_ss.add(when: 'CONFIG_CAN_FLEXCAN', if_true: files('flexcan.c')) diff --git a/hw/net/can/trace-events b/hw/net/can/trace-events index de64ac1b31..7500f10d7a 100644 --- a/hw/net/can/trace-events +++ b/hw/net/can/trace-events @@ -1,3 +1,21 @@ +# flexcan.c +flexcan_irq_update(const char *inst, uint32_t mb_irqs1, uint32_t mb_irqs2,= int setting) "%s: irqs1 0x%08x irqs2 0x%08x request %i" +flexcan_set_mcr(const char *inst, const char *enabled, const char *freeze,= const char *fifo, const char *rdy, const char *sync) "%s: %s %s %s %s %s" +flexcan_mb_write(const char *inst, int mbidx, const char *code, int is_mai= lbox, uint32_t ctrl, uint32_t id) "%s: mbidx %i code %s is_mailbox %i ctrl = 0x%08x id 0x%08x" +flexcan_mb_lock(const char *inst, int mbidx, int had_rx_code) "%s: mbidx %= i had_rx_code %i" +flexcan_mb_unlock(const char *inst, int mbidx, const char *pending_frame) = "%s: mbidx %i%s" +flexcan_fifo_pop(const char *inst, int non_empty_before, int non_empty_aft= er) "%s: non_empty before %i non_empty_after %i" +flexcan_fifo_push(const char *inst, int n_occupied) "%s: n_slots_occupied = %i" +flexcan_reset(const char *inst) "%s: resetting" +flexcan_mem_op(const char *inst, const char *op, uint32_t v, int offset, c= onst char *reg_name, int size) "%s: %s 0x%08x at offset %i register %s size= %i" +flexcan_get_timestamp(const char *inst, int64_t time_elapsed_ms, uint32_t = bitrate, uint64_t cycles, uint32_t shift, uint32_t timestamp) "%s: time_ela= psed %" PRIi64 "ms bitrate %ub/s cycles %" PRIu64 " shift %u timestamp 0x%0= 4x" +flexcan_get_bitrate(const char *inst, uint32_t pe_freq, uint32_t prediv, u= int32_t s_freq, uint32_t tseg1, uint32_t tseg2, uint32_t quata_per_bit, uin= t32_t bitrate) "%s: pe_freq %uHz prescaler %u s_freq %uHz tseg1 %uq tseg2 %= uq total %uq/b bitrate %ub/s" +flexcan_timer_start(const char *inst, uint32_t bitrate, uint32_t value) "%= s: bitrate %ub/s value 0x%04x" +flexcan_timer_stop(const char *inst, uint32_t bitrate, uint32_t value) "%s= : bitrate %ub/s value 0x%04x" +flexcan_timer_overflow(const char *inst, int64_t current_time, int64_t tim= er_start, int64_t elapsed_ns) "%s: current_time %" PRIi64 "timer_start %" P= RIi64 "elapsed_ns %" PRIi64 +flexcan_mb_rx_check_mb(const char *inst, int mbidx, const char *code, int = is_matched, int is_ftr, int is_serviced, int is_locked) "%s: checking mb %i= code %s is_matched %i is_free_to_receive %i is_serviced %i is_locked %i" +flexcan_receive(const char *inst, size_t n_frames) "%s: received %zu frame= s" + # xlnx-zynqmp-can.c xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x= IER: 0x%08x IRQ: 0x%08x" xlnx_can_reset(uint32_t val) "Resetting controller with value =3D 0x%08x" diff --git a/include/hw/net/flexcan.h b/include/hw/net/flexcan.h new file mode 100644 index 0000000000..153afc1e03 --- /dev/null +++ b/include/hw/net/flexcan.h @@ -0,0 +1,145 @@ +/* + * QEMU model of the NXP FLEXCAN device. + * + * Copyright (c) 2025 Matyas Bobek + * + * Based on CTU CAN FD emulation implemented by Jan Charvat. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_CAN_FLEXCAN_H +#define HW_CAN_FLEXCAN_H + +#include "net/can_emu.h" +#include "qom/object.h" +#include "hw/misc/imx_ccm.h" + +#define FLEXCAN_FIFO_DEPTH 6 +#define FLEXCAN_MAILBOX_COUNT 64 + +/** + * Definitions of structs FlexcanRegs and FlexcanRegsMessageBuffer were + * originally written for the Linux kernel by: + * Andrey Volkov + * Sascha Hauer + * Marc Kleine-Budde + * David Jander + * and they have agreed to license them under GPL-2.0-or-later. + */ + +/* view of single message buffer registers */ +typedef struct FlexcanRegsMessageBuffer { + uint32_t can_ctrl; + uint32_t can_id; + uint32_t data[2]; +} FlexcanRegsMessageBuffer; + +/* RX FIFO view of message buffer registers */ +typedef struct FlexcanRegsRXFifo { + /* 6 message buffer deep queue, queue back first */ + FlexcanRegsMessageBuffer mb_back; + FlexcanRegsMessageBuffer mbs_queue[FLEXCAN_FIFO_DEPTH - 1]; + + /* number of filter elements active depends on ctrl2 | FLEXCAN_CTRL2_R= FFN */ + uint32_t filter_table_els[128]; +} FlexcanRegsRXFifo; + +/* FlexCAN register in hw layout */ +typedef struct FlexcanRegs { + uint32_t mcr; /* 0x00 */ + uint32_t ctrl; /* 0x04 - not affected by soft reset */ + uint32_t timer; /* 0x08 */ + uint32_t tcr; /* 0x0C */ + uint32_t rxmgmask; /* 0x10 - not affected by soft reset */ + uint32_t rx14mask; /* 0x14 - not affected by soft reset */ + uint32_t rx15mask; /* 0x18 - not affected by soft reset */ + uint32_t ecr; /* 0x1C */ + uint32_t esr; /* 0x20 */ + uint32_t imask2; /* 0x24 */ + uint32_t imask1; /* 0x28 */ + uint32_t iflag2; /* 0x2C */ + uint32_t iflag1; /* 0x30 */ + union { /* 0x34 */ + uint32_t gfwr_mx28; /* MX28, MX53 */ + uint32_t ctrl2; /* MX6, VF610 - not affected by soft rese= t */ + }; + uint32_t esr2; /* 0x38 */ + uint32_t imeur; /* 0x3C, unused */ + uint32_t lrfr; /* 0x40, unused */ + uint32_t crcr; /* 0x44 */ + uint32_t rxfgmask; /* 0x48 */ + uint32_t rxfir; /* 0x4C - not affected by soft reset */ + uint32_t cbt; /* 0x50, unused - not affected by soft re= set */ + uint32_t _reserved2; /* 0x54 */ + uint32_t dbg1; /* 0x58, unused */ + uint32_t dbg2; /* 0x5C, unused */ + uint32_t _reserved3[8]; /* 0x60 */ + union { /* 0x80 - not affected by soft reset */ + uint32_t mb[sizeof(FlexcanRegsMessageBuffer) * FLEXCAN_MAILBOX_COU= NT]; + FlexcanRegsMessageBuffer mbs[FLEXCAN_MAILBOX_COUNT]; + FlexcanRegsRXFifo fifo; + }; + uint32_t _reserved4[256]; /* 0x480 */ + uint32_t rximr[64]; /* 0x880 - not affected by soft reset */ + uint32_t _reserved5[24]; /* 0x980 */ + uint32_t gfwr_mx6; /* 0x9E0 - MX6 */ + + /* the rest is unused except for SMB */ + uint32_t _reserved6[39]; /* 0x9E4 */ + uint32_t _rxfir[6]; /* 0xA80 */ + uint32_t _reserved8[2]; /* 0xA98 */ + uint32_t _rxmgmask; /* 0xAA0 */ + uint32_t _rxfgmask; /* 0xAA4 */ + uint32_t _rx14mask; /* 0xAA8 */ + uint32_t _rx15mask; /* 0xAAC */ + uint32_t tx_smb[4]; /* 0xAB0 */ + union { /* 0xAC0, used for SMB emulation */ + uint32_t rx_smb0_raw[4]; + FlexcanRegsMessageBuffer rx_smb0; + }; + uint32_t rx_smb1[4]; /* 0xAD0 */ + uint32_t mecr; /* 0xAE0 */ + uint32_t erriar; /* 0xAE4 */ + uint32_t erridpr; /* 0xAE8 */ + uint32_t errippr; /* 0xAEC */ + uint32_t rerrar; /* 0xAF0 */ + uint32_t rerrdr; /* 0xAF4 */ + uint32_t rerrsynr; /* 0xAF8 */ + uint32_t errsr; /* 0xAFC */ + uint32_t _reserved7[64]; /* 0xB00 */ + uint32_t fdctrl; /* 0xC00 - not affected by soft reset */ + uint32_t fdcbt; /* 0xC04 - not affected by soft reset */ + uint32_t fdcrc; /* 0xC08 */ + uint32_t _reserved9[199]; /* 0xC0C */ + uint32_t tx_smb_fd[18]; /* 0xF28 */ + uint32_t rx_smb0_fd[18]; /* 0xF70 */ + uint32_t rx_smb1_fd[18]; /* 0xFB8 */ +} FlexcanRegs; + +typedef struct FlexcanState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + IMXCCMState *ccm; + qemu_irq irq; + + CanBusState *canbus; + CanBusClientState bus_client; + + union { + FlexcanRegs regs; + uint32_t regs_raw[sizeof(FlexcanRegs) / 4]; + }; + int64_t timer_start; + uint64_t last_rx_timer_cycles; + int32_t locked_mbidx; + int32_t smb_target_mbidx; + uint32_t timer_freq; +} FlexcanState; + +#define TYPE_CAN_FLEXCAN "flexcan" + +OBJECT_DECLARE_SIMPLE_TYPE(FlexcanState, CAN_FLEXCAN); + +#endif --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734663; cv=none; d=zohomail.com; s=zohoarc; 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Add two new machine properties to Sabrelite machine for linking the embedded FlexCAN instances to QEMU CAN buses by name. No other machine uses FslIMX6State. Signed-off-by: Maty=C3=A1=C5=A1 Bobek Signed-off-by: Pavel Pisa Tested-by: Pavel Pisa Reviewed-by: Bernhard Beschow Reviewed-by: Pavel Pisa Message-id: 4159df998b0508bb411284ef406de23bbc5edfd8.1782140438.git.matyas.= bobek@gmail.com Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/fsl-imx6.c | 29 +++++++++++++++++++++++++++++ hw/arm/sabrelite.c | 24 ++++++++++++++++++++++++ include/hw/arm/fsl-imx6.h | 6 ++++++ 4 files changed, 60 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 500bfdfe2a..5f5c4899ad 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -520,6 +520,7 @@ config FSL_IMX6 select IMX_FEC select IMX_I2C select IMX_USBPHY + select CAN_FLEXCAN select WDT_IMX2 select PL310 # cache controller select PCI_EXPRESS_DESIGNWARE diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index f663ddbf0a..bf106a9063 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -90,6 +90,10 @@ static void fsl_imx6_init(Object *obj) snprintf(name, NAME_SIZE, "spi%d", i + 1); object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); } + for (i =3D 0; i < FSL_IMX6_NUM_CANS; i++) { + snprintf(name, NAME_SIZE, "flexcan%d", i + 1); + object_initialize_child(obj, name, &s->flexcan[i], TYPE_CAN_FLEXCA= N); + } for (i =3D 0; i < FSL_IMX6_NUM_WDTS; i++) { snprintf(name, NAME_SIZE, "wdt%d", i); object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); @@ -377,6 +381,27 @@ static void fsl_imx6_realize(DeviceState *dev, Error *= *errp) qdev_get_gpio_in(gic, spi_table[i].irq)); } =20 + /* Initialize all FLEXCANs */ + for (i =3D 0; i < FSL_IMX6_NUM_CANS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } flexcan_table[FSL_IMX6_NUM_CANS] =3D { + { FSL_IMX6_CAN1_ADDR, FSL_IMX6_FLEXCAN1_IRQ }, + { FSL_IMX6_CAN2_ADDR, FSL_IMX6_FLEXCAN2_IRQ }, + }; + + s->flexcan[i].ccm =3D IMX_CCM(&s->ccm); + object_property_set_link(OBJECT(&s->flexcan[i]), "canbus", + OBJECT(s->canbus[i]), &error_abort); + + sysbus_realize(SYS_BUS_DEVICE(&s->flexcan[i]), &error_abort); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->flexcan[i]), 0, flexcan_table[i= ].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->flexcan[i]), 0, + qdev_get_gpio_in(gic, flexcan_table[i].irq)); + } + object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &error_abort); qemu_configure_nic_device(DEVICE(&s->eth), true, NULL); @@ -480,6 +505,10 @@ static void fsl_imx6_realize(DeviceState *dev, Error *= *errp) =20 static const Property fsl_imx6_properties[] =3D { DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0), + DEFINE_PROP_LINK("canbus0", FslIMX6State, canbus[0], TYPE_CAN_BUS, + CanBusState *), + DEFINE_PROP_LINK("canbus1", FslIMX6State, canbus[1], TYPE_CAN_BUS, + CanBusState *), }; =20 static void fsl_imx6_class_init(ObjectClass *oc, const void *data) diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 7e036e6388..84bbc2f979 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -24,6 +24,7 @@ struct SabreliteMachineState { MachineState parent_obj; =20 FslIMX6State soc; + CanBusState *canbus[FSL_IMX6_NUM_CANS]; }; =20 #define TYPE_SABRELITE_MACHINE MACHINE_TYPE_NAME("sabrelite") @@ -64,6 +65,13 @@ static void sabrelite_init(MachineState *machine) /* Ethernet PHY address is 6 */ object_property_set_int(OBJECT(&s->soc), "fec-phy-num", 6, &error_fata= l); =20 + for (int i =3D 0; i < FSL_IMX6_NUM_CANS; i++) { + g_autofree char *bus_name =3D g_strdup_printf("canbus%d", i); + + object_property_set_link(OBJECT(&s->soc), bus_name, + OBJECT(s->canbus[i]), &error_fatal); + } + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR, @@ -112,6 +120,21 @@ static void sabrelite_init(MachineState *machine) } } =20 +static void sabrelite_machine_instance_init(Object *obj) +{ + SabreliteMachineState *s =3D SABRELITE_MACHINE(obj); + + object_property_add_link(obj, "canbus0", TYPE_CAN_BUS, + (Object **)&s->canbus[0], + object_property_allow_set_link, + 0); + + object_property_add_link(obj, "canbus1", TYPE_CAN_BUS, + (Object **)&s->canbus[1], + object_property_allow_set_link, + 0); +} + static void sabrelite_machine_class_init(ObjectClass *oc, const void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -128,6 +151,7 @@ static const TypeInfo sabrelite_machine_init_typeinfo = =3D { .name =3D TYPE_SABRELITE_MACHINE, .parent =3D TYPE_MACHINE, .class_init =3D sabrelite_machine_class_init, + .instance_init =3D sabrelite_machine_instance_init, .instance_size =3D sizeof(SabreliteMachineState), .abstract =3D false, .interfaces =3D arm_machine_interfaces, diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index cddd100dd6..376deea3a4 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -30,12 +30,14 @@ #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" #include "hw/net/imx_fec.h" +#include "hw/net/flexcan.h" #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" #include "hw/pci-host/designware.h" #include "hw/core/or-irq.h" #include "system/memory.h" #include "target/arm/cpu.h" +#include "net/can_emu.h" #include "qom/object.h" =20 #define TYPE_FSL_IMX6 "fsl-imx6" @@ -51,6 +53,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6State, FSL_IMX6) #define FSL_IMX6_NUM_WDTS 2 #define FSL_IMX6_NUM_USB_PHYS 2 #define FSL_IMX6_NUM_USBS 4 +#define FSL_IMX6_NUM_CANS 2 =20 struct FslIMX6State { /*< private >*/ @@ -73,6 +76,7 @@ struct FslIMX6State { IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS]; ChipideaState usb[FSL_IMX6_NUM_USBS]; IMXFECState eth; + FlexcanState flexcan[FSL_IMX6_NUM_CANS]; DesignwarePCIEHost pcie; OrIRQState pcie4_msi_irq; MemoryRegion rom; @@ -80,6 +84,8 @@ struct FslIMX6State { MemoryRegion ocram; MemoryRegion ocram_alias; uint32_t phy_num; + + CanBusState *canbus[FSL_IMX6_NUM_CANS]; }; =20 =20 --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734650; cv=none; d=zohomail.com; s=zohoarc; b=F7BEl/bZtYROglRPbznjgurB6KVZUgeo+370Kv0rJyIbjo2ViVKNzideIyqdpslxeDcWxFFN1hxKZyDGRxaUH/lL6aP4J7e8kaHg04poWjIZFnw23wB7cFzOl29dufFqTt+DZAPhFrqihmL6qmH96q4auhXFjaH3BQCatxS5DcA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-473dddcb295sm8753061f8f.35.2026.06.29.05.01.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 05:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1782734471; x=1783339271; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=sMdTNOXJicNmVfYzhq2NcQJIsw1TOMX0LeFJFszgqUI=; b=nHk5pD0Hqe8MS51Yn/Amyn5N+r61spT7RM0OsbX9/mNAJxHFXZKzwgPfL7BQLdzaRb JNI6k6cj3deRamnrCgwtIamWlnRVnC1R4o2lCXnl57/uNwnsbRTl77cO3WaHzizq04K/ BjHEzqMFrk05T44W0hk6dvvjTPdkCPfkPtmNV7301brTlaWfH8I8922e6DuumS/85K0b CQLJDh8VPJSV0qu4tZL0fZlCtGpiXLdYeMi6KBfdas113W8tfoCqntn/+Ar8XmB787E5 lZJzIhQ9AXFTwo66uC9j+x/MC0fZdAWf7ON5MH1cZuSPn5uCdu1UIy3Thl641YV9R/+c QIHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782734471; x=1783339271; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=sMdTNOXJicNmVfYzhq2NcQJIsw1TOMX0LeFJFszgqUI=; b=O33/qKeU8h9tcZfSCo/uEnxrGHeiFACqs428R/z5uuO9HvhX8cnpSRLNLdQ0/TGOS4 knW80+V4U6bC7ctPCqAlBHPtEgNRXYHm2ve2ZFnTSVrkOTTWLXd8f9pga/xqJV6AOmda 5dQdwih3oMe11bvLRPbWSo0+sot0ygMui2hfgu3hSYoEXGhM/7Dt/XdjQYgiJc0rGBA7 zkWnjlf29Z7IwlZ0RSGs8fEEXnWU3/BbZdC0fvv86XXvDASpf5ECkHEOdqvplUqqovyc gX2lEsdf/Ua+16SWiXqvHkT5MnN6keYMu6Tta3355Go/9SQxtUF7TpCyY6uoyUgeiHK2 9GRg== X-Gm-Message-State: AOJu0YwCIgmt2+KLwonLfRBxbal+WgQFu/Cnojfoh7FWVJvsP/6H3n8W TOU3V3EPkK7/nfN5Yuvuq0XVbKr+MpKNbEGr5dW7nZ5AoPq+I3Dvwc4PEuL58I/ga3Rk2tfXjub q4ecy X-Gm-Gg: AfdE7cmSv6OBjlNEywe02hrSa37/BzDVewiYgxqln7Xd8NRahw5fposOB1VTM931mI/ 2d2KngZCCekidHzBvXRx2vBXweMK38HuPBpZv09Z6RISIXXb53xJF6cqKjwbsPRYhBNySCXDLbI zejYmNGuDoKYU5XIe7f+H2q3iNN/V5y2tZRsa/DZzg5sSrWHePgf6+Z4/9aasetYjLdoXaJBSd1 nI68P8MZvdrO5Adw61CGUcO7tVMTU0yTfk93omCFxRtZa5Z5la5jYx6MXNzkaIgUp/BysLe8sFS b9dGlv7Nkj9ziaw+4l52A1V1O9lzzTisTmQvaFrPyyxRLTQQ4SQZBAXi4LeA8MpgbgP6I5dxm6g mU8XQ7zbNy8OUpVRFJVBKKiT0itDf6PAua2EhAEeXAZt5IpKeggNLAbiteOOiy9RDaX7HLBtrfU zUS3dFPzJ8E7tW5VXUbnLXfIMIBNYEhPqdZrGHHQu6RCCBVF1XYlJKCU1tD9wl98bJs+8IKwqD2 o3OBqeVZRrlXbHdtQBOcw== X-Received: by 2002:a05:6000:38d:b0:474:6a5b:8603 with SMTP id ffacd0b85a97d-4750079f913mr250368f8f.24.1782734471259; Mon, 29 Jun 2026 05:01:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/54] tests: Add qtests for FlexCAN Date: Mon, 29 Jun 2026 13:00:14 +0100 Message-ID: <20260629120032.1645265-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734651966158500 From: Maty=C3=A1=C5=A1 Bobek The tests do not test all of the FlexCAN emulator functionality. Signed-off-by: Maty=C3=A1=C5=A1 Bobek Signed-off-by: Pavel Pisa Tested-by: Pavel Pisa Reviewed-by: Bernhard Beschow Reviewed-by: Pavel Pisa Message-id: 3d47746ef30f29c58fec10267bdce7dac2c756a7.1782140438.git.matyas.= bobek@gmail.com Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + tests/qtest/flexcan-test.c | 421 +++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 3 files changed, 423 insertions(+) create mode 100644 tests/qtest/flexcan-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 91317818bf..0385418ce7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2114,6 +2114,7 @@ S: Maintained F: hw/net/can/flexcan.c F: hw/net/can/flexcan_regs.h F: include/hw/net/flexcan.h +F: tests/qtest/flexcan-test.c =20 EDU M: Jiri Slaby diff --git a/tests/qtest/flexcan-test.c b/tests/qtest/flexcan-test.c new file mode 100644 index 0000000000..87d947a806 --- /dev/null +++ b/tests/qtest/flexcan-test.c @@ -0,0 +1,421 @@ +/* + * QTests for FlexCAN CAN controller device model + * + * Copyright (c) 2025 Matyas Bobek + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +#include "hw/net/flexcan.h" +#include "hw/net/can/flexcan_regs.h" + +#define FSL_IMX6_CAN2_ADDR 0x02094000 +#define FSL_IMX6_CAN2_SIZE 0x4000 +#define FSL_IMX6_CAN1_ADDR 0x02090000 +#define FSL_IMX6_CAN1_SIZE 0x4000 + +#define FC_QEMU_ARGS "-nographic -M sabrelite " \ + "-object can-bus,id=3Dqcan0 " \ + "-machine canbus0=3Dqcan0 -machine canbus1=3Dqcan0" + +/* used for masking out unused/reserved bits */ +#define FC_MB_CNT_USED_MASK (~0xF080FFFFu) + +#define FCREG(BASE_ADDR, REG) ((BASE_ADDR) + offsetof(FlexcanRegs, REG)) +#define FCMB(BASE_ADDR, MB_IDX, WORD_IDX) (FCREG(BASE_ADDR, mbs) + \ + 0x10 * (MB_IDX) + 4 * (WORD_IDX)) + +typedef struct FcTestFrame { + uint32_t id; + uint32_t data[2]; + uint8_t len; + bool ide; + bool rtr; + + /* rx only */ + bool expect_overrun; +} FcTestFrame; + +static const FcTestFrame fc_test_frame_1 =3D { + .id =3D 0x5AF, + .len =3D 8, + .data =3D { + 0x01020304, + 0x0A0B0C0D + }, + .ide =3D false +}; + +static const FcTestFrame fc_test_frame_1_ide =3D { + .id =3D 0x105AF5AF, + .len =3D 8, + .data =3D { + 0x01020304, + 0x0A0B0C0D + }, + .ide =3D true +}; + +static void fc_reset(hwaddr ba, uint32_t mcr_flags) +{ + /* disable */ + writel(FCREG(ba, mcr), 0xD890000F); + + /* enable in freeze mode */ + writel(FCREG(ba, mcr), 0x5980000F); + + /* soft reset */ + writel(FCREG(ba, mcr), 0x5980000F | FLEXCAN_MCR_SOFTRST); + + g_assert_cmpuint(readl(FCREG(ba, mcr)), =3D=3D, 0x5980000F); + g_assert_cmpuint(readl(FCREG(ba, ctrl)), =3D=3D, 0); + g_assert_cmpuint(readl(FCREG(ba, ctrl2)), =3D=3D, 0); + + writel(FCREG(ba, mcr), (0x5980000F & ~FLEXCAN_MCR_HALT) | mcr_flags); + writel(FCREG(ba, ctrl2), FLEXCAN_CTRL2_RRS); + + /* initialize all mailboxes as rx inactive */ + for (int i =3D 0; i < FLEXCAN_MAILBOX_COUNT; i++) { + writel(FCMB(ba, i, 0), FLEXCAN_MB_CODE_RX_INACTIVE); + writel(FCMB(ba, i, 1), 0); + writel(FCMB(ba, i, 2), 0); + writel(FCMB(ba, i, 3), 0); + } +} + +static uint64_t fc_get_irqs(hwaddr ba) +{ + return (uint64_t)readl(FCREG(ba, iflag1)) | + ((uint64_t)readl(FCREG(ba, iflag2)) << 32); +} + +static void fc_clear_irq(hwaddr ba, int idx) +{ + if (idx >=3D 32) { + writel(FCREG(ba, iflag2), (uint32_t)1 << (idx - 32)); + } else { + writel(FCREG(ba, iflag1), (uint32_t)1 << idx); + } + + g_assert_cmpuint(fc_get_irqs(ba) & ((uint64_t)1 << idx), =3D=3D, 0); +} + +static void fc_setup_rx_mb(hwaddr ba, int mbidx) +{ + writel(FCMB(ba, mbidx, 0), FLEXCAN_MB_CODE_RX_EMPTY); + writel(FCMB(ba, mbidx, 1), 0); + /* the data value should be ignored for RX mb */ + writel(FCMB(ba, mbidx, 2), 0); + writel(FCMB(ba, mbidx, 3), 0); + + g_assert_cmpuint(readl(FCMB(ba, mbidx, 0)), =3D=3D, FLEXCAN_MB_CODE_RX= _EMPTY); +} + +static void fc_tx(hwaddr ba, int mbidx, const FcTestFrame *frame) +{ + g_assert_cmpuint(frame->len, <=3D, 8); + + writel(FCMB(ba, mbidx, 0), FLEXCAN_MB_CODE_TX_INACTIVE); + uint32_t id =3D frame->ide ? frame->id : frame->id << 18; + writel(FCMB(ba, mbidx, 1), id); + writel(FCMB(ba, mbidx, 2), frame->data[0]); + writel(FCMB(ba, mbidx, 3), frame->data[1]); + + uint32_t ctrl =3D FLEXCAN_MB_CODE_TX_DATA | FLEXCAN_MB_CNT_LENGTH(fram= e->len); + if (frame->ide) { + ctrl |=3D FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; + } + if (frame->rtr) { + ctrl |=3D FLEXCAN_MB_CNT_RTR; + } + writel(FCMB(ba, mbidx, 0), ctrl); + + /* check frame was transmitted */ + g_assert_cmpuint(fc_get_irqs(ba) & ((uint64_t)1 << mbidx), + !=3D, 0); + + uint32_t xpectd_ctrl =3D (ctrl & ~FLEXCAN_MB_CODE_MASK) | + FLEXCAN_MB_CODE_TX_INACTIVE; + g_assert_cmpuint(readl(FCMB(ba, mbidx, 0)) & FC_MB_CNT_USED_MASK, =3D= =3D, + xpectd_ctrl); + /* other fields should stay unchanged */ + g_assert_cmpuint(readl(FCMB(ba, mbidx, 1)), =3D=3D, id); + g_assert_cmpuint(readl(FCMB(ba, mbidx, 2)), =3D=3D, frame->data[0]); + g_assert_cmpuint(readl(FCMB(ba, mbidx, 3)), =3D=3D, frame->data[1]); +} + +static void fc_rx_check(hwaddr ba, int mbidx, const FcTestFrame *frame) +{ + uint32_t xpectd_ctrl =3D frame->expect_overrun ? FLEXCAN_MB_CODE_RX_OV= ERRUN + : FLEXCAN_MB_CODE_RX_FULL; + xpectd_ctrl |=3D FLEXCAN_MB_CNT_LENGTH(frame->len) | FLEXCAN_MB_CNT_SR= R; + if (frame->ide) { + xpectd_ctrl |=3D FLEXCAN_MB_CNT_IDE; + } + if (frame->rtr) { + xpectd_ctrl |=3D FLEXCAN_MB_CNT_RTR; + } + + uint32_t xpectd_id =3D frame->ide ? frame->id : frame->id << 18; + + uint32_t ctrl =3D readl(FCMB(ba, mbidx, 0)) & FC_MB_CNT_USED_MASK; + if ((ctrl & FLEXCAN_MB_CODE_MASK) =3D=3D FLEXCAN_MB_CODE_RX_EMPTY) { + fprintf(stderr, "expected frame (id=3D0x%X) not received\n", frame= ->id); + } + + g_assert_cmpuint(ctrl, =3D=3D, xpectd_ctrl); + g_assert_cmpuint(readl(FCMB(ba, mbidx, 1)), =3D=3D, xpectd_id); + g_assert_cmpuint(readl(FCMB(ba, mbidx, 2)), =3D=3D, frame->data[0]); + g_assert_cmpuint(readl(FCMB(ba, mbidx, 3)), =3D=3D, frame->data[1]); +} + +static void fc_check_empty_multi(hwaddr ba, int idx_count, int mbidxs[]) +{ + for (int i =3D 0; i < FLEXCAN_MAILBOX_COUNT; i++) { + bool check_empty =3D true; + int ctrl =3D readl(FCMB(ba, i, 0)); + + for (int j =3D 0; j < idx_count; j++) { + if (i =3D=3D mbidxs[j]) { + check_empty =3D false; + } + } + + if (check_empty) { + if (!(ctrl =3D=3D FLEXCAN_MB_CODE_RX_EMPTY || + ctrl =3D=3D FLEXCAN_MB_CODE_RX_INACTIVE)) { + g_assert_cmpuint(ctrl, =3D=3D, FLEXCAN_MB_CODE_RX_INACTIVE= ); + } + g_assert_cmpuint(readl(FCMB(ba, i, 1)), =3D=3D, 0); + g_assert_cmpuint(readl(FCMB(ba, i, 2)), =3D=3D, 0); + g_assert_cmpuint(readl(FCMB(ba, i, 3)), =3D=3D, 0); + } else { + g_assert_cmpuint( + ctrl & FLEXCAN_MB_CODE_MASK, !=3D, + FLEXCAN_MB_CODE_RX_INACTIVE + ); + } + } +} + +static void fc_check_empty(hwaddr ba, int mbidx) +{ + fc_check_empty_multi(ba, 1, &mbidx); +} + +static void flexcan_test_linux_probe_impl(hwaddr fba) +{ + /* -- test a Linux driver-like probe sequence -- */ + /* disable */ + writel(FCREG(fba, mcr), 0xD890000F); + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0xD890000F); + g_assert_cmpuint(readl(FCREG(fba, ctrl)), =3D=3D, 0); + + /* set bit in reserved field we do not implement (CTRL_CLK_SRC) */ + writel(FCREG(fba, ctrl), 0x00002000); + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0xD890000F); + + /* enable in freeze mode */ + writel(FCREG(fba, mcr), 0x5980000F); + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0x5980000F); + + /* enable Rx-FIFO */ + writel(FCREG(fba, mcr), 0x7980000F); + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0x7980000F); + g_assert_cmpuint(readl(FCREG(fba, ecr)), =3D=3D, 0); + + /* disable */ + writel(FCREG(fba, mcr), 0xF890000F); + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0xF890000F); +} + +static void flexcan_test_freeze_disable_interaction_impl(hwaddr fba) +{ + /* -- test normal <=3D> freeze <=3D> disable transitions -- */ + + /* leave freeze in disabled, FRZ_ACK should stay cleared */ + writel(FCREG(fba, mcr), 0xF890000F); /* disable */ + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0xF890000F); + writel(FCREG(fba, mcr), 0xB890000F); /* by clearing FRZ */ + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0xB890000F); + + writel(FCREG(fba, mcr), 0xF890000F); /* disable */ + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0xF890000F); + writel(FCREG(fba, mcr), 0xE890000F); /* by clearing HALT */ + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0xE890000F); + + writel(FCREG(fba, mcr), 0xF890000F); /* disable */ + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0xF890000F); + writel(FCREG(fba, mcr), 0xA890000F); /* by clearing both */ + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0xA890000F); + + /* enter and leave freeze */ + writel(FCREG(fba, mcr), 0x7980000F); /* enable in freeze mode */ + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0x7980000F); + writel(FCREG(fba, mcr), 0x3980000F); /* leave by clearing FRZ */ + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0x3080000F); + + writel(FCREG(fba, mcr), 0x7980000F); /* enable in freeze mode */ + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0x7980000F); + writel(FCREG(fba, mcr), 0x6980000F); /* leave by clearing HALT */ + g_assert_cmpuint(readl(FCREG(fba, mcr)), =3D=3D, 0x6080000F); +} + +static void flexcan_test_mailbox_io_impl(hwaddr ba_tx, hwaddr ba_rx) +{ + /* -- test correct handling of mailbox IO -- */ + const int test_1_mbidx =3D 0; + fc_reset(ba_tx, + FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_MAXMB(FLEXCAN_MAILBOX_COUNT= )); + fc_reset(ba_rx, + FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_MAXMB(FLEXCAN_MAILBOX_COUNT= )); + + fc_setup_rx_mb(ba_rx, test_1_mbidx); + fc_tx(ba_tx, test_1_mbidx, &fc_test_frame_1_ide); + g_assert_cmpuint(fc_get_irqs(ba_rx), =3D=3D, 1 << test_1_mbidx); + fc_rx_check(ba_rx, test_1_mbidx, &fc_test_frame_1_ide); + readl(FCREG(ba_rx, timer)); /* reset lock */ + + writel(FCMB(ba_rx, test_1_mbidx, 0), 0); + g_assert_cmpuint(readl(FCMB(ba_rx, test_1_mbidx, 0)), =3D=3D, 0); + writel(FCMB(ba_rx, test_1_mbidx, 1), 0x99AABBCC); + g_assert_cmpuint(readl(FCMB(ba_rx, test_1_mbidx, 1)), =3D=3D, 0x99AABB= CC); +} + +static void flexcan_test_dual_transmit_receive_impl(hwaddr ba_tx, hwaddr b= a_rx) +{ + /* -- test TX and RX between the two FlexCAN instances -- */ + const int test_1_mbidx =3D 50; + const int test_rounds =3D 50; + + /* self-receive enabled on tx FC */ + fc_reset(ba_tx, + FLEXCAN_MCR_MAXMB(FLEXCAN_MAILBOX_COUNT)); + fc_reset(ba_rx, + FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_MAXMB(FLEXCAN_MAILBOX_COUNT= )); + + /* tests self-receive on tx and reception on rx */ + fc_setup_rx_mb(ba_rx, test_1_mbidx); + fc_check_empty(ba_rx, test_1_mbidx); + fc_setup_rx_mb(ba_tx, test_1_mbidx + 1); + fc_check_empty(ba_tx, test_1_mbidx + 1); + g_assert_cmpuint(fc_get_irqs(ba_rx), =3D=3D, 0); + g_assert_cmpuint(fc_get_irqs(ba_tx), =3D=3D, 0); + + fc_tx(ba_tx, test_1_mbidx, &fc_test_frame_1); + fc_clear_irq(ba_tx, test_1_mbidx); + + fc_rx_check(ba_rx, test_1_mbidx, &fc_test_frame_1); + fc_check_empty(ba_rx, test_1_mbidx); + fc_rx_check(ba_tx, test_1_mbidx + 1, &fc_test_frame_1); + int tx_non_empty_mbidxs[] =3D {test_1_mbidx, test_1_mbidx + 1}; + + fc_check_empty_multi(ba_tx, 2, tx_non_empty_mbidxs); + fc_clear_irq(ba_rx, test_1_mbidx); + fc_clear_irq(ba_tx, test_1_mbidx + 1); + readl(FCREG(ba_rx, timer)); /* reset lock */ + + for (int ridx =3D 0; ridx < test_rounds; ridx++) { + /* test extended IDs sent to all mailboxes */ + for (int i =3D 0; i < FLEXCAN_MAILBOX_COUNT; i++) { + fc_setup_rx_mb(ba_rx, i); + } + fc_check_empty_multi(ba_rx, 0, NULL); + g_assert_cmpuint(fc_get_irqs(ba_rx), =3D=3D, 0); + g_assert_cmpuint(fc_get_irqs(ba_tx), =3D=3D, 0); + + for (int i =3D 0; i < FLEXCAN_MAILBOX_COUNT; i++) { + fc_tx(ba_tx, i, &fc_test_frame_1_ide); + } + g_assert_cmpuint(fc_get_irqs(ba_rx), =3D=3D, UINT64_MAX); + g_assert_cmpuint(fc_get_irqs(ba_tx), =3D=3D, UINT64_MAX); + for (int i =3D 0; i < FLEXCAN_MAILBOX_COUNT; i++) { + fc_rx_check(ba_rx, i, &fc_test_frame_1_ide); + } + + /* reset interrupts */ + writel(FCREG(ba_rx, iflag1), UINT32_MAX); + writel(FCREG(ba_rx, iflag2), UINT32_MAX); + writel(FCREG(ba_tx, iflag1), UINT32_MAX); + writel(FCREG(ba_tx, iflag2), UINT32_MAX); + g_assert_cmpuint(fc_get_irqs(ba_rx), =3D=3D, 0); + g_assert_cmpuint(fc_get_irqs(ba_tx), =3D=3D, 0); + } +} + +static void flexcan_test_tx_abort_impl(hwaddr ba) +{ + /* -- test the TX abort feature -- */ + fc_reset(ba, + FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_MAXMB(FLEXCAN_MAILBOX_COUNT= )); + + + for (int mbidx =3D 0; mbidx < FLEXCAN_MAILBOX_COUNT; mbidx++) { + fc_tx(ba, mbidx, &fc_test_frame_1); + + writel(FCMB(ba, mbidx, 0), FLEXCAN_MB_CODE_TX_ABORT); + g_assert_cmpuint(readl(FCMB(ba, mbidx, 0)), =3D=3D, + FLEXCAN_MB_CODE_TX_INACTIVE); + } +} + +static void flexcan_test_freeze_disable_interaction(void) +{ + qtest_start(FC_QEMU_ARGS); + flexcan_test_freeze_disable_interaction_impl(FSL_IMX6_CAN1_ADDR); + flexcan_test_freeze_disable_interaction_impl(FSL_IMX6_CAN2_ADDR); + qtest_end(); +} + +static void flexcan_test_linux_probe(void) +{ + qtest_start(FC_QEMU_ARGS); + flexcan_test_linux_probe_impl(FSL_IMX6_CAN1_ADDR); + flexcan_test_linux_probe_impl(FSL_IMX6_CAN2_ADDR); + qtest_end(); +} + +static void flexcan_test_dual_transmit_receive(void) +{ + qtest_start(FC_QEMU_ARGS); + flexcan_test_dual_transmit_receive_impl(FSL_IMX6_CAN1_ADDR, + FSL_IMX6_CAN2_ADDR); + flexcan_test_dual_transmit_receive_impl(FSL_IMX6_CAN2_ADDR, + FSL_IMX6_CAN1_ADDR); + qtest_end(); +} + +static void flexcan_test_tx_abort(void) +{ + qtest_start(FC_QEMU_ARGS); + flexcan_test_tx_abort_impl(FSL_IMX6_CAN1_ADDR); + flexcan_test_tx_abort_impl(FSL_IMX6_CAN2_ADDR); + qtest_end(); +} + +static void flexcan_test_mailbox_io(void) +{ + qtest_start(FC_QEMU_ARGS); + flexcan_test_mailbox_io_impl(FSL_IMX6_CAN1_ADDR, FSL_IMX6_CAN2_ADDR); + flexcan_test_mailbox_io_impl(FSL_IMX6_CAN2_ADDR, FSL_IMX6_CAN1_ADDR); + qtest_end(); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/net/flexcan/linux_probe", flexcan_test_linux_probe); + qtest_add_func("/net/flexcan/freeze_disable_interaction", + flexcan_test_freeze_disable_interaction); + qtest_add_func("/net/flexcan/dual_transmit_receive", + flexcan_test_dual_transmit_receive); + qtest_add_func("/net/flexcan/tx_abort", + flexcan_test_tx_abort); + qtest_add_func("/net/flexcan/mailbox_io", flexcan_test_mailbox_io); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index e154abb05d..2a0ed815d2 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -251,6 +251,7 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : [])= + \ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 := []) + \ (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-= test'] : []) + \ + (config_all_devices.has_key('CONFIG_CAN_FLEXCAN') ? ['flexcan-test'] : [= ]) + \ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \ ['arm-cpu-features', --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735162; cv=none; d=zohomail.com; s=zohoarc; b=nebLqdVT1NNN8ScwZR1cDY2rNcp/jzxLPFcjR5Bmn/+4X7OCWxDVTSUPE81+WcOePYuzbnMve2KT0teIB7mfTp97wVxPPjZ6/uDTVeRKYCCoaZGsGtgE0OlhSX6r2bdwPQKCb/3OdrzH2Wxlf4rJ/6Id1AVrbDkfIbWxCpo365M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735162; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=dZ68e+lllc2ko4koDZi1fAQ+t+8zwCavECbfgDMJFSI=; b=LdpOpH+0/hLic3lKoRICFlhgAsocLmt5v9QUvkkDMvxKS98fQSz0famJMyx6nS/z/t+d+tWg8J68dPdqMVBQ4Ykvi5GaBzMfNkd4m47tUuhdSJjnYZ34NPA12HOEwhtZs5iHuxkiAcL5Ywdw3STu9iQBDK+nMI110eq45L0wZpE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735162438127.92655003550828; Mon, 29 Jun 2026 05:12:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgK-0007Nr-33; Mon, 29 Jun 2026 08:01:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAft-00071N-5C for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:19 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfq-0007YK-Es for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:15 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-46ed4f66256so2707393f8f.3 for ; Mon, 29 Jun 2026 05:01:13 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Maty=C3=A1=C5=A1 Bobek Signed-off-by: Pavel Pisa Tested-by: Pavel Pisa Reviewed-by: Bernhard Beschow Reviewed-by: Pavel Pisa Message-id: 19407fc30bdf6b264d1c093a82903609e9cfee48.1782140438.git.matyas.= bobek@gmail.com Signed-off-by: Peter Maydell --- docs/system/arm/sabrelite.rst | 1 + docs/system/devices/can.rst | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/docs/system/arm/sabrelite.rst b/docs/system/arm/sabrelite.rst index 4ccb0560af..d3a3c01dd6 100644 --- a/docs/system/arm/sabrelite.rst +++ b/docs/system/arm/sabrelite.rst @@ -24,6 +24,7 @@ The SABRE Lite machine supports the following devices: * 4 SDHC storage controllers * 4 USB 2.0 host controllers * 5 ECSPI controllers + * 2 FlexCAN CAN controllers * 1 SST 25VF016B flash =20 Please note above list is a complete superset the QEMU SABRE Lite machine = can diff --git a/docs/system/devices/can.rst b/docs/system/devices/can.rst index 09121836fd..622f898952 100644 --- a/docs/system/devices/can.rst +++ b/docs/system/devices/can.rst @@ -173,6 +173,30 @@ The test can also be run the other way around, generat= ing messages in the guest system and capturing them in the host system. Other combinations are also possible. =20 +Examples on how to use CAN emulation for FlexCAN on SabreLite board +------------------------------------------------------------------- +FlexCANs are connected to QEMU CAN buses by passing the bus IDs as machine +properties: + +* property ``canbus0`` for connecting ``flexcan1`` +* property ``canbus1`` for connecting ``flexcan2`` + +Note that upstream Linux SabreLite DTs have only a single FlexCAN (``flexc= an1``) +enabled. + +An example command to run QEMU emulating a Sabrelite development board +with both FlexCANs connected to a single QEMU CAN bus (called ``qcan0``), +bridged to host system ``can0`` interface:: + + qemu-system-arm -M sabrelite -smp 4 -m 1G \ + -object can-bus,id=3Dqcan0 \ + -machine canbus0=3Dqcan0 -machine canbus1=3Dqcan0 \ + -object can-host-socketcan,if=3Dcan0,canbus=3Dqcan0,id=3Dqcan0-socketc= an \ + -kernel ... -dtb ... -initrd ... + +Note that in the Linux guest, bitrate for the FlexCAN device is ignored, +but needs to be set via the ``ip`` command. + Links to other resources ------------------------ =20 --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735137; cv=none; d=zohomail.com; s=zohoarc; b=ZS486XHtUrA4tLEi8gSHBfozaBJiv6kHSzPv/2t6ziQKDYKcBQJoUwsOSJq2ntpwNhHdTDmkaObLboBI9udOIWlXh4Dwmu3bIW+cwhAmehaRf5xDRAW9/+4dqj4CH/bkr54Gx6rEPozoFrz0XhbBtBeHADW47G9RBsEr05lZT7M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735137; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=GSKi1D8EQOBK2DIYO8trrK7f2HEfo4qnjX06x2B+U8I=; b=cqtVaTO9YJsfTFrTSs/f9bqs2zqEDTaxRgbE/Al1ByxiAr/3dcraDCA4dAf/V1bPfQVfLyDZF7hRRSF4HwZPRgU7MjnIpQqJxkwZpxmzf+RN7Vaw/o3FT4TJqozYnyQIpZU6fImxLHTKJUNCr/c3rRl+zodikWncsMruZuqpdIE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735137280588.6033179247718; Mon, 29 Jun 2026 05:12:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgH-0007MJ-Ui; Mon, 29 Jun 2026 08:01:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfu-00071m-EE for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:20 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfs-0007Ya-UX for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:18 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-46066e640easo1732755f8f.1 for ; Mon, 29 Jun 2026 05:01:15 -0700 (PDT) Received: from lanath.. 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While unlikely to be seen in real life we should still make sure we behave correctly. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260624124527.1018912-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ddca634538..202ac99f69 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1802,7 +1802,8 @@ static void gt_cnthctl_write(CPUARMState *env, const = ARMCPRegInfo *ri, =20 if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) { gt_update_irq(cpu, GTIMER_VIRT); - } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) { + } + if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) { gt_update_irq(cpu, GTIMER_PHYS); } } --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734579; cv=none; d=zohomail.com; s=zohoarc; b=Y/OT9eEFuTODWQwPsQljKieZUjr/WRk62L8YvXnsQmJ2Teyf/way25BYkPoD3n2dX3riPb7spg8uq8jZdgZSEec4rwsA3tBasUARO8jSWJXUumlq58LvhXDzG0aaeKColO4jMP9H+ByT+7NXckPMqi4w9Ga590WVePY9tvkhJoM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734579; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=F0x/ajmQ2uQVMdgcXju1w+He09D8jrvrrV+1HV0u4K0=; b=Kw1VfmmpLwGUJqX6jZcUnDYN3gJ9yjEJwPzP5O83K0qUQGBthOJp31AiXvsRNHeyMM4e1R2jKfAWPTEAf/5QeROla1fPLNplkaZ1j5ALZ+TShkcYVzkGHr9NMusiXBvxqJLLMvY+vEF/3JByXyj3NFTHl6zyA0q4QUAZ0MvKfZ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734579419468.31160254256076; Mon, 29 Jun 2026 05:02:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgG-0007LP-UI; Mon, 29 Jun 2026 08:01:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfv-00071u-MW for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:20 -0400 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfu-0007ZX-0K for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:19 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-c12614b81c9so190123466b.3 for ; Mon, 29 Jun 2026 05:01:17 -0700 (PDT) Received: from lanath.. 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As a result we should trigger a recalculation of the timer value to take into account the new offset. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260624124527.1018912-3-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 202ac99f69..71c0d3f4d3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1806,6 +1806,9 @@ static void gt_cnthctl_write(CPUARMState *env, const = ARMCPRegInfo *ri, if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) { gt_update_irq(cpu, GTIMER_PHYS); } + if ((oldval ^ value) & R_CNTHCTL_ECV_MASK) { + gt_recalc_timer(cpu, GTIMER_PHYS); + } } =20 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734794; cv=none; d=zohomail.com; s=zohoarc; b=clOvuyXK1nIu48WsHHw13XhVqk6q774nCMjDtLsWPOaq1vZCEuAjlnSFAJ3er4ze6VnndVVbo6WB0+bD+2rglqSHhYHE0WQyaCdHtoBgb0fUr8MnuxiHYu6oXV6Tvh+Uno86tRYct+BxsxGlsqmphrkIbQ7MdvGSY/wL974sKME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734794; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=F3Usoptu4/Ftkfff+NbElWmrL+NRp28tLW+NHEpvB9g=; b=bKUPRDOPDy3Lq4f1bGE42GQNwLozfCK4jFI8t4nxJfeLpbhmvZNgfBqHyfM159vyynSzoTa36PlboxOUHypumhs56ckNr3BMGDZhMGDUPJaXN1XNC6T68tn8Gix5kli4Bj4GmKMJVCCs4m4wM+jJghziEX4Vi0bZXpArj2UEhuU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734794245731.6194969512351; Mon, 29 Jun 2026 05:06:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgV-0007ov-7v; Mon, 29 Jun 2026 08:01:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfv-00071t-54 for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:20 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAft-0007ZD-NK for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:18 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4924593f45dso42249525e9.1 for ; Mon, 29 Jun 2026 05:01:17 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260624124527.1018912-4-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 71c0d3f4d3..4f3281feaf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -37,6 +37,9 @@ #include "qemu/plugin.h" =20 static void switch_mode(CPUARMState *env, int mode); +#ifndef CONFIG_USER_ONLY +static void gt_recalc_timer(ARMCPU *cpu, int timeridx); +#endif =20 int compare_u64(const void *a, const void *b) { @@ -821,6 +824,12 @@ static void scr_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) changed =3D env->cp15.scr_el3 ^ value; env->cp15.scr_el3 =3D value; =20 +#ifndef CONFIG_USER_ONLY + if (changed & SCR_ECVEN) { + gt_recalc_timer(cpu, GTIMER_PHYS); + } +#endif + /* * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, * we must invalidate all TLBs below EL3. --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735106; cv=none; d=zohomail.com; s=zohoarc; b=d6lPxwW6IeGNUiS5DBcCqnE8VIX59UHB2M5K+AvlKV2T4wQENxb5B6kXhMqVjK2wUdDr3dugFsZ96EjFs6Gzu3l4P467JuYltg5IiBgMJzeSHfxVDAXRnxfP0APb27ILytkfDABHjLcluh6tSYx+Rd5J4GltnJc/kHTgHyG4suo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735106; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ypN3/i7YqXJgMmeeqZEABskabQGp8rFqcVVtbknYAMU=; b=IjI3qE8ymSbaRKXQvMNlQ4q+eMB9K7+VZo/QdIAtcs+elQQYcIesOu9QAavpuHdkP19hVIkXtzG6zqUcmd5qQLrzGRwT+JGdk+u5M/gggpXBAYrfI5VsEryNBLsrQyoKp+cU7tuFAT1URcLZf3clxCBNhiuuCMWKxbMfDDNjo+s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735106217211.2683093946497; Mon, 29 Jun 2026 05:11:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgU-0007mw-6b; Mon, 29 Jun 2026 08:01:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfw-000722-BX for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:20 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfu-0007Zl-FX for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:20 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-493b27c7451so5782135e9.0 for ; Mon, 29 Jun 2026 05:01:18 -0700 (PDT) Received: from lanath.. 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Suggested-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20260624124527.1018912-5-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4f3281feaf..20165dbf48 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1413,10 +1413,10 @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignor= ed) =20 static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env) { - if ((env->cp15.scr_el3 & SCR_ECVEN) && - FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) && - arm_is_el2_enabled(env) && - (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + if ((!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_EC= VEN)) + && FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) + && arm_is_el2_enabled(env) + && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HC= R_TGE)) { return env->cp15.cntpoff_el2; } return 0; --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735143; cv=none; d=zohomail.com; s=zohoarc; b=Fkcfhdl0/GS8i211xu0FwSWGByfCxMpAfUJgWypB+ONYaHLXAK2E4HKaWXFhNStut4LnH+yvNq0m0xAy1sajeYHo2NHEJ/KDYXDqzlNhFH7nvCl9UT0Q9g0B57Hq4U2g1k0kfQE/X5Mg1bTyo8xDKM94ms5IhKDfDlpMIg6bIPA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735143; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=uABLgJwHmKoW5wIwYEcwRXxpSE6Uum9z9tY7YjVQSII=; b=VC64fpSMEF6cyAziH8/YR+owTy8QHavYZz4n6DfrsIuvDiLlo5qBym1isrc9vMEu6i0LHSBN+CfhDWqeYhiGe1R4tQQzLZq1oJhaIJMmGoINoL9qkW1pyJlaF9zsXGoLch0bmmfCLIpDF77IVzIPZIB7BqyfJNnQ4Bfip+tJU1w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735143400315.91104240204277; Mon, 29 Jun 2026 05:12:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgV-0007pG-NT; Mon, 29 Jun 2026 08:01:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfx-00072e-GU for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:22 -0400 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfv-0007aB-Tj for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:21 -0400 Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-691c5776f35so4922363a12.3 for ; Mon, 29 Jun 2026 05:01:19 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-473dddcb295sm8753061f8f.35.2026.06.29.05.01.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 05:01:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1782734478; x=1783339278; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uABLgJwHmKoW5wIwYEcwRXxpSE6Uum9z9tY7YjVQSII=; b=szr4o+OkdyyXnKVL5+r844eVRY4BlMgpeiYLTVJM8ivJf5NAPiT1IDkXGmAsW+y9Hz 7RLdzUVJNpo5prVKuIYaaZbfdY5m8EM4DMfy1CVtQ6oho9PD7L2Pk3ji4zFAgIArcVY/ K1/LyZ8obfuCrmlJ7SgZigyto2wTfCoD1su2xaAGvsdQMuQLrmbYAYYSP+56Suw8rW4y r4QGisgGEPwlHFYHxTy5WZDDBKZ7V91MRWe022F2jEvAsjzCIZBu3ADmI8v6yOCsmJDw LpKQs58S4bTTV7paUox6muW79KRQaM12MkQ4eFwgnTfeopY+ByHWW1oiTDS62MchQq2q IxAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782734478; x=1783339278; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=uABLgJwHmKoW5wIwYEcwRXxpSE6Uum9z9tY7YjVQSII=; b=XDB2EDJuiKXAKWoIgRxBQeIoMcU72AFRoSZu6Rl3ReLfA1ZGCDAFMLxIf+7IjUVG1K fIiYTiDHBHiDYzdwpsCpo63KUIKy/+8UAOFrn9md+WfAyzQStjTf2HwcwPmZR3F0wzEI auTiobu8vmt/0sWofsJf/zw8vba1heRONeCgFqnX7cd8RnazM+1ha15/QIkhONzqWpNH XDWr7ocuqrgLOHRaoBA9lcemzZNv0lZPo0tA9dDpCbyaIkTqIPSZ+S2mXrmlbUYJMcpw cV7xGbgFHfWl3VmWZC44SMJyBaDzfDcO5FD6LCzjpGwwN5d0yJgklPvRdd6ywnw+IizI 9JDA== X-Gm-Message-State: AOJu0Yyb1xb3j3ePYz5aE0HFit0ztSuDayuhwDUnfYMxxeiouDwl/DHW YnoeAfSrJseHK58pmAtbdKdXwSVC1mInhg84UdwaQv8aBlbm/OxsAiKrP0WEeRjt94JSwFdqzKV Bp6kr X-Gm-Gg: AfdE7ckaGaDlF95j3lFhgbiaMXyOEAxfPlJgBXOSJBBSXRQZWaTaqaoL2wpMNNGJ8aU oa36bVyaVhRKsw0tdJWBWfIj4TWhOGS3Rvkp+8ouhI/AYeqcGvmMfufeDCytBRIer53S+nuV6s+ CDSJxxa6+2nujN8w4LjQLiCyMR8DMSgDvHr6jtb9aNmAslJkFG4TFYTbD/P0t92Ue2Dl9kbY5hh 1W/u2mwj9G5vhPLYMzOmpzxex6FU3hyunF/HGAVM0XIQu9M75ULkJuUL83qIIMyOuBN0H5ylbsE eX0vkD90VCV2L+yVPIXPXxCoSbQEgheILZX5LPCzHgO945K9ZKPJsKJMDpxnhKU5MCZjchJlVq6 vJ817a5MqWP4K/uRr0tVT8bUO9DWGUde+6FaSnw92J7ULa1AoUvEgae/IAfMTMfB2O8/OR+55Rx qQjfHyYKsxt7giBpcpa/Yy+e5nZajzKwCxlht0+6I79wCoYPZlP3ubEC+ALEi8IxSlNflRHFUkV CEe10yBq/PBgMmJW2XnIA== X-Received: by 2002:a05:6402:43c5:b0:698:5f35:a8e0 with SMTP id 4fb4d7f45d1cf-6985f35b11dmr1979746a12.6.1782734477953; Mon, 29 Jun 2026 05:01:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/54] target/arm: trigger timer recalc on HCR:(E2H|TGE) changes Date: Mon, 29 Jun 2026 13:00:20 +0100 Message-ID: <20260629120032.1645265-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735144069158500 From: Alex Benn=C3=A9e Toggling the HCR state affects the offset calculated in gt_phys_raw_cnt_offset so we should trigger a re-calculation on its change. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260624124527.1018912-6-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 20165dbf48..93e3d8b575 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3716,6 +3716,7 @@ static const ARMCPRegInfo v8_aa32_el1_reginfo[] =3D { static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) { ARMCPU *cpu =3D env_archcpu(env); + bool hcr_change_timer; =20 if (arm_feature(env, ARM_FEATURE_V8)) { valid_mask |=3D MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ @@ -3807,6 +3808,10 @@ static void do_hcr_write(CPUARMState *env, uint64_t = value, uint64_t valid_mask) (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB | HCR_NV | HCR_NV1)= ) { tlb_flush(CPU(cpu)); } + hcr_change_timer =3D (env->cp15.hcr_el2 ^ value) & + (HCR_E2H | HCR_TGE); + + /* update */ env->cp15.hcr_el2 =3D value; =20 /* @@ -3828,6 +3833,11 @@ static void do_hcr_write(CPUARMState *env, uint64_t = value, uint64_t valid_mask) arm_cpu_update_vinmi(cpu); arm_cpu_update_vfnmi(cpu); } + if (hcr_change_timer) { +#ifndef CONFIG_USER_ONLY + gt_recalc_timer(cpu, GTIMER_PHYS); +#endif + } } =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734978; cv=none; d=zohomail.com; s=zohoarc; b=NiBmbO8d7iQ4KiqzVXvYC83pQ3JRx229RdeT1mcHJyPL03tMpSU/VSVmehnl1YN4dr08yxa6NRWvqIexFah1z5icPzNDvaqjpXz8dsUW/hMEmk6hOov8bSArzonlo8L3swU5I4XulukUTfM90H629RMuub16pTs3PjlZoj2KEd4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734978; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=lVp0MF5AxBtesKNoIwmmBsVx0j0PXCsXmpRHhAE5wSI=; b=l55jMAwqwGX39WkThn2LtLZaZUN5g9TatEK5CGHSdL7TxTioi1ITh/Xr8vdq6P+0mWT8DzBdFf6bGz3q4WRNOQPUawoeDpvlcSVUoCPKT9bp9quTZGGXD1n++mh1bcYMnKM9x3WxXSBx9Caa0LRE7btpivPnkWEwnpd3zvwUdIE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734978810858.0949348293396; Mon, 29 Jun 2026 05:09:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgU-0007ng-K8; Mon, 29 Jun 2026 08:01:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfy-00072i-L0 for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:24 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfw-0007aR-LO for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:21 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-4720d22c94aso1281030f8f.1 for ; Mon, 29 Jun 2026 05:01:20 -0700 (PDT) Received: from lanath.. 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Add it to the list. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260624124527.1018912-7-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index a3a1607ff9..6b02bd829a 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -60,6 +60,7 @@ the following architecture extensions: - FEAT_E2H0 (Programming of HCR_EL2.E2H) - FEAT_EBF16 (AArch64 Extended BFloat16 instructions) - FEAT_ECV (Enhanced Counter Virtualization) +- FEAT_ECV_POFF (Enhanced Counter Virtualization Physical Offset) - FEAT_EL0 (Support for execution at EL0) - FEAT_EL1 (Support for execution at EL1) - FEAT_EL2 (Support for execution at EL2) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735010; cv=none; d=zohomail.com; s=zohoarc; b=LBGPPLhmwoZUNd6y9n+6KJZWzy19u11Kj6NbF0Qxdi2Jhz6x3ZSI9c1vJeEvRwMErfap8zbNdTgFcX+duPbykniNmYX4nlvuOUD9DMoyhhhlnz9ZHLKMk66cPNIxQFy7kL0FdFxbt6YPuys+fvBdXy7fyEjpk4C4eTenqzj+CUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735010; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=UieAOkcCm4++Nv0pwychI8mLwpbs12/8vlMvEYuNlpk=; b=NEHQd5RyYXqSZ5d2GWe+73m+4jttpB7uIXUZ831wyNyrYCskrorEMl0jZcKFvD2SQqm+HAZhqBmaMd9xm7pM2aYIMTXlzhhQnP3sKzki90ToBeaI0TTr2mdwHHHzmaAgC/8tU1yk5Xe2vAjeMQFiLGF/DmGgIyKNYRMgYs3eEcs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735010296308.68986312104596; Mon, 29 Jun 2026 05:10:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAib-00029f-2W; Mon, 29 Jun 2026 08:04:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAfz-00073E-Vq for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:24 -0400 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfy-0007bF-CA for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:23 -0400 Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-c127a694ccbso53867666b.3 for ; Mon, 29 Jun 2026 05:01:21 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Richard Henderson [PMM: fix && vs || mixup in feature function] Reviewed-by: Peter Maydell Message-id: 20260625015159.719300-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 11 +++++++++++ target/arm/tcg/translate-sme.c | 4 ++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 2e4f22f193..98102d75bf 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1610,6 +1610,11 @@ static inline bool isar_feature_aa64_sme_f8f32(const= ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F8F32); } =20 +static inline bool isar_feature_aa64_sme_f8f16(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F8F16); +} + static inline bool isar_feature_aa64_sme_f16f16(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F16F16); @@ -1781,6 +1786,12 @@ isar_feature_aa64_sme2_or_sve2_lut(const ARMISARegis= ters *id) return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_lut(id); } =20 +static inline bool +isar_feature_aa64_sme_f16f16_or_f8f16(const ARMISARegisters *id) +{ + return isar_feature_aa64_sme_f16f16(id) || isar_feature_aa64_sme_f8f16= (id); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index a79b0a9b80..b8dde80c20 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1335,9 +1335,9 @@ static bool do_faddsub(DisasContext *s, arg_az_n *a, = ARMFPStatusFlavour fpst, return true; } =20 -TRANS_FEAT(FADD_nn_h, aa64_sme_f16f16, do_faddsub, a, +TRANS_FEAT(FADD_nn_h, aa64_sme_f16f16_or_f8f16, do_faddsub, a, FPST_ZA_F16, gen_helper_gvec_fadd_h) -TRANS_FEAT(FSUB_nn_h, aa64_sme_f16f16, do_faddsub, a, +TRANS_FEAT(FSUB_nn_h, aa64_sme_f16f16_or_f8f16, do_faddsub, a, FPST_ZA_F16, gen_helper_gvec_fsub_h) =20 TRANS_FEAT(FADD_nn_s, aa64_sme2, do_faddsub, a, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782734794; cv=none; d=zohomail.com; s=zohoarc; b=hngIaiAgsk6MEdNwiWvD64buos327YFHrCpDSEqSsH+qJogG0oXJBkMAQEXLp6UNBVMtjfIVpCtnTVTcfKMXugWish5ZW/Il49bH4fcJGsnb2yX5rhyV51/W0yDrT7/DjzsaeYLfMgDIkBFjXTb2tUjflKNuyj161OjfEhAFqcA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782734794; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=c1CLvQpxi98w8hCCGMuReQm8cigrXYogjEHOmllUeYE=; b=oJzctpqlQVk3HdN9rlIAri/MKVHqK4lC9bPhdPZC1ArUpSevM+RkOctAdBijHlx+1QM5diK8gIk7mXBIEhAP/nOhPADjBzZNAIJ8MPj+BpTzHapwuheS6ZqoaSIWh667ImKgocsso2BvSzcsinwwPNHofjViufHtWElzh6SBXYE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782734794341474.65568173880297; Mon, 29 Jun 2026 05:06:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgQ-0007YN-A3; Mon, 29 Jun 2026 08:01:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAg1-00073x-Gn for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:26 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAfy-0007bR-Rg for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:25 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-47231f1f8f3so2284586f8f.1 for ; Mon, 29 Jun 2026 05:01:22 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260625015159.719300-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 32 ++++++++++++++++---------------- target/arm/tcg/translate-sme.c | 12 ++++++------ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 1de5f341ef..90ee161461 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -324,13 +324,13 @@ SUB_azz_n1_d 11000001 0111 .... 0 .. 110 ..... 11 = ... @azz_nx1_o3 n=3D4 @azz_nx1_o2x2 ........ ... . zm:4 . .. ... zn:5 ... .. \ &azz_n off=3D%off2_x2 rv=3D%mova_rv =20 -FMLAL_n1 11000001 001 0 .... 0 .. 011 ..... 00 ... @azz_nx1_o3x2 = n=3D1 -FMLAL_n1 11000001 001 0 .... 0 .. 010 ..... 000 .. @azz_nx1_o2x2 = n=3D2 -FMLAL_n1 11000001 001 1 .... 0 .. 010 ..... 000 .. @azz_nx1_o2x2 = n=3D4 +FMLAL_n1_sh 11000001 001 0 .... 0 .. 011 ..... 00 ... @azz_nx1_o3x2 = n=3D1 +FMLAL_n1_sh 11000001 001 0 .... 0 .. 010 ..... 000 .. @azz_nx1_o2x2 = n=3D2 +FMLAL_n1_sh 11000001 001 1 .... 0 .. 010 ..... 000 .. @azz_nx1_o2x2 = n=3D4 =20 -FMLSL_n1 11000001 001 0 .... 0 .. 011 ..... 01 ... @azz_nx1_o3x2 = n=3D1 -FMLSL_n1 11000001 001 0 .... 0 .. 010 ..... 010 .. @azz_nx1_o2x2 = n=3D2 -FMLSL_n1 11000001 001 1 .... 0 .. 010 ..... 010 .. @azz_nx1_o2x2 = n=3D4 +FMLSL_n1_sh 11000001 001 0 .... 0 .. 011 ..... 01 ... @azz_nx1_o3x2 = n=3D1 +FMLSL_n1_sh 11000001 001 0 .... 0 .. 010 ..... 010 .. @azz_nx1_o2x2 = n=3D2 +FMLSL_n1_sh 11000001 001 1 .... 0 .. 010 ..... 010 .. @azz_nx1_o2x2 = n=3D4 =20 BFMLAL_n1 11000001 001 0 .... 0 .. 011 ..... 10 ... @azz_nx1_o3x2 = n=3D1 BFMLAL_n1 11000001 001 0 .... 0 .. 010 ..... 100 .. @azz_nx1_o2x2 = n=3D2 @@ -477,11 +477,11 @@ SUB_azz_nn_d 11000001 111 ...01 0 .. 110 ...00 11 = ... @azz_4x4_o3 @azz_4x4_o2x2 ........ ... ..... . .. ... ..... ... .. \ &azz_n n=3D4 rv=3D%mova_rv zn=3D%zn_ax4 zm=3D%zm_ax4 off= =3D%off2_x2 =20 -FMLAL_nn 11000001 101 ....0 0 .. 010 ....0 000 .. @azz_2x2_o2x2 -FMLAL_nn 11000001 101 ...01 0 .. 010 ...00 000 .. @azz_4x4_o2x2 +FMLAL_nn_sh 11000001 101 ....0 0 .. 010 ....0 000 .. @azz_2x2_o2x2 +FMLAL_nn_sh 11000001 101 ...01 0 .. 010 ...00 000 .. @azz_4x4_o2x2 =20 -FMLSL_nn 11000001 101 ....0 0 .. 010 ....0 010 .. @azz_2x2_o2x2 -FMLSL_nn 11000001 101 ...01 0 .. 010 ...00 010 .. @azz_4x4_o2x2 +FMLSL_nn_sh 11000001 101 ....0 0 .. 010 ....0 010 .. @azz_2x2_o2x2 +FMLSL_nn_sh 11000001 101 ...01 0 .. 010 ...00 010 .. @azz_4x4_o2x2 =20 BFMLAL_nn 11000001 101 ....0 0 .. 010 ....0 100 .. @azz_2x2_o2x2 BFMLAL_nn 11000001 101 ...01 0 .. 010 ...00 100 .. @azz_4x4_o2x2 @@ -617,13 +617,13 @@ BFSUB_nn 11000001 111 00101 0 .. 111 ...00 01 = ... @az_4x4_o3 @azx_4x1_o2x2 ........ .... zm:4 . .. . .. ..... .. ... \ &azx_n n=3D4 rv=3D%mova_rv off=3D%off2_x2 zn=3D%zn_ax4 idx= =3D%idx2_10_2 =20 -FMLAL_nx 11000001 1000 .... . .. 1 .. ..... 00 ... @azx_1x1_o3x2 -FMLAL_nx 11000001 1001 .... 0 .. 1 .. ....0 00 ... @azx_2x1_o2x2 -FMLAL_nx 11000001 1001 .... 1 .. 1 .. ...00 00 ... @azx_4x1_o2x2 +FMLAL_nx_sh 11000001 1000 .... . .. 1 .. ..... 00 ... @azx_1x1_o3x2 +FMLAL_nx_sh 11000001 1001 .... 0 .. 1 .. ....0 00 ... @azx_2x1_o2x2 +FMLAL_nx_sh 11000001 1001 .... 1 .. 1 .. ...00 00 ... @azx_4x1_o2x2 =20 -FMLSL_nx 11000001 1000 .... . .. 1 .. ..... 01 ... @azx_1x1_o3x2 -FMLSL_nx 11000001 1001 .... 0 .. 1 .. ....0 01 ... @azx_2x1_o2x2 -FMLSL_nx 11000001 1001 .... 1 .. 1 .. ...00 01 ... @azx_4x1_o2x2 +FMLSL_nx_sh 11000001 1000 .... . .. 1 .. ..... 01 ... @azx_1x1_o3x2 +FMLSL_nx_sh 11000001 1001 .... 0 .. 1 .. ....0 01 ... @azx_2x1_o2x2 +FMLSL_nx_sh 11000001 1001 .... 1 .. 1 .. ...00 01 ... @azx_4x1_o2x2 =20 BFMLAL_nx 11000001 1000 .... . .. 1 .. ..... 10 ... @azx_1x1_o3x2 BFMLAL_nx 11000001 1001 .... 0 .. 1 .. ....0 10 ... @azx_2x1_o2x2 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index b8dde80c20..7aa270d3ec 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1107,10 +1107,10 @@ static bool do_fmlal(DisasContext *s, arg_azz_n *a,= bool sub, bool multi) multi, FPST_ENV, gen_helper_sve2_fmlal_zzzw_s); } =20 -TRANS_FEAT(FMLAL_n1, aa64_sme2, do_fmlal, a, false, false) -TRANS_FEAT(FMLSL_n1, aa64_sme2, do_fmlal, a, true, false) -TRANS_FEAT(FMLAL_nn, aa64_sme2, do_fmlal, a, false, true) -TRANS_FEAT(FMLSL_nn, aa64_sme2, do_fmlal, a, true, true) +TRANS_FEAT(FMLAL_n1_sh, aa64_sme2, do_fmlal, a, false, false) +TRANS_FEAT(FMLSL_n1_sh, aa64_sme2, do_fmlal, a, true, false) +TRANS_FEAT(FMLAL_nn_sh, aa64_sme2, do_fmlal, a, false, true) +TRANS_FEAT(FMLSL_nn_sh, aa64_sme2, do_fmlal, a, true, true) =20 static bool do_fmlall_fp8(DisasContext *s, arg_azz_n *a, bool multi) { @@ -1128,8 +1128,8 @@ static bool do_fmlal_nx(DisasContext *s, arg_azx_n *a= , bool sub) false, FPST_ENV, gen_helper_sve2_fmlal_zzxw_s); } =20 -TRANS_FEAT(FMLAL_nx, aa64_sme2, do_fmlal_nx, a, false) -TRANS_FEAT(FMLSL_nx, aa64_sme2, do_fmlal_nx, a, true) +TRANS_FEAT(FMLAL_nx_sh, aa64_sme2, do_fmlal_nx, a, false) +TRANS_FEAT(FMLSL_nx_sh, aa64_sme2, do_fmlal_nx, a, true) =20 static bool do_bfmlal(DisasContext *s, arg_azz_n *a, bool sub, bool multi) { --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jun 2026 05:01:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/54] target/arm: Implement FMLAL (multiple, multiple and single, FP8 to FP16) Date: Mon, 29 Jun 2026 13:00:24 +0100 Message-ID: <20260629120032.1645265-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734860058158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260625015159.719300-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 7 +++++++ target/arm/tcg/translate-sme.c | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 90ee161461..b735f3de82 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -452,6 +452,10 @@ FMLALL_n1_b 11000001 001 1 .... 0 .. 000 ..... 000= 1 . @azz_nx1_o1x4 n=3D4 FDOT_n1_sb 11000001 001 0 .... 0 .. 100 ..... 11 ... @azz_nx1_o3 n= =3D2 FDOT_n1_sb 11000001 001 1 .... 0 .. 100 ..... 11 ... @azz_nx1_o3 n= =3D4 =20 +FMLAL_n1_hb 11000001 001 1 .... 0 .. 011 ..... 00 ... @azz_nx1_o3x2 = n=3D1 +FMLAL_n1_hb 11000001 001 0 .... 0 .. 010 ..... 001 .. @azz_nx1_o2x2 = n=3D2 +FMLAL_n1_hb 11000001 001 1 .... 0 .. 010 ..... 001 .. @azz_nx1_o2x2 = n=3D4 + ### SME2 Multi-vector Multiple Array Vectors =20 %zn_ax2 6:4 !function=3Dtimes_2 @@ -578,6 +582,9 @@ FMLALL_nn_b 11000001 101 ...01 0 .. 000 ...01 0000 = . @azz_4x4_o1x4 FDOT_nn_sb 11000001 101 ....0 0 .. 100 ....1 10 ... @azz_2x2_o3 FDOT_nn_sb 11000001 101 ...01 0 .. 100 ...01 10 ... @azz_4x4_o3 =20 +FMLAL_nn_hb 11000001 101 ....0 0 .. 010 ....1 000 .. @azz_2x2_o2x2 +FMLAL_nn_hb 11000001 101 ...01 0 .. 010 ...01 000 .. @azz_4x4_o2x2 + &az_n n off rv zm @az_2x2_o3 ........ ... ..... . .. ... ..... .. off:3 \ &az_n n=3D2 rv=3D%mova_rv zm=3D%zn_ax2 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 7aa270d3ec..7cb7b71e74 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1121,6 +1121,15 @@ static bool do_fmlall_fp8(DisasContext *s, arg_azz_n= *a, bool multi) TRANS_FEAT(FMLALL_n1_b, aa64_sme_f8f32, do_fmlall_fp8, a, false) TRANS_FEAT(FMLALL_nn_b, aa64_sme_f8f32, do_fmlall_fp8, a, true) =20 +static bool do_fmlal_fp8(DisasContext *s, arg_azz_n *a, bool multi) +{ + return do_azz_acc_fp8(s, a->n, 2, a->rv, a->off, a->zn, a->zm, + 0, 0, multi, gen_helper_gvec_fmla_hb); +} + +TRANS_FEAT(FMLAL_n1_hb, aa64_sme_f8f16, do_fmlal_fp8, a, false) +TRANS_FEAT(FMLAL_nn_hb, aa64_sme_f8f16, do_fmlal_fp8, a, true) + static bool do_fmlal_nx(DisasContext *s, arg_azx_n *a, bool sub) { return do_azz_acc_fp(s, a->n, 2, a->rv, a->off, a->zn, a->zm, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735202; cv=none; d=zohomail.com; s=zohoarc; b=PhF+vc9OI4jmdRB4n3+CtoUZWdj4R+qKnjRKnpi2qn3JhZqFTQ6HSr4dWSUOySdNyZ1xnmxGW8iFoArdOTODTxT7aZtEYdcyDOZpQ+aCVURmCoso1GLuKQRonnGJQKwfxHPt4Ggeq+bsxKe7Aej3p6/tYnTuBuKOzd8HLf8E5WI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735202; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Mon, 29 Jun 2026 05:01:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 47/54] target/arm: Implement FMLAL (multiple and indexed, FP8 to FP16) Date: Mon, 29 Jun 2026 13:00:25 +0100 Message-ID: <20260629120032.1645265-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735204389158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260625015159.719300-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 13 +++++++++++++ target/arm/tcg/translate-sme.c | 4 ++++ 2 files changed, 17 insertions(+) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index b735f3de82..c6e22c4999 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -791,6 +791,19 @@ FMLALL_nx_b 11000001 0001 .... 1 .. 0.. ...10 00..= . @azx_4x1_i4_o1 FDOT_nx_b 11000001 0101 .... 0 .. 0.. ....1 11 ... @azx_2x1_i2_o3 FDOT_nx_b 11000001 0101 .... 1 .. 0.. ...00 01 ... @azx_4x1_i2_o3 =20 +%idx4_15_10_3 15:1 10:2 3:1 +%idx4_10_2 10:2 2:2 +@azx_1x1_i4_o3x2 ........ .... zm:4 . .. . .. zn:5 .. ... \ + &azx_n n=3D1 rv=3D%mova_rv off=3D%off3_x2 idx=3D%idx4_15_= 10_3 +@azx_2x2_i4_o3x2 ........ .... zm:4 . .. . .. .... .. .. .. \ + &azx_n n=3D2 rv=3D%mova_rv zn=3D%zn_ax2 off=3D%off2_x2 id= x=3D%idx4_10_2 +@azx_4x4_i4_o3x2 ........ .... zm:4 . .. . .. ... ... .. .. \ + &azx_n n=3D4 rv=3D%mova_rv zn=3D%zn_ax4 off=3D%off2_x2 id= x=3D%idx4_10_2 + +FMLAL_nx_hb 11000001 1100 .... . .. 0.. ..... 0. ... @azx_1x1_i4_o3= x2 +FMLAL_nx_hb 11000001 1001 .... 0 .. 1.. ....1 1.. .. @azx_2x2_i4_o3= x2 +FMLAL_nx_hb 11000001 1001 .... 1 .. 1.. ...01 0.. .. @azx_4x4_i4_o3= x2 + %idx2_10_3 10:1 3:1 @azx_4x2_i2_o3 ........ .... zm:4 . .. ... .... ... off:3 \ &azx_n n=3D4 rv=3D%mova_rv zn=3D%zn_ax2 idx=3D%idx2_10_3 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 7cb7b71e74..98f6eb0b70 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1140,6 +1140,10 @@ static bool do_fmlal_nx(DisasContext *s, arg_azx_n *= a, bool sub) TRANS_FEAT(FMLAL_nx_sh, aa64_sme2, do_fmlal_nx, a, false) TRANS_FEAT(FMLSL_nx_sh, aa64_sme2, do_fmlal_nx, a, true) =20 +TRANS_FEAT(FMLAL_nx_hb, aa64_sme_f8f16, do_azz_acc_fp8, + a->n, 2, a->rv, a->off, a->zn, a->zm, + a->idx << 2, 0, false, gen_helper_gvec_fmla_idx_hb) + static bool do_bfmlal(DisasContext *s, arg_azz_n *a, bool sub, bool multi) { return do_azz_acc_fp(s, a->n, 2, a->rv, a->off, a->zn, a->zm, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jun 2026 05:01:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 48/54] target/arm: Implement FDOT (multiple, multiple and single, FP8 to FP16) Date: Mon, 29 Jun 2026 13:00:26 +0100 Message-ID: <20260629120032.1645265-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734649993158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20260625015159.719300-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 6 ++++++ target/arm/tcg/translate-sme.c | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index c6e22c4999..fbf5f3720d 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -456,6 +456,9 @@ FMLAL_n1_hb 11000001 001 1 .... 0 .. 011 ..... 00 .= .. @azz_nx1_o3x2 n=3D1 FMLAL_n1_hb 11000001 001 0 .... 0 .. 010 ..... 001 .. @azz_nx1_o2x2 = n=3D2 FMLAL_n1_hb 11000001 001 1 .... 0 .. 010 ..... 001 .. @azz_nx1_o2x2 = n=3D4 =20 +FDOT_n1_hb 11000001 001 0 .... 0 .. 100 ..... 01 ... @azz_nx1_o3 n= =3D2 +FDOT_n1_hb 11000001 001 1 .... 0 .. 100 ..... 01 ... @azz_nx1_o3 n= =3D4 + ### SME2 Multi-vector Multiple Array Vectors =20 %zn_ax2 6:4 !function=3Dtimes_2 @@ -585,6 +588,9 @@ FDOT_nn_sb 11000001 101 ...01 0 .. 100 ...01 10 ..= . @azz_4x4_o3 FMLAL_nn_hb 11000001 101 ....0 0 .. 010 ....1 000 .. @azz_2x2_o2x2 FMLAL_nn_hb 11000001 101 ...01 0 .. 010 ...01 000 .. @azz_4x4_o2x2 =20 +FDOT_nn_hb 11000001 101 ....0 0 .. 100 ....1 00 ... @azz_2x2_o3 +FDOT_nn_hb 11000001 101 ...01 0 .. 100 ...01 00 ... @azz_4x4_o3 + &az_n n off rv zm @az_2x2_o3 ........ ... ..... . .. ... ..... .. off:3 \ &az_n n=3D2 rv=3D%mova_rv zm=3D%zn_ax2 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 98f6eb0b70..3174b10c30 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1196,6 +1196,15 @@ static bool do_fdot_fp8(DisasContext *s, arg_azz_n *= a, bool multi) TRANS_FEAT(FDOT_n1_sb, aa64_sme_f8f32, do_fdot_fp8, a, false) TRANS_FEAT(FDOT_nn_sb, aa64_sme_f8f32, do_fdot_fp8, a, true) =20 +static bool do_fdot_hb(DisasContext *s, arg_azz_n *a, bool multi) +{ + return do_azz_acc_fp8(s, a->n, 1, a->rv, a->off, a->zn, a->zm, + 0, 0, multi, gen_helper_gvec_fdot_hb); +} + +TRANS_FEAT(FDOT_n1_hb, aa64_sme_f8f16, do_fdot_hb, a, false) +TRANS_FEAT(FDOT_nn_hb, aa64_sme_f8f16, do_fdot_hb, a, true) + static bool do_fdot_nx(DisasContext *s, arg_azx_n *a) { return do_azz_acc_fp(s, a->n, 1, a->rv, a->off, a->zn, a->zm, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735118; cv=none; d=zohomail.com; s=zohoarc; b=J3MZhJg9qAbpzQuantgWmdxwi6wMMvzhnXN4bN1HJpoBF8rudfxXYf07f/TWFMB5htFEq84DDnbyQjnEW3TTIjjwXjt89Tgh5mtDLrAQNcs/hafGlUjTBKWoeJVGTF7k9mHjAmTkKOTP4ytBtDlMxByCRxWlRuilEfXQg9yqLA8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735118; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Mon, 29 Jun 2026 05:01:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 49/54] target/arm: Implement FDOT (multiple and indexed, FP8 to FP16) Date: Mon, 29 Jun 2026 13:00:27 +0100 Message-ID: <20260629120032.1645265-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735119895158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell [PMM: fixed subject line] Message-id: 20260625015159.719300-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 3 +++ target/arm/tcg/translate-sme.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index fbf5f3720d..1dd3b7c8b2 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -810,6 +810,9 @@ FMLAL_nx_hb 11000001 1100 .... . .. 0.. ..... 0. ..= . @azx_1x1_i4_o3x2 FMLAL_nx_hb 11000001 1001 .... 0 .. 1.. ....1 1.. .. @azx_2x2_i4_o3= x2 FMLAL_nx_hb 11000001 1001 .... 1 .. 1.. ...01 0.. .. @azx_4x4_i4_o3= x2 =20 +FDOT_nx_hb 11000001 1101 .... 0 .. 0.. ....1 0. ... @azx_2x1_i3_o3 +FDOT_nx_hb 11000001 0001 .... 1 .. 1.. ...10 0. ... @azx_4x1_i3_o3 + %idx2_10_3 10:1 3:1 @azx_4x2_i2_o3 ........ .... zm:4 . .. ... .... ... off:3 \ &azx_n n=3D4 rv=3D%mova_rv zn=3D%zn_ax2 idx=3D%idx2_10_3 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 3174b10c30..197274d00e 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1178,6 +1178,10 @@ TRANS_FEAT(FDOT_nx_b, aa64_sme_f8f32, do_azz_acc_fp8, a->n, 1, a->rv, a->off, a->zn, a->zm, a->idx, 0, false, gen_helper_gvec_fdot_idx_sb) =20 +TRANS_FEAT(FDOT_nx_hb, aa64_sme_f8f16, do_azz_acc_fp8, + a->n, 1, a->rv, a->off, a->zn, a->zm, + a->idx, 0, false, gen_helper_gvec_fdot_idx_hb) + static bool do_fdot(DisasContext *s, arg_azz_n *a, bool multi) { return do_azz_acc_fp(s, a->n, 1, a->rv, a->off, a->zn, a->zm, 1, 0, --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jun 2026 05:01:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/54] target/arm: Implement FMOPA (widening, 2-way, FP8 to FP16) Date: Mon, 29 Jun 2026 13:00:28 +0100 Message-ID: <20260629120032.1645265-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782734607532158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260625015159.719300-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/fp8_helper.c | 35 ++++++++++++++++++++++++++++++++ target/arm/tcg/helper-fp8-defs.h | 1 + target/arm/tcg/sme.decode | 1 + target/arm/tcg/translate-sme.c | 24 +++++++++++++--------- 4 files changed, 51 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c index 3c2d959099..5606f0fd8e 100644 --- a/target/arm/tcg/fp8_helper.c +++ b/target/arm/tcg/fp8_helper.c @@ -893,6 +893,41 @@ void HELPER(sme_fmopa_sb)(void *vza, void *vzn, void *= vzm, void *vpn, } } =20 +void HELPER(sme_fmopa_hb)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, CPUARMState *env, uint32_t desc) +{ + FP8MulContext ctx =3D fp8_mul_start(env, 0xf); + intptr_t oprsz =3D simd_maxsz(desc); + uint16_t *pn =3D vpn, *pm =3D vpm; + + for (intptr_t row =3D 0; row < oprsz; ) { + uint16_t prow =3D pn[H2(row >> 4)]; + do { + void *vza_row =3D vza + tile_vslice_offset(row); + uint16_t n =3D *(uint16_t *)(vzn + H1_2(row)); + + n &=3D expand_pred_b(prow & 3); + + for (intptr_t col =3D 0; col < oprsz; ) { + uint16_t pcol =3D pm[H2(col >> 4)]; + do { + if (prow & pcol & 0x3) { + uint16_t *a =3D vza_row + H1_2(col); + uint16_t m =3D *(uint16_t *)(vzm + H1_2(col)); + + m &=3D expand_pred_b(pcol & 3); + *a =3D f8dotadd_h(n, m, 2, *a, &ctx); + } + col +=3D 2; + pcol >>=3D 2; + } while (col & 15); + } + row +=3D 2; + prow >>=3D 2; + } while (row & 15); + } +} + void HELPER(sme_fvdot_idx_sb)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) { diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-d= efs.h index ef1375fea7..05bf8dbdc2 100644 --- a/target/arm/tcg/helper-fp8-defs.h +++ b/target/arm/tcg/helper-fp8-defs.h @@ -40,5 +40,6 @@ DEF_HELPER_FLAGS_5(gvec_fmmla_sb, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, env, i32 DEF_HELPER_FLAGS_5(gvec_fmmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, en= v, i32) =20 DEF_HELPER_FLAGS_7(sme_fmopa_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , ptr, env, i32) +DEF_HELPER_FLAGS_7(sme_fmopa_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , ptr, env, i32) =20 DEF_HELPER_FLAGS_5(sme_fvdot_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,= env, i32) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 1dd3b7c8b2..755d5f00d0 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -199,6 +199,7 @@ BFMOPA_w 10000001 100 ..... ... ... ..... . 00 .= . @op_32 FMOPA_w_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 =20 FMOPA_sb 10000000 101 zm:5 pm:3 pn:3 zn:5 0 00 zad:2 &op sub=3D0 +FMOPA_hb 10000000 101 zm:5 pm:3 pn:3 zn:5 0100 zad:1 &op sub=3D0 =20 SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32 SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 197274d00e..7eeac28480 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -616,25 +616,29 @@ TRANS_FEAT(BFMOPA_w, aa64_sme, do_outprod_env, a, MO_= 32, : !s->fpcr_ah ? gen_helper_sme_bfmops_w : gen_helper_sme_ah_bfmops_w) =20 -static bool trans_FMOPA_sb(DisasContext *s, arg_op *a) +static bool do_outprod_fp8(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5_ptr *fn) { - if (!dc_isar_feature(aa64_sme_f8f32, s)) { - return false; - } if (fpmr_access_check(s) && sme_smza_enabled_check(s)) { int svl =3D streaming_vec_reg_size(s); uint32_t desc =3D simd_desc(svl, svl, 0); =20 - gen_helper_sme_fmopa_sb(get_tile(s, MO_32, a->zad), - vec_full_reg_ptr(s, a->zn), - vec_full_reg_ptr(s, a->zm), - pred_full_reg_ptr(s, a->pn), - pred_full_reg_ptr(s, a->pm), - tcg_env, tcg_constant_i32(desc)); + TCGv_ptr za =3D get_tile(s, esz, a->zad); + TCGv_ptr zn =3D vec_full_reg_ptr(s, a->zn); + TCGv_ptr zm =3D vec_full_reg_ptr(s, a->zm); + TCGv_ptr pn =3D pred_full_reg_ptr(s, a->pn); + TCGv_ptr pm =3D pred_full_reg_ptr(s, a->pm); + + fn(za, zn, zm, pn, pm, tcg_env, tcg_constant_i32(desc)); } return true; } =20 +TRANS_FEAT(FMOPA_sb, aa64_sme_f8f32, do_outprod_fp8, + a, MO_32, gen_helper_sme_fmopa_sb) +TRANS_FEAT(FMOPA_hb, aa64_sme_f8f16, do_outprod_fp8, + a, MO_16, gen_helper_sme_fmopa_hb) + TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s) TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s) TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa= _s) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260625015159.719300-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 2 +- target/arm/tcg/translate-sme.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 755d5f00d0..160cf130d4 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -662,7 +662,7 @@ FDOT_nx 11000001 0101 .... 1 .. 1 .. ...00 01 .= .. @azx_4x1_i2_o3 BFDOT_nx 11000001 0101 .... 0 .. 1 .. ....0 11 ... @azx_2x1_i2_o3 BFDOT_nx 11000001 0101 .... 1 .. 1 .. ...00 11 ... @azx_4x1_i2_o3 =20 -FVDOT 11000001 0101 .... 0 .. 0 .. ....0 01 ... @azx_2x1_i2_o3 +FVDOT_sh 11000001 0101 .... 0 .. 0 .. ....0 01 ... @azx_2x1_i2_o3 BFVDOT 11000001 0101 .... 0 .. 0 .. ....0 11 ... @azx_2x1_i2_o3 =20 SDOT_nx_2h 11000001 0101 .... 0 .. 1 .. ....0 00 ... @azx_2x1_i2_o3 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 7eeac28480..267a6b0d9b 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1260,7 +1260,7 @@ static bool do_vdot(DisasContext *s, arg_azx_n *a, ge= n_helper_gvec_4_ptr *fn) return true; } =20 -TRANS_FEAT(FVDOT, aa64_sme, do_vdot, a, gen_helper_sme2_fvdot_idx_h) +TRANS_FEAT(FVDOT_sh, aa64_sme, do_vdot, a, gen_helper_sme2_fvdot_idx_h) TRANS_FEAT(BFVDOT, aa64_sme, do_vdot, a, gen_helper_sme2_bfvdot_idx) =20 static bool do_fvdot_sb(DisasContext *s, arg_azx_n *a, bool top) --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1782735240; cv=none; d=zohomail.com; s=zohoarc; b=lDO3mLefpyVjRcpqEBNenK7rVAfQ16Pt0cTItDTTueAMmV0gdm3G5kAOhT6m0zhVWT85aYYmBeo0a61BU4hk+Vt3fpq+9/niWlr/Q96YSdApdmW2/3P9lK1uVqZOUJ4Nt7J1iGStz/1FxPMe4CP2XeGhSDg0LCiWPWBMyFbreQw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1782735240; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=TAfHLqwt5iHzf6/peRCXoSNhAQXJDY0rvTyHjXtfmmc=; b=irWpxufvyLRQ981u+7pw2P2dIX7FaD5SD2RjPJ9IOdQTKLZ+7E0oT67sXC3Pwqi9YmgnBjf9HoiCS5yKLlfHkRDBLxwARYVpkUvkN9yu9kjiGBM0qKaIkdea02HIrgmesgzMM4pLLR4/WKy9kefrDZQwaFQpuGvxRjMIcFpWaG0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1782735240212202.96743848474716; Mon, 29 Jun 2026 05:14:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1weAgI-0007MK-3a; Mon, 29 Jun 2026 08:01:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1weAg8-00075c-34 for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:32 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1weAg6-0007fd-9n for qemu-devel@nongnu.org; Mon, 29 Jun 2026 08:01:31 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-4745492ed3aso411174f8f.1 for ; Mon, 29 Jun 2026 05:01:29 -0700 (PDT) Received: from lanath.. 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Mon, 29 Jun 2026 05:01:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 52/54] target/arm: Implement FVDOT (FP8 to FP16) Date: Mon, 29 Jun 2026 13:00:30 +0100 Message-ID: <20260629120032.1645265-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735240903158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson [PMM: fix wrong sizeof(type) for fp16 output] Reviewed-by: Peter Maydell Message-id: 20260625015159.719300-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/fp8_helper.c | 23 +++++++++++++++++++++++ target/arm/tcg/helper-fp8-defs.h | 1 + target/arm/tcg/sme.decode | 2 ++ target/arm/tcg/translate-sme.c | 4 ++++ 4 files changed, 30 insertions(+) diff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c index 5606f0fd8e..902e4b0ae9 100644 --- a/target/arm/tcg/fp8_helper.c +++ b/target/arm/tcg/fp8_helper.c @@ -950,3 +950,26 @@ void HELPER(sme_fvdot_idx_sb)(void *vd, void *vn, void= *vm, } while (++i & 3); } while (i < elements); } + +void HELPER(sme_fvdot_idx_hb)(void *vd, void *vn, void *vm, + CPUARMState *env, uint32_t desc) +{ + FP8MulContext ctx =3D fp8_mul_start(env, 0xf); + intptr_t oprsz =3D simd_maxsz(desc); + intptr_t elements =3D oprsz / sizeof(float16); + int idx_n =3D extract32(desc, SIMD_DATA_SHIFT, 1); + int idx_m =3D extract32(desc, SIMD_DATA_SHIFT + 1, 3); + float16 *d =3D vd; + uint8_t *n0 =3D vn; + uint8_t *n1 =3D vn + sizeof(ARMVectorReg); + uint16_t *m =3D vm; + intptr_t i =3D 0; + + do { + uint16_t mm =3D m[H2(2 * i + idx_m)]; + do { + uint16_t nn =3D n0[H1(4 * i + idx_n)] | (n1[H1(4 * i + idx_n)]= << 8); + d[H2(i)] =3D f8dotadd_h(nn, mm, 2, d[H2(i)], &ctx); + } while (++i & 7); + } while (i < elements); +} diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-d= efs.h index 05bf8dbdc2..126dcadf77 100644 --- a/target/arm/tcg/helper-fp8-defs.h +++ b/target/arm/tcg/helper-fp8-defs.h @@ -43,3 +43,4 @@ DEF_HELPER_FLAGS_7(sme_fmopa_sb, TCG_CALL_NO_RWG, void, p= tr, ptr, ptr, ptr, ptr, DEF_HELPER_FLAGS_7(sme_fmopa_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , ptr, env, i32) =20 DEF_HELPER_FLAGS_5(sme_fvdot_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,= env, i32) +DEF_HELPER_FLAGS_5(sme_fvdot_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,= env, i32) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 160cf130d4..3a65e1ad4b 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -821,6 +821,8 @@ FDOT_nx_hb 11000001 0001 .... 1 .. 1.. ...10 0. ..= . @azx_4x1_i3_o3 FVDOTB_sb 11000001 1101 .... 0 .. 01. ....0 0. ... @azx_4x2_i2_o3 FVDOTT_sb 11000001 1101 .... 0 .. 01. ....0 1. ... @azx_4x2_i2_o3 =20 +FVDOT_hb 11000001 1101 .... 0 .. 1.. ....1 0. ... @azx_2x1_i3_o3 + ### SME2 Add / Sub array accumulators =20 ADD_aaz_s 11000001 101 000000 .. 111 ....0 10 ... @az_2x2_o3 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 267a6b0d9b..ff5554eefb 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1273,6 +1273,10 @@ static bool do_fvdot_sb(DisasContext *s, arg_azx_n *= a, bool top) TRANS_FEAT(FVDOTB_sb, aa64_sme_f8f32, do_fvdot_sb, a, false) TRANS_FEAT(FVDOTT_sb, aa64_sme_f8f32, do_fvdot_sb, a, true) =20 +TRANS_FEAT(FVDOT_hb, aa64_sme_f8f16, do_azz_acc_fp8, + a->n, 2, a->rv, a->off, a->zn, a->zm, + (a->idx << 1), 0, false, gen_helper_sme_fvdot_idx_hb) + static bool do_fmla(DisasContext *s, arg_azz_n *a, bool multi, ARMFPStatusFlavour fpst, gen_helper_gvec_3_ptr *fn) { --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 29 Jun 2026 05:01:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 53/54] target/arm: Enable FEAT_SME_F8F16 for -cpu max Date: Mon, 29 Jun 2026 13:00:31 +0100 Message-ID: <20260629120032.1645265-54-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260629120032.1645265-1-peter.maydell@linaro.org> References: <20260629120032.1645265-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1782735124205158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260625015159.719300-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + linux-user/aarch64/elfload.c | 1 + target/arm/tcg/cpu64.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 6b02bd829a..191d1a8c93 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -170,6 +170,7 @@ the following architecture extensions: - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) - FEAT_SME_F16F16 (Non-widening half-precision FP16 arithmetic for SME2) - FEAT_SME_F64F64 (Double-precision floating-point outer product instructi= ons) +- FEAT_SME_F8F16 (SME2 ZA-targeting FP8 multiply-accumulate, dot product, = and outer product to half-precision instructions) - FEAT_SME_F8F32 (SME2 ZA-targeting FP8 multiply-accumulate, dot product, = and outer product to single-precision instructions) - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instruc= tions) - FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit e= lements) diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 20b9838520..42aeb29306 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -236,6 +236,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs) GET_FEATURE_ID(aa64_ssve_f8dp4, ARM_HWCAP2_A64_SME_SF8DP4); GET_FEATURE_ID(aa64_ssve_f8dp2, ARM_HWCAP2_A64_SME_SF8DP2); GET_FEATURE_ID(aa64_sme_f8f32, ARM_HWCAP2_A64_SME_F8F32); + GET_FEATURE_ID(aa64_sme_f8f16, ARM_HWCAP2_A64_SME_F8F16); =20 return hwcaps; } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index a5734446dd..ae3952a1ed 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1393,6 +1393,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F32, 1); /* FEAT_SME_F8F32 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F8F16, 1); /* FEAT_SME_F8F16 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F16, 1); /* FEAT_SME_F16F16 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, B16B16, 1); /* FEAT_SME_B16B16 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I32, 5); /* FEAT_SME2 */ --=20 2.43.0 From nobody Sun Jul 26 11:51:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Signed-off-by: Shameer Kolothum Message-id: 20260623104003.36590-1-skolothumtho@nvidia.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index f811e662d6..ae0be35d57 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -288,6 +288,32 @@ User-creatable SMMUv3 devices -device pxb-pcie,id=3Dpcie.1,numa_node=3D1 -device arm-smmuv3,primary-bus=3Dpcie.1,id=3Dsmmuv3.1 =20 + *Accelerated SMMUv3 (nested translation)* + + The ``accel=3Don`` option enables hardware-accelerated nested translation + for vfio-pci passthrough devices. In this mode the guest SMMU driver + programs its own Stage-1 page tables, with the host SMMUv3 handling both + Stage-1 (guest) and Stage-2 (host) translations in hardware. The host + SMMUv3 must support nested translation. This mode requires the iommufd + backend and is only supported when booting with ACPI (not device tree). + + When ``accel=3Don``, QEMU automatically derives the values for the + ``ril``, ``ats``, ``oas``, ``ssidsize`` and ``cmdqv`` sub-options + from the host SMMUv3 capabilities unless they are set explicitly. + + Example:: + + -device arm-smmuv3,primary-bus=3Dpcie.0,id=3Dsmmuv3.0,accel=3Don + + *Accelerated SMMUv3 command queues (Tegra241 CMDQV)* + + The ``cmdqv`` sub-option enables NVIDIA Tegra241 Command Queue + Virtualization (CMDQV) on supported hosts. With CMDQV, each accelerated + ``arm-smmuv3`` device gets dedicated hardware command queues and the + guest issues SMMU invalidation commands directly to real hardware, + bypassing QEMU and improving throughput for workloads that issue many + invalidations. Without it, every invalidation command traps into QEMU. + Linux guest kernel configuration """""""""""""""""""""""""""""""" =20 --=20 2.43.0