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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1782421771786158500 Content-Type: text/plain; charset="utf-8" The existing nomenclature can be misleading: regs_rw can cosplay as 'read and write' mask, in particular because we have regs_ro which is a read only mask. regs_rw is the current reg value, and all bits that aren't on the regs_ro mask is considered r/w bits. Rename regs_rw to 'regs' to be on par with the nomenclature other devices uses (e.g. cadence_gem). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/riscv-iommu-hpm.c | 4 ++-- hw/riscv/riscv-iommu.c | 36 ++++++++++++++++++------------------ hw/riscv/riscv-iommu.h | 26 +++++++++++++++----------- 3 files changed, 35 insertions(+), 31 deletions(-) diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c index 5bf80a8db9..9bfef6db45 100644 --- a/hw/riscv/riscv-iommu-hpm.c +++ b/hw/riscv/riscv-iommu-hpm.c @@ -60,8 +60,8 @@ static void hpm_incr_ctr(RISCVIOMMUState *s, uint32_t ctr= _idx) const uint32_t off =3D ctr_idx << 3; uint64_t cntr_val; =20 - cntr_val =3D ldq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]= ); - stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + = 1); + cntr_val =3D ldq_le_p(&s->regs[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]); + stq_le_p(&s->regs[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1); =20 trace_riscv_iommu_hpm_incr_ctr(cntr_val); =20 diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index a500cb8440..30f16b999c 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2034,8 +2034,8 @@ static void riscv_iommu_process_cq_control(RISCVIOMMU= State *s) s->cq_mask =3D (2ULL << get_field(base, RISCV_IOMMU_CQB_LOG2SZ)) -= 1; s->cq_addr =3D PPN_PHYS(get_field(base, RISCV_IOMMU_CQB_PPN)); stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQT], ~s->cq_mask); - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_CQH], 0); - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_CQT], 0); + stl_le_p(&s->regs[RISCV_IOMMU_REG_CQH], 0); + stl_le_p(&s->regs[RISCV_IOMMU_REG_CQT], 0); ctrl_set =3D RISCV_IOMMU_CQCSR_CQON; ctrl_clr =3D RISCV_IOMMU_CQCSR_BUSY | RISCV_IOMMU_CQCSR_CQMF | RISCV_IOMMU_CQCSR_CMD_ILL | RISCV_IOMMU_CQCSR_CMD_TO | @@ -2075,8 +2075,8 @@ static void riscv_iommu_process_fq_control(RISCVIOMMU= State *s) s->fq_mask =3D (2ULL << get_field(base, RISCV_IOMMU_FQB_LOG2SZ)) -= 1; s->fq_addr =3D PPN_PHYS(get_field(base, RISCV_IOMMU_FQB_PPN)); stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_FQH], ~s->fq_mask); - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_FQH], 0); - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_FQT], 0); + stl_le_p(&s->regs[RISCV_IOMMU_REG_FQH], 0); + stl_le_p(&s->regs[RISCV_IOMMU_REG_FQT], 0); ctrl_set =3D RISCV_IOMMU_FQCSR_FQON; ctrl_clr =3D RISCV_IOMMU_FQCSR_BUSY | RISCV_IOMMU_FQCSR_FQMF | RISCV_IOMMU_FQCSR_FQOF; @@ -2105,8 +2105,8 @@ static void riscv_iommu_process_pq_control(RISCVIOMMU= State *s) s->pq_mask =3D (2ULL << get_field(base, RISCV_IOMMU_PQB_LOG2SZ)) -= 1; s->pq_addr =3D PPN_PHYS(get_field(base, RISCV_IOMMU_PQB_PPN)); stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_PQH], ~s->pq_mask); - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_PQH], 0); - stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_PQT], 0); + stl_le_p(&s->regs[RISCV_IOMMU_REG_PQH], 0); + stl_le_p(&s->regs[RISCV_IOMMU_REG_PQT], 0); ctrl_set =3D RISCV_IOMMU_PQCSR_PQON; ctrl_clr =3D RISCV_IOMMU_PQCSR_BUSY | RISCV_IOMMU_PQCSR_PQMF | RISCV_IOMMU_PQCSR_PQOF; @@ -2276,9 +2276,9 @@ static void riscv_iommu_write_reg_val(RISCVIOMMUState= *s, { uint64_t ro =3D ldn_le_p(&s->regs_ro[reg_addr], size); uint64_t wc =3D ldn_le_p(&s->regs_wc[reg_addr], size); - uint64_t rw =3D ldn_le_p(&s->regs_rw[reg_addr], size); + uint64_t curr_val =3D ldn_le_p(&s->regs[reg_addr], size); =20 - stn_le_p(dest, size, ((rw & ro) | (data & ~ro)) & ~(data & wc)); + stn_le_p(dest, size, ((curr_val & ro) | (data & ~ro)) & ~(data & wc)); } =20 static MemTxResult riscv_iommu_mmio_write(void *opaque, hwaddr addr, @@ -2378,12 +2378,12 @@ static MemTxResult riscv_iommu_mmio_write(void *opa= que, hwaddr addr, * is set IOMMU behavior of additional writes to the register * is UNSPECIFIED. */ - riscv_iommu_write_reg_val(s, &s->regs_rw[addr], addr, size, data); + riscv_iommu_write_reg_val(s, &s->regs[addr], addr, size, data); =20 /* Busy flag update, MSB 4-byte register. */ if (busy) { - uint32_t rw =3D ldl_le_p(&s->regs_rw[regb]); - stl_le_p(&s->regs_rw[regb], rw | busy); + uint32_t rw =3D ldl_le_p(&s->regs[regb]); + stl_le_p(&s->regs[regb], rw | busy); } =20 /* Process HPM writes and update any internal state if needed. */ @@ -2428,13 +2428,13 @@ static MemTxResult riscv_iommu_mmio_read(void *opaq= ue, hwaddr addr, * it's not dependent over the timer callback and is computed * from cycle overflow. */ - val =3D ldq_le_p(&s->regs_rw[addr]); + val =3D ldq_le_p(&s->regs[addr]); val |=3D (riscv_iommu_hpmcycle_read(s) & RISCV_IOMMU_IOHPMCYCLES_O= VF) ? RISCV_IOMMU_IOCOUNTOVF_CY : 0; ptr =3D (uint8_t *)&val + (addr & 3); } else { - ptr =3D &s->regs_rw[addr]; + ptr =3D &s->regs[addr]; } =20 val =3D ldn_le_p(ptr, size); @@ -2529,7 +2529,7 @@ static void riscv_iommu_instance_init(Object *obj) s->cap |=3D RISCV_IOMMU_CAP_PD8; =20 /* register storage */ - s->regs_rw =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); + s->regs =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); s->regs_ro =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); s->regs_wc =3D g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); =20 @@ -2554,7 +2554,7 @@ static void riscv_iommu_instance_finalize(Object *obj) { RISCVIOMMUState *s =3D RISCV_IOMMU(obj); =20 - g_free(s->regs_rw); + g_free(s->regs); g_free(s->regs_ro); g_free(s->regs_wc); =20 @@ -2608,8 +2608,8 @@ static void riscv_iommu_realize(DeviceState *dev, Err= or **errp) "riscv-iommu-regs", RISCV_IOMMU_REG_SIZE); =20 /* Set power-on register state */ - stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_CAP], s->cap); - stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_FCTL], 0); + stq_le_p(&s->regs[RISCV_IOMMU_REG_CAP], s->cap); + stq_le_p(&s->regs[RISCV_IOMMU_REG_FCTL], 0); stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_FCTL], ~(RISCV_IOMMU_FCTL_BE | RISCV_IOMMU_FCTL_WSI)); stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_DDTP], @@ -2634,7 +2634,7 @@ static void riscv_iommu_realize(DeviceState *dev, Err= or **errp) RISCV_IOMMU_PQCSR_BUSY); stl_le_p(&s->regs_wc[RISCV_IOMMU_REG_IPSR], ~0); stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_ICVEC], 0); - stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_DDTP], s->ddtp); + stq_le_p(&s->regs[RISCV_IOMMU_REG_DDTP], s->ddtp); /* If debug registers enabled. */ if (s->cap & RISCV_IOMMU_CAP_DBG) { stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_TR_REQ_IOVA], 0); diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h index 2a9f6fccd5..a778e86fb7 100644 --- a/hw/riscv/riscv-iommu.h +++ b/hw/riscv/riscv-iommu.h @@ -76,9 +76,13 @@ struct RISCVIOMMUState { =20 /* MMIO Hardware Interface */ MemoryRegion regs_mr; - uint8_t *regs_rw; /* register state (user write) */ + uint8_t *regs; /* current register state */ uint8_t *regs_wc; /* write-1-to-clear mask */ - uint8_t *regs_ro; /* read-only mask */ + /* + * read-only mask. NOTE: bits not present in this RO + * mask are assumed to be read and write. + */ + uint8_t *regs_ro; =20 QLIST_ENTRY(RISCVIOMMUState) iommus; QLIST_HEAD(, RISCVIOMMUSpace) spaces; @@ -120,39 +124,39 @@ struct RISCVIOMMUContext { static inline uint32_t riscv_iommu_reg_mod32(RISCVIOMMUState *s, unsigned idx, uint32_t set, uint32_t clr) { - uint32_t val =3D ldl_le_p(s->regs_rw + idx); - stl_le_p(s->regs_rw + idx, (val & ~clr) | set); + uint32_t val =3D ldl_le_p(s->regs + idx); + stl_le_p(s->regs + idx, (val & ~clr) | set); return val; } =20 static inline void riscv_iommu_reg_set32(RISCVIOMMUState *s, unsigned idx, uint32_t set) { - stl_le_p(s->regs_rw + idx, set); + stl_le_p(s->regs + idx, set); } =20 static inline uint32_t riscv_iommu_reg_get32(RISCVIOMMUState *s, unsigned = idx) { - return ldl_le_p(s->regs_rw + idx); + return ldl_le_p(s->regs + idx); } =20 static inline uint64_t riscv_iommu_reg_mod64(RISCVIOMMUState *s, unsigned = idx, uint64_t set, uint64_t clr) { - uint64_t val =3D ldq_le_p(s->regs_rw + idx); - stq_le_p(s->regs_rw + idx, (val & ~clr) | set); + uint64_t val =3D ldq_le_p(s->regs + idx); + stq_le_p(s->regs + idx, (val & ~clr) | set); return val; } =20 static inline void riscv_iommu_reg_set64(RISCVIOMMUState *s, unsigned idx, uint64_t set) { - stq_le_p(s->regs_rw + idx, set); + stq_le_p(s->regs + idx, set); } =20 static inline uint64_t riscv_iommu_reg_get64(RISCVIOMMUState *s, - unsigned idx) + unsigned idx) { - return ldq_le_p(s->regs_rw + idx); + return ldq_le_p(s->regs + idx); } #endif --=20 2.43.0 From nobody Sun Jul 26 11:51:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1782421751; cv=none; d=zohomail.com; s=zohoarc; b=gYof/6UqdDur7q7OE2TM49kXHudZIKJRxR6F0QIX3t7x48ygiUklydWyXMXs9DlIyfLRdFgWxdJvBfeFHgnfPOMbjGkvJLmRB1Id2q0xPwar0T57y2+Wy7Cf1UxMQ87qRaIVgjap1CWySjiE+tss24AEYBmBeKEu5D+QEEkDvPY= ARC-Message-Signature: i=1; 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Thu, 25 Jun 2026 14:08:45 -0700 (PDT) X-Received: by 2002:a05:620a:4613:b0:915:6cfc:5018 with SMTP id af79cd13be357-9293d4bbd52mr629293785a.58.1782421725252; Thu, 25 Jun 2026 14:08:45 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, andrew.jones@oss.qualcomm.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH 2/2] hw/riscv/riscv-iommu.c: make FCTL.BE read only 0 Date: Thu, 25 Jun 2026 18:08:33 -0300 Message-ID: <20260625210833.3294437-3-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260625210833.3294437-1-daniel.barboza@oss.qualcomm.com> References: <20260625210833.3294437-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDE4MyBTYWx0ZWRfX2x814Dpe8pT1 AEDXrwLB1Ysjii25bW/rY2nKI/VAyRwarhs1iFy+bW4760jQl7HdhehhkWELab2lZX1VU6r0K5c i8P6fLl85pZZq4+zXa68IEtn5weJuR/8+MEsoWkM6qfesul3dV1ZDwUl5awACbibtydHPi0SNlx lHYwAAPMn/fQE056ZotkZjwlD4zzUtSclc/wUhthA4C8EX0VrZ7VzbpmM4devCRCTgobRBHk7N8 qXJMbGFUiEOla2EYRB/Fwm8Ge0iU1kpfopKtCVGUqGrnM0S81pHn5I7wxiuF7eoNry4z6jEvysa +Bmcy2GiVl+1CXxTc5b7fPclm2wlll+5yjWa6gnMuoI1DyPS8awaOdsiyqZwL1fqN8DOuB+iUVm 2jY4nV9JYMQv/kk/c84v/1rREr74w+Ol0DlEwdwCWHmUl4eOumYev9TTWPTYgQh0tNzVsiAFcaJ ZxzVrDlAVmgBLpcXksQ== X-Authority-Analysis: v=2.4 cv=aoyCzyZV c=1 sm=1 tr=0 ts=6a3d98de cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=sHJf4AwOIoU3qjeHFPlg6Q==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=p0WdMEafAAAA:8 a=EUspDBNiAAAA:8 a=y0Gly9JQx-F5jikTsYcA:9 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-ORIG-GUID: wVZKrHYSYXKg6ISlLMB8Mdl-HD76T6FU X-Proofpoint-GUID: wVZKrHYSYXKg6ISlLMB8Mdl-HD76T6FU X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDE4MyBTYWx0ZWRfX3s6yQrNf5PsI BHS4BhvgendsKLrlnBBJ+dBOVTaktgPOhrApY2vW4g5+iHSnWJTcdwaBwlejO66Z47RGqGzwUt6 LrCFw/YVMNYnGUx5wkwoVQxNQBi8RSI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_02,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 spamscore=0 priorityscore=1501 clxscore=1015 adultscore=0 malwarescore=0 phishscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1782421753738158500 Content-Type: text/plain; charset="utf-8" We do not support FCTL.BE equal to 1 hence do not allow this bit to be set by software. While we're at it: the riscv-iommu spec allows FCTL.GXL to be set freely and we do not have hardcoded restrictions on it, so make it writable. Fixes: 0c54acb824 ("hw/riscv: add RISC-V IOMMU base emulation") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3576 Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 30f16b999c..c9687e01a8 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2609,9 +2609,11 @@ static void riscv_iommu_realize(DeviceState *dev, Er= ror **errp) =20 /* Set power-on register state */ stq_le_p(&s->regs[RISCV_IOMMU_REG_CAP], s->cap); + stq_le_p(&s->regs[RISCV_IOMMU_REG_FCTL], 0); stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_FCTL], - ~(RISCV_IOMMU_FCTL_BE | RISCV_IOMMU_FCTL_WSI)); + ~(RISCV_IOMMU_FCTL_GXL | RISCV_IOMMU_FCTL_WSI)); + stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_DDTP], ~(RISCV_IOMMU_DDTP_PPN | RISCV_IOMMU_DDTP_MODE)); stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQB], --=20 2.43.0