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Wed, 24 Jun 2026 23:27:00 -0700 (PDT) From: Charlie Jenkins Date: Wed, 24 Jun 2026 23:26:58 -0700 Subject: [PATCH] target/riscv: Report QEMU CPU archid as 42 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260624-marchid-v1-1-a0af7997071f@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDMyMT3dzEouSMzBRdC4MUQ3OzJAtz4xQLJaDqgqLUtMwKsEnRsRB+cWl SVmpyCUi7Um0tABrpk5VrAAAA X-Change-ID: 20260624-marchid-80d176b873d8 To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Atish Patra , qemu-riscv@nongnu.org, Charlie Jenkins X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782368818; l=2894; i=thecharlesjenkins@gmail.com; s=20260605; h=from:subject:message-id; bh=i3lugvgwi4wk/h5CJjNv2v/O9jMvaAK6shErITKU7Lk=; b=RfzL0vuvstQgO+amSp4BL4Fia7lFf5SqiWBTSGxmDs1jLIdkmkqKiWSnPpZT6+4Q5BEyt012Q ELmvACAMwueC2ynddlhTMQR5laeoxUQ6kwZbXx2qrCcFGmCsn28q1vp X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=ajnnRQ98PIdwKp4HeMkq9U32okYbnh6Zb4G3o5XXvkg= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1333; envelope-from=thecharlesjenkins@gmail.com; helo=mail-dy1-x1333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 25 Jun 2026 08:09:07 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1782389396902158500 When a non-vendor CPU is used, report the archid as 42 which has been allocated for QEMU in the riscv isa manual [1]. This can help software check if it is running in QEMU. [1] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra --- This series was original proposed by Palmer Dabbelt [1] with a follow up by Daniel Henrique Barboza. This patch implement's Daniel's suggestion. When booting with a non-vendor CPU such as with the qemu arg "-cpu rv64" marchid will now be reported as 42. > qemu-system-riscv64 ... -cpu rv64 processor : 0 hart : 0 isa : rv64imafdch_zicbom_zicbop_zicboz_ziccrse_zicntr_zicsr_zif= encei_zihintntl_zihintpause_zihpm_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zb= c_zbs_sstc_svadu_svvptc mmu : sv57 mvendorid : 0x0 marchid : 0x2a mimpid : 0x0 hart isa : rv64imafdch_zicbom_zicbop_zicboz_ziccrse_zicntr_zicsr_zif= encei_zihintntl_zihintpause_zihpm_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zb= c_zbs_sstc_svadu_svvptc When booting with a vendor CPU like veyron-v1, the proper marchid will still appear. > qemu-system-riscv64 ... -cpu veyron-v1 processor : 0 hart : 0 isa : rv64imafdch_zicbom_zicboz_ziccrse_zicntr_zicsr_zifencei_z= ihpm_zaamo_zalrsc_zca_zcd_zba_zbb_zbc_zbs_smaia_smstateen_ssaia_sscofpmf_ss= tc_svinval_svnapot_svpbmt mmu : sv48 mvendorid : 0x61f marchid : 0x8000000000010000 mimpid : 0x111 hart isa : rv64imafdch_zicbom_zicboz_ziccrse_zicntr_zicsr_zifencei_z= ihpm_zaamo_zalrsc_zca_zcd_zba_zbb_zbc_zbs_smaia_smstateen_ssaia_sscofpmf_ss= tc_svinval_svnapot_svpbmt [1] https://lore.kernel.org/all/20240131182430.20174-1-palmer@rivosinc.com/ --- target/riscv/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fa497e5e8a..59d63f82c2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -44,6 +44,9 @@ #endif =20 /* RISC-V CPU definitions */ +#define RISCV_CPU_MVENDORID 0 +#define RISCV_CPU_MARCHID 42 +#define RISCV_CPU_MIMPID 0 static const char riscv_single_letter_exts[] =3D "IEMAFDQCBPVH"; const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, RVD, RVV, RVC, RVS, RVU, RVH, RVG, RVB, 0}; @@ -1198,6 +1201,12 @@ static void riscv_cpu_init(Object *obj) } #endif =20 + if (!riscv_cpu_is_vendor(obj)) { + RISCV_CPU(obj)->cfg.mvendorid =3D RISCV_CPU_MVENDORID; + RISCV_CPU(obj)->cfg.marchid =3D RISCV_CPU_MARCHID; + RISCV_CPU(obj)->cfg.mimpid =3D RISCV_CPU_MIMPID; + } + accel_cpu_instance_init(CPU(obj)); } =20 --- base-commit: b83371668192a705b878e909c5ae9c1233cbd5fb change-id: 20260624-marchid-80d176b873d8 Best regards, -- =20 - Charlie