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Mon, 22 Jun 2026 15:45:42 -0700 (PDT) From: stephensportia@gmail.com To: qemu-devel@nongnu.org Cc: Liu Zhiwei , Daniel Henrique Barboza , Chao Liu , Alistair Francis , Palmer Dabbelt , Weiwei Li , qemu-riscv@nongnu.org, Portia Stephens Subject: [PATCH] target/riscv: Generate illegal exception for inval.ir and w.inval in U-mode Date: Tue, 23 Jun 2026 08:45:34 +1000 Message-ID: <20260622224534.1923407-1-stephensportia@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=stephensportia@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 22 Jun 2026 20:24:12 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1782174305127158500 Content-Type: text/plain; charset="utf-8" From: Portia Stephens According to the priv spec "Attempting to execute SFENCE.W.INVAL or SFENCE.INVAL.IR in U-mode raises an illegal-instruction exception." Fix the current implementation to generate exception. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3543 Signed-off-by: Portia Stephens --- target/riscv/insn_trans/trans_svinval.c.inc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/ins= n_trans/trans_svinval.c.inc index a06c3b214f..10cb9e32b6 100644 --- a/target/riscv/insn_trans/trans_svinval.c.inc +++ b/target/riscv/insn_trans/trans_svinval.c.inc @@ -39,6 +39,12 @@ static bool trans_sfence_w_inval(DisasContext *ctx, arg_= sfence_w_inval *a) { REQUIRE_SVINVAL(ctx); REQUIRE_EXT(ctx, RVS); + if (ctx->priv =3D=3D PRV_U) { + /* Set the virtual exception if virt enabled */ + ctx->virt_inst_excp =3D ctx->virt_enabled; + gen_exception_illegal(ctx); + return false; + } /* Do nothing currently */ return true; } @@ -47,6 +53,12 @@ static bool trans_sfence_inval_ir(DisasContext *ctx, arg= _sfence_inval_ir *a) { REQUIRE_SVINVAL(ctx); REQUIRE_EXT(ctx, RVS); + if (ctx->priv =3D=3D PRV_U) { + /* Set the virtual exception if virt enabled */ + ctx->virt_inst_excp =3D ctx->virt_enabled; + gen_exception_illegal(ctx); + return false; + } /* Do nothing currently */ return true; } --=20 2.43.0