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Sat, 20 Jun 2026 20:25:30 -0700 (PDT) From: Andrey Polivoda To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson Subject: [PATCH] target/i386: decode opcode extensions group 3 /1 as TEST Date: Sun, 21 Jun 2026 13:25:23 +1000 Message-ID: <20260621032524.1138213-1-apolivodaa433@gmail.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=apolivodaa433@gmail.com; helo=mail-lj1-x22b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1782012386582154100 Content-Type: text/plain; charset="utf-8" According to Table A-6 in Volume 3 of AMD64 Architecture Programmer's Manua= l, opcodes F6 and F7 (opcode extensions group 3) with ModRM's reg field values of 0 and 1 can be used to encode a TEST instruction. Although Intel 64 and IA-32 Architectures Software Developer's Manual leaves the cell 1 of opcode extensions group 3 blank in the opcode table=20 (Table A-6, Volume 2D), the instruction in a group 3 with reg field of ModRM byte set to 1 actually behaves like TEST instruction on Intel CPUs. Currently, QEMU decodes group 3 instruction as TEST only if reg field of Mo= dRM byte is 0. When the reg field is 1, QEMU raises a #UD exception. This behavior does not match real Intel and AMD hardware. This patch fixes this issue by duplicating the existing [0x00] and [0x08] X86_OP_ENTRYrr(AND, ...) entries into slots [0x01] and [0x09] in the opcodes_grp3 table. Fixes: d7c41a60d0c5 ("target/i386: move C0-FF opcodes to new decoder (excep= t for x87)") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3580=20 Signed-off-by: Andrey Polivoda Cc: qemu-devel@nongnu.org Cc: Paolo Bonzini Cc: Richard Henderson Reviewed-by: Richard Henderson --- Note: checkpatch.pl reports style errors regarding spaces after commas. These are false positives, as the patch intentionally matches the formatting of the surrounding macro table. target/i386/tcg/decode-new.c.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index ac181308ca..a0bc6d1901 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1614,6 +1614,7 @@ static void decode_group3(DisasContext *s, CPUX86Stat= e *env, X86OpEntry *entry, static const X86OpEntry opcodes_grp3[16] =3D { /* 0xf6 */ [0x00] =3D X86_OP_ENTRYrr(AND, E,b, I,b), + [0x01] =3D X86_OP_ENTRYrr(AND, E,b, I,b), [0x02] =3D X86_OP_ENTRY1(NOT, E,b, lock), [0x03] =3D X86_OP_ENTRY1(NEG, E,b, lock), [0x04] =3D X86_OP_ENTRYrr(MUL, E,b, 0,b, zextT0), @@ -1623,6 +1624,7 @@ static void decode_group3(DisasContext *s, CPUX86Stat= e *env, X86OpEntry *entry, =20 /* 0xf7 */ [0x08] =3D X86_OP_ENTRYrr(AND, E,v, I,z), + [0x09] =3D X86_OP_ENTRYrr(AND, E,v, I,z), [0x0a] =3D X86_OP_ENTRY1(NOT, E,v, lock), [0x0b] =3D X86_OP_ENTRY1(NEG, E,v, lock), [0x0c] =3D X86_OP_ENTRYrr(MUL, E,v, 0,v, zextT0), --=20 2.53.0