From nobody Sun Jul 26 12:28:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=163.com ARC-Seal: i=1; a=rsa-sha256; t=1781873854; cv=none; d=zohomail.com; s=zohoarc; b=BWo8iNhRO8xyXgTjdmOMnn9jr0xNIxbPGlHdrKAAKcXeeuu0NJWa0NpL6QnB4OrbbuEu3ZIyNYCrvWXmYggSwIzZM7LzhZDotTxIxnU/2KpGrnugQpriI8JgCydGBPDQ23r6r59/X/DKcEsRJ+g0B9J3JjZAs0ISHrnMgONulWU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781873854; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FWfwgt/RYORWfGGcHg0oUzXsMLElsn2RU2CA0zXmwfQ=; b=K62P4+wM07j9yhcpa5ucCEHtMbS1bcm/4TQCB/mNU0wmb0DPQT4isYPp9HKN3CB0X8HV1EX+C5d458JO1LTyHWcAE1IOvFeuBXMJUToHwBn54pxY3z27PUNzrBVa2mCD+vgaY4MvmFrkNCYHZPKsthoQDOavGihDVL6dDjhkh+o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781873854688195.3477278780208; Fri, 19 Jun 2026 05:57:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1waYm1-0000ki-8T; Fri, 19 Jun 2026 08:56:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1waYlv-0000hj-Rm for qemu-devel@nongnu.org; Fri, 19 Jun 2026 08:56:36 -0400 Received: from m16.mail.163.com ([220.197.31.3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1waYlq-0007qx-UA for qemu-devel@nongnu.org; Fri, 19 Jun 2026 08:56:34 -0400 Received: from alano.. (unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgDnKbllPDVqD4oSDQ--.50474S2; Fri, 19 Jun 2026 20:56:06 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=FW fwgt/RYORWfGGcHg0oUzXsMLElsn2RU2CA0zXmwfQ=; b=DS3ykD5TYdms9ZJ++7 L7nqiNsSalc8WIGqtvrhGQfSjdX9IVL4NzjJbuMw7RTMgvJ1ONwM5knKLx6tA3U2 XwqgCp2dDm+vqPljcckPV7/1egBZ+9GvnZD/Vfix4Damn3upwOUdDUJqgm9qOqb4 2ULb815wksypjmqeEDJQ5DDRA= From: AlanoSong@163.com To: qemu-devel@nongnu.org Cc: dave@treblig.org, pbonzini@redhat.com, zhao1.liu@intel.com, Alano Song Subject: [PATCH v2] target/i386/monitor: Refine `info tlb` command Date: Fri, 19 Jun 2026 20:56:02 +0800 Message-ID: <20260619125602.17077-1-AlanoSong@163.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: PigvCgDnKbllPDVqD4oSDQ--.50474S2 X-Coremail-Antispam: 1Uf129KBjvJXoW3JryUCr1rKFW7tw45CrWDtwb_yoW3WFy5p3 y3ZrnYgan5tr13XwsxCrnFgr15ArsY9398XF9xCFyFk3WfXF9Fva4Dtw4jkwsxX34xWw43 Zr4qkw4UGw43XaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pi9YFkUUUUU= X-Originating-IP: [59.173.202.243] X-CM-SenderInfo: xdod00pvrqwqqrwthudrp/xtbC1AYQJGo1PGYglwAA3U Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=220.197.31.3; envelope-from=alanosong@163.com; helo=m16.mail.163.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @163.com) X-ZM-MESSAGEID: 1781873856229158500 Content-Type: text/plain; charset="utf-8" When booting an i386 target, the `info tlb` command may walk the entire page table hierarchy and emit an enormous amount of output. It will take dozens of minutes to print all the info, because each monitor print function will holds 'mon_lock'. This effectively hangs the qemu monitor. It may be better to add warning note in help message, and add a address range by argument to help user control the number of output items. Signed-off-by: Alano Song --- hmp-commands-info.hx | 12 ++++--- target/i386/monitor.c | 82 +++++++++++++++++++++++++++++-------------- 2 files changed, 64 insertions(+), 30 deletions(-) diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx index 82134eb6c2..3189e20de3 100644 --- a/hmp-commands-info.hx +++ b/hmp-commands-info.hx @@ -188,17 +188,21 @@ ERST =20 { .name =3D "tlb", - .args_type =3D "", - .params =3D "", - .help =3D "show virtual to physical memory mappings", + .args_type =3D "start:l?,end:l?", + .params =3D "[start [end]]", + .help =3D "show virtual to physical memory mappings. " + "output can be extremely large for i386 target. " + "use 'info tlb [start] [end]' to show a range of ent= ries.", .cmd =3D hmp_info_tlb, .arch_bitmask =3D QEMU_ARCH_I386 | QEMU_ARCH_SH4 | QEMU_ARCH_SPARC= \ | QEMU_ARCH_PPC | QEMU_ARCH_XTENSA | QEMU_ARCH_M68= K, }, =20 SRST - ``info tlb`` + ``info tlb`` [*start* [*end*]] Show virtual to physical memory mappings. + The output can be extremely large for i386 target. + Use *start* and *end* to print entries located in address range [start= , end]. ERST =20 { diff --git a/target/i386/monitor.c b/target/i386/monitor.c index a536712c75..c0e0c3e405 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -48,11 +48,9 @@ static hwaddr addr_canonical(CPUArchState *env, hwaddr a= ddr) return addr; } =20 -static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr, - hwaddr pte, hwaddr mask) +static void do_print_pte(Monitor *mon, CPUArchState *env, hwaddr addr, + hwaddr pte, hwaddr mask) { - addr =3D addr_canonical(env, addr); - monitor_printf(mon, HWADDR_FMT_plx ": " HWADDR_FMT_plx " %c%c%c%c%c%c%c%c%c\n", addr, @@ -68,7 +66,20 @@ static void print_pte(Monitor *mon, CPUArchState *env, h= waddr addr, pte & PG_RW_MASK ? 'W' : '-'); } =20 -static void tlb_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as) +static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr, + hwaddr pte, hwaddr mask, + hwaddr start, hwaddr end) +{ + addr =3D addr_canonical(env, addr); + if (addr < start || addr > end) { + return; + } + + do_print_pte(mon, env, addr, pte, mask); +} + +static void tlb_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as, + hwaddr start, hwaddr end) { const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; unsigned int l1, l2; @@ -80,15 +91,15 @@ static void tlb_info_32(Monitor *mon, CPUArchState *env= , AddressSpace *as) if (pde & PG_PRESENT_MASK) { if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { /* 4M pages */ - print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1)); + print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1), + start, end); } else { for(l2 =3D 0; l2 < 1024; l2++) { pte =3D address_space_ldl_le(as, (pde & ~0xfff) + l2 *= 4, attrs, NULL); if (pte & PG_PRESENT_MASK) { print_pte(mon, env, (l1 << 22) + (l2 << 12), - pte & ~PG_PSE_MASK, - ~0xfff); + pte & ~PG_PSE_MASK, ~0xfff, start, end); } } } @@ -96,7 +107,8 @@ static void tlb_info_32(Monitor *mon, CPUArchState *env,= AddressSpace *as) } } =20 -static void tlb_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *= as) +static void tlb_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *= as, + hwaddr start, hwaddr end) { const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; unsigned int l1, l2, l3; @@ -114,17 +126,19 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState= *env, AddressSpace *as) if (pde & PG_PSE_MASK) { /* 2M pages with PAE, CR4.PSE is ignored */ print_pte(mon, env, (l1 << 30) + (l2 << 21), pde, - ~((hwaddr)(1 << 20) - 1)); + ~((hwaddr)(1 << 20) - 1), + start, end); } else { pt_addr =3D pde & 0x3fffffffff000ULL; for (l3 =3D 0; l3 < 512; l3++) { pte =3D address_space_ldq_le(as, pt_addr + l3 = * 8, attrs, NULL); if (pte & PG_PRESENT_MASK) { - print_pte(mon, env, (l1 << 30) + (l2 << 21) - + (l3 << 12), + print_pte(mon, env, + (l1 << 30) + (l2 << 21) + (l3 <<= 12), pte & ~PG_PSE_MASK, - ~(hwaddr)0xfff); + ~(hwaddr)0xfff, + start, end); } } } @@ -136,7 +150,8 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *= env, AddressSpace *as) =20 #ifdef TARGET_X86_64 static void tlb_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *a= s, - uint64_t l0, uint64_t pml4_addr) + uint64_t l0, uint64_t pml4_addr, hwaddr start, + hwaddr end) { const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; uint64_t l1, l2, l3, l4; @@ -159,7 +174,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *e= nv, AddressSpace *as, if (pdpe & PG_PSE_MASK) { /* 1G pages, CR4.PSE is ignored */ print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30), - pdpe, 0x3ffffc0000000ULL); + pdpe, 0x3ffffc0000000ULL, start, end); continue; } =20 @@ -172,8 +187,9 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *e= nv, AddressSpace *as, =20 if (pde & PG_PSE_MASK) { /* 2M pages, CR4.PSE is ignored */ - print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 3= 0) + - (l3 << 21), pde, 0x3ffffffe00000ULL); + print_pte(mon, env, + (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 <= < 21), + pde, 0x3ffffffe00000ULL, start, end); continue; } =20 @@ -182,9 +198,11 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *= env, AddressSpace *as, pte =3D address_space_ldq_le(as, pt_addr + l4 * 8, attrs, NULL); if (pte & PG_PRESENT_MASK) { - print_pte(mon, env, (l0 << 48) + (l1 << 39) + - (l2 << 30) + (l3 << 21) + (l4 << 12), - pte & ~PG_PSE_MASK, 0x3fffffffff000ULL); + print_pte(mon, env, + (l0 << 48) + (l1 << 39) + (l2 << 30) + + (l3 << 21) + (l4 << 12), + pte & ~PG_PSE_MASK, + 0x3fffffffff000ULL, start, end); } } } @@ -192,7 +210,8 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *e= nv, AddressSpace *as, } } =20 -static void tlb_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *a= s) +static void tlb_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *a= s, + hwaddr start, hwaddr end) { const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; uint64_t l0; @@ -203,7 +222,8 @@ static void tlb_info_la57(Monitor *mon, CPUArchState *e= nv, AddressSpace *as) for (l0 =3D 0; l0 < 512; l0++) { pml5e =3D address_space_ldq_le(as, pml5_addr + l0 * 8, attrs, NULL= ); if (pml5e & PG_PRESENT_MASK) { - tlb_info_la48(mon, env, as, l0, pml5e & 0x3fffffffff000ULL); + tlb_info_la48(mon, env, as, l0, pml5e & 0x3fffffffff000ULL, + start, end); } } } @@ -213,6 +233,14 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) { CPUArchState *env; AddressSpace *as; + hwaddr start =3D 0, end =3D HWADDR_MAX; + + if (qdict_haskey(qdict, "start")) { + start =3D (hwaddr)qdict_get_int(qdict, "start"); + } + if (qdict_haskey(qdict, "end")) { + end =3D (hwaddr)qdict_get_int(qdict, "end"); + } =20 env =3D mon_get_cpu_env(mon); if (!env) { @@ -229,17 +257,19 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) #ifdef TARGET_X86_64 if (env->hflags & HF_LMA_MASK) { if (env->cr[4] & CR4_LA57_MASK) { - tlb_info_la57(mon, env, as); + tlb_info_la57(mon, env, as, start, end); } else { - tlb_info_la48(mon, env, as, 0, env->cr[3] & 0x3fffffffff00= 0ULL); + tlb_info_la48(mon, env, as, 0, + env->cr[3] & 0x3fffffffff000ULL, + start, end); } } else #endif { - tlb_info_pae32(mon, env, as); + tlb_info_pae32(mon, env, as, start, end); } } else { - tlb_info_32(mon, env, as); + tlb_info_32(mon, env, as, start, end); } } =20 --=20 2.43.0