From nobody Sun Jul 26 12:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1781775653; cv=none; d=zohomail.com; s=zohoarc; b=Imry94xifbqp2RMDe88JP8tJW5qFKU2zocVyenhdEXnC/0WvY4l0mMU6xAIhmP7ZQBZ6k1zxsyV3vAqTlms+GRyvcnMDlXbSn9RySXvIf28A8+9cCP7Ki86JwONs+WA26xPwjm7hGiyeccYpac6aqfsK3lNTVgp6e+RzM5me1fg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781775653; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XL9ehYAlIK5xBXPqBRCJ62qfknRHEuXN3NuX5sOY1Uo=; b=Ny7sG79bnM9zx7lEan6j4HvpBD0rI+F0Fjh9SJ4FBY+5yQVEaL2wmSqkA2qDUpP5f9iOT/xeKBkAgrks9FdEGvTpPionb19Jq37R69OoBO7swaNao5oNnzD4hL72gAvQFuCxW8684tAEJ/n9A6NFBIZkreRGdqFMoPa9lXdng/M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781775653113622.4970322336889; Thu, 18 Jun 2026 02:40:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wa9DL-000537-0V; Thu, 18 Jun 2026 05:39:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wa9DG-000506-5r; Thu, 18 Jun 2026 05:39:07 -0400 Received: from [115.124.30.132] (helo=out30-132.freemail.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wa9D8-0007FM-GY; Thu, 18 Jun 2026 05:39:03 -0400 Received: from DESKTOP-S9E58SO.localdomain(mailfrom:cp0613@linux.alibaba.com fp:SMTPD_---0X56RwMW_1781775515 cluster:ay36) by smtp.aliyun-inc.com; Thu, 18 Jun 2026 17:38:35 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1781775516; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=XL9ehYAlIK5xBXPqBRCJ62qfknRHEuXN3NuX5sOY1Uo=; b=yc4x5MXFh14hGaSJ62duT3ubJQ+kyqqLM+oAjKRDpUlsQVni5qWXy0FJT2BOFrF0xkfn/jjaE/8EEWlq3Z07XIN7bAdABNmrwxm8mXVVeWgorksERHETShiYuj/f7dkoC8G3k11aTg7jotl0VenedPqdM/MMw+3TedmqXh3ckiE= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R131e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045098064; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=17; SR=0; TI=SMTPD_---0X56RwMW_1781775515; From: Chen Pei To: jic23@kernel.org, pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, sunilvl@ventanamicro.com, dave.jiang@intel.com, alison.schofield@intel.com, imammedo@redhat.com, mst@redhat.com, guoren@kernel.org Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v2 1/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine Date: Thu, 18 Jun 2026 17:38:23 +0800 Message-ID: <20260618093827.3507-2-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260618093827.3507-1-cp0613@linux.alibaba.com> References: <20260618093827.3507-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.132 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.30.132; envelope-from=cp0613@linux.alibaba.com; helo=out30-132.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1781775654603158500 Content-Type: text/plain; charset="utf-8" Enable CXL support on the RISC-V virt machine following the same approach used by the ARM virt machine: - Add PXB and ACPI_CXL Kconfig selections - Add CXLState and PCIBus pointer to RISCVVirtState - Register CXL machine properties via cxl_machine_init() - Create CXL host register region above the PCIe high MMIO region - Call cxl_hook_up_pxb_registers() and cxl_fmws_link_targets() at machine_done time - Map Fixed Memory Windows above the CXL host register region - Add ACPI0017 device in DSDT and build CEDT table in virt-acpi-build.c Signed-off-by: Chen Pei --- hw/riscv/Kconfig | 2 ++ hw/riscv/virt-acpi-build.c | 20 +++++++++++++++++++ hw/riscv/virt.c | 40 ++++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 3 +++ 4 files changed, 65 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 2518b04175..ebd0355f09 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -66,8 +66,10 @@ config RISCV_VIRT select VIRTIO_MMIO select FW_CFG_DMA select PLATFORM_BUS + select PXB select ACPI select ACPI_PCI + select ACPI_CXL =20 config SHAKTI_C bool diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 413d47d70e..309d64b322 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -29,12 +29,16 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/pci.h" #include "hw/acpi/utils.h" +#include "hw/acpi/cxl.h" #include "hw/intc/riscv_aclint.h" #include "hw/nvram/fw_cfg_acpi.h" #include "hw/pci-host/gpex.h" +#include "hw/pci/pci_bus.h" #include "hw/riscv/virt.h" #include "hw/riscv/numa.h" #include "hw/virtio/virtio-acpi.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "kvm/kvm_riscv.h" #include "migration/vmstate.h" #include "qapi/error.h" @@ -503,6 +507,17 @@ static void build_dsdt(GArray *table_data, acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES= * 2); } =20 + if (s->cxl_devices_state.is_enabled) { + Aml *cxl_dev =3D aml_device("CXLM"); + aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + Aml *method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0B))); + aml_append(cxl_dev, method); + build_cxl_dsm_method(cxl_dev); + + aml_append(scope, cxl_dev); + } + aml_append(dsdt, scope); =20 /* copy AML table into ACPI tables blob and patch header there */ @@ -910,6 +925,11 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBui= ldTables *tables) s->oem_table_id); } =20 + if (s->cxl_devices_state.is_enabled) { + cxl_build_cedt(table_offsets, tables_blob, tables->linker, + s->oem_id, s->oem_table_id, &s->cxl_devices_state); + } + if (ms->numa_state->num_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, s); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ce64eaaef7..84b91b4322 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -55,6 +55,8 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "hw/acpi/aml-build.h" #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" @@ -1259,9 +1261,27 @@ static inline DeviceState *gpex_pcie_init(MemoryRegi= on *sys_mem, } =20 GPEX_HOST(dev)->gpex_cfg.bus =3D PCI_HOST_BRIDGE(dev)->bus; + s->pci_bus =3D PCI_HOST_BRIDGE(dev)->bus; return dev; } =20 +static void create_cxl_host_reg_region(RISCVVirtState *s) +{ + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *mr =3D &s->cxl_devices_state.host_mr; + hwaddr base; + + if (!s->cxl_devices_state.is_enabled) { + return; + } + + base =3D virt_high_pcie_memmap.base + virt_high_pcie_memmap.size; + base =3D ROUND_UP(base, 64 * KiB); + + memory_region_init(mr, OBJECT(s), "cxl_host_reg", 64 * KiB * 16); + memory_region_add_subregion(sysmem, base, mr); +} + static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) { FWCfgState *fw_cfg; @@ -1426,6 +1446,13 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) machine_done); MachineState *machine =3D MACHINE(s); hwaddr start_addr =3D s->memmap[VIRT_DRAM].base; + + cxl_hook_up_pxb_registers(s->pci_bus, &s->cxl_devices_state, + &error_fatal); + + if (s->cxl_devices_state.is_enabled) { + cxl_fmws_link_targets(&error_fatal); + } hwaddr firmware_end_addr; vaddr kernel_start_addr; const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); @@ -1663,6 +1690,17 @@ static void virt_machine_init(MachineState *machine) ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.siz= e); } =20 + create_cxl_host_reg_region(s); + + if (s->cxl_devices_state.is_enabled) { + hwaddr cxl_base =3D virt_high_pcie_memmap.base + + virt_high_pcie_memmap.size; + cxl_base +=3D memory_region_size(&s->cxl_devices_state.host_mr); + cxl_base =3D ROUND_UP(cxl_base, 256 * MiB); + cxl_fmws_set_memmap(cxl_base, UINT64_MAX); + cxl_fmws_update_mmio(); + } + /* register system main memory (actual RAM) */ memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, machine->ram); @@ -1769,6 +1807,8 @@ static void virt_machine_instance_init(Object *obj) s->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); s->acpi =3D ON_OFF_AUTO_AUTO; s->iommu_sys =3D ON_OFF_AUTO_AUTO; + + cxl_machine_init(obj, &s->cxl_devices_state); } =20 static char *virt_get_aia_guests(Object *obj, Error **errp) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 18a2a323a3..7d559ac610 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,6 +24,7 @@ #include "hw/core/sysbus.h" #include "hw/block/flash.h" #include "hw/intc/riscv_imsic.h" +#include "hw/cxl/cxl.h" =20 #define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) @@ -64,6 +65,8 @@ struct RISCVVirtState { struct GPEXHost *gpex_host; OnOffAuto iommu_sys; uint16_t pci_iommu_bdf; + CXLState cxl_devices_state; + PCIBus *pci_bus; }; =20 enum { --=20 2.50.1 From nobody Sun Jul 26 12:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1781775648; cv=none; d=zohomail.com; s=zohoarc; b=G+Y+UZjSixvrXiJtIFaQdbr4vgJwu8qBNYcGtEYttlEKwMztwY/iHDR7/W7OeF7OG8yaUx5JnCVTVnXNMnZICsm/3sCEdK5O5yW5qD9SqdsB+e0BNjKSXcXNNpMBnS+oFJUELV1ZP3XXrr06XuimMhAnmHU1IodTTj6gBA/bvY0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781775648; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XfZ905nYQgkGS4XfPh5nE3bF0mThL6pU9qgBQH+MnRE=; b=YGq8XQESmJmj24CPRAojLuVzMHys6DuoF4Sz3G90yUVEYxsRVIDi/oLkf5M8cjEzwfPwxw53YAEsQEboqZ+Njo+OiIYZqaBzscjEdH7InIWucRoVk4BXtVc6lQUBYZvq4nRS6wleKCfG5Bfbe+tylFfzjU1Cb5eemTg00msrylk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781775648261606.3306014941232; Thu, 18 Jun 2026 02:40:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wa9DL-00053P-IX; Thu, 18 Jun 2026 05:39:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wa9DG-000504-4u; Thu, 18 Jun 2026 05:39:06 -0400 Received: from [115.124.30.98] (helo=out30-98.freemail.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wa9D8-0007Gm-GB; Thu, 18 Jun 2026 05:39:04 -0400 Received: from DESKTOP-S9E58SO.localdomain(mailfrom:cp0613@linux.alibaba.com fp:SMTPD_---0X56RwMn_1781775515 cluster:ay36) by smtp.aliyun-inc.com; Thu, 18 Jun 2026 17:38:36 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1781775517; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=XfZ905nYQgkGS4XfPh5nE3bF0mThL6pU9qgBQH+MnRE=; b=ujkqYhN2wSOZQf61RHJ3GjeOd2EateaplIaAEjdaOOPxCvAe46+8h54cQJpNE4VDZYncg3kngn2s+w2lTSBJdhfqGsR7CDHUSBxH2O9Nfx/JSkahbLi5M8L9eb/Y2iTNAHuTgtiRuGpNTdNInoagn8r2CsbjEPbLCbYjWSfnEPw= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R201e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037033178; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=17; SR=0; TI=SMTPD_---0X56RwMn_1781775515; From: Chen Pei To: jic23@kernel.org, pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, sunilvl@ventanamicro.com, dave.jiang@intel.com, alison.schofield@intel.com, imammedo@redhat.com, mst@redhat.com, guoren@kernel.org Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v2 2/4] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Date: Thu, 18 Jun 2026 17:38:24 +0800 Message-ID: <20260618093827.3507-3-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260618093827.3507-1-cp0613@linux.alibaba.com> References: <20260618093827.3507-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.98 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.30.98; envelope-from=cp0613@linux.alibaba.com; helo=out30-98.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1781775648628158500 Content-Type: text/plain; charset="utf-8" On RISC-V QEMU virt platform with CXL enabled, the probe ordering of acpi_pci_root (ACPI0016) and cxl_acpi (ACPI0017) is not guaranteed. If cxl_acpi probes before acpi_pci_root has attached the CXL host bridges, the CXL port topology will be incomplete because to_cxl_host_bridge() silently skips devices whose PCI root is not yet ready. Add a _DEP object to the ACPI0017 device in the DSDT, declaring its dependency on the ACPI0016 CXL host bridge devices. This tells the OS to defer ACPI0017 enumeration until all ACPI0016 devices have been attached by acpi_pci_root. This requires a corresponding kernel change to call acpi_dev_clear_dependencies() in acpi_pci_root_add(). The resulting DSDT fragment (iasl -d output) for a single CXL host bridge at bus 0x01 looks like: Device (CXLM) { Name (_HID, "ACPI0017") Name (_DEP, Package (0x01) { \_SB.PC01 }) Method (_STA, 0, NotSerialized) { Return (0x0B) } ... } Signed-off-by: Chen Pei --- hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 309d64b322..3598e55243 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -510,6 +510,38 @@ static void build_dsdt(GArray *table_data, if (s->cxl_devices_state.is_enabled) { Aml *cxl_dev =3D aml_device("CXLM"); aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + + /* + * Declare a _DEP on every ACPI0016 CXL host bridge so the OS + * defers ACPI0017 enumeration until acpi_pci_root has attached + * the CXL host bridges. Without this, cxl_acpi may probe before + * to_cxl_host_bridge() can resolve the PCI root and the CXL + * port topology comes up empty. + */ + if (s->pci_bus) { + PCIBus *bus; + uint32_t num_cxl_hbs =3D 0; + + QLIST_FOREACH(bus, &s->pci_bus->child, sibling) { + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { + num_cxl_hbs++; + } + } + + if (num_cxl_hbs > 0) { + Aml *dep_pkg =3D aml_package(num_cxl_hbs); + + QLIST_FOREACH(bus, &s->pci_bus->child, sibling) { + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { + aml_append(dep_pkg, + aml_name("\\_SB.PC%.02X", + pci_bus_num(bus))); + } + } + aml_append(cxl_dev, aml_name_decl("_DEP", dep_pkg)); + } + } + Aml *method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); aml_append(method, aml_return(aml_int(0x0B))); aml_append(cxl_dev, method); --=20 2.50.1 From nobody Sun Jul 26 12:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.alibaba.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781775639666680.4458180429256; Thu, 18 Jun 2026 02:40:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wa9DL-00053f-Le; Thu, 18 Jun 2026 05:39:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wa9DG-000508-5b; Thu, 18 Jun 2026 05:39:07 -0400 Received: from [115.124.30.98] (helo=out30-98.freemail.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wa9D8-0007HU-Fi; Thu, 18 Jun 2026 05:39:04 -0400 Received: from DESKTOP-S9E58SO.localdomain(mailfrom:cp0613@linux.alibaba.com fp:SMTPD_---0X56RwN-_1781775516 cluster:ay36) by smtp.aliyun-inc.com; Thu, 18 Jun 2026 17:38:37 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1781775517; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; bh=3XQdS48sPXuJmO8K+dNMGNXxL97FmWYc63jMl0VUAiE=; b=WeJTiTaLfT0uyPYt638xJUmfk1Y6ryuKkiMhh9Dd+y+X80xsiU/lxLnM6sHzoHjzhaSkjp4ZE0HmcRfgUa9MYsJIdarT+AqZOWWrelc+6KJBoua/kEihyFqO3Z0Lk3w0C76VW5WlF4mwFxv+MD9RJJ3K3D5+CFx0NJjORWJo01Q= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R161e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037009110; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=17; SR=0; TI=SMTPD_---0X56RwN-_1781775516; From: Chen Pei To: jic23@kernel.org, pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, sunilvl@ventanamicro.com, dave.jiang@intel.com, alison.schofield@intel.com, imammedo@redhat.com, mst@redhat.com, guoren@kernel.org Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v2 3/4] hw/riscv/virt, gpex: Provide 32-bit MMIO window for CXL host bridges Date: Thu, 18 Jun 2026 17:38:25 +0800 Message-ID: <20260618093827.3507-4-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260618093827.3507-1-cp0613@linux.alibaba.com> References: <20260618093827.3507-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.98 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.30.98; envelope-from=cp0613@linux.alibaba.com; helo=out30-98.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1781775640714158500 CXL component register BAR (BAR0 on CXL Root Port and Type3 device) and the CXL device register BAR (BAR2 on Type3 device) are declared as 64-bit non-prefetchable memory. Per the PCI-to-PCI Bridge Architecture Specification Rev 1.2 (PCI-SIG, 2003): - =C2=A73.2.5.8 (Memory Base/Limit): the non-prefetchable window covers only 32-bit addresses (AD[31:20]); the Type 1 header defines no upper-32-bit extension for it. - =C2=A73.2.5.9 (Prefetchable Memory Base/Limit): the bottom 4 bits encode 64-bit support (01h), but this applies exclusively to the *prefetchable* window. - =C2=A73.2.5.10 (Prefetchable Base/Limit Upper 32 Bits): optional registers for AD[63:32] of the prefetchable range only. The architecture therefore allows a 64-bit window only when it is also prefetchable; there is no 64-bit non-prefetchable form. PCIe inherits this Type 1 header layout unchanged. Linux thus places 64-bit non-prefetchable BARs in the 32-bit non-prefetchable bridge window, which requires the bridge to own enough address space below 4 GiB. On RISC-V virt the 32-bit PCIe MMIO range (1 GiB at 0x40000000) is currently consumed entirely by PCI0, so CXL host bridges (ACPI0016) have no non-prefetchable window and Linux fails to assign these BARs. Marking the BARs prefetchable would work around it, but the CXL component registers have read/write side effects and are not prefetchable per the PCIe specification. Reserve the top 256 MiB of the 32-bit MMIO window exclusively for CXL host bridges: - Shrink PCI0's mmio32 window by 256 MiB in virt.c so that UEFI's PciHostBridgeDxe and the ACPI _CRS for PCI0 never claim that range - Store the reserved range in a new gpex_cfg.cxl_mmio32 field - In gpex-acpi.c, emit the cxl_mmio32 range as the Memory resource in the CXL host bridge _CRS instead of re-using build_crs() (which returns an empty set when UEFI has not assigned resources yet) - Reduce the FDT 'ranges' for PCI0 by the same 256 MiB so that UEFI firmware driven by device-tree also respects the reservation Signed-off-by: Chen Pei --- hw/pci-host/gpex-acpi.c | 36 +++++++++++++++++++++-- hw/riscv/virt.c | 58 +++++++++++++++++++++++++++++++------- include/hw/pci-host/gpex.h | 1 + 3 files changed, 83 insertions(+), 12 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index d9820f9b41..d8b943b665 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -158,9 +158,41 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig = *cfg) * Resources defined for PXBs are composed of the following pa= rts: * 1. The resources the pci-bridge/pcie-root-port need. * 2. The resources the devices behind pxb need. + * + * For CXL host bridges on platforms where UEFI (driven by + * FDT 'ranges') does not assign PCI resources for the CXL + * root bridge before ACPI table construction, build_crs() + * would return an empty resource set. When the platform + * has reserved a dedicated MMIO window for CXL host bridges + * (cfg->cxl_mmio32), emit that window as a static _CRS + * instead. The platform is responsible for shrinking PCI0's + * mmio32 window so the two do not overlap. */ - crs =3D build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_rang= e_set, - cfg->pio.base, 0, 0, 0); + if (is_cxl && cfg->cxl_mmio32.size) { + uint64_t cxl_base =3D cfg->cxl_mmio32.base; + uint64_t cxl_size =3D cfg->cxl_mmio32.size; + + crs =3D aml_resource_template(); + + /* 32-bit MMIO range for CXL devices */ + aml_append(crs, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, 0, + cxl_base, + cxl_base + cxl_size - 1, + 0, cxl_size)); + + /* Bus number range */ + aml_append(crs, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, 0, + bus_num, bus_num + 15, + 0, 16)); + } else { + crs =3D build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), + &crs_range_set, cfg->pio.base, 0, 0, 0); + } aml_append(dev, aml_name_decl("_CRS", crs)); =20 if (is_cxl) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 84b91b4322..9c1a001553 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -113,6 +113,9 @@ static const MemMapEntry virt_memmap[] =3D { /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) =20 +/* 32-bit MMIO range carved out of VIRT_PCIE_MMIO for CXL host bridges */ +#define VIRT_CXL_MMIO32_SIZE (256 * MiB) + static MemMapEntry virt_high_pcie_memmap; =20 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) @@ -890,15 +893,28 @@ static void create_fdt_pcie(RISCVVirtState *s, } qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", - 1, FDT_PCI_RANGE_IOPORT, 2, 0, - 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size, - 1, FDT_PCI_RANGE_MMIO, - 2, s->memmap[VIRT_PCIE_MMIO].base, - 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].si= ze, - 1, FDT_PCI_RANGE_MMIO_64BIT, - 2, virt_high_pcie_memmap.base, - 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); + { + /* + * When CXL is enabled, reserve the last 256 MiB of the 32-bit + * MMIO window for CXL host bridges and exclude it from the main + * PCIe host bridge's FDT 'ranges' so UEFI's PciHostBridgeDxe + * does not allocate that range to PCI0. The CXL host bridge + * _CRS declares this range independently. + */ + hwaddr mmio32_size =3D s->memmap[VIRT_PCIE_MMIO].size; + if (s->cxl_devices_state.is_enabled) { + mmio32_size -=3D VIRT_CXL_MMIO32_SIZE; + } + qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", + 1, FDT_PCI_RANGE_IOPORT, 2, 0, + 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].= size, + 1, FDT_PCI_RANGE_MMIO, + 2, s->memmap[VIRT_PCIE_MMIO].base, + 2, s->memmap[VIRT_PCIE_MMIO].base, 2, mmio32_size, + 1, FDT_PCI_RANGE_MMIO_64BIT, + 2, virt_high_pcie_memmap.base, + 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); + } =20 if (virt_is_iommu_sys_enabled(s)) { qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", @@ -1728,7 +1744,29 @@ static void virt_machine_init(MachineState *machine) qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); } =20 - gpex_pcie_init(system_memory, pcie_irqchip, s); + DeviceState *pcie_dev =3D gpex_pcie_init(system_memory, pcie_irqchip, = s); + + /* + * If CXL is enabled, reserve the last 256 MiB of the 32-bit MMIO + * window for CXL host bridges so the bridge non-prefetchable window + * can hold CXL device BARs (component registers and similar 64-bit + * non-prefetchable BARs that need a < 4 GiB address). + * + * - Shrink PCI0's mmio32 advertised in the ACPI _CRS by the same + * 256 MiB so the two ranges do not overlap (the FDT 'ranges' + * shrink happens in create_fdt_pcie()). + * - Store the reserved range in cxl_mmio32 so gpex-acpi.c can emit + * a correct _CRS for the CXL host bridge (ACPI0016). + */ + if (s->cxl_devices_state.is_enabled) { + GPEXHost *gpex =3D GPEX_HOST(pcie_dev); + gpex->gpex_cfg.cxl_mmio32.size =3D VIRT_CXL_MMIO32_SIZE; + gpex->gpex_cfg.cxl_mmio32.base =3D + s->memmap[VIRT_PCIE_MMIO].base + + s->memmap[VIRT_PCIE_MMIO].size - VIRT_CXL_MMIO32_SIZE; + /* Shrink PCI0's advertised 32-bit MMIO window to exclude CXL rang= e */ + gpex->gpex_cfg.mmio32.size -=3D VIRT_CXL_MMIO32_SIZE; + } =20 create_platform_bus(s, mmio_irqchip); =20 diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index 1da9c85bce..d38fbbacd6 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -43,6 +43,7 @@ struct GPEXConfig { MemMapEntry mmio32; MemMapEntry mmio64; MemMapEntry pio; + MemMapEntry cxl_mmio32; int irq; PCIBus *bus; bool pci_native_hotplug; --=20 2.50.1 From nobody Sun Jul 26 12:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1781775595; cv=none; d=zohomail.com; s=zohoarc; b=cVwbG/33gRiPGTNLPFM1YNozmRgjBWNhBycPBYVMeuvyeboTpPZeFLxxjz0i/JDPs5fAjPk5AZq98J5EkmwM3YDpeqiJQbTztRL60m/kbu1p/2+iPOPfAX75YmofDY+b+10++saLzYxhbjaMZosDb+TLO7tRRHpQyazUgT69jxA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781775595; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VV94c9wtKw6ZwOmBFRfajEdtwdPPb2DI7A490RggnXw=; b=d1/ggz+z50fSDuVqek8sxrqyv2g98Urgm20oeNaylzOeMXQKMJj1TIo0L1Bzh/9ELsozD3WTmhXUWzogZdt0p46yHRd4pyOImdfpMLCPr5GHPH7R0To7MSqabbTbbrMm6kyrZceIwpPYWpaVw+BkAsfxvPpYvXeY4PveSoP+vgU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781775594915112.49014295374548; Thu, 18 Jun 2026 02:39:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wa9DK-00052e-H8; Thu, 18 Jun 2026 05:39:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wa9DG-000507-5h; Thu, 18 Jun 2026 05:39:07 -0400 Received: from [115.124.30.131] (helo=out30-131.freemail.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wa9D8-0007I6-GX; Thu, 18 Jun 2026 05:39:02 -0400 Received: from DESKTOP-S9E58SO.localdomain(mailfrom:cp0613@linux.alibaba.com fp:SMTPD_---0X56RwN9_1781775517 cluster:ay36) by smtp.aliyun-inc.com; Thu, 18 Jun 2026 17:38:37 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1781775519; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=VV94c9wtKw6ZwOmBFRfajEdtwdPPb2DI7A490RggnXw=; b=GVH+Ll/DrrMq1RaXjeurNaMC7TGB67QPo2U+VJdoIE8NbmttwiaSDK2Hm7K7qqiFQOAbl9VU44Ti92+qMVcsf6zAOt7am+Zxmnmd0IkMQQ8WGEkzSn5l2aEOq4nKh7KUZPPK7pbQo2bzTMheDYsY0sKv1Ym/BlipRuEvT+GYnRs= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R181e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045098064; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=17; SR=0; TI=SMTPD_---0X56RwN9_1781775517; From: Chen Pei To: jic23@kernel.org, pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, sunilvl@ventanamicro.com, dave.jiang@intel.com, alison.schofield@intel.com, imammedo@redhat.com, mst@redhat.com, guoren@kernel.org Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org Subject: [PATCH v2 4/4] tests/qtest: Add RISC-V ACPI bios tables test for CXL Date: Thu, 18 Jun 2026 17:38:26 +0800 Message-ID: <20260618093827.3507-5-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260618093827.3507-1-cp0613@linux.alibaba.com> References: <20260618093827.3507-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.131 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.30.131; envelope-from=cp0613@linux.alibaba.com; helo=out30-131.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1781775596309158500 Content-Type: text/plain; charset="utf-8" Add test_acpi_riscv64_virt_tcg_cxl() to verify that enabling CXL on the RISC-V virt machine produces correct ACPI tables, including the ACPI0017 CXLM device with _DEP in the DSDT and the CEDT table. The test boots with cxl=3Don, one pxb-cxl bus (bus_nr=3D12), a CXL root port, a cxl-type3 persistent memory device, and a fixed memory window, mirroring the existing x86 q35 CXL test pattern. Since pxb-cxl is a root bus, using -cdrom causes QEMU to auto-plug the cdrom drive into pxb-cxl, triggering "Only PCI/PCIe bridges can be plugged into pxb-cxl". The ISO is instead attached explicitly via a virtio-scsi-pci controller on pcie.0, following the same approach as test_acpi_aarch64_virt_tcg_pxb(). Signed-off-by: Chen Pei Acked-by: Alistair Francis --- tests/data/acpi/riscv64/virt/CEDT.cxl | Bin 0 -> 108 bytes tests/data/acpi/riscv64/virt/DSDT.cxl | Bin 0 -> 6212 bytes tests/qtest/bios-tables-test.c | 54 ++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) create mode 100644 tests/data/acpi/riscv64/virt/CEDT.cxl create mode 100644 tests/data/acpi/riscv64/virt/DSDT.cxl diff --git a/tests/data/acpi/riscv64/virt/CEDT.cxl b/tests/data/acpi/riscv6= 4/virt/CEDT.cxl new file mode 100644 index 0000000000000000000000000000000000000000..81d746dfb09ccb147e26bb64060= 404ca3191d097 GIT binary patch literal 108 zc-nJzbqUE~U|?VjaPoKd2v%^42yj*a0!E-1hz+6{7!(+IKx!BefCEf2LP-snumA^? O0aMEg#QH!C(hmS*@&^F` literal 0 Hc-jL100001 diff --git a/tests/data/acpi/riscv64/virt/DSDT.cxl b/tests/data/acpi/riscv6= 4/virt/DSDT.cxl new file mode 100644 index 0000000000000000000000000000000000000000..45999636a05a16f68d1f418a58d= 9b80a8a62c9bd GIT binary patch literal 6212 zc-pO)%WoS+9LHzvjqR-0&f0Mj=3Djrqzae%_tantltHTF7bT*Zm;rVlBV91*2z8`P#y z5CtJh4?H3sYJ<3NaYa=3DA0Zs@65?r`dLI_kOZd^FR0U;rUnO)o2Z@QIw$VS?ovFG=3Dl z`E1tSkGJfUm&#coLJv!e_M9_bI$yKL<)#TCR9hXbkKfiVG@Mdn`SzS{1Bf-|D&<7c zu2p1bO2isxDrLE^7MD^_8HclnHKEG<+ur{2?c=3DlO>{&19`I+h&88jgyoTZ`>k2P$& zsL6fZNu`YBJKd_>vg9hoO<6frvD-_iJN8*wneQy&lv5IW3WX`eid$$$?Zqlr7CM!x zX2=3D+5)mUo(ene=3DR;m#Usl$~;VB9!Vitjw=3DF55KzlL3Q)a*PnfR`g1KktfjM|#OjOJ zR@aYQd};0aD{EI*Z^~(>kIPAm`q_GWx$_J4MLFr@?xY>g_SBa9=3DS{7(fZd3EP=3Dpo~ zG46{9wIWI?Vj?KQ2nA)pml5`76aq8CK^fD&4Bek`G%!OC%BcA=3Dy8IcFff-#v87sbw zh(F_4U`8Y;W5bsb^=3DC{4W<-NBZuv4|t&EC354&}B)D~*8J=3D?iBYO*$I#NF}Zt*g*} z(|kiiUL|(BVc#rax3bXbX}+OhuQI>e4f|%%h48IF7n*OVF4~ms zuAj4uIJ=3D0mi#fZPGeVpZ;*2n7ggK+c870mrb4HmnMw~I?j4@}7IlGCon>f3fvzs{$ z;xvfUU`~TMQ0G?_C&oC)GgFlT}}lf;=3DM&LndtnX`vDdx*1# zIeVDXB2J4qE#|bCGew*!;!H7TiaFE7nI_IObEcWImpFTgvzIx0nKMJ28RE<^XNEcZ zh_jD4`CC)5!W|?!4I0uPykU0mLbBH*H zh;xWJhnRDiIERUIm^p`;bA&iYh;xKFN0@VzI7f+dlsQM4bBs90h;xiN$CxumoH^pm zF=3DwvL>D{=3DWGoE=3D@UJYj3_cwNScHU~Wt@jclWV%8=3D>?*dr+dF4!H4(Fy>ho^fcH6ed z%qJU*j;(L53%h(S-&`>7Y+X|ByaQ!f?yQ{sUS!N!72z=3DL68c9R1mC!U=3D;+ZAV>wlDhO6V zkP3oS5Uhe=3D6$GguNCm+v2v$Lm3W8J+tb$+_1gRiM1;Hu^RzZ*of>aQ!f?yQ{sUS!N z!72z=3DL68c9R1mC!U=3D;+ZAV>wlDhO6VkP3oS5Uhe=3D6$GguNCm+v2v$Lm3W8J+tb$+_ z1gRiM1;Hu^RzZ*of>aQ!f?yQ{sUS!N!72z=3DL68c9R1mC!U=3D;+ZAV>wlDhO6VkP3oS z5Uhe=3D6$GguNCm+v2v$Lm3W8J+tb$+_1gRiM1;Hu^RzZ*of>aQ!f?yQ{sUS!N!72z=3D zL68c9R1mC!U=3D;+ZAV>wlDhO6VkP3oS5Uhe=3D6$GguNCm+v2v$KkOU7*2rJ~qYt_SZ{ zJ{L7^wDnJjxGRAqiqldQueI8c?`USY{j6Btg4GsQPmwpD_SLwX?v8M83}Wx=3DQX1x? zERtQp9{E^f9D71zbp7z2Nn)2d(kMGsy?MZ!^TE`Qe>jt`SMLn`Ssnb|t~R^3u88ea zSo3zvx2t-6#vu)CYjwfEBjoVT&Cba^;Ff4VTa4J}=3Dd1LzOg*bF&(zYUcHvp|Kwmvh z%XF)!?qb`BXQtG8%_h9{-v4*)@87?;K7Ienmu7tNqk3n(S~IzIMcYotLRwmvlJY;~ Cu_#Oc literal 0 Hc-jL100001 diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 510751799e..4625b76692 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2194,6 +2194,56 @@ static void test_acpi_riscv64_virt_tcg(void) free_test_data(&data); } =20 +#ifdef CONFIG_POSIX +static void test_acpi_riscv64_virt_tcg_cxl(void) +{ + gchar *tmp_path =3D g_dir_make_tmp("qemu-test-cxl.XXXXXX", NULL); + gchar *params; + + test_data data =3D { + .machine =3D "virt", + .arch =3D "riscv64", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-riscv-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-riscv-vars.fd", + .ram_start =3D 0x80000000ULL, + .scan_len =3D 128ULL * MiB, + .variant =3D ".cxl", + }; + + /* + * While using -cdrom, the cdrom would auto-plug into pxb-cxl because + * its bus is also a root bus, triggering "Only PCI/PCIe bridges can be + * plugged into pxb-cxl". Attach the ISO explicitly to a scsi control= ler + * on pcie.0 instead, following the same pattern as + * test_acpi_aarch64_virt_tcg_pxb(). + */ + params =3D g_strdup_printf("-cpu rva22s64" + " -machine cxl=3Don" + " -device pcie-root-port,chassis=3D1,id=3Dpci= .1,bus=3Dpcie.0" + " -device virtio-scsi-pci,id=3Dscsi0,bus=3Dpc= i.1" + " -drive file=3Dtests/data/uefi-boot-images/" + "bios-tables-test.riscv64.iso.qcow2," + "if=3Dnone,media=3Dcdrom,id=3Ddrive-scsi0-0-0= -1,readonly=3Don" + " -device scsi-cd,bus=3Dscsi0.0,scsi-id=3D0," + "drive=3Ddrive-scsi0-0-0-1,id=3Dscsi0-0-0-1,b= ootindex=3D1" + " -object memory-backend-file,id=3Dcxl-mem1,m= em-path=3D%s,size=3D256M" + " -object memory-backend-file,id=3Dlsa1,mem-p= ath=3D%s,size=3D256M" + " -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id= =3Dcxl.1" + " -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Drp= 1,chassis=3D0,slot=3D2" + " -device cxl-type3,bus=3Drp1,persistent-memd= ev=3Dcxl-mem1,lsa=3Dlsa1" + " -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.si= ze=3D4G," + "cxl-fmw.0.interleave-granularity=3D8k", + tmp_path, tmp_path); + test_acpi_one(params, &data); + + g_free(params); + g_assert(g_rmdir(tmp_path) =3D=3D 0); + g_free(tmp_path); + free_test_data(&data); +} +#endif /* CONFIG_POSIX */ + static void test_acpi_aarch64_virt_tcg(void) { test_data data =3D { @@ -2888,6 +2938,10 @@ int main(int argc, char *argv[]) test_acpi_riscv64_virt_tcg_numamem); qtest_add_func("acpi/virt/acpispcr", test_acpi_riscv64_virt_tcg_acpi_spcr); +#ifdef CONFIG_POSIX + qtest_add_func("acpi/virt/cxl", + test_acpi_riscv64_virt_tcg_cxl); +#endif } } else if (strcmp(arch, "loongarch64") =3D=3D 0) { if (has_tcg && qtest_has_machine("virt")) { --=20 2.50.1