From nobody Sun Jul 26 12:32:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1781754623; cv=none; d=zohomail.com; s=zohoarc; b=ZfZOEEykduMIUNBbHAqr7P4XOEYzvFz9mbkHg3VJ6UCVhp04+1g5dOuEYu7iXRLz0CGQ5N/+UMMphUdO+sIYXiSMv72qQG/gEPfrZAOL1xQNeh/zLeHNlg0wP9IyR3uA1TIgKoHvQeAuvr93vwuBldce1sgoB5jB5zWKlUuUCow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781754623; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9T1EfGyKt7YQcOUhXilo7/Oos4YJqChHEF0HJDZg1rA=; b=aPTESFyA48iMxfkUnQ8AKf5gykk8T51wMRa0ttA/wO1J1c3S5mEspkD/YIGAOaRjSasQwmcF169lRIwC/b4NP0FYd6yTOEOT3ylne/X3Uo+ryUa6ifcLpC340R8rGB6ALKVOzEoeJf9UEjVScejy49zhLr3RYI8VKLGW5Ju1Ets= ARC-Authentication-Results: i=1; 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Wed, 17 Jun 2026 23:49:02 -0400 Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2026 20:48:59 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2026 20:48:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781754541; x=1813290541; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dBgCqtONCptyZXJ2k+3tDlSp+lfxKq17l6cUqH3J2Q0=; b=g+n2OppFN/aNDEVnbzN/Ma6Co1mVvx9SIdR/8BfRmVvxy/29KDjKS7Gs G/D3xKXua7p4BvBS8ehPJy+agYd74zmyUM7nybUcZYwPy7iHwb2FEXKDk EjqgpEgov91us0BzTMomvVApfCBjJEaYcmme5mopNbVDzhAgPuz+65pvJ CYNFngmW5g8FxvpvES3Y/9SKcIKiEhQtXqbQWsKWmRJK3LPAw+QbVNhl9 MNXrlT1q4ukSbuTjLE/m/lF3tVYHHz/JoIW/ZgAvxIdSws2GRytCDbKu9 cM6A5fy5RtRUkaDXjsB1rx3Dy4C3U6M+OB3iWyRA4+sZfmyOoWO/rbmEq A==; X-CSE-ConnectionGUID: DlYOoQuvQk6/w6W3M7qFdQ== X-CSE-MsgGUID: kE1I7UoDT46Q96sQa7Wi5A== X-IronPort-AV: E=McAfee;i="6800,10657,11820"; a="82776826" X-IronPort-AV: E=Sophos;i="6.24,210,1774335600"; d="scan'208";a="82776826" X-CSE-ConnectionGUID: CTngwMwpT4CPQfG9BWq6rg== X-CSE-MsgGUID: A37hcDYiTm6l1KqQ8uc6lg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,210,1774335600"; d="scan'208";a="253352574" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v2 1/5] backends/iommufd: Introduce iommufd_backend_alloc_faultq Date: Wed, 17 Jun 2026 23:48:39 -0400 Message-ID: <20260618034844.618011-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260618034844.618011-1-zhenzhong.duan@intel.com> References: <20260618034844.618011-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1781754623974158500 Content-Type: text/plain; charset="utf-8" Add a new helper for IOMMU_FAULT_QUEUE_ALLOC ioctl to allocate a fault handling object which will be used in hwpt allocation. Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- include/system/iommufd.h | 3 +++ backends/iommufd.c | 21 +++++++++++++++++++++ backends/trace-events | 1 + 3 files changed, 25 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 17bf1a3727..c287767b11 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -106,6 +106,9 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, = uint32_t viommu_id, uint32_t *out_veventq_id, uint32_t *out_veventq_fd, Error **errp); =20 +bool iommufd_backend_alloc_faultq(IOMMUFDBackend *be, uint32_t *fault_id, + int *fault_fd, Error **errp); + bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, uint32_t queue_type, uint32_t index, uint64_t addr, uint64_t length, diff --git a/backends/iommufd.c b/backends/iommufd.c index 09624cd652..9c56a7bcd6 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -549,6 +549,27 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, return true; } =20 +bool iommufd_backend_alloc_faultq(IOMMUFDBackend *be, uint32_t *fault_id, + int *fault_fd, Error **errp) +{ + int ret, fd =3D be->fd; + struct iommu_fault_alloc cmd =3D { + .size =3D sizeof(cmd), + }; + + ret =3D ioctl(fd, IOMMU_FAULT_QUEUE_ALLOC, &cmd); + trace_iommufd_backend_alloc_faultq(fd, cmd.out_fault_id, cmd.out_fault= _fd, + ret); + if (ret) { + error_setg_errno(errp, errno, "Failed to allocate fault queue"); + return false; + } + + *fault_id =3D cmd.out_fault_id; + *fault_fd =3D cmd.out_fault_fd; + return true; +} + bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, uint32_t queue_type, uint32_t index, uint64_t addr, uint64_t length, diff --git a/backends/trace-events b/backends/trace-events index b63420b73e..1df3efb353 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -17,6 +17,7 @@ iommufd_backend_unmap_dma_non_exist(int iommufd, uint32_t= ioas, uint64_t iova, u iommufd_backend_unmap_dma(int iommufd, uint32_t ioas, uint64_t iova, uint6= 4_t size, int ret) " iommufd=3D%d ioas=3D%d iova=3D0x%"PRIx64" size=3D0x%"P= RIx64" (%d)" iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) " iommufd=3D%d ioas= =3D%d" iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, u= int32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_= t out_hwpt_id, int ret) " iommufd=3D%d dev_id=3D%u pt_id=3D%u flags=3D0x%x = hwpt_type=3D%u len=3D%u data_ptr=3D0x%"PRIx64" out_hwpt=3D%u (%d)" +iommufd_backend_alloc_faultq(int iommufd, uint32_t fault_id, int fault_fd,= int ret) " iommufd=3D%d fault_id=3D%u fault_fd=3D%d (%d)" iommufd_backend_free_id(int iommufd, uint32_t id, int ret) " iommufd=3D%d = id=3D%d (%d)" iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd= =3D%d hwpt=3D%u iova=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D0x%"PRIx64" p= age_size=3D0x%"PRIx64" (%d)" --=20 2.52.0 From nobody Sun Jul 26 12:32:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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17 Jun 2026 20:49:03 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2026 20:48:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781754545; x=1813290545; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1W5Ny9u8ZAzpK6G0mIReOsANN5rXzwZDbaRuyTggaYw=; b=J+fCAy3pJ4KFSmvtCarsA/e/rTAf+fM0NOCimnHuZKH22JKb2xU/osjr wvaDtZcCADvwIYQIJr8JrFmMm6PyJ/RKfuO+xIyTeR9ilNnq6SXD4FLbG qBXM7a65vuSAGLPVfCZpNQs484Viq4pDAcvraI8O1VdZdV4LYcPefQK5Q zcinIxJ3tlzlM1dDAUMecQDFHDESkIP/13DiwrO8a3om0ctKwZuPXUYKL LyXFR0r74tlg/LN0DTtOGLRH4QkJRl7DCeLywGEA+iRK/1TgmKhQHiKzS lrTj3WvQ8DZLcjmxQ1gWd97ZulbdQqtKMBS4D9gHnUCxid2E+8xwZi4In Q==; X-CSE-ConnectionGUID: q2nWGg0tSA6uiHdWRyBe7w== X-CSE-MsgGUID: 6o6s0tUOT5WG9mpxVofo7Q== X-IronPort-AV: E=McAfee;i="6800,10657,11820"; a="82776835" X-IronPort-AV: E=Sophos;i="6.24,210,1774335600"; d="scan'208";a="82776835" X-CSE-ConnectionGUID: /TRYG5W3T9yMbxu1evljVA== X-CSE-MsgGUID: w2lbVb+jT86p8IstVYWB8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,210,1774335600"; d="scan'208";a="253352613" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan , qemu-arm@nongnu.org Subject: [PATCH v2 2/5] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id Date: Wed, 17 Jun 2026 23:48:40 -0400 Message-ID: <20260618034844.618011-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260618034844.618011-1-zhenzhong.duan@intel.com> References: <20260618034844.618011-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1781754597594158500 Content-Type: text/plain; charset="utf-8" We should set flags IOMMU_HWPT_FAULT_ID_VALID when pass in a fault object id in the caller. Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao Reviewed-by: Clement Mathieu--Drif --- include/system/iommufd.h | 4 ++-- backends/iommufd.c | 7 ++++--- hw/arm/smmuv3-accel.c | 6 +++--- hw/i386/intel_iommu_accel.c | 2 +- hw/vfio/iommufd.c | 2 +- backends/trace-events | 2 +- 6 files changed, 12 insertions(+), 11 deletions(-) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index c287767b11..924129d7f9 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -90,8 +90,8 @@ bool iommufd_backend_get_device_info(IOMMUFDBackend *be, = uint32_t devid, bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t data_type, uint32_t data_len, - void *data_ptr, uint32_t *out_hwpt, - Error **errp); + void *data_ptr, uint32_t fault_id, + uint32_t *out_hwpt, Error **errp); bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, void *data_ptr, uint32_t data_len, diff --git a/backends/iommufd.c b/backends/iommufd.c index 9c56a7bcd6..3a8b587225 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -310,8 +310,8 @@ int iommufd_backend_unmap_dma(IOMMUFDBackend *be, uint3= 2_t ioas_id, bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t data_type, uint32_t data_len, - void *data_ptr, uint32_t *out_hwpt, - Error **errp) + void *data_ptr, uint32_t fault_id, + uint32_t *out_hwpt, Error **errp) { int ret, fd =3D be->fd; struct iommu_hwpt_alloc alloc_hwpt =3D { @@ -322,11 +322,12 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, u= int32_t dev_id, .data_type =3D data_type, .data_len =3D data_len, .data_uptr =3D (uintptr_t)data_ptr, + .fault_id =3D fault_id, }; =20 ret =3D ioctl(fd, IOMMU_HWPT_ALLOC, &alloc_hwpt); trace_iommufd_backend_alloc_hwpt(fd, dev_id, pt_id, flags, data_type, - data_len, (uintptr_t)data_ptr, + data_len, (uintptr_t)data_ptr, fault_= id, alloc_hwpt.out_hwpt_id, ret); if (ret) { error_setg_errno(errp, errno, "Failed to allocate hwpt"); diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 5e83dbd8ee..fe57ba5aef 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -268,7 +268,7 @@ smmuv3_accel_dev_alloc_translate(SMMUv3AccelDevice *acc= el_dev, STE *ste, accel->viommu->viommu_id, flags, IOMMU_HWPT_DATA_ARM_SMMUV3, sizeof(nested_data), &nested_data, - &hwpt_id, errp)) { + 0, &hwpt_id, errp)) { return NULL; } =20 @@ -622,14 +622,14 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *hiodi, if (!iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, viommu_i= d, 0, IOMMU_HWPT_DATA_ARM_SMMUV3, sizeof(abort_data), &abort_data, - &accel->abort_hwpt_id, errp)) { + 0, &accel->abort_hwpt_id, errp)) { goto free_viommu; } =20 if (!iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, viommu_i= d, 0, IOMMU_HWPT_DATA_ARM_SMMUV3, sizeof(bypass_data), &bypass_data, - &accel->bypass_hwpt_id, errp)) { + 0, &accel->bypass_hwpt_id, errp)) { goto free_abort_hwpt; } =20 diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index c03435f8a2..d2f41f18f1 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -94,7 +94,7 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hi= od, return iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, hiodi->hwpt_id, flags, IOMMU_HWPT_DATA_VTD_S1, sizeof(vtd),= &vtd, - fs_hwpt_id, errp); + 0, fs_hwpt_id, errp); } =20 static void vtd_destroy_old_fs_hwpt(VTDAccelPASIDCacheEntry *vtd_pce) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 68f2ae6f9f..24c4948b8c 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -451,7 +451,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, if (!iommufd_backend_alloc_hwpt(iommufd, vbasedev->devid, container->ioas_id, flags, IOMMU_HWPT_DATA_NONE, 0, NULL, - &hwpt_id, errp)) { + 0, &hwpt_id, errp)) { return false; } =20 diff --git a/backends/trace-events b/backends/trace-events index 1df3efb353..6ef7a9fee8 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -16,7 +16,7 @@ iommufd_backend_map_file_dma(int iommufd, uint32_t ioas, = uint64_t iova, uint64_t iommufd_backend_unmap_dma_non_exist(int iommufd, uint32_t ioas, uint64_t i= ova, uint64_t size, int ret) " Unmap nonexistent mapping: iommufd=3D%d ioas= =3D%d iova=3D0x%"PRIx64" size=3D0x%"PRIx64" (%d)" iommufd_backend_unmap_dma(int iommufd, uint32_t ioas, uint64_t iova, uint6= 4_t size, int ret) " iommufd=3D%d ioas=3D%d iova=3D0x%"PRIx64" size=3D0x%"P= RIx64" (%d)" iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) " iommufd=3D%d ioas= =3D%d" -iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, u= int32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_= t out_hwpt_id, int ret) " iommufd=3D%d dev_id=3D%u pt_id=3D%u flags=3D0x%x = hwpt_type=3D%u len=3D%u data_ptr=3D0x%"PRIx64" out_hwpt=3D%u (%d)" +iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, u= int32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_= t fault_id, uint32_t out_hwpt_id, int ret) " iommufd=3D%d dev_id=3D%u pt_id= =3D%u flags=3D0x%x hwpt_type=3D%u len=3D%u data_ptr=3D0x%"PRIx64" fault_id= =3D%u out_hwpt=3D%u (%d)" iommufd_backend_alloc_faultq(int iommufd, uint32_t fault_id, int fault_fd,= int ret) " iommufd=3D%d fault_id=3D%u fault_fd=3D%d (%d)" iommufd_backend_free_id(int iommufd, uint32_t id, int ret) " iommufd=3D%d = id=3D%d (%d)" iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" --=20 2.52.0 From nobody Sun Jul 26 12:32:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="82776844" X-IronPort-AV: E=Sophos;i="6.24,210,1774335600"; d="scan'208";a="82776844" X-CSE-ConnectionGUID: 7YCYG75TSu6ihYFnwbkTmw== X-CSE-MsgGUID: gVJzl0mTTNq0y5klxYf2yQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,210,1774335600"; d="scan'208";a="253352681" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v2 3/5] intel_iommu_accel: Add PRQ injection for passthrough device Date: Wed, 17 Jun 2026 23:48:41 -0400 Message-ID: <20260618034844.618011-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260618034844.618011-1-zhenzhong.duan@intel.com> References: <20260618034844.618011-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1781754616370158500 Content-Type: text/plain; charset="utf-8" When the guest enables the PRQ in vIOMMU, allocate a FAULTQ object so that host-side recoverable fault events can be received and propagated back to the guest. Install an event handler on the FAULTQ fd to read and propagate host generated recoverable fault events to the guest. The handler runs in QEMU's main loop, using a non-blocking fd registered via qemu_set_fd_handler(). Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.h | 2 + hw/i386/intel_iommu_accel.c | 161 ++++++++++++++++++++++++++++++++++-- hw/i386/trace-events | 1 + 3 files changed, 158 insertions(+), 6 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 4a9003c92d..d861f0f648 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -17,6 +17,8 @@ typedef struct VTDAccelPASIDCacheEntry { VTDPASIDEntry pasid_entry; uint32_t pasid; uint32_t fs_hwpt_id; + uint32_t fault_id; + int fault_fd; QLIST_ENTRY(VTDAccelPASIDCacheEntry) next; } VTDAccelPASIDCacheEntry; =20 diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index d2f41f18f1..fe09de07e2 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -9,6 +9,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "system/iommufd.h" #include "intel_iommu_internal.h" #include "intel_iommu_accel.h" @@ -16,6 +17,8 @@ #include "hw/pci/pci_bus.h" #include "trace.h" =20 +static PCIIOMMUOps *accel_ops; + bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp) { @@ -77,14 +80,148 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSp= ace *as) return NULL; } =20 -static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, - VTDPASIDEntry *pe, uint32_t *fs_hwpt_id, - Error **errp) +static void vtd_prq_report_fault(VTDAccelPASIDCacheEntry *vtd_pce, + struct iommu_hwpt_pgfault *fault, int cnt) +{ + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; + + for (; cnt--; fault++) { + bool last_page =3D fault->flags & IOMMU_PGFAULT_FLAGS_LAST_PAGE; + + accel_ops->pri_request_page(vtd_hiod->bus, vtd_hiod->iommu_state, + vtd_hiod->devfn, vtd_pce->pasid, + fault->perm & IOMMU_PGFAULT_PERM_PRIV, + fault->perm & IOMMU_PGFAULT_PERM_EXEC, + fault->addr, last_page, fault->grpid, + fault->perm & IOMMU_PGFAULT_PERM_READ, + fault->perm & IOMMU_PGFAULT_PERM_WRITE= ); + } +} + +/* Batch size per read(); remaining faults trigger another callback */ +#define FAULTQ_BUF_SIZE 100 + +static void vtd_prq_read_fault(void *opaque) +{ + VTDAccelPASIDCacheEntry *vtd_pce =3D opaque; + struct iommu_hwpt_pgfault fault[FAULTQ_BUF_SIZE]; + uint32_t id =3D vtd_pce->fault_id; + int fd =3D vtd_pce->fault_fd; + ssize_t bytes, last_bytes; + + bytes =3D read(fd, fault, sizeof(fault)); + trace_vtd_prq_read_fault(id, fd, bytes); + if (bytes < 0) { + if (errno !=3D EAGAIN && errno !=3D EINTR) { + error_report_once("FAULTQ(id %u): read failed (%m)", id); + } + return; + } else if (!bytes) { + error_report_once("FAULTQ(id %u): fault group too big", id); + return; + } + + last_bytes =3D bytes % sizeof(fault[0]); + if (last_bytes) { + error_report_once("FAULTQ(id %u): discard partial fault data: %zd/= %zu", + id, last_bytes, sizeof(fault)); + } + + vtd_prq_report_fault(vtd_pce, fault, bytes / sizeof(fault[0])); +} + +static void vtd_destroy_fs_faultq(VTDHostIOMMUDevice *vtd_hiod, + uint32_t fault_id, int fault_fd) +{ + HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); + + if (fault_fd < 0) { + return; + } + + close(fault_fd); + iommufd_backend_free_id(hiodi->iommufd, fault_id); +} + +static bool vtd_create_fs_faultq(VTDHostIOMMUDevice *vtd_hiod, + uint32_t *fault_id_p, int *fault_fd_p, + Error **errp) +{ + HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + uint8_t bus_n =3D pci_bus_num(vtd_hiod->bus); + uint32_t fault_id; + VTDContextEntry ce; + int flags, fault_fd; + + if (!s->svm || + vtd_dev_to_context_entry(s, bus_n, vtd_hiod->devfn, &ce) || + !VTD_CE_GET_PRE(&ce)) { + *fault_id_p =3D 0; + *fault_fd_p =3D -1; + return true; + } + + if (!iommufd_backend_alloc_faultq(hiodi->iommufd, &fault_id, &fault_fd, + errp)) { + return false; + } + + flags =3D fcntl(fault_fd, F_GETFL); + if (flags < 0) { + error_setg_errno(errp, errno, "Failed to get flags for FAULTQ fd"); + goto free_faultq; + } + + if (fcntl(fault_fd, F_SETFL, flags | O_NONBLOCK) < 0) { + error_setg_errno(errp, errno, "Failed to set O_NONBLOCK on FAULTQ = fd"); + goto free_faultq; + } + + *fault_id_p =3D fault_id; + *fault_fd_p =3D fault_fd; + return true; + +free_faultq: + vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd); + return false; +} + +static void vtd_destroy_old_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce) +{ + if (vtd_pce->fault_fd < 0) { + return; + } + + qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL); + vtd_destroy_fs_faultq(vtd_pce->vtd_hiod, vtd_pce->fault_id, + vtd_pce->fault_fd); + vtd_pce->fault_id =3D 0; + vtd_pce->fault_fd =3D -1; +} + +static void vtd_setup_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce, + uint32_t fault_id, int fault_fd) +{ + if (fault_fd < 0) { + return; + } + + vtd_pce->fault_id =3D fault_id; + vtd_pce->fault_fd =3D fault_fd; + qemu_set_fd_handler(fault_fd, vtd_prq_read_fault, NULL, vtd_pce); +} + +static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, VTDPASIDEntry= *pe, + bool has_fault_id, uint32_t fault_id, + uint32_t *fs_hwpt_id, Error **errp) { HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); struct iommu_hwpt_vtd_s1 vtd =3D {}; uint32_t flags =3D vtd_hiod->iommu_state->pasid ? IOMMU_HWPT_ALLOC_PAS= ID : 0; =20 + flags |=3D has_fault_id ? IOMMU_HWPT_FAULT_ID_VALID : 0; + vtd.flags =3D (VTD_SM_PASID_ENTRY_SRE(pe) ? IOMMU_VTD_S1_SRE : 0) | (VTD_SM_PASID_ENTRY_WPE(pe) ? IOMMU_VTD_S1_WPE : 0) | (VTD_SM_PASID_ENTRY_EAFE(pe) ? IOMMU_VTD_S1_EAFE : 0); @@ -94,7 +231,7 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_h= iod, return iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, hiodi->hwpt_id, flags, IOMMU_HWPT_DATA_VTD_S1, sizeof(vtd),= &vtd, - 0, fs_hwpt_id, errp); + fault_id, fs_hwpt_id, errp); } =20 static void vtd_destroy_old_fs_hwpt(VTDAccelPASIDCacheEntry *vtd_pce) @@ -115,7 +252,8 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCach= eEntry *vtd_pce, VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); VTDPASIDEntry *pe =3D &vtd_pce->pasid_entry; - uint32_t hwpt_id =3D hiodi->hwpt_id, pasid =3D vtd_pce->pasid; + uint32_t hwpt_id =3D hiodi->hwpt_id, pasid =3D vtd_pce->pasid, fault_i= d; + int fault_fd; bool ret; =20 /* @@ -130,7 +268,12 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCac= heEntry *vtd_pce, } =20 if (vtd_pe_pgtt_is_fst(pe)) { - if (!vtd_create_fs_hwpt(vtd_hiod, pe, &hwpt_id, errp)) { + if (!vtd_create_fs_faultq(vtd_hiod, &fault_id, &fault_fd, errp)) { + return false; + } + if (!vtd_create_fs_hwpt(vtd_hiod, pe, fault_fd >=3D 0, fault_id, + &hwpt_id, errp)) { + vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd); return false; } } @@ -140,11 +283,14 @@ static bool vtd_device_attach_iommufd(VTDAccelPASIDCa= cheEntry *vtd_pce, if (ret) { /* Destroy old fs_hwpt if it's a replacement */ vtd_destroy_old_fs_hwpt(vtd_pce); + vtd_destroy_old_fs_faultq(vtd_pce); if (vtd_pe_pgtt_is_fst(pe)) { vtd_pce->fs_hwpt_id =3D hwpt_id; + vtd_setup_fs_faultq(vtd_pce, fault_id, fault_fd); } } else if (vtd_pe_pgtt_is_fst(pe)) { iommufd_backend_free_id(hiodi->iommufd, hwpt_id); + vtd_destroy_fs_faultq(vtd_hiod, fault_id, fault_fd); } =20 return ret; @@ -177,6 +323,7 @@ static bool vtd_device_detach_iommufd(VTDAccelPASIDCach= eEntry *vtd_pce, =20 if (ret) { vtd_destroy_old_fs_hwpt(vtd_pce); + vtd_destroy_old_fs_faultq(vtd_pce); } =20 return ret; @@ -276,6 +423,7 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_h= iod, uint32_t pasid, vtd_pce->vtd_hiod =3D vtd_hiod; vtd_pce->pasid =3D pasid; vtd_pce->pasid_entry =3D *pe; + vtd_pce->fault_fd =3D -1; QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); =20 if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) { @@ -526,4 +674,5 @@ static uint64_t vtd_get_host_iommu_quirks(uint32_t type, void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops) { ops->get_host_iommu_quirks =3D vtd_get_host_iommu_quirks; + accel_ops =3D ops; } diff --git a/hw/i386/trace-events b/hw/i386/trace-events index a1dfade20f..5168e00ad8 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -77,6 +77,7 @@ vtd_reset_exit(void) "" vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, = int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_prq_read_fault(uint32_t fault_id, uint32_t fault_fd, ssize_t bytes) "f= ault_id %d fault_fd %d ret: %zd" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.52.0 From nobody Sun Jul 26 12:32:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="82776852" X-IronPort-AV: E=Sophos;i="6.24,210,1774335600"; d="scan'208";a="82776852" X-CSE-ConnectionGUID: jzcHC2UxR9KVCM+9fZxw+Q== X-CSE-MsgGUID: 0w905qVFTCalmrdZ52nS6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,210,1774335600"; d="scan'208";a="253352732" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v2 4/5] intel_iommu_accel: Accept PRQ response for passthrough device Date: Wed, 17 Jun 2026 23:48:42 -0400 Message-ID: <20260618034844.618011-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260618034844.618011-1-zhenzhong.duan@intel.com> References: <20260618034844.618011-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1781754597483158500 Content-Type: text/plain; charset="utf-8" Propagate guest's PRQ response to host by writing to fault_fd. Create a new VTDPRQEntry to cache cookie for each fault group, this cookie is used to mark the fault group on host side. Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.h | 12 +++++++ include/hw/i386/intel_iommu.h | 6 ++++ hw/i386/intel_iommu.c | 4 +++ hw/i386/intel_iommu_accel.c | 59 +++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 1 + 5 files changed, 82 insertions(+) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index d861f0f648..b508f05cde 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -19,6 +19,7 @@ typedef struct VTDAccelPASIDCacheEntry { uint32_t fs_hwpt_id; uint32_t fault_id; int fault_fd; + QLIST_HEAD(, VTDPRQEntry) vtd_prq_list; QLIST_ENTRY(VTDAccelPASIDCacheEntry) next; } VTDAccelPASIDCacheEntry; =20 @@ -31,6 +32,9 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s,= uint16_t domain_id, uint64_t npages, bool ih); void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info); void vtd_accel_pasid_cache_reset(IntelIOMMUState *s); +bool vtd_accel_propagate_page_group_response(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response); void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, @@ -69,6 +73,14 @@ static inline void vtd_accel_pasid_cache_reset(IntelIOMM= UState *s) { } =20 +static inline +bool vtd_accel_propagate_page_group_response(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response) +{ + return false; +} + static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops) { } diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 1842ba5840..5d44eac0ed 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -100,6 +100,12 @@ typedef struct VTDPASIDCacheEntry { bool valid; } VTDPASIDCacheEntry; =20 +typedef struct VTDPRQEntry { + uint32_t grpid; + uint32_t cookie; + QLIST_ENTRY(VTDPRQEntry) next; +} VTDPRQEntry; + struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 744cdfd2e6..2e867817aa 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3371,6 +3371,10 @@ static bool vtd_process_page_group_response_desc(Int= elIOMMUState *s, response.response_code =3D IOMMU_PRI_RESP_FAILURE; } =20 + if (vtd_accel_propagate_page_group_response(s, rid, pasid, &response))= { + return true; + } + if (vtd_dev_as->pri_notifier) { vtd_dev_as->pri_notifier->notify(vtd_dev_as->pri_notifier, &respon= se); } diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index fe09de07e2..9746355cd6 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -80,6 +80,57 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpac= e *as) return NULL; } =20 +static void vtd_prq_response_notify(VTDAccelPASIDCacheEntry *vtd_pce, + IOMMUPRIResponse *response) +{ + struct iommu_hwpt_page_response resp; + uint32_t id =3D vtd_pce->fault_id; + int fd =3D vtd_pce->fault_fd; + VTDPRQEntry *prqe, *tmp; + ssize_t bytes; + + QLIST_FOREACH_SAFE(prqe, &vtd_pce->vtd_prq_list, next, tmp) { + if (prqe->grpid !=3D response->prgi) { + continue; + } + + resp.cookie =3D prqe->cookie; + resp.code =3D response->response_code; + bytes =3D write(fd, &resp, sizeof(resp)); + trace_vtd_prq_response_notify(id, fd, resp.cookie, resp.code, byte= s); + if (bytes < 0) { + error_report_once("FAULTQ(id %u): write failed " + "[cookie 0x%x code 0x%x] (%m)", + id, resp.cookie, resp.code); + } + + QLIST_REMOVE(prqe, next); + g_free(prqe); + } +} + +bool vtd_accel_propagate_page_group_response(IntelIOMMUState *s, + uint16_t rid, uint32_t pasid, + IOMMUPRIResponse *response) +{ + VTDAddressSpace *vtd_as =3D vtd_get_as_by_sid(s, rid); + VTDAccelPASIDCacheEntry *vtd_pce; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); + + if (!vtd_hiod) { + return false; + } + + QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) { + if (vtd_pce->pasid =3D=3D pasid) { + vtd_prq_response_notify(vtd_pce, response); + return true; + } + } + + return false; +} + static void vtd_prq_report_fault(VTDAccelPASIDCacheEntry *vtd_pce, struct iommu_hwpt_pgfault *fault, int cnt) { @@ -95,6 +146,13 @@ static void vtd_prq_report_fault(VTDAccelPASIDCacheEntr= y *vtd_pce, fault->addr, last_page, fault->grpid, fault->perm & IOMMU_PGFAULT_PERM_READ, fault->perm & IOMMU_PGFAULT_PERM_WRITE= ); + if (last_page) { + VTDPRQEntry *prqe =3D g_malloc0(sizeof(*prqe)); + + prqe->grpid =3D fault->grpid; + prqe->cookie =3D fault->cookie; + QLIST_INSERT_HEAD(&vtd_pce->vtd_prq_list, prqe, next); + } } } =20 @@ -424,6 +482,7 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_h= iod, uint32_t pasid, vtd_pce->pasid =3D pasid; vtd_pce->pasid_entry =3D *pe; vtd_pce->fault_fd =3D -1; + QLIST_INIT(&vtd_pce->vtd_prq_list); QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); =20 if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 5168e00ad8..bbb2350f1d 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -78,6 +78,7 @@ vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, u= int32_t hwpt_id, int re vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" vtd_prq_read_fault(uint32_t fault_id, uint32_t fault_fd, ssize_t bytes) "f= ault_id %d fault_fd %d ret: %zd" +vtd_prq_response_notify(uint32_t fault_id, uint32_t fault_fd, uint32_t coo= kie, uint32_t code, ssize_t bytes) "fault_id %d fault_fd %d cookie %d code = %d ret: %zd" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.52.0 From nobody Sun Jul 26 12:32:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="82776859" X-IronPort-AV: E=Sophos;i="6.24,210,1774335600"; d="scan'208";a="82776859" X-CSE-ConnectionGUID: MkK1UpkbT0CfiztApv6ORA== X-CSE-MsgGUID: cfzU51jeTLCyVwNEipWiFg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,210,1774335600"; d="scan'208";a="253352777" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v2 5/5] intel_iommu_accel: teardown FAULTQ resources in bottom half Date: Wed, 17 Jun 2026 23:48:43 -0400 Message-ID: <20260618034844.618011-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260618034844.618011-1-zhenzhong.duan@intel.com> References: <20260618034844.618011-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1781754597401158500 Content-Type: text/plain; charset="utf-8" When a pasid entry becomes invalid, we need to release all resources allocated for that entry including FAULTQ object and fault_fd. We call qemu_set_fd_handler() to detach fault_fd's io_read handler and wakes up main thread from poll(), but there could still be a small window we call iommufd_backend_free_id(fault_id) before poll() exit and release fault_id file reference. In this rare case, FAULTQ object free return -EBUSY because opened fault_id file keeps reference of FAULTQ object. Teardown FAULTQ resources in bottom half to ensure poll() has released fault_id file reference. Suggested-by: Shameer Kolothum Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 9746355cd6..4857edbcce 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -245,15 +245,40 @@ free_faultq: return false; } =20 +typedef struct IOMMUFaultQueue { + IOMMUFDBackend *iommufd; + uint32_t id; + int fd; +} IOMMUFaultQueue; + +static void faultq_teardown_bh(void *opaque) +{ + IOMMUFaultQueue *fq =3D opaque; + + qemu_set_fd_handler(fq->fd, NULL, NULL, NULL); + close(fq->fd); + iommufd_backend_free_id(fq->iommufd, fq->id); + + g_free(fq); +} + static void vtd_destroy_old_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce) { + HostIOMMUDeviceIOMMUFD *idev =3D + HOST_IOMMU_DEVICE_IOMMUFD(vtd_pce->vtd_hiod->hiod); + if (vtd_pce->fault_fd < 0) { return; } =20 - qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL); - vtd_destroy_fs_faultq(vtd_pce->vtd_hiod, vtd_pce->fault_id, - vtd_pce->fault_fd); + IOMMUFaultQueue *fq =3D g_malloc(sizeof(IOMMUFaultQueue)); + fq->iommufd =3D idev->iommufd; + fq->fd =3D vtd_pce->fault_fd; + fq->id =3D vtd_pce->fault_id; + + aio_bh_schedule_oneshot(iohandler_get_aio_context(), + faultq_teardown_bh, fq); + vtd_pce->fault_id =3D 0; vtd_pce->fault_fd =3D -1; } --=20 2.52.0