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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716586198158500 Avoid including TCG-specific headers in non-TCG builds. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/internals.h | 4 +++- target/arm/cpu-irq.c | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f7a57d3ea70..fcce3804f34 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -29,9 +29,11 @@ #include "exec/vaddr.h" #include "exec/breakpoint.h" #include "exec/memop.h" +#ifdef CONFIG_TCG #include "accel/tcg/tb-cpu-state.h" -#include "hw/core/registerfields.h" #include "tcg/tcg-gvec-desc.h" +#endif +#include "hw/core/registerfields.h" #include "system/memory.h" #include "syndrome.h" #include "cpu-features.h" diff --git a/target/arm/cpu-irq.c b/target/arm/cpu-irq.c index fe514cc93af..883e8a176c3 100644 --- a/target/arm/cpu-irq.c +++ b/target/arm/cpu-irq.c @@ -8,10 +8,11 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "accel/tcg/cpu-ops.h" #include "internals.h" =20 #ifdef CONFIG_TCG +#include "accel/tcg/cpu-ops.h" + static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el, unsigned int cur_el, bool secure, --=20 2.53.0 From nobody Sun Jul 26 12:29:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781716554; cv=none; d=zohomail.com; s=zohoarc; b=Lym44TlOVctFIPey19FcDYAZrbT1vTMfrNhDPU7MHoPd5OjIjfq2FaB8eZ88stiLy3fD/XE+8bcENCHW8/Jccrsrl/GUeQlRAoC3lQUzu+8qJ7JOpNKEv8q+V9K2W5E5APBSSvodXoW8C2V3kTm0zpkjcC8q04aVYab7NU+o6Ao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781716554; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=paZaHfnqARyuzdyBchJ5nZVV2dKousWukxyV8h1bi4c=; b=mz7D0+JGVNLwjj3HgH8p0RVscEKULJTLZnx7E8Ykysnij8NUQ4wV+Pdm5d/XTcUBod4+bPY+nLDioHxYgZFd+sLxkx+/P+JijIq1B+zyeSb7cqgwZQEIKymwQ3zMBzZPtSwOthofB+GlWVMT4Ru5HUsYN6DJlgjfurI/D66WNn0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781716554980581.5149100652533; Wed, 17 Jun 2026 10:15:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZtrO-0000SR-4x; Wed, 17 Jun 2026 13:15:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtqs-0000GP-N2 for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:15:05 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtqq-0006aJ-MI for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:14:58 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65HFpKs23015136 for ; Wed, 17 Jun 2026 17:14:55 GMT Received: from mail-ua1-f72.google.com (mail-ua1-f72.google.com [209.85.222.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4euees4hbh-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 17 Jun 2026 17:14:55 +0000 (GMT) Received: by mail-ua1-f72.google.com with SMTP id a1e0cc1a2514c-966cf5e2a48so659693241.3 for ; Wed, 17 Jun 2026 10:14:55 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716556588158500 Rather than calling a TCG specific method in s390_ipl_reset_request(), have handle_diag_308() return whether a vCPU reset is pending, and use that in the TCG DIAG helper to return to the main loop. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/s390x/s390x-internal.h | 3 ++- hw/s390x/ipl.c | 5 ----- target/s390x/diag.c | 32 ++++++++++++++++---------------- target/s390x/tcg/misc_helper.c | 5 ++++- 4 files changed, 22 insertions(+), 23 deletions(-) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index e7e4f2b45d4..35d1e34ef4d 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -385,7 +385,8 @@ int mmu_translate_real(CPUS390XState *env, hwaddr raddr= , int rw, =20 /* misc_helper.c */ int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3); -void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, +/* Return whether a CPU reset is pending */ +bool handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra); =20 =20 diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index fa50749a7d3..4cca21c6217 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -18,7 +18,6 @@ #include "system/physmem.h" #include "system/reset.h" #include "system/runstate.h" -#include "system/tcg.h" #include "elf.h" #include "hw/core/loader.h" #include "hw/core/qdev-properties.h" @@ -690,10 +689,6 @@ void s390_ipl_reset_request(CPUState *cs, enum s390_re= set reset_type) } else { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } - /* as this is triggered by a CPU, make sure to exit the loop */ - if (tcg_enabled()) { - cpu_loop_exit(cs); - } } =20 void s390_ipl_get_reset_request(CPUState **cs, enum s390_reset *reset_type) diff --git a/target/s390x/diag.c b/target/s390x/diag.c index 01cc802eaed..80f09584789 100644 --- a/target/s390x/diag.c +++ b/target/s390x/diag.c @@ -95,7 +95,7 @@ static void s390_ipl_write(CPUS390XState *env, uint64_t a= ddr, } } =20 -void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr= _t ra) +bool handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr= _t ra) { bool valid; CPUState *cs =3D env_cpu(env); @@ -105,34 +105,34 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1,= uint64_t r3, uintptr_t ra) =20 if (env->psw.mask & PSW_MASK_PSTATE) { s390_program_interrupt(env, PGM_PRIVILEGED, ra); - return; + return false; } =20 if (subcode & ~0x0ffffULL) { s390_program_interrupt(env, PGM_SPECIFICATION, ra); - return; + return false; } =20 if (subcode >=3D DIAG308_PV_SET && !s390_has_feat(S390_FEAT_UNPACK)) { s390_program_interrupt(env, PGM_SPECIFICATION, ra); - return; + return false; } =20 switch (subcode) { case DIAG308_RESET_MOD_CLR: s390_ipl_reset_request(cs, S390_RESET_MODIFIED_CLEAR); - break; + return true; case DIAG308_RESET_LOAD_NORM: s390_ipl_reset_request(cs, S390_RESET_LOAD_NORMAL); - break; + return true; case DIAG308_LOAD_CLEAR: /* Well we still lack the clearing bit... */ s390_ipl_reset_request(cs, S390_RESET_REIPL); - break; + return true; case DIAG308_SET: case DIAG308_PV_SET: if (diag308_parm_check(env, r1, addr, ra, false)) { - return; + return false; } iplb =3D g_new0(IplParameterBlock, 1); s390_ipl_read(env, addr, iplb, sizeof(iplb->len)); @@ -159,11 +159,11 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1,= uint64_t r3, uintptr_t ra) env->regs[r1 + 1] =3D DIAG_308_RC_OK; out: g_free(iplb); - return; + return false; case DIAG308_STORE: case DIAG308_PV_STORE: if (diag308_parm_check(env, r1, addr, ra, true)) { - return; + return false; } if (subcode =3D=3D DIAG308_PV_STORE) { iplb =3D s390_ipl_get_iplb_pv(); @@ -172,30 +172,30 @@ out: } if (!iplb) { env->regs[r1 + 1] =3D DIAG_308_RC_NO_CONF; - return; + return false; } =20 s390_ipl_write(env, addr, iplb, be32_to_cpu(iplb->len)); env->regs[r1 + 1] =3D DIAG_308_RC_OK; - return; + return false; case DIAG308_PV_START: iplb =3D s390_ipl_get_iplb_pv(); if (!iplb) { env->regs[r1 + 1] =3D DIAG_308_RC_NO_PV_CONF; - return; + return false; } =20 if (kvm_enabled() && kvm_s390_get_hpage_1m()) { error_report("Protected VMs can currently not be backed with " "huge pages"); env->regs[r1 + 1] =3D DIAG_308_RC_INVAL_FOR_PV; - return; + return false; } =20 s390_ipl_reset_request(cs, S390_RESET_PV); - break; + return true; default: s390_program_interrupt(env, PGM_SPECIFICATION, ra); - break; + return false; } } diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 3d13c8bd8ea..036be93fb32 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -135,7 +135,10 @@ void HELPER(diag)(CPUS390XState *env, uint32_t r1, uin= t32_t r3, uint32_t num) case 0x308: /* ipl */ bql_lock(); - handle_diag_308(env, r1, r3, GETPC()); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716556529158500 Last commit removed the last non-TCG use of cpu_loop_exit(). This method is now only called within TCG files, so we can remove its stub for non-TCG accelerators. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/stubs/tcg-stub.c | 20 -------------------- accel/stubs/meson.build | 1 - 2 files changed, 21 deletions(-) delete mode 100644 accel/stubs/tcg-stub.c diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c deleted file mode 100644 index 855e5d43171..00000000000 --- a/accel/stubs/tcg-stub.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * QEMU TCG accelerator stub - * - * Copyright Red Hat, Inc. 2013 - * - * Author: Paolo Bonzini - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include "system/tcg.h" -#include "exec/cpu-common.h" - -G_NORETURN void cpu_loop_exit(CPUState *cpu) -{ - g_assert_not_reached(); -} diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build index ccad583e647..7c6d7ad9432 100644 --- a/accel/stubs/meson.build +++ b/accel/stubs/meson.build @@ -4,7 +4,6 @@ stub_ss.add(files( 'nitro-stub.c', 'mshv-stub.c', 'nvmm-stub.c', - 'tcg-stub.c', 'whpx-stub.c', 'xen-stub.c', )) --=20 2.53.0 From nobody Sun Jul 26 12:29:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781716625; cv=none; d=zohomail.com; s=zohoarc; b=ZTBgV+IxSoiUaOP5gWEtHCDQ1NAzpE7a+KRzz5Vyp/TaWdmVrt6q2Sf+2V0BsX0KzA12QYE2nQGzAHMWDh5ZQ9p7C+1R5mpeFRt6WqEdqPpjjgHONyZHLauF5IRExe8Vyffm0Ba3960JKxkZgDQ3h+u3LKe3ZWwOmkap3Xv/c4Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781716625; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=shBZaHEVi8dZt+d608wg6Iz3OCSBoWL8lHFLUYL6pVo=; b=H+Ntctc3tI24LJPrjoRedG9mIrrghbh8oNN/RGHt/pmebfH44kPEQEG7e6jmSXI0cuzxErnVtWCVG2MNIUwhHl/rUnDNIkFsD/12y7azySwOff+TJwhbzKsmRKOGwjFqbCLOHFaT4gmEVI6tV0np8MPb77oKQPsMSIgLD2SEhVY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781716625795761.7797507239903; Wed, 17 Jun 2026 10:17:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZtrf-0000Xy-6v; Wed, 17 Jun 2026 13:15:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtr6-0000Iy-UK for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:15:22 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtr4-0006pf-CU for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:15:11 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65HFokNO3212085 for ; Wed, 17 Jun 2026 17:15:09 GMT Received: from mail-ua1-f70.google.com (mail-ua1-f70.google.com [209.85.222.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4eueerck4t-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 17 Jun 2026 17:15:09 +0000 (GMT) Received: by mail-ua1-f70.google.com with SMTP id a1e0cc1a2514c-963d7e5ac77so2618141241.2 for ; Wed, 17 Jun 2026 10:15:09 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716626455158501 In order to keep TCG-specific functions under a TCG API namespace, add the "accel/tcg/cpu-loop.h" header and move cpu_exec() declaration to it. Add a bit of documentation. Include "accel/tcg/cpu-loop.h" where appropriate. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- bsd-user/freebsd/os-proc.h | 1 + include/accel/tcg/cpu-loop.h | 16 ++++++++++++++++ include/exec/cpu-common.h | 3 --- include/user/cpu_loop.h | 2 +- accel/tcg/cpu-exec.c | 1 + accel/tcg/tcg-accel-ops.c | 1 + bsd-user/main.c | 1 + 7 files changed, 21 insertions(+), 4 deletions(-) create mode 100644 include/accel/tcg/cpu-loop.h diff --git a/bsd-user/freebsd/os-proc.h b/bsd-user/freebsd/os-proc.h index 72ccf23e17e..1cf3c43de34 100644 --- a/bsd-user/freebsd/os-proc.h +++ b/bsd-user/freebsd/os-proc.h @@ -14,6 +14,7 @@ #include #include =20 +#include "accel/tcg/cpu-loop.h" #include "target_arch_cpu.h" =20 pid_t safe_wait4(pid_t wpid, int *status, int options, struct rusage *rusa= ge); diff --git a/include/accel/tcg/cpu-loop.h b/include/accel/tcg/cpu-loop.h new file mode 100644 index 00000000000..528adb5588c --- /dev/null +++ b/include/accel/tcg/cpu-loop.h @@ -0,0 +1,16 @@ +#ifndef ACCEL_TCG_CPU_LOOP_COMMON_H +#define ACCEL_TCG_CPU_LOOP_COMMON_H + +#ifndef CONFIG_TCG +#error Can only include this header with TCG +#endif + +/** + * cpu_exec: + * @cpu: the cpu context + * + * Returns one of the EXCP_* definitions (see "exec/cpu-common.h"). + */ +int cpu_exec(CPUState *cpu); + +#endif diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 883389b0abf..ac3ab0e1cdf 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -114,9 +114,6 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, ui= ntptr_t pc); #endif /* CONFIG_TCG */ G_NORETURN void cpu_loop_exit(CPUState *cpu); =20 -/* accel/tcg/cpu-exec.c */ -int cpu_exec(CPUState *cpu); - /** * env_archcpu(env) * @env: The architecture environment diff --git a/include/user/cpu_loop.h b/include/user/cpu_loop.h index 346e37ede8b..c9d49398f01 100644 --- a/include/user/cpu_loop.h +++ b/include/user/cpu_loop.h @@ -22,7 +22,7 @@ =20 #include "exec/vaddr.h" #include "exec/mmu-access-type.h" - +#include "accel/tcg/cpu-loop.h" =20 /** * adjust_signal_pc: diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 7292ff15060..9c754b03656 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -22,6 +22,7 @@ #include "qapi/error.h" #include "qapi/type-helpers.h" #include "hw/core/cpu.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/helper-retaddr.h" #include "trace.h" diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 3bd98005042..c179cd4adeb 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -28,6 +28,7 @@ #include "qemu/osdep.h" #include "accel/accel-ops.h" #include "accel/accel-cpu-ops.h" +#include "accel/tcg/cpu-loop.h" #include "system/tcg.h" #include "system/replay.h" #include "exec/icount.h" diff --git a/bsd-user/main.c b/bsd-user/main.c index 73aae8c3274..4f1544342eb 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -39,6 +39,7 @@ #include "user/guest-base.h" #include "user/page-protection.h" #include "accel/accel-ops.h" +#include "accel/tcg/cpu-loop.h" #include "tcg/startup.h" #include "qemu/timer.h" #include "qemu/envlist.h" --=20 2.53.0 From nobody Sun Jul 26 12:29:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 17 Jun 2026 10:15:15 -0700 (PDT) X-Received: by 2002:a05:6102:f0f:b0:631:2dc6:2f5c with SMTP id ada2fe7eead31-7245a1ee5f3mr2833408137.0.1781716515142; Wed, 17 Jun 2026 10:15:15 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson Subject: [PATCH v2 05/11] accel/tcg: Move cpu_exec_step_atomic() out of 'exec/cpu-common.h' Date: Wed, 17 Jun 2026 19:14:32 +0200 Message-ID: <20260617171438.75914-6-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260617171438.75914-1-philmd@oss.qualcomm.com> References: <20260617171438.75914-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: h138AydSQPMfOZHyaa9IsWsGpOojvjDa X-Proofpoint-GUID: h138AydSQPMfOZHyaa9IsWsGpOojvjDa X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDE2NiBTYWx0ZWRfX3N+erViZlcjo 5T5I1vhk1h34e/4KmfaXqVzgctHaCL8fJRpw/OPPZnUNFN8TCTzv72UnNehrf6bLBChQncsWGki yy5RgXgUhz3crQiT0Zjby/cGTORAYm/CTf5qJxCi1iB12PivqpbZ0kC6PbTenumc38aKl6TzsNN BSa4sFuGSpqXSW35dW7umrgJRhohoQLxWY/BzWNR+MbNUfzuIP5ASMtFC/Qo+oIiBq44z+eqRar zIcDsEP+kr6ZGphKn+G+d/qmwjLCEgUW41li5AySuawWT3HO+FtoM2drx3nTMbUwLAez4tlvW1v LYZLa7xtiDuhze2GOt++X4j5+mZlIWVtJeDksIYuSoZuQsVLccAISzWYQkkwb/FOWkjmngpjJv0 JYA41haWJyUD/LoUpPbbCknn2ioEL77WuAlHFLkYBk/HjPTjsiZobuFRTbLDN7YfUCHvc4DDTXH e/vkpX9l80gTUTGwm1g== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDE2NiBTYWx0ZWRfX1mOaNCX/TuCI o+LZmmEkl9BfmyvgI20f8UhXRFx8yrQeeiH7X17x609jiV/6D40mL0Q11S1PA+iw7dcRNfQZN9O P7O3neF56cJ4NMunW3RGM0NNpjlVB6g= X-Authority-Analysis: v=2.4 cv=YJKvDxGx c=1 sm=1 tr=0 ts=6a32d624 cx=c_pps a=R6oCqFB+Yf/t2GF8e0/dFg==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=xWu8-Agft_6X_INOG6MA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=TD8TdBvy0hsOASGTdmB-:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-17_02,2026-06-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 adultscore=0 impostorscore=0 clxscore=1015 suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606170166 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716560977158500 Move the TCG-specific cpu_exec_step_atomic() declaration out of the generic "exec/cpu-common.h" header, to the recently created "accel/tcg/cpu-loop.h" one. Include "accel/tcg/cpu-loop.h" where appropriate. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-loop.h | 2 ++ include/exec/cpu-common.h | 2 -- accel/tcg/tcg-accel-ops-mttcg.c | 1 + accel/tcg/tcg-accel-ops-rr.c | 1 + 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/accel/tcg/cpu-loop.h b/include/accel/tcg/cpu-loop.h index 528adb5588c..d8a5f98f9cf 100644 --- a/include/accel/tcg/cpu-loop.h +++ b/include/accel/tcg/cpu-loop.h @@ -13,4 +13,6 @@ */ int cpu_exec(CPUState *cpu); =20 +void cpu_exec_step_atomic(CPUState *cpu); + #endif diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index ac3ab0e1cdf..ea9a49a1435 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -21,8 +21,6 @@ #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another= */ #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ =20 -void cpu_exec_step_atomic(CPUState *cpu); - #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_si= ze()) =20 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index 4160e2ba947..69560fdb9d8 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -32,6 +32,7 @@ #include "qemu/notify.h" #include "qemu/guest-random.h" #include "hw/core/boards.h" +#include "accel/tcg/cpu-loop.h" #include "tcg/startup.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index f84342e0449..5b132d3d5d8 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -32,6 +32,7 @@ #include "qemu/notify.h" #include "qemu/guest-random.h" #include "exec/cpu-common.h" +#include "accel/tcg/cpu-loop.h" #include "tcg/startup.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-rr.h" --=20 2.53.0 From nobody Sun Jul 26 12:29:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781716595; cv=none; d=zohomail.com; s=zohoarc; b=WaqkK4X6OT1By9kY8HmOj6dwtsnbeSCnUDOexotpdJywQh4mv2Jk+O6bxVHLlnqt2+0W9ERi0kar/Jwdz8tFLqPUrNOhxmgJ98ZPVT4hV8Xr9HUY67nQ9miLoQkKmgJvnIQpP+jAU0RlNUJ0RqN2THRdeOhqSbhInzp2Y/lKUto= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781716595; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ulJUzi3X4qrPHf09McK6t5ZuFBWvi0xGnqqU2jl+eZY=; b=dGND0svGK8GhtAkFjfr/ueo0+Kz5+nZw3dkYk0F1MLYe+9cN4pKYrWj0azWFKm5HN0vnMXOoTLuHVUgkh27gnPUD/iLqeAw02GFgqQMMTjLrG+V7tl2JQMpTwoL1aDOJVZAME07eQVkNiEwDEC9WDSlgikLKMGSPg3cvl5+lutI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781716595670737.0371760682292; Wed, 17 Jun 2026 10:16:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZtrg-0000YB-Bc; Wed, 17 Jun 2026 13:15:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtrN-0000Tu-0k for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:15:30 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtrL-0006wU-3h for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:15:28 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65HFoXOE083400 for ; Wed, 17 Jun 2026 17:15:25 GMT Received: from mail-ua1-f69.google.com (mail-ua1-f69.google.com [209.85.222.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4euw9vh15q-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 17 Jun 2026 17:15:25 +0000 (GMT) Received: by mail-ua1-f69.google.com with SMTP id a1e0cc1a2514c-966c4d68d91so733885241.2 for ; Wed, 17 Jun 2026 10:15:25 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716596547158500 Move the TCG-specific cpu_unwind_state_data() declaration out of the generic "exec/cpu-common.h" header, to the recently created "accel/tcg/cpu-loop.h" one. Include "accel/tcg/cpu-loop.h" where appropriate. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-loop.h | 13 +++++++++++++ include/exec/cpu-common.h | 13 ------------- accel/tcg/translate-all.c | 1 + target/i386/helper.c | 1 + target/or1k/sys_helper.c | 1 + target/riscv/csr.c | 1 + 6 files changed, 17 insertions(+), 13 deletions(-) diff --git a/include/accel/tcg/cpu-loop.h b/include/accel/tcg/cpu-loop.h index d8a5f98f9cf..f328aaa0377 100644 --- a/include/accel/tcg/cpu-loop.h +++ b/include/accel/tcg/cpu-loop.h @@ -15,4 +15,17 @@ int cpu_exec(CPUState *cpu); =20 void cpu_exec_step_atomic(CPUState *cpu); =20 +/** + * cpu_unwind_state_data: + * @cpu: the cpu context + * @host_pc: the host pc within the translation + * @data: output data + * + * Attempt to load the unwind state for a host pc occurring in + * translated code. If @host_pc is not in translated code, the + * function returns false; otherwise @data is loaded. + * This is the same unwind info as given to restore_state_to_opc. + */ +bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *dat= a); + #endif diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index ea9a49a1435..ba98304c5fa 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -64,19 +64,6 @@ void list_cpus(void); #ifdef CONFIG_TCG #include "qemu/atomic.h" =20 -/** - * cpu_unwind_state_data: - * @cpu: the cpu context - * @host_pc: the host pc within the translation - * @data: output data - * - * Attempt to load the unwind state for a host pc occurring in - * translated code. If @host_pc is not in translated code, the - * function returns false; otherwise @data is loaded. - * This is the same unwind info as given to restore_state_to_opc. - */ -bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *dat= a); - /** * cpu_restore_state: * @cpu: the cpu context diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 05d9ce512a4..78c560c7980 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -29,6 +29,7 @@ #include "qemu/target-info.h" #include "exec/log.h" #include "exec/icount.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-ops.h" #include "tb-jmp-cache.h" #include "tb-hash.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index c3cba04e142..68362141621 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -32,6 +32,7 @@ #endif #include "qemu/log.h" #ifdef CONFIG_TCG +#include "accel/tcg/cpu-loop.h" #include "tcg/insn-start-words.h" #endif =20 diff --git a/target/or1k/sys_helper.c b/target/or1k/sys_helper.c index ca627bd7194..8ffa31b84fd 100644 --- a/target/or1k/sys_helper.c +++ b/target/or1k/sys_helper.c @@ -23,6 +23,7 @@ #include "exec/cputlb.h" #include "exec/target_page.h" #include "exec/helper-proto.h" +#include "accel/tcg/cpu-loop.h" #include "exception.h" #ifndef CONFIG_USER_ONLY #include "hw/core/boards.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5514e0f455f..de583396f29 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -26,6 +26,7 @@ #include "time_helper.h" #include "exec/cputlb.h" #include "exec/icount.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/getpc.h" #include "qemu/guest-random.h" #include "qapi/error.h" --=20 2.53.0 From nobody Sun Jul 26 12:29:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781716581; cv=none; d=zohomail.com; s=zohoarc; b=Itzaf3SyM4zPK+EC+PMoRmDCtA6cnkQSu+/kt0IUQQTC+QnZrb2HFPto2RmR1Y4Vuw8GZabGeKg/fupkjBqrsn6eOheCL4lCC91YjCyQDqsIMR5a8DLH2w8v7dmAp0tlNsS8mpA7MOHvv31WL7A8FCHlo0KD1GeiiwCORflUcBk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781716581; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SYTycsYV8IBDgqm0YFuqjeDvuJkqJsQvzubIvsOiL5w=; b=nU9cAbcKExuraIxiJJ/DjQRgYBO+vwRGynE3GQsYws6zhO7A+2ZdWrAKim7dhUbvnx4Ml1e9AUVKxj7vBsz52stsN4oPXxCSu0hIDpD2i/pYp+2/6nuQijqBAiXxdHCGQte7iTKa3O/Huz3A5OnClp05sBT3UEC34gRBnaQ6KXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781716581904961.3508183555299; Wed, 17 Jun 2026 10:16:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZtrh-0000Yq-2Z; Wed, 17 Jun 2026 13:15:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtrU-0000Us-0z for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:15:36 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtrR-0006yj-QB for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:15:35 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65HFoULd2731330 for ; Wed, 17 Jun 2026 17:15:32 GMT Received: from mail-ua1-f72.google.com (mail-ua1-f72.google.com [209.85.222.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4eux2c8pd5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 17 Jun 2026 17:15:32 +0000 (GMT) Received: by mail-ua1-f72.google.com with SMTP id a1e0cc1a2514c-963d24c3886so5012252241.0 for ; Wed, 17 Jun 2026 10:15:32 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716584242158500 Move the TCG-specific cpu_restore_state() declaration out of the generic "exec/cpu-common.h" header, to the recently created "accel/tcg/cpu-loop.h" one. Include "accel/tcg/cpu-loop.h" where appropriate. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-loop.h | 12 ++++++++++++ include/exec/cpu-common.h | 12 ------------ accel/tcg/cpu-exec-common.c | 1 + accel/tcg/user-exec.c | 1 + target/alpha/helper.c | 1 + target/alpha/mem_helper.c | 1 + target/arm/tcg/op_helper.c | 1 + target/arm/tcg/tlb_helper.c | 1 + target/hppa/cpu.c | 1 + target/hppa/mem_helper.c | 1 + target/hppa/op_helper.c | 1 + target/i386/tcg/system/svm_helper.c | 1 + target/m68k/op_helper.c | 1 + target/microblaze/helper.c | 1 + target/ppc/tcg-excp_helper.c | 1 + target/s390x/tcg/excp_helper.c | 1 + target/sh4/op_helper.c | 1 + target/tricore/op_helper.c | 1 + target/xtensa/helper.c | 1 + 19 files changed, 29 insertions(+), 12 deletions(-) diff --git a/include/accel/tcg/cpu-loop.h b/include/accel/tcg/cpu-loop.h index f328aaa0377..2fc38c8f1c4 100644 --- a/include/accel/tcg/cpu-loop.h +++ b/include/accel/tcg/cpu-loop.h @@ -28,4 +28,16 @@ void cpu_exec_step_atomic(CPUState *cpu); */ bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *dat= a); =20 +/** + * cpu_restore_state: + * @cpu: the cpu context + * @host_pc: the host pc within the translation + * @return: true if state was restored, false otherwise + * + * Attempt to restore the state for a fault occurring in translated + * code. If @host_pc is not in translated code no state is + * restored and the function returns false. + */ +bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); + #endif diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index ba98304c5fa..3757ab15967 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -64,18 +64,6 @@ void list_cpus(void); #ifdef CONFIG_TCG #include "qemu/atomic.h" =20 -/** - * cpu_restore_state: - * @cpu: the cpu context - * @host_pc: the host pc within the translation - * @return: true if state was restored, false otherwise - * - * Attempt to restore the state for a fault occurring in translated - * code. If @host_pc is not in translated code no state is - * restored and the function returns false. - */ -bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); - /** * cpu_loop_exit_requested: * @cpu: The CPU state to be tested diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index c5c513f1e4a..e48ea31373f 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -21,6 +21,7 @@ #include "exec/log.h" #include "system/tcg.h" #include "qemu/plugin.h" +#include "accel/tcg/cpu-loop.h" #include "internal-common.h" =20 bool tcg_allowed; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index d283d3cc724..7704e4017dd 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -25,6 +25,7 @@ #include "qemu/bitops.h" #include "qemu/rcu.h" #include "accel/tcg/cpu-ldst-common.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "user/cpu_loop.h" diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 2abf07c1919..c3614ecafda 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -28,6 +28,7 @@ #include "exec/helper-proto.h" #include "qemu/qemu-print.h" #include "system/memory.h" +#include "accel/tcg/cpu-loop.h" #include "qemu/plugin.h" =20 =20 diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 572ea9cb418..b3988417e4b 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" =20 static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t = retaddr) { diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 504526153a6..9f9ea39be5a 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -23,6 +23,7 @@ #include "helper.h" #include "internals.h" #include "cpu-features.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/probe.h" #include "cpregs.h" =20 diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index f90765cb597..2ce63734099 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "helper.h" +#include "accel/tcg/cpu-loop.h" #include "internals.h" #include "cpu-features.h" =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6443122cf1a..a68152f9682 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -29,6 +29,7 @@ #include "fpu/softfloat.h" #include "tcg/tcg.h" #include "hw/hppa/hppa_hardware.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-ops.h" =20 static void hppa_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index f5076492264..01e6149c811 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/cputlb.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-mmu-index.h" #include "accel/tcg/probe.h" #include "exec/page-protection.h" diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index f961046e4c5..76a8d8a0d34 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/probe.h" #include "qemu/timer.h" #include "trace.h" diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/s= vm_helper.c index d5ffabc2f4d..52a234e7fac 100644 --- a/target/i386/tcg/system/svm_helper.c +++ b/target/i386/tcg/system/svm_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "tcg/helper-tcg.h" =20 /* Secure Virtual Machine helpers */ diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 8148a8852e7..38f7a689814 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "semihosting/semihost.h" #include "qemu/plugin.h" =20 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 6a982c18c0f..05a90f5ecb2 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cputlb.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "exec/target_page.h" diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 5e6c1e326d4..b04f07a6377 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "target/ppc/cpu.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "exec/helper-proto.h" #include "system/runstate.h" =20 diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 05e448d3f20..d952bb20cf1 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "exec/cputlb.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-loop.h" #include "s390x-internal.h" #include "tcg_s390x.h" #ifndef CONFIG_USER_ONLY diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index cf0f80e4a54..90c065b217b 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "fpu/softfloat.h" =20 #ifndef CONFIG_USER_ONLY diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 3cff5000c73..46b17da2bc6 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -19,6 +19,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "qemu/plugin.h" #include /* for crc32 */ =20 diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 2d93b45036d..5a0e8655146 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -32,6 +32,7 @@ #include "exec/target_page.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" +#include "accel/tcg/cpu-loop.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "qemu/host-utils.h" --=20 2.53.0 From nobody Sun Jul 26 12:29:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781716639; cv=none; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716640484158500 Since the CPUState argument is simply read-only accessed, make it const. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 3757ab15967..9919ffb1838 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -76,7 +76,7 @@ void list_cpus(void); * call can be used to check if it makes sense to return to the main loop * or to continue executing the interruptible instruction. */ -static inline bool cpu_loop_exit_requested(CPUState *cpu) +static inline bool cpu_loop_exit_requested(const CPUState *cpu) { return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0; } --=20 2.53.0 From nobody Sun Jul 26 12:29:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781716624; cv=none; d=zohomail.com; s=zohoarc; b=ZfpgROxAzmPQP62/K8zbfCpNAtgIhil/OMTfguP6uSgbVvbzZ7/K0oy7KZv+7jxtr857Fcx/pge5wF7+fgdcruj2eTLdC+soMuSBbZY4yMA3AMtUIanSQqt2vcOMpatLHKXZBC9pOJU7nCNKURtReAfK6MAhol5cfGnqYjm490o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781716624; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=r/Vk/6apucM4nBt03xY1qhRC+Z5fpGBh/10BnHaz5YI=; b=a7TRckmrJrWedTag8wlUbnN3VJDqRWg23CfTs82WAVZYwW21e08xHRMUexo/ujUygw/8jL5eYxukdl8hD4DFwA+rlEJSioywS1y1RQrDYkwsNBr7F5SJ3D/TreTKImULagJ2Jjv1BcnWLXo02LQRrc7Nxt1c5y3fZ8h6VXYyOGo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781716624719319.2208498567529; Wed, 17 Jun 2026 10:17:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZtri-0000ZQ-Oo; Wed, 17 Jun 2026 13:15:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtrg-0000YV-JP for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:15:48 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtre-00075g-N2 for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:15:48 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65HHAjeN3446894 for ; Wed, 17 Jun 2026 17:15:45 GMT Received: from mail-ua1-f69.google.com (mail-ua1-f69.google.com [209.85.222.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4eux2jrpub-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 17 Jun 2026 17:15:45 +0000 (GMT) Received: by mail-ua1-f69.google.com with SMTP id a1e0cc1a2514c-966d2fd33b1so565576241.2 for ; Wed, 17 Jun 2026 10:15:45 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716626440158500 cpu_loop_exit_requested() is part of the TCG cpu-loop API, defined in "accel/tcg/cpu-loop.h". Ideally we'd move it declaration there, but it is defined inlined and access CPUState internal fields, itself defined in "hw/core/cpu.h". Since keeping it inlined in the 3 call sites is important, move the definition to "hw/core/cpu.h" and call it a day. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-common.h | 19 ------------------- include/hw/core/cpu.h | 20 ++++++++++++++++++++ target/arm/tcg/helper-a64.c | 1 + target/s390x/tcg/mem_helper.c | 1 + 4 files changed, 22 insertions(+), 19 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 9919ffb1838..aedd60a6986 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -62,25 +62,6 @@ void cpu_destroy_address_spaces(CPUState *cpu); void list_cpus(void); =20 #ifdef CONFIG_TCG -#include "qemu/atomic.h" - -/** - * cpu_loop_exit_requested: - * @cpu: The CPU state to be tested - * - * Indicate if somebody asked for a return of the CPU to the main loop - * (e.g., via cpu_exit() or cpu_interrupt()). - * - * This is helpful for architectures that support interruptible - * instructions. After writing back all state to registers/memory, this - * call can be used to check if it makes sense to return to the main loop - * or to continue executing the interruptible instruction. - */ -static inline bool cpu_loop_exit_requested(const CPUState *cpu) -{ - return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0; -} - G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 72666189774..eaf30d13e8e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -612,6 +612,26 @@ static inline CPUTLBDescFast *cpu_tlb_fast(CPUState *c= pu, int mmu_idx) { return &cpu->neg.tlb.f[mmuidx_to_fast_index(mmu_idx)]; } + +#include "qemu/atomic.h" + +/** + * cpu_loop_exit_requested: + * @cpu: The CPU state to be tested + * + * Indicate if somebody asked for a return of the CPU to the main loop + * (e.g., via cpu_exit() or cpu_interrupt()). + * + * This is helpful for architectures that support interruptible + * instructions. After writing back all state to registers/memory, this + * call can be used to check if it makes sense to return to the main loop + * or to continue executing the interruptible instruction. + */ +static inline bool cpu_loop_exit_requested(const CPUState *cpu) +{ + return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0; +} + #endif =20 typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index a0f9215f1c9..cdac560d086 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -43,6 +43,7 @@ #include "user/page-protection.h" #endif #include "vec_internal.h" +#include "hw/core/cpu.h" =20 #define HELPER_H "tcg/helper-a64-defs.h" #include "exec/helper-info.c.inc" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 8474a694110..bfe0208324c 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -43,6 +43,7 @@ #include "hw/core/boards.h" #include "system/memory.h" #endif +#include "hw/core/cpu.h" =20 #ifdef CONFIG_USER_ONLY # define user_or_likely(X) true --=20 2.53.0 From nobody Sun Jul 26 12:29:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781716642; cv=none; d=zohomail.com; s=zohoarc; b=V/3/81m7J+rBt7gw8QaiTqdCu/h5VH/N6jWJKYMoSEDcmlrCUm5h58wvtIDTNVxFtUy5A9iX0QlKk6GnjEsT5tWRu/CowyTZqAXczf8HBpgD/nAhgZrlO/rWditWoAS9wP2TbHlgKpVqPER8fKfNo+6/f0SH2ja4QNXIiaAV5mg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781716642; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PtKLf+JLfWQC0nqpMAHw1zZfvB9sJ/wLTHK66olaC2Y=; b=dwQoVgKD9ql5SXXC8Hm+6BJesbMMXqN/60Z8WRMJQ5Id6j2s56B4DFvTD3L1TYMjQeg/i11vtjJRnmAe0FCHnnzcFDSYoDWwIJl4m0BEN5IXstjRhL53R6IgP5AfmoKobBXJ+OqxnmUAaoKULJWeRMaAhztLvDWJIV0KhXh6S0s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781716642117435.07128382097346; Wed, 17 Jun 2026 10:17:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZts8-0000kh-Si; Wed, 17 Jun 2026 13:16:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtrs-0000gU-D4 for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:16:09 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZtro-00078o-2Z for qemu-devel@nongnu.org; Wed, 17 Jun 2026 13:15:59 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65HFpLEr3015154 for ; Wed, 17 Jun 2026 17:15:55 GMT Received: from mail-vs1-f72.google.com (mail-vs1-f72.google.com [209.85.217.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4euees4hfy-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 17 Jun 2026 17:15:54 +0000 (GMT) Received: by mail-vs1-f72.google.com with SMTP id ada2fe7eead31-6751c50552dso13426137.2 for ; Wed, 17 Jun 2026 10:15:54 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716642897158500 Move the following TCG-specific cpu_loop_exit_*() declarations out of the generic "exec/cpu-common.h" header, to the recently created "accel/tcg/cpu-loop.h" one, documenting them: - cpu_loop_exit_noexc() - cpu_loop_exit_atomic() - cpu_loop_exit_restore() - cpu_loop_exit() Include "accel/tcg/cpu-loop.h" where appropriate. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-loop.h | 30 ++++++++++++++++++++++++++++ include/exec/cpu-common.h | 7 ------- accel/tcg/cputlb.c | 1 + accel/tcg/tb-maint.c | 1 + accel/tcg/tcg-runtime.c | 1 + accel/tcg/watchpoint.c | 1 + hw/misc/mips_itu.c | 1 + plugins/api.c | 1 + semihosting/console.c | 1 + target/arm/tcg/helper-a64.c | 1 + target/avr/helper.c | 1 + target/hexagon/op_helper.c | 1 + target/i386/tcg/excp_helper.c | 1 + target/i386/tcg/misc_helper.c | 1 + target/i386/tcg/system/bpt_helper.c | 1 + target/i386/tcg/system/misc_helper.c | 1 + target/i386/tcg/user/excp_helper.c | 1 + target/i386/tcg/user/seg_helper.c | 1 + target/loongarch/tcg/tcg_cpu.c | 1 + target/loongarch/tcg/tlb_helper.c | 1 + target/m68k/helper.c | 1 + target/microblaze/op_helper.c | 1 + target/mips/tcg/exception.c | 1 + target/mips/tcg/system/tlb_helper.c | 1 + target/or1k/exception_helper.c | 1 + target/or1k/fpu_helper.c | 1 + target/or1k/mmu.c | 1 + target/ppc/user_only_helper.c | 1 + target/riscv/cpu_helper.c | 1 + target/riscv/op_helper.c | 1 + target/rx/op_helper.c | 1 + target/s390x/mmu_helper.c | 3 +++ target/s390x/tcg/cc_helper.c | 1 + target/s390x/tcg/debug.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/s390x/tcg/misc_helper.c | 1 + target/sh4/helper.c | 1 + target/sparc/helper.c | 1 + target/sparc/mmu_helper.c | 1 + target/tricore/helper.c | 1 + target/xtensa/exc_helper.c | 1 + 41 files changed, 71 insertions(+), 7 deletions(-) diff --git a/include/accel/tcg/cpu-loop.h b/include/accel/tcg/cpu-loop.h index 2fc38c8f1c4..8559e99efaf 100644 --- a/include/accel/tcg/cpu-loop.h +++ b/include/accel/tcg/cpu-loop.h @@ -5,6 +5,8 @@ #error Can only include this header with TCG #endif =20 +#include "qemu/atomic.h" + /** * cpu_exec: * @cpu: the cpu context @@ -40,4 +42,32 @@ bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host= _pc, uint64_t *data); */ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); =20 +/** + * cpu_loop_exit_noexc: + * @cpu: the cpu context + * + * Exit the current TB, but without causing any exception to be raised. + */ +G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); + +/** + * cpu_loop_exit_restore: + * @cpu: the cpu context + * @host_pc: the host pc within the translation + * + * Attempt to restore the state for a fault occurring in translated + * code. If @host_pc is not in translated code no state is + * restored. Finally, exit the current TB. + */ +G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t host_pc); +G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t host_pc); + +/** + * cpu_loop_exit: + * @cpu: the cpu context + * + * Exit the current TB. + */ +G_NORETURN void cpu_loop_exit(CPUState *cpu); + #endif diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index aedd60a6986..da359ee3128 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -61,13 +61,6 @@ void cpu_destroy_address_spaces(CPUState *cpu); /* vl.c */ void list_cpus(void); =20 -#ifdef CONFIG_TCG -G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); -G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); -G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); -#endif /* CONFIG_TCG */ -G_NORETURN void cpu_loop_exit(CPUState *cpu); - /** * env_archcpu(env) * @env: The architecture environment diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 31c8351231a..6860ac97081 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "qemu/target-info.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/iommu.h" #include "accel/tcg/probe.h" diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 0c7ac5a72c0..d9801a34275 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -26,6 +26,7 @@ #include "exec/mmap-lock.h" #include "exec/tb-flush.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-ops.h" #include "tb-internal.h" #include "system/tcg.h" diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index f483c9c2ba2..7c0aab98a80 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -25,6 +25,7 @@ #include "qemu/host-utils.h" #include "exec/cpu-common.h" #include "exec/helper-proto-common.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/getpc.h" =20 #define HELPER_H "accel/tcg/tcg-runtime.h" diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index cfb37a49e72..c75ed278459 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -25,6 +25,7 @@ #include "exec/translation-block.h" #include "system/tcg.h" #include "system/replay.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-ops.h" #include "hw/core/cpu.h" #include "internal-common.h" diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 82c0a90f704..c20eca28a1e 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -25,6 +25,7 @@ #include "hw/core/cpu.h" #include "hw/misc/mips_itu.h" #include "hw/core/qdev-properties.h" +#include "accel/tcg/cpu-loop.h" #include "target/mips/cpu.h" =20 #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8) diff --git a/plugins/api.c b/plugins/api.c index 2d5fe9327f7..690b5994f62 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -40,6 +40,7 @@ #include "qemu/plugin.h" #include "qemu/log.h" #include "system/memory.h" +#include "accel/tcg/cpu-loop.h" #include "tcg/tcg.h" #include "exec/cpu-common.h" #include "exec/gdbstub.h" diff --git a/semihosting/console.c b/semihosting/console.c index a4db8d8e76d..91e5d50d502 100644 --- a/semihosting/console.c +++ b/semihosting/console.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "semihosting/semihost.h" #include "semihosting/console.h" +#include "accel/tcg/cpu-loop.h" #include "exec/cpu-common.h" #include "exec/gdbstub.h" #include "qemu/log.h" diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index cdac560d086..ca8cfc6c9a3 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -31,6 +31,7 @@ #include "qemu/crc32c.h" #include "exec/cpu-common.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "exec/target_page.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index f3be8483b27..f452c9d9040 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,6 +23,7 @@ #include "qemu/error-report.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/cpu-loop.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 368391bb846..0a946433644 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/probe.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index 32f2784e923..1eaa602c91d 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "accel/tcg/cpu-loop.h" #include "cpu.h" #include "qemu/log.h" #include "system/runstate.h" diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index 2b5f092a23f..f7342871ded 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "accel/tcg/cpu-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "exec/cputlb.h" diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index aebb5caac37..2feea69c8a1 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "accel/tcg/cpu-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "exec/watchpoint.h" diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/= misc_helper.c index bb79d4e470e..2998b1aae75 100644 --- a/target/i386/tcg/system/misc_helper.c +++ b/target/i386/tcg/system/misc_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "system/address-spaces.h" #include "system/memory.h" #include "exec/cputlb.h" diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp= _helper.c index 6c5df5e0e88..0957ad2e9ec 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "accel/tcg/cpu-loop.h" #include "cpu.h" #include "tcg/helper-tcg.h" =20 diff --git a/target/i386/tcg/user/seg_helper.c b/target/i386/tcg/user/seg_h= elper.c index 28bbef1bbae..3a4a6d5a745 100644 --- a/target/i386/tcg/user/seg_helper.c +++ b/target/i386/tcg/user/seg_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "tcg/helper-tcg.h" #include "tcg/seg_helper.h" =20 diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c index f556234d9d2..8dc4bb15a1d 100644 --- a/target/loongarch/tcg/tcg_cpu.c +++ b/target/loongarch/tcg/tcg_cpu.c @@ -10,6 +10,7 @@ #include "qemu/log.h" #include "qemu/plugin.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-ops.h" #include "exec/translation-block.h" #include "exec/target_page.h" diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 7623f4f9bdb..a4b90beca65 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -17,6 +17,7 @@ #include "exec/page-protection.h" #include "exec/target_page.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "exec/log.h" #include "cpu-csr.h" #include "tcg/tcg_loongarch.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 2dd9ec1bdcb..5f91d206f59 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -25,6 +25,7 @@ #include "exec/target_page.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" +#include "accel/tcg/cpu-loop.h" #include "system/memory.h" #include "gdbstub/helpers.h" #include "fpu/softfloat.h" diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 84c60c2636e..3da0c68da39 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "accel/tcg/cpu-ldst-common.h" +#include "accel/tcg/cpu-loop.h" #include "fpu/softfloat.h" =20 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index d32bcebf469..630b8b809fa 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -24,6 +24,7 @@ #include "internal.h" #include "exec/helper-proto.h" #include "exec/translation-block.h" +#include "accel/tcg/cpu-loop.h" =20 target_ulong exception_resume_pc(CPUMIPSState *env) { diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index c850ddd9650..4398c6f80b4 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -26,6 +26,7 @@ #include "exec/page-protection.h" #include "exec/target_page.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "exec/log.h" #include "exec/helper-proto.h" =20 diff --git a/target/or1k/exception_helper.c b/target/or1k/exception_helper.c index 3e76acae9c3..eeb82bc49f4 100644 --- a/target/or1k/exception_helper.c +++ b/target/or1k/exception_helper.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "accel/tcg/cpu-loop.h" #include "exec/helper-proto.h" =20 #include "target/or1k/cpu.h" diff --git a/target/or1k/fpu_helper.c b/target/or1k/fpu_helper.c index 39b6195dd7d..e680606d4da 100644 --- a/target/or1k/fpu_helper.c +++ b/target/or1k/fpu_helper.c @@ -19,6 +19,7 @@ */ =20 #include "qemu/osdep.h" +#include "accel/tcg/cpu-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/or1k/mmu.c b/target/or1k/mmu.c index 3ff288a1f94..3fc56e1b771 100644 --- a/target/or1k/mmu.c +++ b/target/or1k/mmu.c @@ -24,6 +24,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-loop.h" #include "qemu/host-utils.h" #include "hw/core/loader.h" =20 diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index ae210eb8474..cc6d7ee88aa 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -19,6 +19,7 @@ */ =20 #include "qemu/osdep.h" +#include "accel/tcg/cpu-loop.h" #include "cpu.h" #include "internal.h" =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 17305e1bb75..97fea4d0c7e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -29,6 +29,7 @@ #include "system/memory.h" #include "instmap.h" #include "tcg/tcg-op.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-ops.h" #include "trace.h" #include "semihosting/common-semi.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 81873014cb8..987ef67d177 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -23,6 +23,7 @@ #include "internals.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/probe.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index ca3e9e85fc7..36df7d377e5 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" =20 diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 255271b9d34..2f886d424a1 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -24,6 +24,9 @@ #include "system/kvm.h" #include "system/tcg.h" #include "system/memory.h" +#ifdef CONFIG_TCG +#include "accel/tcg/cpu-loop.h" +#endif #include "exec/page-protection.h" #include "exec/target_page.h" #include "hw/core/hw-error.h" diff --git a/target/s390x/tcg/cc_helper.c b/target/s390x/tcg/cc_helper.c index 6595ac763c3..e538a75d713 100644 --- a/target/s390x/tcg/cc_helper.c +++ b/target/s390x/tcg/cc_helper.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "accel/tcg/cpu-loop.h" #include "s390x-internal.h" #include "tcg_s390x.h" #include "exec/helper-proto.h" diff --git a/target/s390x/tcg/debug.c b/target/s390x/tcg/debug.c index 50d2853d443..99140b1ac9a 100644 --- a/target/s390x/tcg/debug.c +++ b/target/s390x/tcg/debug.c @@ -7,6 +7,7 @@ #include "qemu/osdep.h" #include "exec/breakpoint.h" #include "exec/watchpoint.h" +#include "accel/tcg/cpu-loop.h" #include "target/s390x/cpu.h" #include "target/s390x/s390x-internal.h" #include "tcg_s390x.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index bfe0208324c..ecdecd5102f 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -28,6 +28,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/probe.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 036be93fb32..09a45e58a5d 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -28,6 +28,7 @@ #include "qemu/timer.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-ldst-common.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/target_page.h" #include "qapi/error.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index b3ec7ce64d0..b6b057f104b 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -24,6 +24,7 @@ #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/log.h" +#include "accel/tcg/cpu-loop.h" #include "qemu/plugin.h" =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/sparc/helper.c b/target/sparc/helper.c index c5d88de37c9..8de261b0e30 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "qemu/timer.h" #include "qemu/host-utils.h" +#include "accel/tcg/cpu-loop.h" #include "exec/cpu-common.h" #include "exec/helper-proto.h" =20 diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index e441ffb8f7e..07ba25dfcea 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/cputlb.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "exec/target_page.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index ce1693622b7..273713a1473 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -20,6 +20,7 @@ #include "hw/core/registerfields.h" #include "cpu.h" #include "exec/cputlb.h" +#include "accel/tcg/cpu-loop.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "exec/target_page.h" diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index fdc522698dc..7cb67d179a8 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -28,6 +28,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/main-loop.h" +#include "accel/tcg/cpu-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" --=20 2.53.0 From nobody Sun Jul 26 12:29:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781716590270158500 Forbid including TCG-specific headers in non-TCG builds. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/accel/tcg/cpu-mmu-index.h | 4 ++++ include/accel/tcg/cpu-ops.h | 4 ++++ include/accel/tcg/getpc.h | 4 ++++ include/accel/tcg/helper-retaddr.h | 4 ++++ include/accel/tcg/probe.h | 4 ++++ include/accel/tcg/tb-cpu-state.h | 4 ++++ 6 files changed, 24 insertions(+) diff --git a/include/accel/tcg/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-= index.h index e681a90844c..e0fb6ef91c8 100644 --- a/include/accel/tcg/cpu-mmu-index.h +++ b/include/accel/tcg/cpu-mmu-index.h @@ -9,6 +9,10 @@ #ifndef ACCEL_TCG_CPU_MMU_INDEX_H #define ACCEL_TCG_CPU_MMU_INDEX_H =20 +#ifndef CONFIG_TCG +#error Can only include this header with TCG +#endif + #include "hw/core/cpu.h" #include "accel/tcg/cpu-ops.h" #include "tcg/debug-assert.h" diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 5950cdcaab1..710da12b828 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -10,6 +10,10 @@ #ifndef TCG_CPU_OPS_H #define TCG_CPU_OPS_H =20 +#ifndef CONFIG_TCG +#error Can only include this header with TCG +#endif + #include "exec/breakpoint.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" diff --git a/include/accel/tcg/getpc.h b/include/accel/tcg/getpc.h index 0fc08addcf3..8a97ce34e76 100644 --- a/include/accel/tcg/getpc.h +++ b/include/accel/tcg/getpc.h @@ -8,6 +8,10 @@ #ifndef ACCEL_TCG_GETPC_H #define ACCEL_TCG_GETPC_H =20 +#ifndef CONFIG_TCG +#error Can only include this header with TCG +#endif + /* GETPC is the true target of the return instruction that we'll execute. = */ #ifdef CONFIG_TCG_INTERPRETER extern __thread uintptr_t tci_tb_ptr; diff --git a/include/accel/tcg/helper-retaddr.h b/include/accel/tcg/helper-= retaddr.h index 037fda2b83d..ebdc8b378d4 100644 --- a/include/accel/tcg/helper-retaddr.h +++ b/include/accel/tcg/helper-retaddr.h @@ -6,6 +6,10 @@ #ifndef ACCEL_TCG_HELPER_RETADDR_H #define ACCEL_TCG_HELPER_RETADDR_H =20 +#ifndef CONFIG_TCG +#error Can only include this header with TCG +#endif + /* * For user-only, helpers that use guest to host address translation * must protect the actual host memory access by recording 'retaddr' diff --git a/include/accel/tcg/probe.h b/include/accel/tcg/probe.h index dd9ecbbdf11..0b788901ba0 100644 --- a/include/accel/tcg/probe.h +++ b/include/accel/tcg/probe.h @@ -7,6 +7,10 @@ #ifndef ACCEL_TCG_PROBE_H #define ACCEL_TCG_PROBE_H =20 +#ifndef CONFIG_TCG +#error Can only include this header with TCG +#endif + #include "exec/mmu-access-type.h" #include "exec/vaddr.h" =20 diff --git a/include/accel/tcg/tb-cpu-state.h b/include/accel/tcg/tb-cpu-st= ate.h index 8f912900ca6..1903af4c2a2 100644 --- a/include/accel/tcg/tb-cpu-state.h +++ b/include/accel/tcg/tb-cpu-state.h @@ -6,6 +6,10 @@ #ifndef EXEC_TB_CPU_STATE_H #define EXEC_TB_CPU_STATE_H =20 +#ifndef CONFIG_TCG +#error Can only include this header with TCG +#endif + #include "exec/vaddr.h" =20 typedef struct TCGTBCPUState { --=20 2.53.0