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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260617-i2c-adc128d818-anacapa-v2-1-fd38764f0465@meta.com> References: <20260617-i2c-adc128d818-anacapa-v2-0-fd38764f0465@meta.com> In-Reply-To: <20260617-i2c-adc128d818-anacapa-v2-0-fd38764f0465@meta.com> To: CC: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Fabiano Rosas , Laurent Vivier , Peter Maydell , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Steven Lee , Troy Lee , "Jamin Lin" , Kane Chen , "Andrew Jeffery" , Joel Stanley , Alexander Hansen , William de Abreu Pinho , , Emmanuel Blot X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781691985; l=24657; i=eblot@meta.com; s=20260602; h=from:subject:message-id; bh=Z6mZxbaE6VSeqtgxTVKNzKEusj+cpnkEMMIludNuwg8=; b=l+0eShE7WTQRmJHKZB8bVe5PVvu9vA1ZqvVS+aU5Q59e3RilD+Ayvw3qeC0/tY//ni+6Ls8YY 0+sd8Z/RqjECSv9nwpWLrYBP4U6P2vNZ7dSmSK2wrLUSVGZN4GO+D9b X-Developer-Key: i=eblot@meta.com; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= X-Originating-IP: [2620:10d:c0a8:1b::30] X-Proofpoint-GUID: oO0Wl9vkDmpj63aXy3sV9mY4ZQPPyh3i X-Proofpoint-ORIG-GUID: oO0Wl9vkDmpj63aXy3sV9mY4ZQPPyh3i X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDA5OCBTYWx0ZWRfX4U/XqwomhBVg BBVh+9k2BYePUk98UMQosZse3yF44IZc5a8MAiGo1wDGaS62gcrXSd/xCuQxCyNe/VGwI2AODjg TCmdkelupKNf7164Wp6SnQ+YE1Fp6UkkT3J6WxYM1GDGyrWmHhHTCB+Ki6XwVZkCg85/yv2s5eB Yk1XrIoUeey6Siq1tQFk3b5oBSimseqnhF8Gxrb1G9WM1+EeP1qegs0/WfKKhY5HCdtcQO/o5YF vSLutavDYhdrBftZvVNnu0y5JyPP4W3yNpKfUt8rsZW/mV5PkaCkqlkXjiisUQ7bbkb2x/7ApUL Kv3Z/D6eKf2txGTHdVtp+DivrK2DTEQ0+9JPHRVaYp5gnHBBopx2iuy0SCMlB9JFFgG6Uk+wRfh zyAyyflU3vYhv9pboXGPAs4YN+lXXpYv8fgmzqn/iINa3X4j1UCiMHl4DqQptBgyTkyqtvfrTUE Owa1F8ID7eHnEKq1rGw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDA5OCBTYWx0ZWRfXxVWxNZn8URdf nunf/idiTnB/yRr5rWyJUig8oEOIXBV8407VFNSMUep8rqgYpAwJ8YbcM2hhD1wYmxZdvztz/xz wr41q0+6SV9EoX5RySxW//cq27ZgGC4= X-Authority-Analysis: v=2.4 cv=VcnH+lp9 c=1 sm=1 tr=0 ts=6a327655 cx=c_pps a=MfjaFnPeirRr97d5FC5oHw==:117 a=MfjaFnPeirRr97d5FC5oHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=7x6HtfJdh03M6CCDgxCd:22 a=JnKecZnUtZousrUlYMGU:22 a=VabnemYjAAAA:8 a=7APM2Y97aGwioPLpVesA:9 a=QEXdDO2ut3YA:10 a=gKebqoRLp9LExxC7YDUY:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-17_01,2026-06-16_02,2025-10-01_01 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=67.231.153.30; envelope-from=prvs=4628a4021f=eblot@meta.com; helo=mx0b-00082601.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @meta.com) X-ZM-MESSAGEID: 1781692187460158500 The ADC128D818 is a TI 12-bit, 8-channel I2C ADC used on several OpenBMC platforms for voltage and temperature monitoring. Implement the device with: - four operating modes - 12-bit voltage conversion from QOM inputs - 9-bit temperature conversion from milli-degree Celsius QOM inputs - switchable internal or external voltage reference - per-channel high/low limit registers - interrupt support - software reset - one-shot conversion support in shutdown mode Signed-off-by: Emmanuel Blot Reviewed-by: Alexander Hansen Tested-by: Alexander Hansen --- hw/sensor/Kconfig | 4 + hw/sensor/adc128d818.c | 695 +++++++++++++++++++++++++++++++++++++= ++++ hw/sensor/meson.build | 1 + hw/sensor/trace-events | 8 + include/hw/sensor/adc128d818.h | 12 + 5 files changed, 720 insertions(+) diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig index bc6331b4ab..b459ac2240 100644 --- a/hw/sensor/Kconfig +++ b/hw/sensor/Kconfig @@ -1,3 +1,7 @@ +config ADC128D818 + bool + depends on I2C + config TMP105 bool depends on I2C diff --git a/hw/sensor/adc128d818.c b/hw/sensor/adc128d818.c new file mode 100644 index 0000000000..46c0f5d71a --- /dev/null +++ b/hw/sensor/adc128d818.c @@ -0,0 +1,695 @@ +/* + * Texas Instruments ADC128D818 12-bit 8-channel ADC with I2C interface + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "qom/object.h" +#include "hw/sensor/adc128d818.h" +#include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" +#include "hw/i2c/i2c.h" +#include "migration/vmstate.h" +#include "trace.h" + + +/* Register addresses */ +#define REG_CONFIG 0x00u +#define REG_INT_STATUS 0x01u +#define REG_INT_MASK 0x03u +#define REG_CONV_RATE 0x07u +#define REG_CH_DISABLE 0x08u +#define REG_ONE_SHOT 0x09u +#define REG_DEEP_SHUTDOWN 0x0Au +#define REG_ADV_CONFIG 0x0Bu +#define REG_BUSY_STATUS 0x0Cu + +/* Channel Reading Registers (16-bit, read-only) */ +#define REG_CH_READING_BASE 0x20u +#define REG_CH_READING_LAST 0x27u + +/* Limit Registers (8-bit, read/write) */ +#define REG_LIMIT_BASE 0x2Au +#define REG_LIMIT_LAST 0x39u + +/* ID Registers (read-only) */ +#define REG_MANUFACTURER_ID 0x3Eu +#define REG_REVISION_ID 0x3Fu + +/* Configuration Register (0x00) bitfields */ +#define CONFIG_START BIT(0) +#define CONFIG_INT_ENABLE BIT(1) +#define CONFIG_INT_CLEAR BIT(3) +#define CONFIG_INITIALIZATION BIT(7) +#define CONFIG_WR_MASK \ + (CONFIG_START | CONFIG_INT_ENABLE | CONFIG_INT_CLEAR) + +/* Advanced Configuration Register (0x0B) bitfields */ +#define ADV_CONFIG_EXT_REF_EN BIT(0) +#define ADV_CONFIG_MODE_SHIFT 1u +#define ADV_CONFIG_MODE_MASK (0x3u << ADV_CONFIG_MODE_SHIFT) +#define ADV_CONFIG_WR_MASK \ + (ADV_CONFIG_EXT_REF_EN | ADV_CONFIG_MODE_MASK) + +/* Busy Status Register (0x0C) bitfields */ +#define BUSY_STATUS_NOT_READY BIT(1) + +/* Conversion Rate Register (0x07) bitfields */ +#define CONV_RATE_MASK 0x01u + +/* Deep Shutdown Register (0x0A) bitfields */ +#define DEEP_SHUTDOWN_EN 0x01u + +/* Device constants */ +#define ADC128D818_NUM_CHANNELS 8u +#define ADC128D818_NUM_REGS 0x40u + +#define ADC128D818_INTERNAL_VREF_MV 2560u +#define ADC128D818_MAX_VDD_MV 5500u +#define ADC128D818_MANUFACTURER_ID_VAL 0x01u +#define ADC128D818_REVISION_ID_VAL 0x09u + +/* ADC resolution */ +#define ADC128D818_ADC_RESOLUTION 4096u +#define ADC128D818_ADC_MAX 4095u + +/* Temperature: 0.5 deg C per LSb =3D 500 milli-degrees per LSb */ +#define ADC128D818_TEMP_LSB_MC 500 +#define ADC128D818_TEMP_RAW_MIN (-256) +#define ADC128D818_TEMP_RAW_MAX 255 + + +typedef struct ADC128D818State ADC128D818State; +DECLARE_INSTANCE_CHECKER(ADC128D818State, ADC128D818, TYPE_ADC128D818) + +struct ADC128D818State { + I2CSlave i2c; + + qemu_irq irq; + + uint8_t len; + uint8_t pointer; + uint8_t rx_byte; + + uint8_t regs[ADC128D818_NUM_REGS]; + uint16_t channel[ADC128D818_NUM_CHANNELS]; + + int16_t ain[ADC128D818_NUM_CHANNELS]; /* mV */ + int32_t temperature; /* milli-degrees Celsius */ + uint16_t ext_vref; /* mV, 0 means not connected */ + bool temp_alarm; /* temperature high-limit alarm latched */ + + char *description; +}; + +static uint16_t adc128d818_get_vref(const ADC128D818State *s) +{ + if (s->regs[REG_ADV_CONFIG] & ADV_CONFIG_EXT_REF_EN) { + if (s->ext_vref > 0u) { + return s->ext_vref; + } + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: external VREF selected but not" + " connected, falling back to internal\n", + __func__, s->description); + } + + return ADC128D818_INTERNAL_VREF_MV; +} + +static uint8_t adc128d818_get_mode(const ADC128D818State *s) +{ + return (s->regs[REG_ADV_CONFIG] & ADV_CONFIG_MODE_MASK) >> + ADV_CONFIG_MODE_SHIFT; +} + +static bool adc128d818_is_temp_channel(const ADC128D818State *s, unsigned = ch) +{ + if (ch !=3D 7u) { + return false; + } + + return adc128d818_get_mode(s) !=3D 1u; +} + +static bool adc128d818_is_reserved_channel(const ADC128D818State *s, + unsigned ch) +{ + switch (adc128d818_get_mode(s)) { + case 2u: + return ch >=3D 4u && ch <=3D 6u; + case 3u: + return ch =3D=3D 6u; + default: + return false; + } +} + +static int16_t adc128d818_channel_voltage(const ADC128D818State *s, unsign= ed ch) +{ + switch (adc128d818_get_mode(s)) { + case 2u: + switch (ch) { + case 0u: + return (int16_t)(s->ain[0] - s->ain[1]); + case 1u: + return (int16_t)(s->ain[3] - s->ain[2]); + case 2u: + return (int16_t)(s->ain[4] - s->ain[5]); + case 3u: + return (int16_t)(s->ain[7] - s->ain[6]); + default: + return 0; + } + case 3u: + switch (ch) { + case 4u: + return (int16_t)(s->ain[4] - s->ain[5]); + case 5u: + return (int16_t)(s->ain[7] - s->ain[6]); + default: + return s->ain[ch]; + } + default: + return s->ain[ch]; + } +} + +static void adc128d818_update_irq(ADC128D818State *s) +{ + uint8_t cfg =3D s->regs[REG_CONFIG]; + uint8_t active; + bool level; + + active =3D s->regs[REG_INT_STATUS] & ~s->regs[REG_INT_MASK]; + + /* INT pin is active-low */ + level =3D !((cfg & CONFIG_INT_ENABLE) && !(cfg & CONFIG_INT_CLEAR) && + (active !=3D 0u)); + + trace_adc128d818_irq(s->description, level); + qemu_set_irq(s->irq, level); +} + +static bool adc128d818_monitoring_active(const ADC128D818State *s) +{ + if (s->regs[REG_DEEP_SHUTDOWN] & DEEP_SHUTDOWN_EN) { + return false; + } + if (!(s->regs[REG_CONFIG] & CONFIG_START)) { + return false; + } + if (s->regs[REG_CONFIG] & CONFIG_INT_CLEAR) { + return false; + } + + return true; +} + +static void adc128d818_check_limits(ADC128D818State *s) +{ + uint8_t disabled =3D s->regs[REG_CH_DISABLE]; + uint8_t int_status =3D 0u; + + for (unsigned ch =3D 0u; ch < ADC128D818_NUM_CHANNELS; ch++) { + if ((disabled & (1u << ch)) || + adc128d818_is_reserved_channel(s, ch)) { + continue; + } + + if (adc128d818_is_temp_channel(s, ch)) { + int raw =3D s->temperature / ADC128D818_TEMP_LSB_MC; + int thot; + int thyst; + + raw =3D MAX(ADC128D818_TEMP_RAW_MIN, + MIN(ADC128D818_TEMP_RAW_MAX, raw)); + thot =3D (int)(int8_t)s->regs[REG_LIMIT_BASE + ch * 2u] * 2; + thyst =3D (int)(int8_t)s->regs[REG_LIMIT_BASE + ch * 2u + 1u] = * 2; + + if (raw > thot) { + s->temp_alarm =3D true; + } else if (raw <=3D thyst) { + s->temp_alarm =3D false; + } + if (s->temp_alarm) { + int_status |=3D (1u << ch); + } + } else { + uint8_t msb =3D (uint8_t)(s->channel[ch] >> 8u); + uint8_t high_lim =3D s->regs[REG_LIMIT_BASE + ch * 2u]; + uint8_t low_lim =3D s->regs[REG_LIMIT_BASE + ch * 2u + 1u]; + + if (msb > high_lim || msb <=3D low_lim) { + int_status |=3D (1u << ch); + } + } + } + + s->regs[REG_INT_STATUS] =3D int_status; + adc128d818_update_irq(s); +} + +static void adc128d818_convert(ADC128D818State *s) +{ + uint8_t disabled; + uint16_t vref; + + disabled =3D s->regs[REG_CH_DISABLE]; + vref =3D adc128d818_get_vref(s); + + for (unsigned ch =3D 0u; ch < ADC128D818_NUM_CHANNELS; ch++) { + if ((disabled & (1u << ch)) || + adc128d818_is_reserved_channel(s, ch)) { + continue; + } + + if (adc128d818_is_temp_channel(s, ch)) { + int32_t raw =3D s->temperature / ADC128D818_TEMP_LSB_MC; + + raw =3D + MAX(ADC128D818_TEMP_RAW_MIN, MIN(ADC128D818_TEMP_RAW_MAX, = raw)); + s->channel[ch] =3D (uint16_t)(((unsigned)raw & 0x1FFu) << 7u); + } else { + int16_t vin =3D adc128d818_channel_voltage(s, ch); + int32_t dout; + + dout =3D vin * (int32_t)ADC128D818_ADC_RESOLUTION / vref; + dout =3D MAX(0, MIN((int32_t)ADC128D818_ADC_MAX, dout)); + s->channel[ch] =3D (uint16_t)(dout << 4u); + } + + trace_adc128d818_convert(s->description, ch, s->channel[ch]); + } + + s->regs[REG_BUSY_STATUS] &=3D ~BUSY_STATUS_NOT_READY; + + adc128d818_check_limits(s); +} + +static uint8_t adc128d818_read_channel(ADC128D818State *s, unsigned ch) +{ + uint8_t val; + + if (s->rx_byte =3D=3D 0u) { + val =3D (uint8_t)(s->channel[ch] >> 8u); + trace_adc128d818_read_channel(s->description, ch, s->channel[ch]); + } else { + val =3D (uint8_t)(s->channel[ch] & 0xFFu); + } + s->rx_byte ^=3D 1u; + + return val; +} + +static uint8_t adc128d818_read_reg(ADC128D818State *s, uint8_t reg) +{ + uint8_t val; + + switch (reg) { + case REG_INT_STATUS: + val =3D s->regs[REG_INT_STATUS]; + s->regs[REG_INT_STATUS] =3D 0x00u; + if (adc128d818_monitoring_active(s)) { + adc128d818_check_limits(s); + } else { + adc128d818_update_irq(s); + } + trace_adc128d818_read(s->description, reg, val); + return val; + case REG_CONFIG: + case REG_INT_MASK: + case REG_CONV_RATE: + case REG_CH_DISABLE: + case REG_ONE_SHOT: + case REG_DEEP_SHUTDOWN: + case REG_ADV_CONFIG: + case REG_BUSY_STATUS: + case REG_LIMIT_BASE ... REG_LIMIT_LAST: + case REG_MANUFACTURER_ID: + case REG_REVISION_ID: + trace_adc128d818_read(s->description, reg, s->regs[reg]); + return s->regs[reg]; + case REG_CH_READING_BASE ... REG_CH_READING_LAST: + return adc128d818_read_channel(s, reg - REG_CH_READING_BASE); + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: read from undefined register 0x%02x\n", + __func__, s->description, reg); + return 0x00u; + } +} + +static void adc128d818_write_reg(ADC128D818State *s, uint8_t reg, uint8_t = val); + +static void adc128d818_reset_regs(ADC128D818State *s) +{ + memset(s->regs, 0, sizeof(s->regs)); + memset(s->channel, 0, sizeof(s->channel)); + s->temp_alarm =3D false; + + s->regs[REG_CONFIG] =3D 0x08u; + s->regs[REG_BUSY_STATUS] =3D 0x02u; + s->regs[REG_MANUFACTURER_ID] =3D ADC128D818_MANUFACTURER_ID_VAL; + s->regs[REG_REVISION_ID] =3D ADC128D818_REVISION_ID_VAL; + + for (unsigned ch =3D 0u; ch < ADC128D818_NUM_CHANNELS; ch++) { + s->regs[REG_LIMIT_BASE + ch * 2u] =3D 0xFFu; + } + + s->pointer =3D 0x00u; + s->len =3D 0u; + s->rx_byte =3D 0u; + + adc128d818_update_irq(s); +} + +static void adc128d818_write_reg(ADC128D818State *s, uint8_t reg, uint8_t = val) +{ + trace_adc128d818_write(s->description, reg, val); + + switch (reg) { + case REG_CONFIG: + if (val & CONFIG_INITIALIZATION) { + trace_adc128d818_reset(s->description, "reg"); + adc128d818_reset_regs(s); + break; + } + s->regs[REG_CONFIG] =3D val & CONFIG_WR_MASK; + if ((val & CONFIG_START) && !(val & CONFIG_INT_CLEAR) && + !(s->regs[REG_DEEP_SHUTDOWN] & DEEP_SHUTDOWN_EN)) { + adc128d818_convert(s); + } + adc128d818_update_irq(s); + break; + case REG_INT_MASK: + s->regs[REG_INT_MASK] =3D val; + adc128d818_update_irq(s); + break; + case REG_CONV_RATE: + if (s->regs[REG_CONFIG] & CONFIG_START) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: CONV_RATE written while running\n", + __func__, s->description); + break; + } + s->regs[REG_CONV_RATE] =3D val & CONV_RATE_MASK; + break; + case REG_CH_DISABLE: + if (s->regs[REG_CONFIG] & CONFIG_START) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: CH_DISABLE written while running\n", + __func__, s->description); + break; + } + s->regs[REG_CH_DISABLE] =3D val; + memset(s->channel, 0, sizeof(s->channel)); + s->regs[REG_INT_STATUS] =3D 0x00u; + s->temp_alarm =3D false; + adc128d818_update_irq(s); + break; + case REG_ONE_SHOT: + if (!(s->regs[REG_CONFIG] & CONFIG_START)) { + adc128d818_convert(s); + } + break; + case REG_DEEP_SHUTDOWN: + if ((val & DEEP_SHUTDOWN_EN) && (s->regs[REG_CONFIG] & CONFIG_STAR= T)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: DEEP_SHUTDOWN set while running\n", + __func__, s->description); + break; + } + s->regs[REG_DEEP_SHUTDOWN] =3D val & DEEP_SHUTDOWN_EN; + break; + case REG_ADV_CONFIG: + if (s->regs[REG_CONFIG] & CONFIG_START) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: ADV_CONFIG written while running\n", + __func__, s->description); + break; + } + s->regs[REG_ADV_CONFIG] =3D val & ADV_CONFIG_WR_MASK; + memset(s->channel, 0, sizeof(s->channel)); + s->regs[REG_INT_STATUS] =3D 0x00u; + s->temp_alarm =3D false; + adc128d818_update_irq(s); + break; + case REG_LIMIT_BASE ... REG_LIMIT_LAST: + s->regs[reg] =3D val; + break; + case REG_INT_STATUS: + case REG_BUSY_STATUS: + case REG_MANUFACTURER_ID: + case REG_REVISION_ID: + case REG_CH_READING_BASE ... REG_CH_READING_LAST: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: write to read-only register 0x%02x\n", + __func__, s->description, reg); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s: write to undefined register 0x%02x\n", + __func__, s->description, reg); + break; + } +} + +static uint8_t adc128d818_recv(I2CSlave *i2c) +{ + ADC128D818State *s =3D ADC128D818(i2c); + + return adc128d818_read_reg(s, s->pointer); +} + +static int adc128d818_send(I2CSlave *i2c, uint8_t data) +{ + ADC128D818State *s =3D ADC128D818(i2c); + + if (s->len =3D=3D 0u) { + s->pointer =3D data; + s->len++; + } else { + adc128d818_write_reg(s, s->pointer, data); + } + + return 0; +} + +static int adc128d818_event(I2CSlave *i2c, enum i2c_event event) +{ + ADC128D818State *s =3D ADC128D818(i2c); + + s->len =3D 0u; + s->rx_byte =3D 0u; + + return 0; +} + +static void adc128d818_get_ain(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ADC128D818State *s =3D ADC128D818(obj); + int64_t value; + int ch_num; + int rc; + + rc =3D sscanf(name, "ain%d", &ch_num); + if (rc !=3D 1 || ch_num < 0 || ch_num >=3D (int)ADC128D818_NUM_CHANNEL= S) { + error_setg(errp, "%s: %s: invalid channel '%s'", __func__, + s->description, name); + return; + } + + value =3D s->ain[ch_num]; + visit_type_int(v, name, &value, errp); +} + +static void adc128d818_set_ain(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ADC128D818State *s =3D ADC128D818(obj); + int64_t value; + int ch_num; + int rc; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + rc =3D sscanf(name, "ain%d", &ch_num); + if (rc !=3D 1 || ch_num < 0 || ch_num >=3D (int)ADC128D818_NUM_CHANNEL= S) { + error_setg(errp, "%s: %s: invalid channel '%s'", __func__, + s->description, name); + return; + } + + if (value < INT16_MIN || value > INT16_MAX) { + error_setg(errp, "%s: %s: value %" PRId64 " out of range for '%s'", + __func__, s->description, value, name); + return; + } + + s->ain[ch_num] =3D (int16_t)value; + + if (adc128d818_monitoring_active(s)) { + adc128d818_convert(s); + } +} + +static void adc128d818_get_temperature( + Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) +{ + ADC128D818State *s =3D ADC128D818(obj); + int64_t value =3D s->temperature; + + visit_type_int(v, name, &value, errp); +} + +static void adc128d818_set_temperature( + Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) +{ + ADC128D818State *s =3D ADC128D818(obj); + int64_t value; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + if (value < INT32_MIN || value > INT32_MAX) { + error_setg(errp, "%s: %s: value %" PRId64 " out of range", __func_= _, + s->description, value); + return; + } + + s->temperature =3D (int32_t)value; + + if (adc128d818_monitoring_active(s)) { + adc128d818_convert(s); + } +} + +static const VMStateDescription adc128d818_vmstate =3D { + .name =3D "ADC128D818", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(len, ADC128D818State), + VMSTATE_UINT8(pointer, ADC128D818State), + VMSTATE_UINT8(rx_byte, ADC128D818State), + VMSTATE_UINT8_ARRAY(regs, ADC128D818State, + ADC128D818_NUM_REGS), + VMSTATE_UINT16_ARRAY(channel, ADC128D818State, + ADC128D818_NUM_CHANNELS), + VMSTATE_INT16_ARRAY(ain, ADC128D818State, + ADC128D818_NUM_CHANNELS), + VMSTATE_INT32(temperature, ADC128D818State), + VMSTATE_UINT16(ext_vref, ADC128D818State), + VMSTATE_BOOL(temp_alarm, ADC128D818State), + VMSTATE_I2C_SLAVE(i2c, ADC128D818State), + VMSTATE_END_OF_LIST() + } +}; + +static void adc128d818_reset_hold(Object *obj, ResetType type) +{ + ADC128D818State *s =3D ADC128D818(obj); + + trace_adc128d818_reset(s->description, "hw"); + adc128d818_reset_regs(s); +} + +static void adc128d818_get_ext_vref( + Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) +{ + ADC128D818State *s =3D ADC128D818(obj); + int64_t value =3D (int64_t)s->ext_vref; + + visit_type_int(v, name, &value, errp); +} + +static void adc128d818_set_ext_vref( + Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) +{ + ADC128D818State *s =3D ADC128D818(obj); + int64_t value; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + if (value < 0 || value > ADC128D818_MAX_VDD_MV) { + error_setg(errp, + "%s: %s: ext-vref-mv %" PRId64 " out of range (0..%u mV= )", + __func__, s->description, value, ADC128D818_MAX_VDD_MV); + return; + } + + s->ext_vref =3D (uint16_t)value; + + if (adc128d818_monitoring_active(s)) { + adc128d818_convert(s); + } +} + +static void adc128d818_initfn(Object *obj) +{ + for (unsigned ch =3D 0u; ch < ADC128D818_NUM_CHANNELS; ch++) { + char *name =3D g_strdup_printf("ain%u", ch); + + object_property_add(obj, name, "int", adc128d818_get_ain, + adc128d818_set_ain, NULL, NULL); + g_free(name); + } + + object_property_add(obj, "temperature", "int", adc128d818_get_temperat= ure, + adc128d818_set_temperature, NULL, NULL); + object_property_add(obj, "ext-vref-mv", "int", adc128d818_get_ext_vref, + adc128d818_set_ext_vref, NULL, NULL); +} + +static void adc128d818_realize(DeviceState *dev, Error **errp) +{ + ADC128D818State *s =3D ADC128D818(dev); + + if (!s->description) { + s->description =3D g_strdup(object_get_typename(OBJECT(dev))); + } + + qdev_init_gpio_out(dev, &s->irq, 1u); +} + +static const Property adc128d818_properties[] =3D { + DEFINE_PROP_STRING("description", ADC128D818State, description), +}; + +static void adc128d818_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + I2CSlaveClass *ic =3D I2C_SLAVE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + ic->event =3D adc128d818_event; + ic->recv =3D adc128d818_recv; + ic->send =3D adc128d818_send; + dc->realize =3D adc128d818_realize; + rc->phases.hold =3D adc128d818_reset_hold; + dc->vmsd =3D &adc128d818_vmstate; + device_class_set_props(dc, adc128d818_properties); +} + +static const TypeInfo adc128d818_types[] =3D { + { + .name =3D TYPE_ADC128D818, + .parent =3D TYPE_I2C_SLAVE, + .instance_init =3D adc128d818_initfn, + .instance_size =3D sizeof(ADC128D818State), + .class_init =3D adc128d818_class_init, + }, +}; + +DEFINE_TYPES(adc128d818_types) diff --git a/hw/sensor/meson.build b/hw/sensor/meson.build index 420fdc3359..fe36c9ef91 100644 --- a/hw/sensor/meson.build +++ b/hw/sensor/meson.build @@ -1,3 +1,4 @@ +system_ss.add(when: 'CONFIG_ADC128D818', if_true: files('adc128d818.c')) system_ss.add(when: 'CONFIG_TMP105', if_true: files('tmp105.c')) system_ss.add(when: 'CONFIG_TMP421', if_true: files('tmp421.c')) system_ss.add(when: 'CONFIG_DPS310', if_true: files('dps310.c')) diff --git a/hw/sensor/trace-events b/hw/sensor/trace-events index a3fe54fa6d..5a3630f7bb 100644 --- a/hw/sensor/trace-events +++ b/hw/sensor/trace-events @@ -1,5 +1,13 @@ # See docs/devel/tracing.rst for syntax documentation. =20 +# adc128d818.c +adc128d818_read(const char *id, uint8_t reg, uint8_t value) "%s reg 0x%02x= val 0x%02x" +adc128d818_read_channel(const char *id, uint8_t channel, uint16_t value) "= %s ch %u val 0x%04x" +adc128d818_write(const char *id, uint8_t reg, uint8_t value) "%s reg 0x%02= x val 0x%02x" +adc128d818_convert(const char *id, uint8_t channel, uint16_t value) "%s ch= %u val 0x%04x" +adc128d818_irq(const char *id, bool level) "%s level %u" +adc128d818_reset(const char *id, const char *source) "%s %s" + # tmp105.c tmp105_read(uint8_t dev, uint8_t addr) "device: 0x%02x, addr: 0x%02x" tmp105_write(uint8_t dev, uint8_t addr) "device: 0x%02x, addr 0x%02x" diff --git a/include/hw/sensor/adc128d818.h b/include/hw/sensor/adc128d818.h new file mode 100644 index 0000000000..ce7e94d2b4 --- /dev/null +++ b/include/hw/sensor/adc128d818.h @@ -0,0 +1,12 @@ +/* + * Texas Instruments ADC128D818 12-bit 8-channel ADC with I2C interface + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_SENSOR_ADC128D818_H +#define HW_SENSOR_ADC128D818_H + +#define TYPE_ADC128D818 "adc128d818" + +#endif --=20 2.50.1 From nobody Sun Jul 26 12:36:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260617-i2c-adc128d818-anacapa-v2-2-fd38764f0465@meta.com> References: <20260617-i2c-adc128d818-anacapa-v2-0-fd38764f0465@meta.com> In-Reply-To: <20260617-i2c-adc128d818-anacapa-v2-0-fd38764f0465@meta.com> To: CC: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Fabiano Rosas , Laurent Vivier , Peter Maydell , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Steven Lee , Troy Lee , "Jamin Lin" , Kane Chen , "Andrew Jeffery" , Joel Stanley , Alexander Hansen , William de Abreu Pinho , , Emmanuel Blot X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781691985; l=33791; i=eblot@meta.com; s=20260602; h=from:subject:message-id; bh=KVAdyTlxhkU9lxo6UOkHhASURT0zSymign5ec3hURGM=; b=5LErEHX/k9p2lGoZxefEVMc3+AB30niYf3cTUcyDDOe8k5rx9uIlX1p3ULIpyK9CP1olIhCXa HXH8d5oIBSrDt+gkcBZSHkwrrlaA6p/QxeSRAPQ8+EkgjW9jX7TSAgm X-Developer-Key: i=eblot@meta.com; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= X-Originating-IP: [2620:10d:c0a8:1b::2d] X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDA5OCBTYWx0ZWRfX6Rk9fjew5dKg t7ZWRUzwxYRQwqkPvdiX5TPlNuVMrFB7KMqMQOfU2LHfsTG4l4A9ysxAdVMK8r4E5JQH6Esxg4p +SA1uSwhYTTkIdrlOE/p40ohHQOgHcU= X-Proofpoint-GUID: 76paJR_GELMfD41kVj9fNGyU5o4TDACl X-Authority-Analysis: v=2.4 cv=O6cJeh9W c=1 sm=1 tr=0 ts=6a32765d cx=c_pps a=MfjaFnPeirRr97d5FC5oHw==:117 a=MfjaFnPeirRr97d5FC5oHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=7x6HtfJdh03M6CCDgxCd:22 a=03ozwUkBphtHgyqjj1sw:22 a=VabnemYjAAAA:8 a=TajPwN6qHZDP_Qny09EA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=gKebqoRLp9LExxC7YDUY:22 X-Proofpoint-ORIG-GUID: 76paJR_GELMfD41kVj9fNGyU5o4TDACl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDA5OCBTYWx0ZWRfX6w+emEdPpb+d qmWl1G3vhVNcgFo1bi7OHPPZgj33Ua/pZYb6XB3iMrQ1me3Q6bJg4uZL68/fldU1nFX2hahaM6r PuWNlqMTAONvxEkT7F9C9bHbvM2sCgb0YvASGrDDqIvnLUDxFIPUdvuIJHTwv6lngBhf4z/G24o FqrisXQscq88Q6FH4jTREihr+tDl/Jk8eEkU8PoYbgJ/W0HC0ySKRALM+HE1SOP/ieshydBryPW 5BQVFi7cH7trgNnZ28kDW4Dzzqgk+UG5zxRHWj8e82a9L6vXJEafcstYCsYqiHWymSVFNEYsYR7 negttyQZ4UWk2Gh/jka+GKjQRuOmXf1O6l6za6SDnc9qiIxjb7fxcm4TjAEO7dPqKG8hqLvBGCy GWz+jU6t4Yhws03ykuBIMPENvBz8zoaWTg8wPAUZ3oAAkOGTihSmGt8ztBde3q9PFDItVEtawH2 b6ME9DOTkI9dL8qNkEQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-17_01,2026-06-16_02,2025-10-01_01 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=67.231.145.42; envelope-from=prvs=4628a4021f=eblot@meta.com; helo=mx0a-00082601.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @meta.com) X-ZM-MESSAGEID: 1781692218951158500 Add QOS-based QTest coverage for the ADC128D818: - manufacturer and revision ID registers - power-on-reset defaults - software reset - voltage conversion and edge cases - all channels with distinct values simultaneously - temperature conversion and edge cases - external voltage reference - per-channel interrupt status - INT_CLEAR bit suppresses interrupt assertion - channel disable prevents conversion - one-shot conversion in shutdown mode - deep shutdown blocks conversion - BUSY_STATUS NOT_READY flag lifecycle - operating mode selection - mode 2 pseudo-differential pairs - mode 3 mixed single-ended and differential - mode-change reset of readings and interrupt status - QOM-triggered reconversion Signed-off-by: Emmanuel Blot --- tests/qtest/adc128d818-test.c | 849 ++++++++++++++++++++++++++++++++++++++= ++++ tests/qtest/meson.build | 1 + 2 files changed, 850 insertions(+) diff --git a/tests/qtest/adc128d818-test.c b/tests/qtest/adc128d818-test.c new file mode 100644 index 0000000000..f8a4ba1f50 --- /dev/null +++ b/tests/qtest/adc128d818-test.c @@ -0,0 +1,849 @@ +/* + * QTest testcase for the ADC128D818 ADC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "libqos/i2c.h" +#include "libqos/qgraph.h" +#include "libqtest-single.h" +#include "qobject/qdict.h" + +#define ADC128D818_TEST_ID "adc128d818-test" +#define ADC128D818_TEST_ADDR 0x1F + +/* Register addresses */ +#define REG_CONFIG 0x00u +#define REG_INT_STATUS 0x01u +#define REG_INT_MASK 0x03u +#define REG_CONV_RATE 0x07u +#define REG_CH_DISABLE 0x08u +#define REG_ONE_SHOT 0x09u +#define REG_DEEP_SHUTDOWN 0x0Au +#define REG_ADV_CONFIG 0x0Bu +#define REG_BUSY_STATUS 0x0Cu + +/* Channel Reading Registers (16-bit, read-only) */ +#define REG_CH_READING_BASE 0x20u + +/* Limit Registers (8-bit, read/write) */ +#define REG_LIMIT_BASE 0x2Au + +/* ID Registers (read-only) */ +#define REG_MANUFACTURER_ID 0x3Eu +#define REG_REVISION_ID 0x3Fu + +/* Configuration Register (0x00) bitfields */ +#define CONFIG_START BIT(0) +#define CONFIG_INT_ENABLE BIT(1) +#define CONFIG_INT_CLEAR BIT(3) +#define CONFIG_INITIALIZATION BIT(7) + +/* Advanced Configuration Register (0x0B) bitfields */ +#define ADV_CONFIG_EXT_REF_EN BIT(0) +#define ADV_CONFIG_MODE_1 (1u << 1u) +#define ADV_CONFIG_MODE_2 (2u << 1u) +#define ADV_CONFIG_MODE_3 (3u << 1u) + +/* Number of channels */ +#define NUM_CHANNELS 8u + +/* Internal VREF in mV */ +#define INTERNAL_VREF_MV 2560u + +/* TAP-compatible diagnostic output (g_test_message is silent in TAP mode)= */ +#define test_log(fmt, ...) \ + fprintf(stderr, "# " fmt "\n", ## __VA_ARGS__) + +/* QMP helpers for setting device properties */ + +static void qmp_adc128d818_set(const char *property, int value) +{ + QDict *resp; + + resp =3D qmp("{ 'execute': 'qom-set', 'arguments':" + " { 'path': %s, 'property': %s, 'value': %d } }", + ADC128D818_TEST_ID, property, value); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); +} + +static int qmp_adc128d818_get(const char *property) +{ + QDict *resp; + int ret; + + resp =3D qmp("{ 'execute': 'qom-get', 'arguments':" + " { 'path': %s, 'property': %s } }", + ADC128D818_TEST_ID, property); + g_assert(qdict_haskey(resp, "return")); + ret =3D qdict_get_int(resp, "return"); + qobject_unref(resp); + return ret; +} + +/* Manufacturer and Revision ID registers */ +static void test_id_registers(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + g_assert_cmphex(i2c_get8(dev, REG_MANUFACTURER_ID), =3D=3D, 0x01); + g_assert_cmphex(i2c_get8(dev, REG_REVISION_ID), =3D=3D, 0x09); +} + +/* Power-on-reset default values */ +static void test_defaults(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + unsigned ch; + + g_assert_cmphex(i2c_get8(dev, REG_CONFIG), =3D=3D, 0x08); + g_assert_cmphex(i2c_get8(dev, REG_INT_STATUS), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(dev, REG_INT_MASK), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(dev, REG_CONV_RATE), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(dev, REG_CH_DISABLE), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(dev, REG_DEEP_SHUTDOWN), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(dev, REG_ADV_CONFIG), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(dev, REG_BUSY_STATUS), =3D=3D, 0x02); + + for (ch =3D 0u; ch < NUM_CHANNELS; ch++) { + g_assert_cmphex(i2c_get8(dev, REG_LIMIT_BASE + ch * 2u), =3D=3D, 0= xFF); + g_assert_cmphex(i2c_get8(dev, REG_LIMIT_BASE + ch * 2u + 1u), =3D= =3D, 0x00); + } +} + +/* Software reset via INITIALIZATION bit */ +static void test_soft_reset(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set8(dev, REG_INT_MASK, 0xAA); + i2c_set8(dev, REG_CH_DISABLE, 0x55); + i2c_set8(dev, REG_LIMIT_BASE, 0x42); + + g_assert_cmphex(i2c_get8(dev, REG_INT_MASK), =3D=3D, 0xAA); + g_assert_cmphex(i2c_get8(dev, REG_CH_DISABLE), =3D=3D, 0x55); + g_assert_cmphex(i2c_get8(dev, REG_LIMIT_BASE), =3D=3D, 0x42); + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + + g_assert_cmphex(i2c_get8(dev, REG_CONFIG), =3D=3D, 0x08); + g_assert_cmphex(i2c_get8(dev, REG_INT_MASK), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(dev, REG_CH_DISABLE), =3D=3D, 0x00); + g_assert_cmphex(i2c_get8(dev, REG_LIMIT_BASE), =3D=3D, 0xFF); + g_assert_cmphex(i2c_get8(dev, REG_BUSY_STATUS), =3D=3D, 0x02); +} + +/* Voltage conversion */ +static void test_voltage_conversion(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + qmp_adc128d818_set("ain0", 1280); + test_log("Injected ain0 =3D 1280 mV"); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Read ch0: raw 0x%04x -> %u mV", reading, + (reading >> 4u) * INTERNAL_VREF_MV / 4096u); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + qmp_adc128d818_set("ain1", 2560); + test_log("Injected ain1 =3D 2560 mV"); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 1u); + test_log("Read ch1: raw 0x%04x -> %u mV", reading, + (reading >> 4u) * INTERNAL_VREF_MV / 4096u); + g_assert_cmphex(reading, =3D=3D, 0xFFF0); + + qmp_adc128d818_set("ain2", 0); + test_log("Injected ain2 =3D 0 mV"); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 2u); + test_log("Read ch2: raw 0x%04x -> %u mV", reading, + (reading >> 4u) * INTERNAL_VREF_MV / 4096u); + g_assert_cmphex(reading, =3D=3D, 0x0000); +} + +/* Temperature conversion (mode 0, channel 7 =3D temperature) */ +static void +test_temperature_conversion(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + qmp_adc128d818_set("temperature", 25000); + test_log("Injected temperature =3D 25000 mC (25.0 deg C)"); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 7u); + test_log("Read ch7: raw 0x%04x -> %d mC", reading, + (int16_t)(reading & 0xFF80u) * 500 / 128); + g_assert_cmphex(reading, =3D=3D, 0x1900); +} + +/* Interrupt status set on limit violation; persists while fault remains */ +static void test_interrupt_status(void *obj, void *data, QGuestAllocator *= alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint8_t status; + + i2c_set8(dev, REG_LIMIT_BASE, 0x10); + test_log("Set ch0 high limit =3D 0x10"); + + qmp_adc128d818_set("ain0", 2560); + test_log("Injected ain0 =3D 2560 mV (exceeds limit)"); + + i2c_set8(dev, REG_CONFIG, CONFIG_START | CONFIG_INT_ENABLE); + + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("INT_STATUS =3D 0x%02x (expect bit 0 set)", status); + g_assert_cmphex(status & 0x01u, =3D=3D, 0x01); + + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("INT_STATUS after re-read =3D 0x%02x (expect bit 0 still set)= ", + status); + g_assert_cmphex(status & 0x01u, =3D=3D, 0x01); + + qmp_adc128d818_set("ain0", 80); + test_log("Injected ain0 =3D 80 mV (within limit)"); + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("INT_STATUS after fault cleared =3D 0x%02x (expect bit 0 clea= r)", + status); + g_assert_cmphex(status & 0x01u, =3D=3D, 0x00); +} + +/* INT_CLEAR stops the round-robin monitoring loop */ +static void test_int_clear(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint8_t status; + + i2c_set8(dev, REG_LIMIT_BASE, 0x10); + qmp_adc128d818_set("ain0", 2560); + + i2c_set8(dev, REG_CONFIG, + CONFIG_START | CONFIG_INT_ENABLE | CONFIG_INT_CLEAR); + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("INT_STATUS with INT_CLEAR set =3D 0x%02x (expect 0x00)", sta= tus); + g_assert_cmphex(status, =3D=3D, 0x00); + + i2c_set8(dev, REG_CONFIG, CONFIG_START | CONFIG_INT_ENABLE); + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("INT_STATUS after INT_CLEAR cleared =3D 0x%02x (expect bit 0)= ", + status); + g_assert_cmphex(status & 0x01u, =3D=3D, 0x01); +} + +/* Channel disable prevents conversion */ +static void test_channel_disable(void *obj, void *data, QGuestAllocator *a= lloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_CH_DISABLE, 0x01); + test_log("Disabled channel 0"); + + qmp_adc128d818_set("ain0", 1280); + test_log("Injected ain0 =3D 1280 mV (disabled)"); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Read ch0 (disabled): raw 0x%04x", reading); + g_assert_cmphex(reading, =3D=3D, 0x0000); + + qmp_adc128d818_set("ain1", 1280); + test_log("Injected ain1 =3D 1280 mV (enabled)"); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 1u); + test_log("Read ch1 (enabled): raw 0x%04x -> %u mV", reading, + (reading >> 4u) * INTERNAL_VREF_MV / 4096u); + g_assert_cmphex(reading, =3D=3D, 0x8000); +} + +/* One-shot conversion in shutdown mode */ +static void test_one_shot(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + qmp_adc128d818_set("ain0", 1280); + test_log("Injected ain0 =3D 1280 mV (device stopped)"); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Read ch0 before one-shot: raw 0x%04x", reading); + g_assert_cmphex(reading, =3D=3D, 0x0000); + + g_assert_cmphex(i2c_get8(dev, REG_ONE_SHOT), =3D=3D, 0x00); + + i2c_set8(dev, REG_ONE_SHOT, 0x00); + test_log("Triggered one-shot conversion with value 0x00"); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Read ch0 after one-shot: raw 0x%04x -> %u mV", reading, + (reading >> 4u) * INTERNAL_VREF_MV / 4096u); + g_assert_cmphex(reading, =3D=3D, 0x8000); +} + +/* Mode 1 makes channel 7 a voltage input instead of temperature */ +static void test_mode_selection(void *obj, void *data, QGuestAllocator *al= loc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_1); + test_log("Set mode 1 (all voltage channels)"); + + qmp_adc128d818_set("ain7", 1280); + qmp_adc128d818_set("temperature", 50000); + test_log("Injected ain7 =3D 1280 mV, temperature =3D 50000 mC"); + + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 7u); + test_log("Read ch7 (mode 1): raw 0x%04x -> %u mV", reading, + (reading >> 4u) * INTERNAL_VREF_MV / 4096u); + g_assert_cmphex(reading, =3D=3D, 0x8000); +} + +/* Mode 2 =E2=80=94 4 pseudo-differential pairs */ +static void test_mode2_diff(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_2); + test_log("Set mode 2 (4 pseudo-differential pairs)"); + + qmp_adc128d818_set("ain0", 2000); + qmp_adc128d818_set("ain1", 720); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Pair 0 (IN0-IN1): raw 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + qmp_adc128d818_set("ain3", 1920); + qmp_adc128d818_set("ain2", 640); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 1u); + test_log("Pair 1 (IN3-IN2): raw 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + qmp_adc128d818_set("ain4", 1500); + qmp_adc128d818_set("ain5", 220); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 2u); + test_log("Pair 2 (IN4-IN5): raw 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + qmp_adc128d818_set("ain7", 2560); + qmp_adc128d818_set("ain6", 1280); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 3u); + test_log("Pair 3 (IN7-IN6): raw 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 4u); + test_log("Reserved ch4: raw 0x%04x (expect 0x0000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x0000); + + qmp_adc128d818_set("ain0", 500); + qmp_adc128d818_set("ain1", 1000); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Pair 0 negative =CE=94V: raw 0x%04x (expect 0x0000)", readin= g); + g_assert_cmphex(reading, =3D=3D, 0x0000); +} + +/* Mode 3 =E2=80=94 4 single-ended + 2 pseudo-differential pairs */ +static void test_mode3_mixed(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_3); + test_log("Set mode 3 (4 single-ended + 2 differential)"); + + qmp_adc128d818_set("ain0", 1280); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Ch0 single-ended: raw 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + qmp_adc128d818_set("ain4", 1500); + qmp_adc128d818_set("ain5", 220); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 4u); + test_log("Ch4 diff (IN4-IN5): raw 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + qmp_adc128d818_set("ain7", 2560); + qmp_adc128d818_set("ain6", 1280); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 5u); + test_log("Ch5 diff (IN7-IN6): raw 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 6u); + test_log("Reserved ch6: raw 0x%04x (expect 0x0000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x0000); + + qmp_adc128d818_set("temperature", 25000); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 7u); + test_log("Ch7 temperature: raw 0x%04x (expect 0x1900)", reading); + g_assert_cmphex(reading, =3D=3D, 0x1900); +} + +/* Mode change resets channel readings and interrupt status */ +static void test_mode_change_reset(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + uint8_t status; + + qmp_adc128d818_set("ain0", 1280); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Before mode change, ch0: raw 0x%04x", reading); + g_assert_cmphex(reading, !=3D, 0x0000); + + i2c_set8(dev, REG_CONFIG, 0x00); + i2c_set8(dev, REG_LIMIT_BASE, 0x10); + qmp_adc128d818_set("ain0", 2560); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + i2c_set8(dev, REG_CONFIG, 0x00); + i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_2); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("After mode change, ch0: raw 0x%04x (expect 0x0000)", reading= ); + g_assert_cmphex(reading, =3D=3D, 0x0000); + + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("After mode change, INT_STATUS: 0x%02x (expect 0x00)", status= ); + g_assert_cmphex(status, =3D=3D, 0x00); + + g_assert_cmphex(i2c_get8(dev, REG_LIMIT_BASE), =3D=3D, 0x10); + test_log("Limit register preserved after mode change"); +} + +/* QOM property changes trigger correct differential conversion */ +static void test_diff_qom_trigger(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_2); + + qmp_adc128d818_set("ain0", 0); + qmp_adc128d818_set("ain1", 0); + qmp_adc128d818_set("ain2", 0); + qmp_adc128d818_set("ain3", 0); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + qmp_adc128d818_set("ain0", 2000); + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("After ain0=3D2000, ain1=3D0: pair0 =3D 0x%04x (expect 0xC800= )", + reading); + g_assert_cmphex(reading, =3D=3D, 0xC800); + + qmp_adc128d818_set("ain1", 720); + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("After ain1=3D720: pair0 =3D 0x%04x (expect 0x8000)", reading= ); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + qmp_adc128d818_set("ain3", 1920); + qmp_adc128d818_set("ain2", 640); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 1u); + test_log("Pair 1 (IN3-IN2) via QOM: 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); +} + +/* Channels with distinct voltages */ +static void test_all_channels(void *obj, void *data, QGuestAllocator *allo= c) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + static const uint16_t ain_mv[NUM_CHANNELS] =3D { + 0, 320, 640, 960, 1280, 1920, 2240, 2560 + }; + static const uint16_t expect[NUM_CHANNELS] =3D { + 0x0000, 0x2000, 0x4000, 0x6000, 0x8000, 0xC000, 0xE000, 0xFFF0 + }; + uint16_t reading; + unsigned ch; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_1); + + for (ch =3D 0u; ch < NUM_CHANNELS; ch++) { + char name[8]; + snprintf(name, sizeof(name), "ain%u", ch); + qmp_adc128d818_set(name, ain_mv[ch]); + } + + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + for (ch =3D 0u; ch < NUM_CHANNELS; ch++) { + reading =3D i2c_get16(dev, REG_CH_READING_BASE + ch); + test_log("ch%u: ain %u mV -> raw 0x%04x (expect 0x%04x)", + ch, ain_mv[ch], reading, expect[ch]); + g_assert_cmphex(reading, =3D=3D, expect[ch]); + } +} + +/* Voltage conversion edge cases */ +static void test_voltage_edges(void *obj, void *data, QGuestAllocator *all= oc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_1); + + qmp_adc128d818_set("ain0", 3000); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Over-range 3000 mV: raw 0x%04x (expect 0xFFF0)", reading); + g_assert_cmphex(reading, =3D=3D, 0xFFF0); + + qmp_adc128d818_set("ain1", 1); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 1u); + test_log("1 mV: raw 0x%04x (expect 0x0010)", reading); + g_assert_cmphex(reading, =3D=3D, 0x0010); + + qmp_adc128d818_set("ain2", 640); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 2u); + test_log("640 mV (quarter): raw 0x%04x (expect 0x4000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x4000); + + qmp_adc128d818_set("ain3", 1920); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 3u); + test_log("1920 mV (3/4): raw 0x%04x (expect 0xC000)", reading); + g_assert_cmphex(reading, =3D=3D, 0xC000); +} + +/* Temperature conversion edge cases */ +static void test_temperature_edges(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + + qmp_adc128d818_set("temperature", 0); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 7u); + test_log("0 C: raw 0x%04x (expect 0x0000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x0000); + + qmp_adc128d818_set("temperature", -25000); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 7u); + test_log("-25 C: raw 0x%04x (expect 0xE700)", reading); + g_assert_cmphex(reading, =3D=3D, 0xE700); + + qmp_adc128d818_set("temperature", 127500); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 7u); + test_log("+127.5 C: raw 0x%04x (expect 0x7F80)", reading); + g_assert_cmphex(reading, =3D=3D, 0x7F80); + + qmp_adc128d818_set("temperature", -128000); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 7u); + test_log("-128 C: raw 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + qmp_adc128d818_set("temperature", 200000); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 7u); + test_log("200 C (clamped): raw 0x%04x (expect 0x7F80)", reading); + g_assert_cmphex(reading, =3D=3D, 0x7F80); + + qmp_adc128d818_set("temperature", -200000); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 7u); + test_log("-200 C (clamped): raw 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); +} + +/* External voltage reference */ +static void test_ext_vref(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_MODE_1); + + qmp_adc128d818_set("ext-vref-mv", 4096); + i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_EXT_REF_EN | ADV_CONFIG_MODE_= 1); + + qmp_adc128d818_set("ain0", 1000); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("1000 mV / 4096 mV VREF: raw 0x%04x (expect 0x3E80)", reading= ); + g_assert_cmphex(reading, =3D=3D, 0x3E80); + + qmp_adc128d818_set("ain1", 2048); + reading =3D i2c_get16(dev, REG_CH_READING_BASE + 1u); + test_log("2048 mV / 4096 mV VREF: raw 0x%04x (expect 0x8000)", reading= ); + g_assert_cmphex(reading, =3D=3D, 0x8000); +} + +/* One-shot conversion works in deep shutdown */ +static void test_deep_shutdown(void *obj, void *data, QGuestAllocator *all= oc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + + qmp_adc128d818_set("ain0", 1280); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + i2c_set8(dev, REG_DEEP_SHUTDOWN, 0x01); + test_log("DEEP_SHUTDOWN write while running rejected"); + g_assert_cmphex(i2c_get8(dev, REG_DEEP_SHUTDOWN), =3D=3D, 0x00); + + i2c_set8(dev, REG_CONFIG, 0x00); + i2c_set8(dev, REG_DEEP_SHUTDOWN, 0x01); + qmp_adc128d818_set("ain0", 0); + + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Deep shutdown, no one-shot: raw 0x%04x (expect 0x8000)", rea= ding); + g_assert_cmphex(reading, =3D=3D, 0x8000); + + i2c_set8(dev, REG_ONE_SHOT, 0x01); + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("Deep shutdown one-shot: raw 0x%04x (expect 0x0000)", reading= ); + g_assert_cmphex(reading, =3D=3D, 0x0000); + + g_assert_cmphex(i2c_get8(dev, REG_DEEP_SHUTDOWN), =3D=3D, 0x01); + + i2c_set8(dev, REG_DEEP_SHUTDOWN, 0x00); + qmp_adc128d818_set("ain0", 1280); + i2c_set8(dev, REG_ONE_SHOT, 0x01); + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("After exit shutdown: raw 0x%04x (expect 0x8000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x8000); +} + +/* BUSY_STATUS NOT_READY clears after first conversion */ +static void test_busy_status(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + + g_assert_cmphex(i2c_get8(dev, REG_BUSY_STATUS) & 0x02, =3D=3D, 0x02); + test_log("After reset: BUSY_STATUS =3D 0x%02x (NOT_READY set)", + i2c_get8(dev, REG_BUSY_STATUS)); + + qmp_adc128d818_set("ain0", 0); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + g_assert_cmphex(i2c_get8(dev, REG_BUSY_STATUS) & 0x02, =3D=3D, 0x00); + test_log("After conversion: BUSY_STATUS =3D 0x%02x (NOT_READY cleared)= ", + i2c_get8(dev, REG_BUSY_STATUS)); +} + +/* Low-limit interrupt triggers correctly */ +static void test_low_limit(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint8_t status; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + + i2c_set8(dev, REG_LIMIT_BASE + 3u, 0x80); + test_log("Set ch1 low limit =3D 0x80"); + + i2c_set8(dev, REG_LIMIT_BASE + 5u, 0x80); + test_log("Set ch2 low limit =3D 0x80"); + + qmp_adc128d818_set("ain1", 640); + qmp_adc128d818_set("ain2", 1280); + qmp_adc128d818_set("ain0", 1280); + i2c_set8(dev, REG_CONFIG, CONFIG_START | CONFIG_INT_ENABLE); + + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("INT_STATUS =3D 0x%02x (expect bits 1 and 2 set)", status); + g_assert_cmphex(status & 0x02u, =3D=3D, 0x02); + g_assert_cmphex(status & 0x04u, =3D=3D, 0x04); + + g_assert_cmphex(status & 0x01u, =3D=3D, 0x00); +} + +/* Verify ain property readback via QMP */ +static void test_ain_property(void *obj, void *data, QGuestAllocator *allo= c) +{ + int value; + + qmp_adc128d818_set("ain3", 1500); + value =3D qmp_adc128d818_get("ain3"); + test_log("Set ain3 =3D 1500 mV, readback =3D %d mV", value); + g_assert_cmpint(value, =3D=3D, 1500); + + qmp_adc128d818_set("temperature", 37500); + value =3D qmp_adc128d818_get("temperature"); + test_log("Set temperature =3D 37500 mC, readback =3D %d mC", value); + g_assert_cmpint(value, =3D=3D, 37500); +} + +/* Programming Channel Disable resets channel readings */ +static void test_chan_disable_clears(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + + qmp_adc128d818_set("ain0", 1280); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + g_assert_cmphex(i2c_get16(dev, REG_CH_READING_BASE), =3D=3D, 0x8000); + + i2c_set8(dev, REG_CONFIG, 0x00); + i2c_set8(dev, REG_CH_DISABLE, 0x02); + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("After CH_DISABLE write: ch0 raw 0x%04x (expect 0x0000)", rea= ding); + g_assert_cmphex(reading, =3D=3D, 0x0000); +} + +/* Programming Advanced Configuration always resets channel readings */ +static void test_adv_config_clears(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint16_t reading; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + + qmp_adc128d818_set("ain0", 1280); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + g_assert_cmphex(i2c_get16(dev, REG_CH_READING_BASE), =3D=3D, 0x8000); + + i2c_set8(dev, REG_CONFIG, 0x00); + i2c_set8(dev, REG_ADV_CONFIG, 0x00); + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("After same-mode ADV_CONFIG: ch0 0x%04x (expect 0x0000)", rea= ding); + g_assert_cmphex(reading, =3D=3D, 0x0000); + + i2c_set8(dev, REG_CONFIG, CONFIG_START); + g_assert_cmphex(i2c_get16(dev, REG_CH_READING_BASE), =3D=3D, 0x8000); + i2c_set8(dev, REG_CONFIG, 0x00); + qmp_adc128d818_set("ext-vref-mv", 4096); + i2c_set8(dev, REG_ADV_CONFIG, ADV_CONFIG_EXT_REF_EN); + reading =3D i2c_get16(dev, REG_CH_READING_BASE); + test_log("After ext-vref toggle: ch0 0x%04x (expect 0x0000)", reading); + g_assert_cmphex(reading, =3D=3D, 0x0000); +} + +/* Temperature high-limit interrupt with hysteresis */ +static void test_temp_hysteresis(void *obj, void *data, + QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + uint8_t status; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + + i2c_set8(dev, REG_LIMIT_BASE + 7u * 2u, 0x32); + i2c_set8(dev, REG_LIMIT_BASE + 7u * 2u + 1u, 0x28); + + qmp_adc128d818_set("temperature", 25000); + i2c_set8(dev, REG_CONFIG, CONFIG_START); + + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("25 C: INT_STATUS =3D 0x%02x (temp bit expect clear)", status= ); + g_assert_cmphex(status & 0x80u, =3D=3D, 0x00); + + qmp_adc128d818_set("temperature", 55000); + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("55 C: INT_STATUS =3D 0x%02x (temp bit expect set)", status); + g_assert_cmphex(status & 0x80u, =3D=3D, 0x80); + + qmp_adc128d818_set("temperature", 45000); + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("45 C (hysteresis): INT_STATUS =3D 0x%02x (temp bit expect se= t)", + status); + g_assert_cmphex(status & 0x80u, =3D=3D, 0x80); + + qmp_adc128d818_set("temperature", 35000); + status =3D i2c_get8(dev, REG_INT_STATUS); + test_log("35 C: INT_STATUS =3D 0x%02x (temp bit expect clear)", status= ); + g_assert_cmphex(status & 0x80u, =3D=3D, 0x00); +} + +/* Conversion Rate register may only be programmed while in shutdown */ +static void test_conv_rate(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *dev =3D (QI2CDevice *)obj; + + i2c_set8(dev, REG_CONFIG, CONFIG_INITIALIZATION); + + i2c_set8(dev, REG_CONV_RATE, 0x01); + g_assert_cmphex(i2c_get8(dev, REG_CONV_RATE), =3D=3D, 0x01); + + i2c_set8(dev, REG_CONFIG, CONFIG_START); + i2c_set8(dev, REG_CONV_RATE, 0x00); + test_log("CONV_RATE while running: 0x%02x (expect unchanged 0x01)", + i2c_get8(dev, REG_CONV_RATE)); + g_assert_cmphex(i2c_get8(dev, REG_CONV_RATE), =3D=3D, 0x01); +} + +static void adc128d818_register_nodes(void) +{ + QOSGraphEdgeOptions opts =3D { + .extra_device_opts =3D "id=3D" ADC128D818_TEST_ID + ",address=3D0x1f" + }; + add_qi2c_address(&opts, &(QI2CAddress) { ADC128D818_TEST_ADDR }); + + qos_node_create_driver("adc128d818", i2c_device_create); + qos_node_consumes("adc128d818", "i2c-bus", &opts); + + qos_add_test("id-registers", "adc128d818", test_id_registers, NULL); + qos_add_test("defaults", "adc128d818", test_defaults, NULL); + qos_add_test("soft-reset", "adc128d818", test_soft_reset, NULL); + qos_add_test("voltage-conversion", "adc128d818", test_voltage_conversi= on, + NULL); + qos_add_test("temperature-conversion", "adc128d818", + test_temperature_conversion, NULL); + qos_add_test("interrupt-status", "adc128d818", test_interrupt_status, = NULL); + qos_add_test("int-clear", "adc128d818", test_int_clear, NULL); + qos_add_test("channel-disable", "adc128d818", test_channel_disable, NU= LL); + qos_add_test("one-shot", "adc128d818", test_one_shot, NULL); + qos_add_test("mode-selection", "adc128d818", test_mode_selection, NULL= ); + qos_add_test("mode2-diff", "adc128d818", test_mode2_diff, NULL); + qos_add_test("mode3-mixed", "adc128d818", test_mode3_mixed, NULL); + qos_add_test("mode-change-reset", "adc128d818", test_mode_change_reset, + NULL); + qos_add_test("diff-qom-trigger", "adc128d818", test_diff_qom_trigger, + NULL); + qos_add_test("all-channels", "adc128d818", test_all_channels, NULL); + qos_add_test("voltage-edges", "adc128d818", test_voltage_edges, NULL); + qos_add_test("temperature-edges", "adc128d818", test_temperature_edges, + NULL); + qos_add_test("ext-vref", "adc128d818", test_ext_vref, NULL); + qos_add_test("deep-shutdown", "adc128d818", test_deep_shutdown, NULL); + qos_add_test("busy-status", "adc128d818", test_busy_status, NULL); + qos_add_test("low-limit", "adc128d818", test_low_limit, NULL); + qos_add_test("chan-disable-clears", "adc128d818", test_chan_disable_cl= ears, + NULL); + qos_add_test("adv-config-clears", "adc128d818", test_adv_config_clears, + NULL); + qos_add_test("temp-hysteresis", "adc128d818", test_temp_hysteresis, NU= LL); + qos_add_test("conv-rate", "adc128d818", test_conv_rate, NULL); + qos_add_test("ain-property", "adc128d818", test_ain_property, NULL); +} +libqos_init(adc128d818_register_nodes); diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 45ea497fa5..defa0d9941 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -296,6 +296,7 @@ qtests_riscv64 =3D ['riscv-csr-test'] + \ qos_test_ss =3D ss.source_set() qos_test_ss.add( 'ac97-test.c', + 'adc128d818-test.c', 'adm1272-test.c', 'adm1266-test.c', 'ds1338-test.c', --=20 2.50.1 From nobody Sun Jul 26 12:36:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260617-i2c-adc128d818-anacapa-v2-3-fd38764f0465@meta.com> References: <20260617-i2c-adc128d818-anacapa-v2-0-fd38764f0465@meta.com> In-Reply-To: <20260617-i2c-adc128d818-anacapa-v2-0-fd38764f0465@meta.com> To: CC: Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Fabiano Rosas , Laurent Vivier , Peter Maydell , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Steven Lee , Troy Lee , "Jamin Lin" , Kane Chen , "Andrew Jeffery" , Joel Stanley , Alexander Hansen , William de Abreu Pinho , , Emmanuel Blot X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781691985; l=2857; i=eblot@meta.com; s=20260602; h=from:subject:message-id; bh=ba+SGL39DSQnp4XkhtND2+kjLa/+DABvQWlL9O6paiE=; b=OI1uXMGrCsRIgD7TEmRM1vtbNDjxZ9bFNQNpxr05IwyjcLTU7woIW/uzwGYgaSlNrArNTvuf/ /tIFPE9Ycm/CQVDEZVNlJQRW0HL2UCo6OM9Dn2+DJcOOHSuDPECdIE9 X-Developer-Key: i=eblot@meta.com; a=ed25519; pk=0qFrZ21FAAN8OfVsSoVcCFTk/NMYOWzxJz4paSAVm0g= X-Originating-IP: [2620:10d:c0a8:1c::1b] X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDA5OCBTYWx0ZWRfX52/rCPq8I60I UVsZghEqgkEa55QhekYuDKBnyJ7EtOXmmzeV+oWX/aXtiDQTecElf+Dk4ko0XxrgzKcBpdzJJW1 v98fnm4kEcAjtoG69jhYAEnfqWHXdYE= X-Proofpoint-GUID: GjmwVHEtuW19TcW8Es9NBvyoB_gzGJGV X-Authority-Analysis: v=2.4 cv=O6cJeh9W c=1 sm=1 tr=0 ts=6a32765e cx=c_pps a=MfjaFnPeirRr97d5FC5oHw==:117 a=MfjaFnPeirRr97d5FC5oHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=7x6HtfJdh03M6CCDgxCd:22 a=03ozwUkBphtHgyqjj1sw:22 a=VabnemYjAAAA:8 a=29MC50mZdBDcY4WmDOIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=gKebqoRLp9LExxC7YDUY:22 X-Proofpoint-ORIG-GUID: GjmwVHEtuW19TcW8Es9NBvyoB_gzGJGV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDA5OCBTYWx0ZWRfX3MnLUelZrZya ATKlI+euEDTcfKBRH6djjQu7Of5b8fJgzlMb2O0jxZEjAIZ/mWpff4YI/CU3jaEYY5ulH8XUHDL ySa3k4sGho+4yNKVroBiUbTU9Zux0mkQuc4F9bOwhmsiJKeSaE1zv+/MMUe55HNXmFd6J+r7/PQ bb4raV46Z2JNJNkJhRsDeVKNwNxbo9S2ba/kdiD1BHfYBIOY11ls+T+nvV72xr8E2C3ltFEssFN eh756gBdX/9eT2zbRSAfJJCi/ogGaRZ1VfAVmUCJvqUnw91c7vHWNx8MjwyoEG+cUFHviI7iZha WSEghInV18I5XpNFuGh0emLS+i8U94MvUFtsEUN6mT9lnYKQlVQN2o40JlT+AgfotOpQSPjgiON l2QbSXEcUpSE2Fs533cdiKAx6+B2jbq6nTKcioGtnuFJSJjMRZ+Xge8QLERz35oXwZ8GXiRM+6Q Se16nvInZ0Gb7HxnoVg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-17_01,2026-06-16_02,2025-10-01_01 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=67.231.145.42; envelope-from=prvs=4628a4021f=eblot@meta.com; helo=mx0a-00082601.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @meta.com) X-ZM-MESSAGEID: 1781692187453158500 Wire up the two ADC128D818 instances that appear in the Anacapa DTS: one on i2c8 mux channel 0 and one on i2c13 mux channel 3. Signed-off-by: Emmanuel Blot --- hw/arm/Kconfig | 1 + hw/arm/aspeed_ast2600_anacapa.c | 16 +++++++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index fb798ccbee..04ecf5d473 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -553,6 +553,7 @@ config ASPEED_SOC select LED select PMBUS select MAX31785 + select ADC128D818 select FSI_APB2OPB_ASPEED select AT24C select PCI_EXPRESS diff --git a/hw/arm/aspeed_ast2600_anacapa.c b/hw/arm/aspeed_ast2600_anacap= a.c index a1c8111a93..8f94a830e5 100644 --- a/hw/arm/aspeed_ast2600_anacapa.c +++ b/hw/arm/aspeed_ast2600_anacapa.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "hw/sensor/adc128d818.h" #include "hw/arm/machines-qom.h" #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" @@ -15,7 +16,6 @@ #include "hw/gpio/pca9552.h" #include "hw/nvram/eeprom_at24c.h" =20 -/* Anacapa hardware value */ #define ANACAPA_BMC_HW_STRAP1 0x00002002 #define ANACAPA_BMC_HW_STRAP2 0x00000000 #define ANACAPA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) @@ -221,6 +221,14 @@ static const uint8_t hpm_brd_id_eeprom[] =3D { }; static const size_t hpm_brd_id_eeprom_len =3D sizeof(hpm_brd_id_eeprom); =20 +static void anacapa_add_adc128d818(I2CBus *bus, uint8_t addr, + const char *description) +{ + DeviceState *dev =3D DEVICE(i2c_slave_new(TYPE_ADC128D818, addr)); + qdev_prop_set_string(dev, "description", description); + i2c_slave_realize_and_unref(I2C_SLAVE(dev), bus, &error_fatal); +} + static void anacapa_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference: aspeed-bmc-facebook-anacapa.dts */ @@ -259,7 +267,8 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bm= c) i2c_mux =3D i2c_slave_create_simple(i2c[8], TYPE_PCA9546, 0x72); =20 /* i2c8mux ch0 */ - /* adc128d818@1f =E2=80=94 no model */ + /* adc128d818@1f =E2=80=94 R-PDB ADC (mode 1: 8 voltage channels) */ + anacapa_add_adc128d818(pca954x_i2c_get_bus(i2c_mux, 0), 0x1f, "i2c8:0:= 1f"); /* pca9555@22 */ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_PCA9552, 0x22); @@ -320,7 +329,8 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bm= c) i2c_mux =3D i2c_slave_create_simple(i2c[13], TYPE_PCA9548, 0x70); =20 /* i2c13mux ch3 */ - /* adc128d818@1f - no model */ + /* adc128d818@1f =E2=80=94 MB ADC (mode 1: 8 voltage channels) */ + anacapa_add_adc128d818(pca954x_i2c_get_bus(i2c_mux, 3), 0x1f, "i2c13:3= :1f"); =20 /* i2c13mux ch4 */ /* eeprom@51 */ --=20 2.50.1 From nobody Sun Jul 26 12:36:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=meta.com ARC-Seal: i=1; a=rsa-sha256; t=1781692240; cv=none; d=zohomail.com; s=zohoarc; b=EOyrE9Hnjc8JeQtNims3TJvMD1evNiciUMP28FYj57E/gE4S+R8mF8rGJa30a7pKCUdr7Xsw0VRqv6SK5p8STor9qE/jGtgRv7CV5QgqNXX2f4WFZHwXO+86aMDZs+m3/lDkAcidjiOstaotvqc03Vk92NHrxnrmjZoD3ipBoQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781692240; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=67.231.153.30; envelope-from=prvs=4628a4021f=eblot@meta.com; helo=mx0b-00082601.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @meta.com) X-ZM-MESSAGEID: 1781692242732158500 Verify the ADC128D818 on the Anacapa R-PDB (i2c8 mux channel 0): two channels are driven with distinct voltages and each is checked to be reported back independently through the kernel hwmon interface, and the channel 0 limit registers are validated. Signed-off-by: Emmanuel Blot --- tests/functional/arm/test_aspeed_anacapa.py | 92 +++++++++++++++++++++++++= ++-- 1 file changed, 86 insertions(+), 6 deletions(-) diff --git a/tests/functional/arm/test_aspeed_anacapa.py b/tests/functional= /arm/test_aspeed_anacapa.py index 27f8bd8b56..003d6dfb17 100644 --- a/tests/functional/arm/test_aspeed_anacapa.py +++ b/tests/functional/arm/test_aspeed_anacapa.py @@ -4,22 +4,102 @@ # # SPDX-License-Identifier: GPL-2.0-or-later =20 +import re +import time + from qemu_test import Asset +from qemu_test import exec_command +from qemu_test import exec_command_and_wait_for_pattern +from qemu_test import wait_for_console_pattern from aspeed import FacebookAspeedTest =20 =20 class AnacapaMachine(FacebookAspeedTest): =20 ASSET_ANACAPA_FLASH =3D Asset( - 'https://github.com/legoater/qemu-aspeed-boot/raw/3fa3212827b04be4= 034d43b5adeef57c27d6ab18/images/anacapa-bmc/openbmc-20260512025228/obmc-pho= sphor-image-anacapa-20260512025228.static.mtd.xz', - '2232e241abcfb6d4f6b82cb6c378ce5ce05e364aac6d118785c2b6cc33fe43f3') + "https://github.com/legoater/qemu-aspeed-boot/raw/3fa3212827b04be4= 034d43b5adeef57c27d6ab18/images/anacapa-bmc/openbmc-20260512025228/obmc-pho= sphor-image-anacapa-20260512025228.static.mtd.xz", + "2232e241abcfb6d4f6b82cb6c378ce5ce05e364aac6d118785c2b6cc33fe43f3", + ) + + # ADC128D818 on i2c8 mux (PCA9546 @0x72) channel 0, address 0x1f. + ADC128D818_HWMON =3D "/sys/bus/i2c/devices/*-001f/hwmon/hwmon*" =20 def test_arm_ast2600_anacapa_openbmc(self): image_path =3D self.uncompress(self.ASSET_ANACAPA_FLASH) =20 - self.do_test_arm_aspeed_openbmc('anacapa-bmc', image=3Dimage_path, - uboot=3D'2019.04', cpu_id=3D'0xf00= ', - soc=3D'AST2600 rev A3') + self.do_test_arm_aspeed_openbmc( + "anacapa-bmc", + image=3Dimage_path, + uboot=3D"2019.04", + cpu_id=3D"0xf00", + soc=3D"AST2600 rev A3", + ) =20 -if __name__ =3D=3D '__main__': + # perform login + exec_command_and_wait_for_pattern(self, "root", "Password:") + exec_command_and_wait_for_pattern(self, "0penBmc", "#") + + # ADC128D818 test + # + # The current Anacapa OpenBMC device tree is the AST2600 EVB one, = and + # therefore does not declare the i2c8 mux nor the ADC128D818 behin= d it, + # so bind the emulated PCA9546 (@0x72) and then the ADC128D818 (@0= x1f, + # mux channel 0) from userspace before probing. + # This should not longer be useful once the Anacapa DT is updated. + exec_command_and_wait_for_pattern( + self, + "echo pca9546 0x72 > /sys/bus/i2c/devices/i2c-8/new_device", + "root@anacapa", + ) + exec_command_and_wait_for_pattern( + self, + "bus=3D$(basename $(readlink /sys/bus/i2c/devices/8-0072/chann= el-0)); " + "echo adc128d818 0x1f > /sys/bus/i2c/devices/$bus/new_device", + "root@anacapa", + ) + exec_command_and_wait_for_pattern( + self, f"cat {self.ADC128D818_HWMON}/name", "adc128d818" + ) + + adc =3D self.find_adc128d818_qom_path() + for ch0_mv, ch1_mv in ((108, 2000), (1280, 500)): + self.vm.cmd("qom-set", path=3Dadc, property=3D"ain0", value=3D= ch0_mv) + self.vm.cmd("qom-set", path=3Dadc, property=3D"ain1", value=3D= ch1_mv) + self.wait_adc128d818_value("in0_input", ch0_mv) + self.wait_adc128d818_value("in1_input", ch1_mv) + + self.assertEqual(self.read_adc128d818_value("in0_min"), 0) + self.assertEqual(self.read_adc128d818_value("in0_max"), 2551) + + def find_adc128d818_qom_path(self): + unattached =3D "/machine/unattached" + devices =3D [ + child["name"] + for child in self.vm.cmd("qom-list", path=3Dunattached) + if "adc128d818" in child["type"] + ] + devices.sort(key=3Dlambda name: int(name[len("device[") : -1])) + return f"{unattached}/{devices[0]}" + + def read_adc128d818_value(self, attr): + # split the marker via $m so it only appears in the output, not ec= ho + path =3D f"{self.ADC128D818_HWMON}/{attr}" + exec_command(self, f'm=3DEND; cat {path}; echo "ADC$m"') + out =3D wait_for_console_pattern(self, "ADCEND") + match =3D re.search(rb"(-?\d+)\s+ADCEND", out) + self.assertIsNotNone(match, f"could not read {attr}") + return int(match.group(1)) + + def wait_adc128d818_value(self, attr, expected, timeout=3D20): + deadline =3D time.monotonic() + timeout + value =3D None + while time.monotonic() < deadline: + value =3D self.read_adc128d818_value(attr) + if value =3D=3D expected: + return + time.sleep(2) + self.fail(f"{attr} did not reach {expected} (last read {value})") + + +if __name__ =3D=3D "__main__": FacebookAspeedTest.main() --=20 2.50.1