From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636900; cv=none; d=zohomail.com; s=zohoarc; b=bvRIn4tjRkrrcDYzE+YtDwhDqml9nzrJ2HBhDL1alzxSUt4qQiglonSHRRawMEX0AIRxhOhK/IyFqUmQzQ0SwoGyE6ixlU4NLyy7Xvi0mwm9RCjg7DLwMIj+UAsVEPzouCGd/jHOMfNKgHDWwGhMpCjllOrp/I+8cm6svvlAaOw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636900; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=wiFN8tnkC1oJh00H2lpTvlEfTpjEPheg7d6EAAdG9AA=; b=a2YP+fBu571ju/4/L6TXprM2OeDyc9YFOtVODw6btp5Yu8evPvJk46uub2MeWvURXwEmcn4XGjV7nG7kHYpslDvjZrqW14hU+d9gwNyMk4NIKfZnOF8lLzjBzcJH3uy5jLneM3UaKsZ+ptpIozqVlvzJPQpNKMotofYpFYwqzv8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781636900269678.2115192412517; Tue, 16 Jun 2026 12:08:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZ8S-0004bB-9U; Tue, 16 Jun 2026 15:07:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7W-0004T2-Oj for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:50 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7T-0000qd-Or for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:45 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-491609cdd8fso26127695e9.2 for ; Tue, 16 Jun 2026 12:06:43 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636802; x=1782241602; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wiFN8tnkC1oJh00H2lpTvlEfTpjEPheg7d6EAAdG9AA=; b=fjliTDgpLPTTIqiYsFic4sCk56lkF6bwnwQwtui0A2TOVzhMTg+enZ3GR0IoDGpKtl i+DIWk/FA8+cq6gKy7/zSluG+PY/9/16NZIqn8kbbldU27LJ4i+Ch+yFhpbUDyUCg4/A z3zfchZdXaj1SA0fePIsJcOdWKAG8+o3sn0Tu476I3ArZPibtFGWTN3NrQYVGWVueRPh /BFwSFgV5DgRCmATw021jRqLl1cne4NYCuoFZF5tykiJxetkPPTjUCLZTaWdchNbsEzR C9bnKK0mkapc6VuGpwRpOp+3pxdVfm8zbMZkcr1YDhzPWPFWgkB9nIvnCHoAUKJvd/30 tqxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636802; x=1782241602; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=wiFN8tnkC1oJh00H2lpTvlEfTpjEPheg7d6EAAdG9AA=; b=cAHj8FxicOFQxwOVew3L7sWBN38CeBWaXBeMqLfRKGLjh+H+Sz0JveaHySOSt9rkJ0 SCnrTqtNfZ65NPS/3AK2E2iUlYErmhqJ0vyumpfVGoqPAwmXGBeEA+gu3RAZ+xGLImLW 0nCVqYnlvngZnNBKAdwoYUCMPxLpnNdYM52NSchZF8de/NqmM4CK7Ghv8UpcH6XVfmW0 v+v7nfzrHmx/mBnU3VQGxU+/zGngu3AVo+z39feLfv8JE5baI66PoEcMG+zcqPNWWE2G kPo7TTQsgB6Yeb3eRoQ+fq35aHkchsDpUmrPYc0rcE4dwUdRjWpeNe7eXqPcsJpHP+oU 95xg== X-Gm-Message-State: AOJu0Yy4KUQEIhlsIJReHRktE4+lnbsr91Dm+4chU3sAtpeDxRwMJQ10 gw6LO5RM9ZjpivXOnDDdotGzJgg6Na33AE0pUESRXA21iGYWKD6y+GHpUQ2EIa5gC16AwmGRy3H srJm1 X-Gm-Gg: Acq92OEJpK21XFIZHGbFIc8pVre3ljmLkLC5ZKrsDIaDuJiJXpSBikTVP4XJHrtUBmf p+4/hCslfMX3wOIPyxQwfoeJVh3zAzhW5zQS189mFFDiTog2Fa6YH2GMUnAO3QepGq+J5mOO386 jT9Aq+ZA/DQpc5n3sMMqOIBXkGzDvajMMBDp7PWRy5OWDCdSKkQifg3+Jc7i63kKm+GkCr3f308 RNmCwqzlLWJxMIyHLYWQcWmHe4qMbXvnp6IdoaUxQYyE1mpaI2jcJdcHIIQ/NXygNP6+peQ4+j5 0LTmNZ+XO1F6YUVIK7E15Uq478mfENyzvSpbiGfJLiQwl1+wRNRM+ESqfc0YdZFqdy3VGYSnSq9 S1zQ1bwQJoKYJtFmv6XXq7ybtML1wJsIpneh8zm1m03+DTFiublsL6++WHo0L//pvSUtzWSO8ay 5VKb3LAI/w8iJv1Q454AzKF+gdJ42R7B9uJobf1oEDtFR+/GQYJKLHF73kDUIq3VyZn1DgP5HBF kHJYETw9Auen2XUHx35oz6F1HFoCbkZ X-Received: by 2002:a05:600c:608d:b0:490:53b0:9e53 with SMTP id 5b1f17b1804b1-492333a1556mr17206605e9.1.1781636801968; Tue, 16 Jun 2026 12:06:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/61] hw/arm/smmuv3: Update ATC invalidation check Date: Tue, 16 Jun 2026 20:05:38 +0100 Message-ID: <20260616190639.3462006-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636900746158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Use smmuv3_ats_enabled() to determine whether ATS is enabled for the guest when handling an ATC invalidation command, as setting the ATS property value to 'auto' will resolve to ATS being detected as enabled in the ATC invalidation check otherwise. Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS") Reported-by: Shameer Kolothum Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Signed-off-by: Nathan Chen Tested-by: Eric Auger Message-id: 20260608174900.2227340-2-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 5c2855c377..0c65dc8c91 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1528,7 +1528,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp) { SMMUDevice *sdev =3D smmu_find_sdev(bs, CMD_SID(&cmd)); =20 - if (!sdev || !s->ats) { + if (!sdev || !smmuv3_ats_enabled(s)) { trace_smmuv3_unhandled_cmd(type); break; } --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636894; cv=none; d=zohomail.com; s=zohoarc; b=IhDA0Bj0HF1ha8qRcoohS/chvQyOSm7IvOMtBZHrUgY3L2h0bughTo7llkC5ygbZmH26DDGMGld4JEFMg+oNZSLh3aPA3JpD++CjNDC8q3+N6hPQ/F9xymlPgITzxwSrCg2cRO1QHq6mK/Y1kD+DrfY6N9Y4K2VN4ftyJaH3U84= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636894; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=8h8osnRLiH8j4IL2dsHuh3ADZfsc9tApZMqf6knJ0K4=; b=Mf2FSTlwd2BEZjwzUZ6iohADOd9ueYnOYPJZqTvSSFxVe3SjLDIiN6IQ1CAq7iHbPRHloPweyA9k5H4w3u7ATcLYcPEzu6/oO1lXJF3LQ/zuZ31SseQHnUvFr6VLVhQDByiuc1supZg1BrpS2Lh1abopXswV+IPRQ32eJUmmJpE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781636893970217.64809191643963; Tue, 16 Jun 2026 12:08:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZ8j-0004sp-Fd; Tue, 16 Jun 2026 15:08:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7W-0004T3-Pt for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:50 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7U-0000qi-ID for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:45 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-45f3cf907ceso2636345f8f.2 for ; Tue, 16 Jun 2026 12:06:44 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636803; x=1782241603; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8h8osnRLiH8j4IL2dsHuh3ADZfsc9tApZMqf6knJ0K4=; b=NhnbSb8Q4bwyExAbDA9TB79jU4GDncZ9McLlAtEP6pd/Wwl1ZOAgPkGEUipXGm22FV 3G0DlSHN3PeZsrx/k8mpljiLEZuGKHvZbHpnJ29gtDJgOJSkzsEp+LFkVGqhUAgYz0z1 0wzQ05M9wc4YdhEoFqvSIOMN5m/uz++TVCj9nnFpU1e74arNk5hcq3uuB1W94MUx4ZOt g2BDCmOr1bkv+lwbqmU0UqtWJh/3mTT/Ci4vLwAzJWRA62vKniT4io+gCH4hpq4J28Ao U2gfiv+SucUUKxaJ1In6npyee+8NvviPVtXc7C4uin1PPWrjj8jowSv36cQBooF63u1h jlow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636803; x=1782241603; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=8h8osnRLiH8j4IL2dsHuh3ADZfsc9tApZMqf6knJ0K4=; b=F5/f3L7zLeR/18HB8NAKHzZLCPquOG7j7dfYtD79mz8HEXpWxdEXLPOGKhSSq6/xUS zHnISFU8V2ApOofvqdtFRQXar4YOW/HvQ7sTvBWYb3vE0/sf1RuR2BBwjJTvoG7Uw1II QdrpIYAeS9KWO8f8yascE5zdcGm87N7jEqz7MgikxWEnSNUYW9Fs+jgmsfcp4q0rSHTu 0kJav0uUSuiMJfJy/Gs76hxKK6Fl/nmsObPQU6dA+PNT1SXa2Ey721jkg/2QFX/OLXR6 Mrx9mG8HC11mH6psluflXXBhR8Gsrju94dNeAakfPWNn86yqJPd1lDdw1Hsox6N3VDPE raVw== X-Gm-Message-State: AOJu0YyQ6GLPcunOM/CnPpAeUCJrDClru6jlFBbtJqQDqDggfMhSan5D iIqZE30+kIv5eStKtMns+nQZAdYeUoRtHseh2upt0aFMNJ4x6HVH+xtaPAh6J9sQ8OfBgnUd+Wf jg8ll X-Gm-Gg: Acq92OFCZq5ZMYZXVp2InTwabjYIgvzXeVOSqdkdrPNNVGLHYviSdo78gaEhzYv3fSj Un0ors8onqoo02ouIfVeO1S+aSg1m6Cp/lL4y1zF08pL9rbMkZ3UuWh+vobTkhtBEgY4gaC25KR 6BV2SjbQuzIqDlNH9LLDTUIDKHycDYhts1f4+X7u4e7Nw1vEDRwDPt/HwF7b3RJXW1HExvH4aLG HTXzgeb1YZbLAGpcOuFUsJm5xZBw4RR1E8DOV/mmn4/6V9LYgCjA7eaL8U/2vifnSQsHycpGvbP P9lwnrhCNlExghBQVWN2/Es6ZTgF3pETrI6kRROVkgVSgOTZdnIHQ87raSJa4ivFX7xgpC7f0MV 6rm1jELw78x9dpSMleP7m+bBXzZoNtebyXNr57e1hySvRSfKa2fjln8VRl8n1qy0KDfdZ3cLRDA 38b2FNXZHuVlcfqbU0RFhNoj4tiM8QnTGUZ3R34NzjrJ4gypZbeYsT8eS65o3vjBoGDzANnh/5r yyWPywu1M3pmKpGAftP1gaxg8h4vsvr X-Received: by 2002:a05:600c:608f:b0:490:c0d8:d517 with SMTP id 5b1f17b1804b1-492333ba2cdmr15020135e9.3.1781636803003; Tue, 16 Jun 2026 12:06:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/61] hw/arm/smmuv3: Improve accel SMMUv3 usage documentation Date: Tue, 16 Jun 2026 20:05:39 +0100 Message-ID: <20260616190639.3462006-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636895042158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Add a statement to clarify that the host SMMUv3 must support HW-accelerated vfio-pci device assignment when setting accel=3Don. Reported-by: Eric Auger Reviewed-by: Eric Auger Signed-off-by: Nathan Chen Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Message-id: 20260608174900.2227340-3-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 0c65dc8c91..6b5035e11f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2165,7 +2165,9 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) =20 object_class_property_set_description(klass, "accel", "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " - "configured in nested mode for vfio-pci dev assignment"); + "configured in nested mode for vfio-pci dev assignment. Please " + "ensure the host SMMUv3 supports nested translation before " + "enabling."); object_class_property_set_description(klass, "ril", "Disable range invalidation support (for accel=3Don). ril=3Dauto " "is not supported."); --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636899; cv=none; d=zohomail.com; s=zohoarc; b=jq05sW004NlD6jbglLcIXDFUmK8AgwzeEL9Q6ZXmQQS4F5Zyz8ufz684wFAnbUJSQ/Xpus+5OUFCkWfXbIp37Zh4zWQWGNG/ikR8o8q0zbSIeJ4KbBE8gZaUmrg+fESdWur3EX5VfBhx+IeZ6XNhN/E2mLvdJ9L5c8hkJHeCj0k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636899; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=bCfOcDxy18cXYwHGeiHuAV55BSHA/3vZ5XDQkQvuPDg=; b=GlNnyt9BbwxnIKCu4QneuY/xxqUZSJwaH3iY6a3IkMScmbylWFessWwOAKo8UmW5mhvoojO/+T4tEmeCxGVv8eKUPdAfZyUsztn9BFVkTtG/i1zEuUvAN6ubHZ3CNyVHTFAeAkgCNLBPJCuQQZbO8avAfMoXFdQDlvuv0Q9IHvU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781636899902989.8430119650292; Tue, 16 Jun 2026 12:08:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZ8o-0004wb-C7; Tue, 16 Jun 2026 15:08:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7b-0004Tc-8P for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:52 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7W-0000qx-G3 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:49 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-490b12270b3so30449935e9.1 for ; Tue, 16 Jun 2026 12:06:45 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636804; x=1782241604; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bCfOcDxy18cXYwHGeiHuAV55BSHA/3vZ5XDQkQvuPDg=; b=A/KRhTlIizftQ26oZZV3t71E01p49SF/H7MOA7gqgWE5M37LlLdQil0KwLcJiGckgM DOmflTttIyavp7an0iK1rTfWHsm/KSSZAzvN0jyKtNPBXQYHC/5jhKeIYZZqaLnzCl0x XrXL5ZlsVLhsG/Ry/VGt1ib8VXmcNtMc4i7x2EDxHpIw1LEKvrl261oWlCo0MOv15moK YtjtBU7Yi3YeVfNbiO1KMxpvX3NBUOoNqotxKc+zySDN6thq+g3f21y9D7jG7RNGnZpn HnzeeaVTDsZY97c6u4GjUAHZN/eiausnuqI6UrA/AsdXEHQESlz6hGAh225pCcNRX1QF XgkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636804; x=1782241604; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=bCfOcDxy18cXYwHGeiHuAV55BSHA/3vZ5XDQkQvuPDg=; b=FVhcIm5DApSA9qtGPpck44ShTMABryOH8Tn8XABvuWIeQdRSwjMo/6dfxgUK1/7eFM nOtKgzA+oeoZoh7cg6ldF9VVMH1PhqxfBQ0/JNjIWNdM0hL1/duq5ITtGu4BRoBdtiwT OBKarBhd6Rr/0tWHiC1ugOV3wocyPdnxRz0GOrRM6t3a0AtBmDDl9yd61ccri2HzKfnt hJ3k6fNxAQDKFFp2d6POR6fpcdWANEZtEilsfwdTwCU0zJhbowZbV1FRVaf6oJtDJcpJ fGpy3yDrWK4Ccm0V0XBQfFx4fGBE8yZKPQ8i893CsMaI44DZX18VqDr7BcZ2suf8yXl9 ndfw== X-Gm-Message-State: AOJu0YyMk9gthcx4Ud/dkg3ZtOMgw6erZH3DSC9bLNF07dIMwmEPVV99 mIFmF8EacenKUkSo39LVGlMW0H1CYMvYJ1Vz97N3cczC7koVzfX1ccjMx9Ow4ILgdcEEZ6DlBQS l1NkY X-Gm-Gg: Acq92OHCojhv1oPrTfBPNZiSZeo44xKJhZ9r11/iT6+LMb5+rep36ziyalJCvQcKfLY nfiV/Klozi7YE1gUnD8DC7fxlyOtatkUfTvhaq3qpYFgejr70ywQZJ0XhxATHyWhZ4LvDUtZNFE ApJb3uzM42N+0q9p8zD9bNiYb2V262lXBY4KQcLzTNCzgkaK/Qng/V175wR5K8NwEiiNc3Ppr5a 2XxVA9r2RoHfUfs5Kjfy91tXIFsz3FCPrzDtzTVB1Wq9cZjW74j+NuiaKPy0eGeDVNAxDVymLTf q5w9RolPEzmY+ZE7fS2HgXx8GCttWviX63zBj9vq6dBwdJhdVsqj9U2bjvlDDPJ10wDJTsPbA/t 9SzFMb1p1kglscvVumm6nOoYQhXHhi3N2IYTjMXkjFHCnPOSf8cwKVKQ9YRvBSp2Qwbkh8dC/rm YOqifMR0Eq2uW3OXYqgloT5HBFQWHnrP7YtnZ1WtjERhbihu5Ui3jqrit6phpRELYTaHNMJzaNb Joh2OVTE9FcvMQ9dqX01ojqF1hB2uF3 X-Received: by 2002:a05:600c:a319:b0:492:1e36:8c4b with SMTP id 5b1f17b1804b1-492333df110mr10614235e9.36.1781636804047; Tue, 16 Jun 2026 12:06:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/61] hw/arm/smmuv3-accel: Add helper for resolving auto parameters Date: Tue, 16 Jun 2026 20:05:40 +0100 Message-ID: <20260616190639.3462006-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636900799158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Introduce smmuv3_accel_auto_finalise() to resolve properties that are set to 'auto' for accelerated SMMUv3. This helper function allows properties such as ats, ril, ssidsize, and oas support to be resolved from host IOMMU capabilities via IOMMU_GET_HW_INFO. The later commits in this series set the auto_mode flag to true when an accel SMMUv3 property value is explicitly set to 'auto', or if the property value is not set and defaults to auto mode. Setting these property values to 'auto' requires at least one cold-plugged device to retrieve and finalise these properties. If the auto_mode flag is true, register a machine_init_done notifier to verify this requirement and fail boot if it is not met. Hot-plugged devices into an accel SMMUv3-associated bus will re-use the resolved host values from the initial cold-plug. Subsequent patches will make use of this helper to resolve 'auto' to what is reported by host IOMMU capabilities. Suggested-by: Shameer Kolothum Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Signed-off-by: Nathan Chen Tested-by: Eric Auger Message-id: 20260608174900.2227340-4-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 41 +++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 2 ++ include/hw/arm/smmuv3.h | 3 +++ 3 files changed, 46 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 862be814a0..fa0a97cece 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -18,6 +18,7 @@ =20 #include "smmuv3-internal.h" #include "smmuv3-accel.h" +#include "system/system.h" =20 /* * The root region aliases the global system memory, and shared_as_sysmem @@ -35,11 +36,33 @@ static int smmuv3_oas_bits(uint32_t oas) return map[oas]; } =20 +static void smmuv3_accel_auto_finalise(SMMUv3State *s, + struct iommu_hw_info_arm_smmuv3 *in= fo) +{ + SMMUv3AccelState *accel =3D s->s_accel; + + /* + * Return if 'auto' was not set for any accel SMMUv3 property, or + * if property values were already resolved from a previous call + * to this function (e.g. if this function was called again after + * VM boot during device hot plug). We do not accept new property + * values in this case where auto_finalised =3D=3D true, and we re-use + * the values determined from the initial cold plug. + */ + if (!accel->auto_mode || accel->auto_finalised) { + return; + } + + accel->auto_finalised =3D true; +} + static bool smmuv3_accel_check_hw_compatible(SMMUv3State *s, struct iommu_hw_info_arm_smmuv3 *info, Error **errp) { + smmuv3_accel_auto_finalise(s, info); + /* QEMU SMMUv3 supports both linear and 2-level stream tables */ if (FIELD_EX32(info->idr[0], IDR0, STLEVEL) !=3D FIELD_EX32(s->idr[0], IDR0, STLEVEL)) { @@ -918,6 +941,18 @@ static void smmuv3_accel_as_init(SMMUv3State *s) address_space_init(shared_as_sysmem, &root, "smmuv3-accel-as-sysmem"); } =20 +static void smmuv3_accel_machine_done(Notifier *notifier, void *data) +{ + SMMUv3State *s =3D container_of(notifier, SMMUv3State, machine_done); + SMMUv3AccelState *accel =3D s->s_accel; + + if (accel->auto_mode && !accel->auto_finalised) { + error_report("arm-smmuv3 accel=3Don with 'auto' properties require= s " + "at least one cold-plugged VFIO device"); + exit(1); + } +} + bool smmuv3_accel_init(SMMUv3State *s, Error **errp) { SMMUState *bs =3D ARM_SMMU(s); @@ -925,5 +960,11 @@ bool smmuv3_accel_init(SMMUv3State *s, Error **errp) s->s_accel =3D g_new0(SMMUv3AccelState, 1); bs->iommu_ops =3D &smmuv3_accel_ops; smmuv3_accel_as_init(s); + + if (s->s_accel->auto_mode) { + s->machine_done.notify =3D smmuv3_accel_machine_done; + qemu_add_machine_init_done_notifier(&s->machine_done); + } + return true; } diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 407940616c..87fecb5c68 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -25,6 +25,8 @@ typedef struct SMMUv3AccelState { uint32_t bypass_hwpt_id; uint32_t abort_hwpt_id; QLIST_HEAD(, SMMUv3AccelDevice) device_list; + bool auto_mode; + bool auto_finalised; } SMMUv3AccelState; =20 typedef struct SMMUS1Hwpt { diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 82f18eb090..85be3d7467 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -22,6 +22,7 @@ #include "hw/arm/smmu-common.h" #include "qom/object.h" #include "qapi/qapi-types-misc-arm.h" +#include "qemu/notify.h" =20 #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region" =20 @@ -74,6 +75,8 @@ struct SMMUv3State { OnOffAuto ats; OasMode oas; SsidSizeMode ssidsize; + + Notifier machine_done; }; =20 typedef enum { --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637291; cv=none; d=zohomail.com; s=zohoarc; b=Z8E25dkvuCBANn9cW+3k4O8liG7lrpS3woEv+UaPoLUL9alEG+dreQ2R1bNLBEBTPS1e2wM35lIc5A4kBdDlsA6hz1ZvuRZmlZxJjTzTmZ9BN6k8ehFXuoroLjph3YhaeCkw2vWV8jHd6zneTJOoMcpg9HU5O+C2ZOGk6y2NN8k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637291; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Pm4M0R4Q7tuMhA/6UlAOFIFLqaw2nq+zNN4VlqUo1LY=; b=nxpoDah1GMH/rrOvnKC01FgcvjYUY7H2e5oGY3atyWbaWe3cSoZtO/iYEDhe7iIBuAteGzDsWQ+9jNkuYviaUcm/zTUX9TPH8eJ0dfeRIn66jazxOEhVlgLN7CUKh8zdYHC4cZLiD5pr8+7aqE1UMAIlAHcI8UWMD1i+Q20g+lk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637291729159.1851521171767; Tue, 16 Jun 2026 12:14:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZBQ-0000z4-Rz; Tue, 16 Jun 2026 15:10:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7b-0004Tb-BH for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:52 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7X-0000rx-91 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:49 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-45fd464d51fso2909612f8f.3 for ; Tue, 16 Jun 2026 12:06:46 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636805; x=1782241605; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Pm4M0R4Q7tuMhA/6UlAOFIFLqaw2nq+zNN4VlqUo1LY=; b=fnW4DXBA40/K4sjhh7b/zS7H+6b7nD2GnfzZL3S1kEAy61vSJZ1gWvzRwjXRjhyU9z QURqJGOV7tLhNZXJQsGe0T1T1K2Ht2wQHBXmCQMfCj99K38JrsvnilfzhKOjcTo6lPWA MsMlOEMeAglRTxTtGWXGj8N6QMjkK5/X8Q/CYL1mV5MyF8ilJkRsg/DKbzzR/IYAv2B2 tIQbW9tVamILa4kUVm0PSbNSTr+BjSSVRr+fA3QDe6O19sZ7c5Yww+cek5B3iJd6A/JC siXceQSqE25FC8J/Cof/eGMXKcuEzzkZYd2cB5YfjsQlL34iv6SBhnaxHLQLYoGaf9u/ gN+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636805; x=1782241605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Pm4M0R4Q7tuMhA/6UlAOFIFLqaw2nq+zNN4VlqUo1LY=; b=A16MGLSwi+yWITLThjhaIT1bDtOsgdmnfl6K14DtW1NoWunIo0iS+qSaoHbUqREQMC cE239EqmS5va82UWK83DBP1Zay7QM/FfI533r7HsG49+k+yvbkpUWz1xl1dGREW71bt1 UE7SB/rADuwKvzm079D1hy3WUyNfyjhPAR0apWtU6a/eiorBmzyonlCnrNvRA54srQXH hqhEzKmYICCfJdo3SAhHrchDXsKewy58JSVc1K71Llvev7Xe7W3wHcETCAaDLAFxGE9E J6NxR8jktLSixrQf4Ov5jQO54OlTaxM9H0SED8cRg5sU2Q1zNc6bhQOhUOkGff4vPZ4L XggA== X-Gm-Message-State: AOJu0YyUL9+SPkN64in18ipGMN7BHaVN374bX5cMdJztbjaSu4kF2iPH vZZoRogROVAsZzsCsuh2Gi11v5WBuUWpR7vOfZiyQRaYNtEMsZxq+/IHO+2WYCa5a2wpKnsuLQx w1Stv X-Gm-Gg: Acq92OEBVcghvacjYmyhpVinDA7ytEz+ZOaGbcqrt8Id5zIeSGMfrrx3PdYpX9UJ+XB SH15O8XuHE6d1HgmZnokn9oEWjDST4+3tEzDEc9psGSeySal94NwhOynVm3GphAJIFHlr+SSLZj LtRWCuVaQLvVa8BfpWennQzmxTBV0HyQoUVemcaNGPnVzgR1cAJ8XjpzILwhODtA7PuCiJ5s15U K0ycwW/KLFi1OOzwC4yG6KzWGkI/epJS4y9pWgi6VgoZnC+IVgcsATmCIeqSiMAPCC9dgJ97ISE pro0c/248tVDAtSwLV49DLaj1LHeQFOkVIalFE3QczBEGOV2iE4gXmddPV3cEj1yMcypb32K1+b 2BjJejPUZjpAhhUXyDidy64ZLDBqpW+gDIfkCdlccIKGyL2ccbf9kT4u86yp7yqlc/sCYLkfpPs jo+d0BGustW99rfcZ8FJhH0fQcqTdMFABv9hD3uW4ZT6bL/AHSwief7x1DUGgpW7Ibv+a/LW3Dz ZmrR+19322Op9gqLi5u4P3R1UKJVuba X-Received: by 2002:a05:6000:43c6:20b0:452:75ca:3fab with SMTP id ffacd0b85a97d-4623955b609mr997776f8f.38.1781636804949; Tue, 16 Jun 2026 12:06:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/61] hw/arm/smmuv3-accel: Implement "auto" value for "ats" Date: Tue, 16 Jun 2026 20:05:41 +0100 Message-ID: <20260616190639.3462006-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637293306158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 Address Translation Services support property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving ATS capability from IDR0. Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Signed-off-by: Nathan Chen Tested-by: Eric Auger Message-id: 20260608174900.2227340-5-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 9 +++++++++ hw/arm/smmuv3.c | 11 ++++------- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index fa0a97cece..4c2acbbedf 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -53,6 +53,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, return; } =20 + if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, + FIELD_EX32(info->idr[0], IDR0, ATS)); + } + accel->auto_finalised =3D true; } =20 @@ -961,6 +966,10 @@ bool smmuv3_accel_init(SMMUv3State *s, Error **errp) bs->iommu_ops =3D &smmuv3_accel_ops; smmuv3_accel_as_init(s); =20 + if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + s->s_accel->auto_mode =3D true; + } + if (s->s_accel->auto_mode) { s->machine_done.notify =3D smmuv3_accel_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 6b5035e11f..436155d883 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1965,10 +1965,6 @@ static void smmu_reset_exit(Object *obj, ResetType t= ype) =20 static bool smmu_validate_property(SMMUv3State *s, Error **errp) { - if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { - error_setg(errp, "ats auto mode is not supported"); - return false; - } if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { error_setg(errp, "ril auto mode is not supported"); return false; @@ -2172,9 +2168,10 @@ static void smmuv3_class_init(ObjectClass *klass, co= nst void *data) "Disable range invalidation support (for accel=3Don). ril=3Dauto " "is not supported."); object_class_property_set_description(klass, "ats", - "Enable/disable ATS support (for accel=3Don). Please ensure host " - "platform has ATS support before enabling this. ats=3Dauto is not " - "supported."); + "Enable/disable ATS support (for accel=3Don). " + "Valid values are on, off, and auto. Defaults to off. " + "Please ensure host platform supports ATS before setting it " + "to on."); object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=3Don). Supported values " "are 44 or 48 bits. Defaults to 44 bits. oas=3Dauto is not " --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636920; cv=none; d=zohomail.com; s=zohoarc; b=TfGJRaPfouXadmENjQ96x+JZ0YJy+EI+RbQGZrbsqtnPz5nsTDXG0rDrZv3Dc33PFLrzo+slZckjkcdkR7ie6yMlUATYMavghvwnx3RKtpytdKATdnrAkPq1KoZSfjqE5T2XsS3sPEMcfGtnxu8lxoLRp5Hkqc2GR8de7Ijpw1s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636920; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=/dB7M/fDHtSrW6aC8fEDHLa+zvgj33Xv8Vnh6D9Vtkk=; b=XAQOSP5TemMZskD7QGHpNocoFXPni2e1U6bhJ1LLZoLf0/vHaQA3AlNbdaubVUfQ514DcIhEH63GdTQc+S0tKw2bDdfJI7C1cmLaRqHTJwV5rJjTcNH2wv/cxrbn/lY7d6al0e1w9O1E2jI3CObLsiQ1KOURcQhxYmjwoqkmFGg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781636920461602.7003628424358; Tue, 16 Jun 2026 12:08:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZ8x-00053N-UV; Tue, 16 Jun 2026 15:08:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7b-0004Td-Di for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:52 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7Y-0000sX-A5 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:49 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-490afc47455so22584645e9.2 for ; Tue, 16 Jun 2026 12:06:47 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636806; x=1782241606; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/dB7M/fDHtSrW6aC8fEDHLa+zvgj33Xv8Vnh6D9Vtkk=; b=goPP4TGLmWofvUI7UyBDMFFrFOiJ8L5DxjKTeg+O+Ak6V+Y1cxs2sp+UnjwliK3b5l vcVVic8pI2UHBvzMRxpKNWlJnF+QpQTR4eucw554KsD6P0msKwBTWtQyfUFZ8fAXSnCH XIzGKTr8txaea1n0D+X6rQJ3q55aLYSjTNTTZ5rVkWmejH489u14F65YHUYeyGTuzwPa WobbK5lBJdk2oeH/pLtnsPnTUX/GZTiRt6BEgjwdcvNq7M2MrdlZa59THe7Qe+Yo9lQs 7hXqWW7I3/sNCzeNB1rlwNi0dwT7/2vgBbx+jvl+MPrUCWxC4xiVRh1xH+u2s6JEMCWF BI3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636806; x=1782241606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=/dB7M/fDHtSrW6aC8fEDHLa+zvgj33Xv8Vnh6D9Vtkk=; b=TB+ZAVS0P2fXe23yAKfLyHSXhqIGEHsK/Ii8J6Y3ePZp1QUwA+LSPu2uezxpRDAQLB bP38QVTsJyrt62RMV6FMpyMIz+2a5GbJIh0uJLKM7/GdSyXkD+ZVaXKb9fROxQ9UrGHV KULKvfCiQjjtnRTYAg14ATwU2WuXStQxhU9gj4v+5obqGwA2+N4zKw7Z+Fc4fmk3pdpK 9lYQzxilrVK4hJD34sFgYuAejgA/+0jEcRzCprgRruU0iNd22IablgGlEDC107d9CfJz BkzmvUbbPaj9HQhILt4wSA5MGN+XXOUN0sAIbsJLRrPvxxXjuJF9xKILJ0aiUYPfl/N9 2fhA== X-Gm-Message-State: AOJu0YxXCGJ7vKcrD/1nklXCC7tShr949vG7OJjd9NfH3fWr058Gr9cu mxGnL1a+7MZ21UKyXDIhVFWg+e0G7ujjVAvrSx92C7GaW9IQl3/4QTFD+CPf9YooexasyC9hACp nMb1Z X-Gm-Gg: Acq92OGzrK7oU2zIrhNt7F392COcWtkPPWGzlvk5WBCN1Dj/Em+ca3i0vjB956ojy1l uTN71U5tkFPMuf1MnywZkBiSMhJezzmPqpzPEoBMxIp7mQ+WTk2n54rcpkqKdVpm19mmkFt6AFV 4Dm2KAWYEsngilMqD3oNHSy6AXyy898SDYSeG4CsFDTJL09mVFhaNeThVdj8D0+IxFv2e0jph6j 3F+HEmXg1qa/rKBkoVeO8Ok8dmjyzk567Ao/B97HMjSHVIY7loLJygfph6G35EuroDWIEJUeL4Y 4v6qZwMrFrDCIKcNoIARzWN5eF6HNzcOUMKKQcrEp8Y5q+Ar9Cijq6hO6BSJ84y3/GbzA6qjw0C H8VMKdjD7fFajOEM2yHjyNR8D+7iCfX7VI0t2CVnvpFgMWGH7RAeiM2NWkoZ13sou2K8nCyOPMN ZmjpEqlNt91SG8DTofQUcr+FBS4TIXa5suVeUDpcRh2Onuzossvf1T6GSS/PbTRlRKI5bsk032N 7hdeS8ToUAsZD/GJVvv0aL9zZc3x6mC6luTkYt4xMY= X-Received: by 2002:a05:600c:c094:b0:490:b642:ce2c with SMTP id 5b1f17b1804b1-492333af1b4mr11230595e9.14.1781636806076; Tue, 16 Jun 2026 12:06:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/61] hw/arm/smmuv3-accel: Implement "auto" value for "ril" Date: Tue, 16 Jun 2026 20:05:42 +0100 Message-ID: <20260616190639.3462006-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636921384158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 Range Invalidation support property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving RIL capability from IDR3. Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Signed-off-by: Nathan Chen Tested-by: Eric Auger Message-id: 20260608174900.2227340-6-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 8 +++++++- hw/arm/smmuv3.c | 10 ++++------ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 4c2acbbedf..25699a1317 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -58,6 +58,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, FIELD_EX32(info->idr[0], IDR0, ATS)); } =20 + if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, + FIELD_EX32(info->idr[3], IDR3, RIL)); + } + accel->auto_finalised =3D true; } =20 @@ -966,7 +971,8 @@ bool smmuv3_accel_init(SMMUv3State *s, Error **errp) bs->iommu_ops =3D &smmuv3_accel_ops; smmuv3_accel_as_init(s); =20 - if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + if (s->ats =3D=3D ON_OFF_AUTO_AUTO || + s->ril =3D=3D ON_OFF_AUTO_AUTO) { s->s_accel->auto_mode =3D true; } =20 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 436155d883..c183964b2e 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1965,10 +1965,6 @@ static void smmu_reset_exit(Object *obj, ResetType t= ype) =20 static bool smmu_validate_property(SMMUv3State *s, Error **errp) { - if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { - error_setg(errp, "ril auto mode is not supported"); - return false; - } if (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { error_setg(errp, "ssidsize auto mode is not supported"); return false; @@ -2165,8 +2161,10 @@ static void smmuv3_class_init(ObjectClass *klass, co= nst void *data) "ensure the host SMMUv3 supports nested translation before " "enabling."); object_class_property_set_description(klass, "ril", - "Disable range invalidation support (for accel=3Don). ril=3Dauto " - "is not supported."); + "Enable/disable range invalidation support (for accel=3Don). " + "Valid values are on, off, and auto. Defaults to on. " + "Any attempt to turn it 'on' while the host does not support " + "it would fail."); object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=3Don). " "Valid values are on, off, and auto. Defaults to off. " --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636923; cv=none; d=zohomail.com; s=zohoarc; b=Y0rGUkY7vJ7qoZ7gCurMOsVxPvx4kKImjVBjXjwPclGhS74XMhNdw8XffEpnrNHLTf1pN5duVGw62r71+iXz2Tc8G7TVKLY4xsg36nfAQCA+ThEIp6ooPSTo64oLhf24tmrT4eWFIe9f3N3pb5d5KpUzKWgrnS4sElPT++sZqUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636923; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=x7Z0DitXa1v+MteFgBvClXzp4a3rrnN+3XF0rZy7+F0=; b=TbkAii6guyvRDuaLcLz8iiwuf+YNxzDRjL7kXEAOdef/Xwk0Vchsv6AyZLVAGgHGNAhY5iUtXL5tTNfaXz/DLJ9UYSGEO4ARhnfiziiGmsKjPy+OkG4WYTykCOR53e0WkAUc9qaag4mLamy4W4PQanDpWlciVybW141l4RjP4vk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178163692326020.125858561969835; Tue, 16 Jun 2026 12:08:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZ8h-0004po-34; Tue, 16 Jun 2026 15:08:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7c-0004Tw-HL for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:08 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7a-0000t8-HN for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:52 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-490b4a8e28bso37728185e9.1 for ; Tue, 16 Jun 2026 12:06:48 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636807; x=1782241607; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=x7Z0DitXa1v+MteFgBvClXzp4a3rrnN+3XF0rZy7+F0=; b=Q8PfXhqyODktYtZ/+qduL/6nbok9oeTMtDUGyNVZaxGGlY9/6lU/sDBPpjtSlVVoic t/k7nGLr8sIlhoMVsgGw4W+auxQwjNByX3TSGDTSnxQ9MQX44FaWR5Tvs/tU5SQkI1Uj 5Gua3PXPDaE91VuIgceiwQzTBPThZ5B7rTDVplTMETqyluEeHlZVNFi22LavVzEs3dr/ DmKud8RRQg2tvUChrnO2sJ7MRHSncoL7z98wvKNMQ/6uy9RDtO9Uvxf6lZAiVFBNinc/ jd+N0ibPQfvGYSgDOWij0LbHkaZv0RT/bMEXzUvkgU4+R08yf/F16E5WNLRHbK+0TZBe XOIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636807; x=1782241607; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=x7Z0DitXa1v+MteFgBvClXzp4a3rrnN+3XF0rZy7+F0=; b=SU/7ROIaJ8rdfKBKwdui6sD57VnQOyoVBoXeXWHqynQ6TsvtMRqlx9xToMVwAX33/N 1xN4vkqCYpYqe7LTSdOMBgo/tygycYgcGnsdhtIt/ug4P1uQn/glllMk7J0fOmqcffDb SkXLdhL3NNZvHRSMv8XTNnIt7f1Dlc5aYye0vu+WyQLsX5i5gaQtLhA/zT0AUATRpNYP gmp+usM1qzGi61j18twyTvbn+psoyURWv95thmTdoxWi4m9BMfbfk4qD3Vq3YnaYohu4 GXKkucRPHW6a14gfJlVGGnzFP5/1ub7ktwRL7i89XCN7/nxTZVDYTbamaPl0JqtIKIWi k2Sg== X-Gm-Message-State: AOJu0YyjIJJLylVoVAVpdDhL5eee5R72FNUj7r+003gxIfGssQlYAeWA Di92qd5BWGovCS0GMP+a/w4dj74nZ6YepAp1t+gdo+23Dan2k19jabH1jgrP3+417sgRtIEWPBd CZC8a X-Gm-Gg: Acq92OHq5kfZ+izZ/xWhlxGeHc/17AnaUQwXKhlNj0xKxTcVeeGNIHBMtL3CjQcaerY 3RuyqOCeA2JkcM0O8uDtY69761Pj79kWuAamnOGssrB1RbiOTLAyiTtyc99Yn9rKJO8/9FwYH9Y dQ5CGsexhllTp8zegQ6okii9Sq3iwy8reBGzXTeZOKgKOjDl8rNTS4rnEAOvVKGyl0YyopkDYMR Yri7DGc68Pe7YFeMJQ/Dia5qPZKzsfokj7kkQhDDnISsUoYnnkfihRowLi1Psi64waiicuHSLwD RF5a2O1UB6PiNF0bWr16o66wmxI4aYWSI8jqoEIM5k1XPfOYw1uTotP1cEHvWZzzxJq5za7UEqy HMljpmbhfMBQYyNVq8uOobNkBPahgrN1VVdrA9p1zu5vjEGl6eZv06MMQWw6qtWoUnXweoQBP8r S/GJ5OCTMpfjgFYT/XQlT6WSxMekP0y40TDAYd7y+IvvHfH6Z7AlXRtNtOSs2TiD4MCvfFdwUPF 3GD1E4Z7PKobvi6f5PUGzkCdt47m/ZS X-Received: by 2002:a05:600c:a111:b0:490:e5c1:b89d with SMTP id 5b1f17b1804b1-492333ffd28mr10996215e9.0.1781636807478; Tue, 16 Jun 2026 12:06:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/61] hw/arm/smmuv3-accel: Implement "auto" value for "ssidsize" Date: Tue, 16 Jun 2026 20:05:43 +0100 Message-ID: <20260616190639.3462006-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636925023158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 SSID size property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving SSID size from IDR1. When the auto SSID size is resolved to a non-zero value, PASID capability is advertised to the vIOMMU and accelerated use cases such as Shared Virtual Addressing (SVA) are supported. Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Signed-off-by: Nathan Chen Tested-by: Eric Auger Message-id: 20260608174900.2227340-7-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 17 +++++++++++++++-- hw/arm/smmuv3.c | 22 ++++++++++++---------- 2 files changed, 27 insertions(+), 12 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 25699a1317..3f141991eb 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -63,6 +63,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, FIELD_EX32(info->idr[3], IDR3, RIL)); } =20 + if (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, + FIELD_EX32(info->idr[1], IDR1, SSIDSIZE)); + } + accel->auto_finalised =3D true; } =20 @@ -823,6 +828,13 @@ static AddressSpace *smmuv3_accel_find_add_as(PCIBus *= bus, void *opaque, } } =20 +static inline bool smmuv3_pasid_supported(SMMUv3State *s) +{ + return s->ssidsize > SSID_SIZE_MODE_0 || + (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO && + FIELD_EX32(s->idr[1], IDR1, SSIDSIZE)); +} + static uint64_t smmuv3_accel_get_viommu_flags(void *opaque) { /* @@ -835,7 +847,7 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opa= que) SMMUState *bs =3D opaque; SMMUv3State *s =3D ARM_SMMUV3(bs); =20 - if (s->ssidsize > SSID_SIZE_MODE_0) { + if (smmuv3_pasid_supported(s)) { flags |=3D VIOMMU_FLAG_PASID_SUPPORTED; } return flags; @@ -972,7 +984,8 @@ bool smmuv3_accel_init(SMMUv3State *s, Error **errp) smmuv3_accel_as_init(s); =20 if (s->ats =3D=3D ON_OFF_AUTO_AUTO || - s->ril =3D=3D ON_OFF_AUTO_AUTO) { + s->ril =3D=3D ON_OFF_AUTO_AUTO || + s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { s->s_accel->auto_mode =3D true; } =20 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c183964b2e..d59931d1a7 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -626,7 +626,10 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cf= g, } =20 /* Multiple context descriptors require SubstreamID support */ - if (s->ssidsize =3D=3D SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) !=3D 0) { + if ((s->ssidsize =3D=3D SSID_SIZE_MODE_0 || + (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO && + !FIELD_EX32(s->idr[1], IDR1, SSIDSIZE))) && + STE_S1CDMAX(ste) !=3D 0) { qemu_log_mask(LOG_UNIMP, "SMMUv3: multiple S1 context descriptors require Substream= ID support. " "Configure ssidsize > 0 (requires accel=3Don)\n"); @@ -1965,10 +1968,6 @@ static void smmu_reset_exit(Object *obj, ResetType t= ype) =20 static bool smmu_validate_property(SMMUv3State *s, Error **errp) { - if (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { - error_setg(errp, "ssidsize auto mode is not supported"); - return false; - } if (s->oas !=3D OAS_MODE_44 && s->oas !=3D OAS_MODE_48) { error_setg(errp, "QEMU SMMUv3 model only implements 44 and 48 bit" "OAS; other OasMode values are not supported"); @@ -1989,7 +1988,8 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) return false; } if (s->ssidsize > SSID_SIZE_MODE_0) { - error_setg(errp, "ssidsize can only be set if accel=3Don"); + error_setg(errp, "ssidsize can only be greater than 0 " + "bits if accel=3Don"); return false; } return true; @@ -2175,11 +2175,13 @@ static void smmuv3_class_init(ObjectClass *klass, c= onst void *data) "are 44 or 48 bits. Defaults to 44 bits. oas=3Dauto is not " "supported."); object_class_property_set_description(klass, "ssidsize", - "Number of bits used to represent SubstreamIDs (SSIDs). " + "Set number of bits used to represent SubstreamIDs (SSIDs). " + "Valid values are 0-20 and auto. Defaults to 0. " "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " - "Valid range is 0-20, where 0 disables SubstreamID support. " - "Defaults to 0. A value greater than 0 is required to enable " - "PASID support. ssidsize=3Dauto is not supported."); + "A value of 0 disables SubstreamID support. A value greater " + "than 0 is required to enable PASID support." + "Please ensure the value does not exceed the maximum " + "SubstreamID size supported by the host platform."); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636941; cv=none; d=zohomail.com; s=zohoarc; b=W+DisxaDQje9JAvpKuNi2KM6crQsp7xkxNuY39yLfl5ErSRA0QjZoLPLAuJYbvQqsErhxfTya9z78G7JiZJMrLsVaDZBgsU3KvOCXRdqxgoJ9+EzNf0vkeHWLTLear3VqiA50yR2Syio9ulYXXrIDtVa5yNG8E8m8GRMzkVzkFI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636941; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=+7Eo4SU78o6Ns7AfCRCkuFEyF7iTIz+MbUN5Y5O64T0=; b=nSpKuuOvisf02sPI8EoLIVKNxoQvUj/NRgWPqYRcpjt74/LI0Nj4ndOMr/4oCYmp+ZR/wu5AiJYAD+f4ltKw+6i523ALOfoZv+OG7M025vpVNU3AUVj8HLviOGlCAqkm0dOyLvwCulhiROiDnEXjB1fYf9LL9GDA9mXTlG4t5Es= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781636941237577.665452875989; Tue, 16 Jun 2026 12:09:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZ9F-0005AG-Hq; Tue, 16 Jun 2026 15:08:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7e-0004U5-DS for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:15 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7b-0000tc-5r for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:53 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-490b7866869so50203145e9.2 for ; Tue, 16 Jun 2026 12:06:50 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636809; x=1782241609; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+7Eo4SU78o6Ns7AfCRCkuFEyF7iTIz+MbUN5Y5O64T0=; b=lDTLZoAGVf+tcd960jsnBQXHKOeLsZH5x/w19H/HGsfqelmnqhFQr5i0o3eZZ/pxpB 0T2qaD9Io6J6dVwoME3aLfW9PHTAjAls6HrFjCnI1Pl/Gb+5mBahl1/miBkWvuCeMGCK EC45nhm4w697GbLuKHH6h9hxgsHT056LcLBB4sOinSY4qBf8/kQoYcifcv09Ft+JdXIa aFG86R/eAkOg5xT556mKvnnxJwpBPLkZswVeuBllO1XT1XwBM52kI40JrVbEFjZcs5sQ P8ZmYi7n8aiGDZY+F6Tj3Pw6Mav3qRZ2uejDe63FsyLjIb1b7TMESv5nK4v8EOTavkc+ izpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636809; x=1782241609; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=+7Eo4SU78o6Ns7AfCRCkuFEyF7iTIz+MbUN5Y5O64T0=; b=sSZP9nGzOpWz0ywL3o0S0FlT+UHsoWyPp/Q1GEGQmKNIXEw0+Zqb8+uaFAS1NY35DO 6jHiWT6867pt6VAvGahX7bNfYXE6eGfbrlfE6YSI4ZWKaoOhbRvU35smGqUi4HF2LRI/ ntrezJqVhHda0TbdgPDJ5UT+5pdSSUubRA2F5xxwESf/P54NBUpEhu3NGd39t8KraEMP NK3VCxxM+BP/oShY8IabAazrMQ8LwYAhXhVPgOIYu+pGgTGNZZBCcZn3GVz8ml41q6pz lJoWASP5ncUGMe6Eel7Izgy+VojeyghJ9xE1jVUnFdRN4xJGVW9xZ9GJ3Wquid0PEC/9 etTw== X-Gm-Message-State: AOJu0YxBP32Q8HziQEdsrWL3cAbTebYeSZj5xWWLvp7WSh8tdxgWsFOE n/gOeQ4FdinhogngXFGA7VH7+J25qnt5/Snsz6kuEjOR2H8Avp5kgZUk8MDM+S7jfuDhEOg/ry5 GjhfD X-Gm-Gg: Acq92OEMn9zaEDpW1oanC1ck8eTUA3b9ibzDzOCq72WLlX0qUxv6fZmfxctETY6H4bi XXPdoEuU6CVO3ooG1YfMivqeRs3yfYK0z3rXC8gXC5a94HE9Aou91QP5tEHLuWBt4Gdb75m158R JKQc2jlSgEqSHZ+nbYLQiw2YN6tkJwSCE6XMla+u2sCGNvFoN8sMvDAUc0PlG64kMCgu3OdhlPY boSivTRj5QAudVWRD+yZCoNCSIL6DyiyA0Zlx4bsi7SCaiO5KKnV25dD/QU/vmpIqTQrD7fiEMw 0LbKXImY6xWoccL8+TJmgIobZmI8X49yNGWv0cs6AixNQ4oJe6/PUei0kSVi24rzT4rKoQjhHS0 Pi0ydgFUT8ooN9xBZ+zsetssopcL+qAx/qGKgEPSr0wXqhRqkIf+F8XwpCXrwMV2iDKdpmBNioA UWjEVcBlcx9YSGCLjPk+ibLN916ZS0D9gqBsrKNdhf3SeNs9se1WCi1p4LAXQEDeIZtui86Vu3l KpIhHVXnGl30UVuyZMvzug8rbM+HUYb X-Received: by 2002:a05:600c:8184:b0:490:625e:bb68 with SMTP id 5b1f17b1804b1-4923339f885mr14992975e9.3.1781636809250; Tue, 16 Jun 2026 12:06:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/61] hw/arm/smmuv3-accel: Implement "auto" value for "oas" Date: Tue, 16 Jun 2026 20:05:44 +0100 Message-ID: <20260616190639.3462006-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636943031158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 OAS property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving OAS from IDR5. This keeps the OAS value advertised by the virtual SMMU compatible with the capabilities of the host SMMUv3, so that the intermediate physical addresses (IPA) consumed by host SMMU for stage-2 translation do not exceed the host's max supported IPA size. Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Signed-off-by: Nathan Chen Tested-by: Eric Auger Message-id: 20260608174900.2227340-8-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 8 +++++++- hw/arm/smmuv3.c | 17 ++++++++++------- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 3f141991eb..06dadf9cc7 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -68,6 +68,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, FIELD_EX32(info->idr[1], IDR1, SSIDSIZE)); } =20 + if (s->oas =3D=3D OAS_MODE_AUTO) { + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, + FIELD_EX32(info->idr[5], IDR5, OAS)); + } + accel->auto_finalised =3D true; } =20 @@ -985,7 +990,8 @@ bool smmuv3_accel_init(SMMUv3State *s, Error **errp) =20 if (s->ats =3D=3D ON_OFF_AUTO_AUTO || s->ril =3D=3D ON_OFF_AUTO_AUTO || - s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { + s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO || + s->oas =3D=3D OAS_MODE_AUTO) { s->s_accel->auto_mode =3D true; } =20 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index d59931d1a7..89289ab6d2 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1968,9 +1968,11 @@ static void smmu_reset_exit(Object *obj, ResetType t= ype) =20 static bool smmu_validate_property(SMMUv3State *s, Error **errp) { - if (s->oas !=3D OAS_MODE_44 && s->oas !=3D OAS_MODE_48) { - error_setg(errp, "QEMU SMMUv3 model only implements 44 and 48 bit" - "OAS; other OasMode values are not supported"); + if (s->oas !=3D OAS_MODE_44 && s->oas !=3D OAS_MODE_48 && + s->oas !=3D OAS_MODE_AUTO) { + error_setg(errp, "QEMU SMMUv3 model only implements auto, " + "44 bit, or 48 bit OAS. Other OasMode values are " + "not supported."); return false; } =20 @@ -1984,7 +1986,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) return false; } if (s->oas > OAS_MODE_44) { - error_setg(errp, "OAS must be 44 bits when accel=3Doff"); + error_setg(errp, "oas must be 44 bits when accel=3Doff"); return false; } if (s->ssidsize > SSID_SIZE_MODE_0) { @@ -2171,9 +2173,10 @@ static void smmuv3_class_init(ObjectClass *klass, co= nst void *data) "Please ensure host platform supports ATS before setting it " "to on."); object_class_property_set_description(klass, "oas", - "Specify Output Address Size (for accel=3Don). Supported values " - "are 44 or 48 bits. Defaults to 44 bits. oas=3Dauto is not " - "supported."); + "Set Output Address Size in bits (for accel=3Don). " + "Valid values are 44, 48, and auto. Defaults to 44 bits." + "Please ensure the value does not exceed the maximum " + "Output Address Size supported by the host platform."); object_class_property_set_description(klass, "ssidsize", "Set number of bits used to represent SubstreamIDs (SSIDs). " "Valid values are 0-20 and auto. Defaults to 0. " --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637337; cv=none; d=zohomail.com; s=zohoarc; b=UbzJQqEZKWUWnSj84navbyFkZ46EIE8mlfheoxQrFUwdLxMdk6DoeJC+5DkvUSbah2g0V3Ifc7SQ7xpwv7uh/fS02M36U/1OIiZ1UJqxe6suUAQiGdklE6CZhSPK4Hb5e8XLhIm+WycT43HHoEv5zZ+SZh8XL1kQwLkGBriqLkM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637337; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=AIHwlbRuUl3nYtw5K+xyEs99Ce+k47eRk9h4LhKsLb4=; b=kQVXxB8+03sDU9o4TACUo36M/e//pYeFCqFjkiyMD/qcdWhvUCYngVianI5f/oTlhrxd5zz5F2/zboTsIb9pFtvrKK60jhFMnscQfKA3KF/pFyYPctE9A1XrwGdoIdBp6ajlkTnvrN4fJrv/mTYCMRGx9CtIMwa9jCofBAv8K80= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637337210730.6475856289644; Tue, 16 Jun 2026 12:15:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAU-0006tl-MM; Tue, 16 Jun 2026 15:09:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7k-0004UR-Mi for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:24 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7c-0000uu-P0 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:55 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-49230a567a9so6465995e9.0 for ; Tue, 16 Jun 2026 12:06:52 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636811; x=1782241611; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=AIHwlbRuUl3nYtw5K+xyEs99Ce+k47eRk9h4LhKsLb4=; b=JsquobFpjsNmDIHs3k8tocNby6OOTWDrhgbGYVtY9HWZjbIh4DhrGJH7DMBnVL7Vx5 j+YFDzPNkyfowPLeiP8ku6WUZN20lZ2PCDozPzdyfIpSK9CfzXR9MGFay+sSXkY6flAB ZEW0D/ew/B6z/81GjxHVw2LUVpLcvSEoFpc6UsaC3VFJQJA24Yg3NCjz3urzmbC5hfOQ Ba6wSs8TLTZlkNTlQEI7PF3yMsTQZUp5y3Dt+3EB0yso/I4F40npCpUvgxa5iXevylsK vVn6uHkt5mvw+YWm6J3qZqZ/2NLyQBsijtFPQ2L3w1GfsNC1P2zNp+liy0plmNGPUmsJ 7XTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636811; x=1782241611; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=AIHwlbRuUl3nYtw5K+xyEs99Ce+k47eRk9h4LhKsLb4=; b=Ieio1R2Kp0YKOh5hQWc6ZhvfGQkm1qCt6XC3Q3/F04Ilo1+k2ePdJ+JBXrocwnPhqb PE9IC+1lei5Gu6ojF2ISRl6HY550uTd3ofSIrfjOSPVXZpFCRib9+XFryjKIfDe5E7Ur TlPd4QR5ORaZeQ1/1NP5bV3lTbYtzUdAZFqtRh+C4mb9UrlFz/HsCCgL0ZG3+YsfKHDP jqGgrY7rMSny2gAka9d/ZlveJPVFgJUkvrwPJmqjIW6MlNMugfYnm+8dmA2ROyUoUuAe zFoPEKE4nhhfybhYMrzZVsowOitGIFNpelhiyfLNHE81LfXH6+BHV0PoYzjJ2M2ukzg6 LTmA== X-Gm-Message-State: AOJu0Yyb64uDQoJ/0Km/zQOKai6HU6/WsXnFRJvxknDTifsdVQ58YFiW AEKy7GMcFuuVZhi3nkOEZxXC/DEQW/As0Gj3SRa8cT44U1I2JvPUUfPDB0NJejgFKA6xYIwj1KI jJKQJ X-Gm-Gg: Acq92OHZNGmGzCy/EV1/tH5uR0ruHQiKtTqUSNL6rPXwyuVfxpEsHj3GjF4V71GTlal 1YG5lFsLPOvgbjj1DwCT37H7SfXu9GDc6NcfNXjG9O5Sj3Z2uTaqPu3YvJ89ohh+Zq572JZv0gv lQM/o1+/3CSd1ikHh1a1kvUgRRGJaZGrGImUX7jYQ5UGOkxnIdjSEGkOanpOf/OqILCMdFoAL1C Z1vRUmP/GKuzAszicj5gtkNadFr5FZXTlyxlcW2WEZOuyw5kkPotS8gYD0FLlrHLch3DY+vdSby ZLXblVa3JIWQfCAljZJosst3fK490QYpqoO6ytbOrp8fp9WWN3F7XiQ49r2RPVfhn6b7vYphSb5 4Oo5kDbR+Xr/nSpoUXxMFlDSb0ALLhCe78tBgEJ071STpoIBKjppIySTH6TTQdFVhdfLfIgS7im QO2rEiRNXOE3HyV/3IL3bC5A4uMThv3zWCyDiW/lxmdJC64+YHnjpON7LkKzcEPlwinxw30c5/t ll4S4ZH84qaVUNJmAZn6zrAtQpoEQHv X-Received: by 2002:a05:600c:19c6:b0:48e:6db3:ff33 with SMTP id 5b1f17b1804b1-492333f9b76mr11316645e9.14.1781636811202; Tue, 16 Jun 2026 12:06:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/61] hw/arm/smmuv3: Set default ats, ril, ssidsize, oas to auto Date: Tue, 16 Jun 2026 20:05:45 +0100 Message-ID: <20260616190639.3462006-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637337788158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Set the default value of ATS, RIL, SSIDSIZE, and OAS to auto, in order to match the host IOMMU properties when accel=3Don. If accel=3Doff and these property values are set to auto, the default property values defined in smmuv3_init_id_regs() for OAS and RIL will remain unchanged, while SSIDSIZE and ATS values will remain initialized at 0. Introduce a new compat for the changed defaults. Reviewed-by: Shameer Kolothum Reviewed-by: Eric Auger Signed-off-by: Nathan Chen Tested-by: Eric Auger Message-id: 20260608174900.2227340-9-nathanc@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 23 +++++++++++++++-------- hw/core/machine.c | 5 +++++ 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 89289ab6d2..83fa6468fd 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2129,12 +2129,19 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), + /* + * AUTO values for accel=3Doff will resolve to: + * ril: on + * ats: off + * oas: 44 + * ssidsize: 0 + */ /* RIL can be turned off for accel cases */ - DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), - DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), - DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_44), + DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_AUTO), + DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_AUTO), + DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_AUTO), DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, - SSID_SIZE_MODE_0), + SSID_SIZE_MODE_AUTO), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2164,22 +2171,22 @@ static void smmuv3_class_init(ObjectClass *klass, c= onst void *data) "enabling."); object_class_property_set_description(klass, "ril", "Enable/disable range invalidation support (for accel=3Don). " - "Valid values are on, off, and auto. Defaults to on. " + "Valid values are on, off, and auto. Defaults to auto. " "Any attempt to turn it 'on' while the host does not support " "it would fail."); object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=3Don). " - "Valid values are on, off, and auto. Defaults to off. " + "Valid values are on, off, and auto. Defaults to auto. " "Please ensure host platform supports ATS before setting it " "to on."); object_class_property_set_description(klass, "oas", "Set Output Address Size in bits (for accel=3Don). " - "Valid values are 44, 48, and auto. Defaults to 44 bits." + "Valid values are 44, 48, and auto. Defaults to auto." "Please ensure the value does not exceed the maximum " "Output Address Size supported by the host platform."); object_class_property_set_description(klass, "ssidsize", "Set number of bits used to represent SubstreamIDs (SSIDs). " - "Valid values are 0-20 and auto. Defaults to 0. " + "Valid values are 0-20 and auto. Defaults to auto. " "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " "A value of 0 disables SubstreamID support. A value greater " "than 0 is required to enable PASID support." diff --git a/hw/core/machine.c b/hw/core/machine.c index 4d8b15d99e..9a10e45aab 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -38,11 +38,16 @@ #include "hw/virtio/virtio-iommu.h" #include "hw/acpi/generic_event_device.h" #include "qemu/audio.h" +#include "hw/arm/smmuv3.h" =20 GlobalProperty hw_compat_11_0[] =3D { { "chardev-vc", "encoding", "cp437" }, { "tpm-crb", "cap-chunk", "off" }, { "tpm-crb", "x-allow-chunk-migration", "off" }, + { TYPE_ARM_SMMUV3, "ats", "off" }, + { TYPE_ARM_SMMUV3, "ril", "on" }, + { TYPE_ARM_SMMUV3, "ssidsize", "0" }, + { TYPE_ARM_SMMUV3, "oas", "44" }, }; const size_t hw_compat_11_0_len =3D G_N_ELEMENTS(hw_compat_11_0); =20 --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637286; cv=none; d=zohomail.com; s=zohoarc; b=lMmeewWX0kEmZ4cpLvuqDd8VMbsLNi/b72sIVocAamQQ3W6S/bslrwhg5Kdo58eqzvycS1uB7Cup+99Zd1/+5BcfWZUZRBqugoDuPzmmG5pUqgivlzW6so2xEMAP9+4AZ0UxnSxq1eHq8KxcmG1eAphbb3zTtjpC18PyJ39i8yQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637286; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=WBtSV8TCpO70q9Fff+5grXWMF28TTKbkq2iuNuY8wtw=; b=VJ8HgUVuzFyMQBV9mTdlVMp/HkdkDETqD+d5H4e0DEDPXEIskBLKJeYhTZR4OqfzNchAwOtSxLu1cegvhpGHNYQJ3BIosshIhResYntIsbGprG27ip1p7nywhGnIyOzpRdPYswlC7jBt7URjasMnTUd+Qm2Ne/idSS1UaZhpeyQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637286626597.6925413731364; Tue, 16 Jun 2026 12:14:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAT-0006kk-Ix; Tue, 16 Jun 2026 15:09:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7q-0004Ud-9i for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:24 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7e-0000vH-1p for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:06:56 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-45eea68dd6fso2659745f8f.2 for ; Tue, 16 Jun 2026 12:06:53 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636812; x=1782241612; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WBtSV8TCpO70q9Fff+5grXWMF28TTKbkq2iuNuY8wtw=; b=r3Z4ccZ2gYMrk6rRkmNq71wQ3cXDC1gcqZwcCApsm/1T1KXhllv5VZH3TEpSs8I6Fs IJL0hskQu370QDTSJc7hrLbcuqrcv7O2vvQ/GLtN4YrHiHN+JzH4BD9g7J0st5Iylep/ Qtikwi39rKzQZhAtHSmoJXDeEKHNIanXApoArvnocKawtV7e0oPnHcadrMS7G8aZ5Vmk z62MlSVw5aon5f1cZvbzMogoTefQvpPBsRqf6wXstQ29mSti3FfJ6LrAxncaQtF3yBW+ ixPutPc8DJL/rYoXIIfyJmZv+WwGTZOumwU64EZZoLLKka5qGj9/+mMUPPaaKBlsENC4 H29A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636812; x=1782241612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=WBtSV8TCpO70q9Fff+5grXWMF28TTKbkq2iuNuY8wtw=; b=i6yiZDg9MTT2O6Ng89BOdKASft0oi0s4F9lvVh9etvxVWSVOXqdohDATHflQJlf7n8 uCzTg2EzP6wf8dSV5IbqFmL3DnZ06uLUr1k9KZKRNl5AionSS6ZNLWDO3e3nhV/Z8e5x 33DafbX6lkqojmtVertcqkzc8mpde7iWpr8pL2hc/uyL1OY/4mqShMqPpgJFpNhFyA+z kTc8bbZh/U4SaDuWMYCEJc+DPloIz9rs/+7KgfhyRO7badgIVvUCxZHwcFHy0EcI9pAm vPq2B/PLIt4hNe7sgwakF0t3Nf1R92tlOjZS207B1zMwFTgDys2hXlXeAOesfJjAOSED lwCQ== X-Gm-Message-State: AOJu0YwIORhj/YRC6wRRvdGOSv4Ho1bDdhe/gNoDxMJkUB8RavEq81kX K5aN8kyWjTD9hlZnNxcMTo0eTtYwcVftYXzE/gAqs9G5JHqHQK/+OD1vnI6xiz+eQZZQlwu10NC nyTel X-Gm-Gg: Acq92OFIonh+ri/CdsIuw+VEVby4OXa///Mzvds7JlRDFViqvQD4DlDtJBIN2KinlbI 25NbkQQI7AQZbVP861eSPtdxu7WFPrSGGTpzClbKQN0n+Yu2usx5+4JggqTzze7lUmJUGRIeLQi DKVWsD4T06TRK99h3xuDblMoN/WGs2OK27klw4rBx0mVOjWhAN+0vf3qKoBqz6yO0ABNwLz0izp XawH5MQ0Pgz5yN37RaKN7R4ek3zVAWfTbsT4LTzyWoPRnAiGs2l+NrjZRgbYHUU3PspZ252I8Yr ZHi17yde6uQT4dtCbFPEkaN4sLr//PlANhsuXA9QhgWp3C/HLB6vGWmyGFQAvFdmRvc9ggDPpwQ ZtDRR+Vlgj0hCKWHvkdiaJlI/MYlq+QpBlIpQD2APeMYhg70KDFBYeTxyiiVY5D8ypr6Ql7zkQJ pRlmBr1ORSE+FCz/fxrqhiRw92Z0EnPHJCjrFeflBS9e0LWEujwkHbpv6+7k7X/4rmJ2gJgx2FH s4qB5URC3aLklPK48frM+NfKFMMGUz2 X-Received: by 2002:a05:6000:22c4:b0:45e:fb69:f02b with SMTP id ffacd0b85a97d-4623f2e7641mr939787f8f.1.1781636812179; Tue, 16 Jun 2026 12:06:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/61] qemu-options.hx: Support "auto" for accel SMMUv3 properties Date: Tue, 16 Jun 2026 20:05:46 +0100 Message-ID: <20260616190639.3462006-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637287321158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Update documentation now that "auto" is supported for accelerated SMMUv3 properties. Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Signed-off-by: Nathan Chen Tested-by: Eric Auger Message-id: 20260608174900.2227340-10-nathanc@nvidia.com Signed-off-by: Peter Maydell --- qemu-options.hx | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 2fd21519b2..a5979d0a5b 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1291,31 +1291,44 @@ SRST Enabling accel configures the host SMMUv3 in nested mode to support vfio-pci passthrough. =20 - The following options are available when accel=3Don. - Note: 'auto' mode is not currently supported. + The following options will be set to auto by default if not manually + set. When accel=3Don and these properties are set to auto, the value is + derived from the host SMMUv3 capabilities via IOMMU_GET_HW_INFO. With + accel=3Don, this requires at least one cold-plugged vfio-pci device; if + none is present at machine init, QEMU will abort. =20 - ``ril=3Don|off`` (default: on) + If accel=3Doff, auto values resolve to the non-accel defaults given be= low. + + ``ril=3Don|off|auto`` (default: auto) Support for Range Invalidation, which allows the SMMUv3 driver to invalidate TLB entries for a range of IOVAs at once instead of iss= uing separate commands to invalidate each page. Must match with host SM= MUv3 Range Invalidation support. =20 - ``ats=3Don|off`` (default: off) + - With accel=3Doff, auto is resolved to 'on'. + + ``ats=3Don|off|auto`` (default: auto) Support for Address Translation Services, which enables PCIe devic= es to cache address translations in their local TLB and reduce latency. = Host SMMUv3 must support ATS in order to enable this feature for the vI= OMMU. =20 - ``oas=3Dval`` (supported values are 44 and 48. default: 44) + - With accel=3Doff, auto is resolved to 'off'. + + ``oas=3Dval|auto`` (supported values are 44 and 48. default: auto) Sets the Output Address Size in bits. The value set here must be l= ess than or equal to the host SMMUv3's supported OAS, so that the intermediate physical addresses (IPA) consumed by host SMMU for st= age-2 translation do not exceed the host's max supported IPA size. =20 - ``ssidsize=3Dval`` (val between 0 and 20. default: 0) + - With accel=3Doff, auto is resolved to 44. + + ``ssidsize=3Dval|auto`` (val between 0 and 20. default: auto) Sets the Substream ID size in bits. When set to a non-zero value, PASID capability is advertised to the vIOMMU and accelerated use c= ases such as Shared Virtual Addressing (SVA) are supported. =20 + - With accel=3Doff, auto is resolved to 0. + ``-device amd-iommu[,option=3D...]`` Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). Only available with ``-machine q35``, it supports the following option= s: --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637318; cv=none; d=zohomail.com; s=zohoarc; b=AcGtWGzKdzz6Frw+YBFDLz8OfHbPMfxo8AoErtrPLJT5SHGJn9oj0Or9IFuv2nyPbt7TYq+UuE0Zwja7OY4yJqPWuRnmVrSTDmoPB7Lkg4eFIzKHdUbmMYLOVkvrSZIr9DYyWvcjvKt8nOf1RVP0AfIgHYtq8wRLJZG0/S4YLCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637318; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=weeNUWxYJjehY3MuWZ1bYEiCEGF4TezcF0oM8vo2/xw=; b=FAkuAa/zt614NXq/Owavqufm5Z8o/D5sp+CkfzT+tkYaomFBNouVg0NM72WTP/O+e2XWbsfNBFb4d56OoDx+0eVisB6YZyD4PFuKUYQpbAyeDcpZQ21/J84X4+aPCv1gPGPAWmJmwnO6mrY6m7zf623K2nheWWyieMMMmuz7Yo8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637318418540.6143695337946; Tue, 16 Jun 2026 12:15:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZDT-0003Bi-QO; Tue, 16 Jun 2026 15:12:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7u-0004Uw-Qv for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:24 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7k-0000wA-EE for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:09 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-4600cbb06deso106466f8f.1 for ; Tue, 16 Jun 2026 12:06:55 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636814; x=1782241614; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=weeNUWxYJjehY3MuWZ1bYEiCEGF4TezcF0oM8vo2/xw=; b=o8BosrEYKiM63g5TjeI/m4c81ENgqLyH7gDpRmnLa03TczldI6cFvGOiH7JT/mLtgV rvp5jFfJ1tUZb1L27xF7DtTvONOjTLK1mUHDl3N3I0ZNFvX++4JynNQZ1H1hW9YkWCVj 5vLfN9mFiUJkGwZzOuO05MAgLvmn1UcSP0JSXXXU6wLlKTZpBG2BK7h/PPf4pq4bgyPe Dts46F9NTCFE/5FIT9cPqBwKzm75sJql69la+x/+Ado1FaulGRsIT4SJfI+XmVNTpDwO +w3UoY773HBk5MeX9gQRx/DH3V1TONOKYfP8D7AuP2Co4L/669SA5hGiLInFssEysDvX hV1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636814; x=1782241614; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=weeNUWxYJjehY3MuWZ1bYEiCEGF4TezcF0oM8vo2/xw=; b=kotS2rsCIHmoN1vPmepYTJsgBBa+IuKBsyQIF9s71HvILNr0kkD7MjorPUF3Ucd8jj /ufB+l/Qh2kovIQCKGFg9IiboGJABKJ4WcIk+rJV++dU6Mh8JBJwAchxVARx5JFTs/LI eqjEhK2Uh5su1GAJS11Ppl55dBrC34xZjWOxevhIfyuDRBc+TB8sf7DLyTDOqJ9aCnKt r2u4V01Aq4vHwCE+5RHlD+5Cjjgn33zMyP4J4lLA7ZiqpNNbHZij0YNAaEqJribUCiEa eURIoO8ZWgIHFTylnl6ylZUuV1jAEn68MHSqu4i7BZ9zsfBV9pJdKPjRuNrwdUQ4FvXS rdyA== X-Gm-Message-State: AOJu0Yxx6mcqW3vULBsTwZgwNUiO0Q46w0Re+YfUO0eoiosab3inWux9 f5HBaV+UX4pj0SFfW8x6Cj5xctewfr7EsTd/2Zm7oMZFsxFdw2hdnNb9pXS0W96YjzgbLE65X8M VavWf X-Gm-Gg: Acq92OGNNXvM+ofVFrJ+ifL4rfi96GbPMSnF81Rq+tQ018+Sb3PMSJ4lWZXjp7DoBKl 3WjrPqS8Y25/6uaUxU7WbZLPrT8QiXjiZyJEqvewcCrrJbQdGQH76x1xk1XqWYlELAaXy9+82HT bysDj42fLzET0Ac9l2MWp1kC9Lcy0oz29H0PwDrLSg5+JTEypNVHyHFP6+JPPnXCj1a61/05Su/ Lpu9g672SyrMnR4KQiyi4CQ8DiWbLGcMQKy2niha+tCa+b0fIGnpzHdg8hvtyybUEzacR+4x1nO swS7A2WaBwneeOPt2Zu58GLmGg/yo+1JekBDq2Z33cOFQxeGiaPNCdjVc1jpyDVP1LyHof0QByG 7LVJBS0TQUBShvaNxe3sR3rekYAyPq9KIHYSprfYTxIaFbDcrqlJIeuRotTKRhAR0VrCOmqHC4U Zj99ZRAnQwe7qh/Y2gf+FTVMmfJzt+v4h+if/Y9pKU6zKbHMpGdfpd3iw3iv9zmDvEcDZ5YisPt rMgA0jsR5Flyfz2Ulc6yFDLFImjtZ/H X-Received: by 2002:a05:6000:220b:b0:44f:69f4:39b5 with SMTP id ffacd0b85a97d-4619f325353mr8732365f8f.29.1781636814159; Tue, 16 Jun 2026 12:06:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/61] hw/pci/pci: Enforce pci_setup_iommu_per_bus() is called only once per bus Date: Tue, 16 Jun 2026 20:05:47 +0100 Message-ID: <20260616190639.3462006-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637319667158501 From: Eric Auger Currently it is possible to attach several arm-smmuv3 devices to the same bus although it is a wrong setup. Change the prototype of pci_setup_iommu_per_bus to pass an error handle. This latter is set when iommu_per_bus is already set and used by the single caller (smmu_base_realize) to report a useful error to the end-user. While at it document pci_setup_iommu_per_bus callback in the header. Fixes: 66d2f665e163 ("hw/arm/virt: Allow user-creatable SMMUv3 dev instanti= ation") Signed-off-by: Eric Auger Tested-by: Nathan Chen Reviewed-by: Shameer Kolothum Reviewed-by: Nicolin Chen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260603124415.1120808-1-eric.auger@redhat.com Acked-by: Michael S. Tsirkin Signed-off-by: Peter Maydell --- hw/arm/smmu-common.c | 4 +++- hw/pci/pci.c | 9 +++++++-- include/hw/pci/pci.h | 16 +++++++++++++++- 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 58c4452b1f..8e40ba603d 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -981,7 +981,9 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) } =20 if (s->smmu_per_bus) { - pci_setup_iommu_per_bus(pci_bus, s->iommu_ops, s); + if (!pci_setup_iommu_per_bus(pci_bus, s->iommu_ops, s, errp)) { + return; + } } else { pci_setup_iommu(pci_bus, s->iommu_ops, s); } diff --git a/hw/pci/pci.c b/hw/pci/pci.c index cec065d108..d3191609e2 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -3314,11 +3314,16 @@ void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps= *ops, void *opaque) * IOMMU ops are returned, avoiding the use of the parent=E2=80=99s IOMMU = when * it's not appropriate. */ -void pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, - void *opaque) +bool pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, + void *opaque, Error **errp) { + if (bus->iommu_per_bus) { + error_setg(errp, "An iommu is already attached to this bus"); + return false; + } pci_setup_iommu(bus, ops, opaque); bus->iommu_per_bus =3D true; + return true; } =20 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 5b179091de..f2448e941a 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -863,7 +863,21 @@ int pci_iommu_unregister_iotlb_notifier(PCIDevice *dev= , uint32_t pasid, */ void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque); =20 -void pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, void *op= aque); +/** + * pci_setup_iommu_per_bus: Initialize specific IOMMU handlers for a PCIBus + * + * Similar to pci_setup_iommu but enforces that the iommu only protects + * @bus downstream end points and no other bus hierarchy + * + * @bus: the #PCIBus being updated. + * @ops: the #PCIIOMMUOps + * @opaque: passed to callbacks of the @ops structure. + * @errp: error handle + * + * Returns false on failure with @errp set, true on success + */ +bool pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, + void *opaque, Error **errp); =20 pcibus_t pci_bar_address(PCIDevice *d, int reg, uint8_t type, pcibus_t size); --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637339; cv=none; d=zohomail.com; s=zohoarc; b=Us5E3Vi74A12hMoyCxp+zOv1t1TJd2Uyg0IXm+Ggsb816i3I8mjdon1dAFm9FYiCXAjayLaJtMOpgsOfAx1AvxozY6qeLNB4aBdd4+M59ehQoNVC4hnVHXzHFnpkDTBfRhi9GYMNV7Wsn9YR2ODhdOtze8bc9Q1wDZ+mid5lMpM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637339; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=/PbbrDXH+b4CwM0ZMVh7ZRRPi4k/+m03KAIQLjS5GKw=; b=MR1jZfx7nE6j/fTE741rrJXyfXUvz18a43StNK/YWLzNSek0Bj+n9ws1bQRoVfb6Kbl39yVyjzYKQldTrxYFQhIgh9ctU2glq4dyIy6Bv77oKq48NK8c0DkiBst9H484l4MFv6J+iPB2MEP8zXB5CnFyPC6NwV3TvTktPuyh3pQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637339756599.6820007026104; Tue, 16 Jun 2026 12:15:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZFF-0005qJ-FD; Tue, 16 Jun 2026 15:14:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7x-0004V1-AO for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:28 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7q-0000wj-0D for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:10 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-490bc6a7958so1523615e9.1 for ; Tue, 16 Jun 2026 12:06:56 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636815; x=1782241615; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/PbbrDXH+b4CwM0ZMVh7ZRRPi4k/+m03KAIQLjS5GKw=; b=mAbr0daiXKqvF3JomDC6nqAmN9coDctITWilaLeoABBsZMVf8SISEQt3gSahM1nTZ8 u4oUh56yMrW8gqwgYRyQOo3rDTkhG6Gs6z03gPBL4IfaavWUV7NV5NbSseYWXi7WziXg DoE0C5Qx2hat74kRV24EVJCgcVsu7IIMR4tf2ntEARbcZ/ZRJZTgT4JLnrbp7aWlIaep B59S3Eikcz5JjCJT654Dz/e/+A1pg5F4URwJsBY0tlEVeSTCAl+Gvi/NF2/kLgvLnbFB Mn9RWcE6TvRWZM5lBTdPvj5ba1U0lTz1ynG+YvJYAc4gpHoU4VHf1UZgaQm2w8mYeWtb 9a1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636815; x=1782241615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=/PbbrDXH+b4CwM0ZMVh7ZRRPi4k/+m03KAIQLjS5GKw=; b=E4vFODXPyghFolvNVY9sgMpP72MBqtbnXSip63UtFh/Tyf6ffCc2rb918pqscVu9eR 16u91TZNkqY+RxvXJsB3tEBNEKDH1mudWLQGpCFTolFpmXvplJ/EM4qMxsN1riHE/yDD /YQe//ejTcGHYkMsbBBQ5kk7Z0Z5crJMKiIB3RuUwie6gOXMk6p8WUs97UA2gZd+VY8R zt4aGBnhiCpUx8qsiFdc0RxSvEA/C+QdwdiP2SXzXXssdsyF6R0GKFlCj+Kjoo/Z2ayM VEkFT98NXe8EeB3VPuxhLl2ba+Zz5l5wxibqd4f3wZt69q+82X+Wd5XyK2ayqBksDj+w HAnw== X-Gm-Message-State: AOJu0YxOb7eyuwNzON7cXC7H5Yg1b4qcTXC19vAmTUqNp+Fyskw/WZr3 cM/mxidpep/Hi6brB7Ml95+vppKZxWvGkXmZeX+tvZDZcOnppMBHyDEcL/FPGAnMlv03963Y8l0 rTgGu X-Gm-Gg: Acq92OGnmK4De5pTMcITM3eRMa/KtcXt96leyIC2VOlYOkh5shLqWLL9DqEI0G/Mo+6 Pt5NSUhv8AI8WMJ5sz5H3yPoDDi7zP8OGjNVUnFyZdU8b7RbmP/WKkzXXZb9xEAuy1FaqtA2MTg 4GYkgGQzRp7ZcMI0nQhGmtSuGLHCQJCJxzq+FSb1cYSh56ycuP7jaGw1sKP3kMBR3L1ne14T+yZ Fzt1EJFnRodpUvJlZ1xqSez1lDI9uHYCLIUecGrqN+8QaQgVV2Tz1fAiOZmSwniEMdWjYRIkkY4 53jhlqt8BFSdtPBlVtvC2lS0HoGQo7gtZ/cvY1bCtP5cm4XtUFfbxT8whXJdbuip2ml7jnx8k8I MRkJ0cG1L7kQ0pLSTmTqgOgmMfQf/8mMcQ6en3rYWaFZriIcLdHv1PaYcOvt7bsJ3uYUdFDskxW 2QkS3XJH5NsOG2huckGgnFh2F97s89DPySpv1xwIWzOEbog5Gp1dqHlixqsxU0/Cg22MrtQow9q fml8xbB1urQs1KBJq5r7u9e/Zfb5Jb6XYQ/z7Dmy+Q= X-Received: by 2002:a05:600c:6c10:b0:490:55d9:149a with SMTP id 5b1f17b1804b1-4922fb14703mr68476865e9.18.1781636815432; Tue, 16 Jun 2026 12:06:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/61] backends/iommufd: Update iommufd_backend_get_device_info Date: Tue, 16 Jun 2026 20:05:48 +0100 Message-ID: <20260616190639.3462006-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637341744158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen The updated IOMMUFD uAPI introduces the ability for userspace to request a specific hardware info data type via IOMMU_GET_HW_INFO. Update iommufd_backend_get_device_info() to set IOMMU_HW_INFO_FLAG_INPUT_TYPE when a non-zero type is supplied, and adjust all callers to pass a type value explicitly initialised to zero (IOMMU_HW_INFO_TYPE_DEFAULT) when no specific type is requested. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-2-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- backends/iommufd.c | 7 +++++++ hw/arm/smmuv3-accel.c | 2 +- hw/vfio/iommufd.c | 4 ++-- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/backends/iommufd.c b/backends/iommufd.c index 410b044370..8c3a981392 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -390,16 +390,23 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend = *be, return true; } =20 +/* + * @type can carry a desired HW info type defined in the uapi headers. If = caller + * doesn't have one, indicating it wants the default type, then @type shou= ld be + * zeroed (i.e. IOMMU_HW_INFO_TYPE_DEFAULT). + */ bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid, uint32_t *type, void *data, uint32_t = len, uint64_t *caps, uint8_t *max_pasid_lo= g2, Error **errp) { struct iommu_hw_info info =3D { + .flags =3D (*type) ? IOMMU_HW_INFO_FLAG_INPUT_TYPE : 0, .size =3D sizeof(info), .dev_id =3D devid, .data_len =3D len, .data_uptr =3D (uintptr_t)data, + .in_data_type =3D *type, }; =20 if (ioctl(be->fd, IOMMU_GET_HW_INFO, &info)) { diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 06dadf9cc7..163d3e7279 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -176,7 +176,7 @@ smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDev= iceIOMMUFD *hiodi, Error **errp) { struct iommu_hw_info_arm_smmuv3 info; - uint32_t data_type; + uint32_t data_type =3D IOMMU_HW_INFO_TYPE_DEFAULT; uint64_t caps; =20 if (!iommufd_backend_get_device_info(hiodi->iommufd, hiodi->devid, diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index df148a49a7..495a59cc2e 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -353,7 +353,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, IOMMUFDBackend *iommufd =3D vbasedev->iommufd; VFIOContainer *bcontainer =3D VFIO_IOMMU(container); bool viommu_nesting, viommu_nesting_dirty; - uint32_t type, flags =3D 0; + uint32_t type =3D IOMMU_HW_INFO_TYPE_DEFAULT, flags =3D 0; uint64_t hw_caps; VendorCaps caps; VFIOIOASHwpt *hwpt; @@ -948,7 +948,7 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *= hiod, void *opaque, HostIOMMUDeviceIOMMUFD *hiodi; HostIOMMUDeviceCaps *caps =3D &hiod->caps; VendorCaps *vendor_caps =3D &caps->vendor_caps; - enum iommu_hw_info_type type; + uint32_t type =3D IOMMU_HW_INFO_TYPE_DEFAULT; uint8_t max_pasid_log2; uint64_t hw_caps; =20 --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637373; cv=none; d=zohomail.com; s=zohoarc; b=JPFY1HDM4SPNnNL2FZJ5YC38kJHxLNWbagF5e/WcDXQHeQn73Js/uxpPnAWRg88IrwEdlhvjmO0k7jmLQ1uzE5+n01JyxiARJzshfJUibVXQgFIhaESTdG26Zq1yxMN6YnTsU+PXHB87zbVU8jpJXje2+cVOG4rLFj0STvf61p4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637373; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=cpvEVVFmObCOAVZYrBljFN84sP1hXmtFa5bYh03siP4=; b=hjdyWTLRFWbhD6TUh6fLJfnt76HvtPM3yG3XYAekSFI2FujR3PfB0lOwvXr8vA9g4dBGu79K2Asec4h7Vi1a044z4nDUSI+8hJi4twKEkW2KlYcDdh0cp4PngESctFOECJmcBU86IE3t/fMozVXGK5jf8+c9OcXNsaMo3qZM78M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637373939526.9123372726884; Tue, 16 Jun 2026 12:16:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZC3-000266-1e; Tue, 16 Jun 2026 15:11:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZU-NU for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:38 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ87-0000wv-OR for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:27 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-490cf322ed0so34607795e9.1 for ; Tue, 16 Jun 2026 12:06:58 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636817; x=1782241617; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cpvEVVFmObCOAVZYrBljFN84sP1hXmtFa5bYh03siP4=; b=Oq923evNeMXZRfLLoeKc5ggHmWibOcv0lhMb5P/ztgzdA+1FLizAEdGLY7/FIcD9o6 O/mCily33YNlOqVYPj8yafwjU+t4aoxkSS96m914dnPbzlCBJR4TvfObZQxRGDhJ3Y9A 2gJUZiPmZ2dIZkpQp+wg4JuGjbxUciecqvgICHsNF0UhgjUOmc5FaRIWy7g4rCSqysWn nd2F/j5kK2M7gYZqXxpGFdh87qkpOwFTF+ePj0FpW0mWXV1B34Gb0EFsXQGyBPDh6pYz mGcIS6SHw4WgsfeEig4n099bP+py4hCNV+DFMb1abS21dP9L5pnpl3z96w8M9VTySKJP YAmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636817; x=1782241617; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=cpvEVVFmObCOAVZYrBljFN84sP1hXmtFa5bYh03siP4=; b=auuQ5LZJVxRS0PqKzEhLckAdObmFn/2P9bGjsdxMf6aKrgUwynCYnmTPwpWgmqDMmN 6/3zkMTvw0AP+q/SknBkksczCGG/eqIu27LzPU2ralYjU60R0MQZuTskqExoJJxr4u3r 8aJnD9hPE6U0oYLL6uFjIt3TOWggkeA3BjJ/h/gJLdYekWoZBJBu/pAWVHshUpsxinDQ vSsuXJZr+vlF4QzdlVP510rtn2kkNhChdmEylQh+7tpod0iSdMybCtnHp8IcxThPLC2e A7U5LtDXyQlMtKx0X2jA7tqZ6C056P6s2u8BJBPKSqFqlzUQ4dtzeutucj1dovFuFyiD 0Bxw== X-Gm-Message-State: AOJu0Yz4c0pPuDAT/pvUz/CHlCVSp/vNOW4XgjUlf7KHdB1DMk0pYNjY ifSxAmzNvVeetemacGBTASgFWeLWTgwbL2SlnT8Et+lx/rfUqsTwHhZD24t5gSnCIDxYi7DCLlP K7YCD X-Gm-Gg: Acq92OEBp+WHJQg0yuAckk86OuB2TI1M1hsLuLM8NYvixZhUKCFJYre5gq/s7Yg72aK LxiZuEl+hxKsE7Kr8QaUmd4KlzSsBXjN0NiWk7eK9Og203WOSiWcIjxXDxkqugOOvBD7e64Okjy d5D62unGIg08rgnMk98MLWKJSFfX8eVhLpbwd2sKPu2QNKUFatXwwga1c87dSgD5SG91r3GsGRu MMivQF+T5nt5L/oVdK66nZA2528iEYae6cZ/+TCeTo4MRoew7ka4lh536PJ3RVGsx4eupRQ8gC1 7SwAzX9MsYKCHzsOXMd+zpUY0spNG3Le//0/bY2HdUKe5wvycNCRvZZz4o+KJzY334NCwU+RDLT wG7ANq8emMTP6Bbl3TdOhEsZ7sU0PzdBnT7Eb1Hy3VX9jNQBuV30xz8PXk/fukBoQ82JqxWD4v+ F2PejjdA7fQg3sD5dwUinZyDppe+gfT0c4OFNDeBN3jMok1AhfKXzAoPiL892g4dwzQJO+UlKZ0 kDOoj7d+OOZnw4RjfI6K81V4/yGFlCO X-Received: by 2002:a05:600c:e557:20b0:492:1e36:85dc with SMTP id 5b1f17b1804b1-492333e2b9dmr9219465e9.36.1781636816592; Tue, 16 Jun 2026 12:06:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/61] backends/iommufd: Update iommufd_backend_alloc_viommu to allow user ptr Date: Tue, 16 Jun 2026 20:05:49 +0100 Message-ID: <20260616190639.3462006-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637375906158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen The updated IOMMUFD VIOMMU_ALLOC uAPI allows userspace to provide a data buffer when creating a vIOMMU (e.g. for Tegra241 CMDQV). Extend iommufd_backend_alloc_viommu() to pass a user pointer and size to the kernel. Update the caller accordingly. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-3-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- backends/iommufd.c | 4 ++++ backends/trace-events | 2 +- hw/arm/smmuv3-accel.c | 4 ++-- include/system/iommufd.h | 1 + 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/backends/iommufd.c b/backends/iommufd.c index 8c3a981392..c745dbd2b1 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -463,6 +463,7 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *b= e, uint32_t id, =20 bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, + void *data_ptr, uint32_t data_len, uint32_t *out_viommu_id, Error **errp) { int ret; @@ -471,11 +472,14 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be,= uint32_t dev_id, .type =3D viommu_type, .dev_id =3D dev_id, .hwpt_id =3D hwpt_id, + .data_len =3D data_len, + .data_uptr =3D (uintptr_t)data_ptr, }; =20 ret =3D ioctl(be->fd, IOMMU_VIOMMU_ALLOC, &alloc_viommu); =20 trace_iommufd_backend_alloc_viommu(be->fd, dev_id, viommu_type, hwpt_i= d, + (uintptr_t)data_ptr, data_len, alloc_viommu.out_viommu_id, ret); if (ret) { error_setg_errno(errp, errno, "IOMMU_VIOMMU_ALLOC failed"); diff --git a/backends/trace-events b/backends/trace-events index b9365113e7..3ba0c3503c 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -21,7 +21,7 @@ iommufd_backend_free_id(int iommufd, uint32_t id, int ret= ) " iommufd=3D%d id=3D%d (% iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd= =3D%d hwpt=3D%u iova=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D0x%"PRIx64" p= age_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" -iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" +iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id,= int ret) " iommufd=3D%d type=3D%u dev_id=3D%u hwpt_id=3D%u data_ptr=3D0x%"= PRIx64" data_len=3D0x%x viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" =20 diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 163d3e7279..4cef487679 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -582,8 +582,8 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *hiodi, IOMMUFDViommu *viommu; =20 if (!iommufd_backend_alloc_viommu(hiodi->iommufd, hiodi->devid, - IOMMU_VIOMMU_TYPE_ARM_SMMUV3, - s2_hwpt_id, &viommu_id, errp)) { + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwp= t_id, + NULL, 0, &viommu_id, errp)) { return false; } =20 diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 2925d116ac..1b0266f660 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -89,6 +89,7 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint3= 2_t dev_id, Error **errp); bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, + void *data_ptr, uint32_t data_len, uint32_t *out_hwpt, Error **errp); =20 bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636993; cv=none; d=zohomail.com; s=zohoarc; b=eBocpN8U1WeD8bnf15gA6wowRI4IVqXfD7ikT7kfmzR5ji7GhN5xudC3IMqsUu5HzrevgR1YMeoxLvt4MC2QtAe6INMZQY4SPXI3WyJmgF4aKuSuZCgETvTTABpaSkZkrlgIJyeUm2iw9r8AO4PJm97y6sJKf2Bw99dW5ZZeJhk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636993; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=HvDKsaFNygtdm+lex5RPr5AUTu5fxx81lRj/cLRW5Mo=; b=YQWD2ClXrV2zZszC0vtD+F/zt4w65g5QrE+THuE/tR1vq5ttvP6qZDzAxCQvXk4m4Rl97Z9P1OzOqUQd1IfN4dsnBQYMWDRgwPT2GIy95GBBOWVb9uV+Ou+w1Rn5BcJvPZF74O3Spf8bCjptFz46x1J9WrY0xkYUQiJppjoIyBI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781636993275368.56280037252566; Tue, 16 Jun 2026 12:09:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAJ-0005yS-Ey; Tue, 16 Jun 2026 15:09:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ80-0004V7-1R for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:28 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7u-0000wy-JE for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:13 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4923139e940so6403245e9.3 for ; Tue, 16 Jun 2026 12:06:58 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636818; x=1782241618; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HvDKsaFNygtdm+lex5RPr5AUTu5fxx81lRj/cLRW5Mo=; b=Eq8eEJ5x7yrb6v2uLlGXOkzwNTXb59+Dafq88p6zI7bgADlX/3Z7xXqeJWhLh+/7+X 1oOYLymjRNCF9bXfdskVvRXaiG6egBGakxIT7FInHJ1GWYICvFsU1ZdJFoIjxQEmwa2B 4yIDNFK5ctSRrx9+c5r9eMMS3mREesmHj09KleNyJbaLLOyB94APLJYtOkpmTevrOyFr 5H7GNliNKlW9/ZRPa4lqo7KbdDoymyPE68D+DCAz6BDBUxM0zbXGioZSBcH4FqXKrQV1 AEV4LIjhTSDLF5iXoEDv9BcZu1dfWJXMYa1dEN0KpoCZZZutLLsVcWsdEEGST1Ldk2nH DU4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636818; x=1782241618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=HvDKsaFNygtdm+lex5RPr5AUTu5fxx81lRj/cLRW5Mo=; b=IHyyxPp4XLtOhI1xIettXT9GF7gIZkn/cyxgm9Ma0sLZEUlDeg/QUAEK32FpAhEau2 w00/kyvUIe7R5zKrgUzKOwR2BqSX9zYS11lWyXPM6BP2I0yc/q2MWe/I8r9YvMItSuVv /22qsU8nwgIjUzgj/7kqykQDIXOM8L4fJbsZD4crF9V0qDvS+x9lujhg5rArnFphU9XP PUZnExfvf/tT+/073n91oI0aeghvIS+auJPrjJKTsQ11FyaCDcuVTAk4w6WzRiXPXisv 1NOHiiOtqnnqWNwHVc/2UAN0RUTlZWVGmfBHnXAAeZhR9ygLm26KEFJeKEyfwx/fkgx5 KTlQ== X-Gm-Message-State: AOJu0YyFhYUkVJzoP28uC5GJQ3Mp/3V8odFQgu9HLRJQ/sCBfsU81CCm qTU3BxdAEnHpk8WTIIPtva4zt9pO4/ptQ9vL1w/D4b8lHV/7CqlqIpjFNR8DfseKhkobhI8sHv3 PozlY X-Gm-Gg: Acq92OEwvIp22Cv/dgjg7bzDKOJkxV7DHH9kyLkblf9DC3+dEFrocYFA+0cWXEYAJQf wxMbb4iFR4RXeI1xh8IwMB6od3gP2t87KI1FObjC9yb9vZLljbrjCJLU/uvUhOMB2/ijajlHmXI GqDkBnLKG/VebRqxDcv6UaEJolPkiKsFNeOsUIsX2pJujjCemEkgSV4GG2fej2wewlJhnVtK7mY 2Rj8AbaXAOSkkRw9alTC+RYs75+SiXm4D+t6VdF7Viymmy3+M9v62Xw/Eg9iOEzXWAs3+8qpD6W xjl8jCxC3pq8bsHCvDNPk9v0YlVqBlyxBSxc9h6idBZhuQN7i506akLfPHr/vWMn5Zrv6t5j7N/ lFg7azVb4FfgAl5LTjkpRPfKNUV9wJmyotlaalxoRBLlPTh9/0foDB7FU1At+FlJIKQ7dE3vjrc 2rlUfezF0YNWQ1dho/9Zn/r639Ij8oPVEQAypRrKF3TY6vhwHRhS0DKQySinoINT2RjNRH4xKnU TwDshHJRIdZV5ThicukBrvjVH1pL/Gs1QHFogKBkJY= X-Received: by 2002:a05:600c:6090:b0:492:30f2:963a with SMTP id 5b1f17b1804b1-492340c9cecmr260145e9.0.1781636817577; Tue, 16 Jun 2026 12:06:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/61] backends/iommufd: Introduce iommufd_backend_alloc_hw_queue Date: Tue, 16 Jun 2026 20:05:50 +0100 Message-ID: <20260616190639.3462006-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636995313158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a helper to allocate an iommufd backed HW queue for a vIOMMU. While at it, define a struct IOMMUFDHWqueue for use by vendor implementations. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-4-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- backends/iommufd.c | 31 +++++++++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 11 +++++++++++ 3 files changed, 43 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index c745dbd2b1..8eaaf456e8 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -549,6 +549,37 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, return true; } =20 +bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, + uint32_t queue_type, uint32_t index, + uint64_t addr, uint64_t length, + uint32_t *out_hw_queue_id, Error **err= p) +{ + int ret; + struct iommu_hw_queue_alloc alloc_hw_queue =3D { + .size =3D sizeof(alloc_hw_queue), + .flags =3D 0, + .viommu_id =3D viommu_id, + .type =3D queue_type, + .index =3D index, + .nesting_parent_iova =3D addr, + .length =3D length, + }; + + ret =3D ioctl(be->fd, IOMMU_HW_QUEUE_ALLOC, &alloc_hw_queue); + + trace_iommufd_backend_alloc_hw_queue(be->fd, viommu_id, queue_type, + index, addr, length, + alloc_hw_queue.out_hw_queue_id, r= et); + if (ret) { + error_setg_errno(errp, errno, "IOMMU_HW_QUEUE_ALLOC failed"); + return false; + } + + g_assert(out_hw_queue_id); + *out_hw_queue_id =3D alloc_hw_queue.out_hw_queue_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 3ba0c3503c..c5c1d95aad 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -24,6 +24,7 @@ iommufd_backend_invalidate_cache(int iommufd, uint32_t id= , uint32_t data_type, u iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id,= int ret) " iommufd=3D%d type=3D%u dev_id=3D%u hwpt_id=3D%u data_ptr=3D0x%"= PRIx64" data_len=3D0x%x viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" +iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t q= ueue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id,= int ret) " iommufd=3D%d viommu_id=3D%u queue_type=3D%u index=3D%u addr=3D0= x%"PRIx64" size=3D0x%"PRIx64" queue_id=3D%u (%d)" =20 # igvm-cfg.c igvm_reset_enter(int type) "type=3D%u" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 1b0266f660..c6f2e87a7e 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -65,6 +65,12 @@ typedef struct IOMMUFDVeventq { bool event_start; /* True after first valid event; cleared on overflow= */ } IOMMUFDVeventq; =20 +/* HW queue object for a vIOMMU-specific HW-accelerated queue */ +typedef struct IOMMUFDHWqueue { + IOMMUFDViommu *viommu; + uint32_t hw_queue_id; +} IOMMUFDHWqueue; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 @@ -101,6 +107,11 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, uint32_t *out_veventq_id, uint32_t *out_veventq_fd, Error **errp); =20 +bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, + uint32_t queue_type, uint32_t index, + uint64_t addr, uint64_t length, + uint32_t *out_hw_queue_id, Error **err= p); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636997; cv=none; d=zohomail.com; s=zohoarc; b=eNrudk6w6o2uH5UP67UCHYcOwZL2iI2Dlj9w0+U8XnQnEH0lSB++r7hwBW08fdZ7GmR/OuppoD14MztgxToP4VwMIBrOntRUR1XAdQect71tm+KY6r9WekLyOryXJfjIIIj360orBLLinFyKW4hV7W17+W1upxMoqSmEzhcpArY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636997; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7LbqHsqIIDkdHZnHJlOZ0cciJwmdrPLtN8RdYZYIqwc=; b=QfCPSWFWU4QHn+ChfRG9nP5LU0BaqyaQ2TEkhJba3XOogEHjOfjRkDVD6Ox6AkG+rJaL9p+mahmnHo5Vg7+zPVBVW2p2H1LZsMHtfjw2/IiZ2Kh57KMsWEsw8X9NlyozV6Csc/QUSDy/lX3sD2hixAB4O6k2XT041UQAb+l6rew= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781636997913757.1778616203414; Tue, 16 Jun 2026 12:09:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZ9w-0005sV-1f; Tue, 16 Jun 2026 15:09:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZX-Nc for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ87-0000x2-Q6 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:27 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4903d730b1fso61626695e9.2 for ; Tue, 16 Jun 2026 12:06:59 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636818; x=1782241618; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7LbqHsqIIDkdHZnHJlOZ0cciJwmdrPLtN8RdYZYIqwc=; b=IW3NSkrVx6ozoEdTxh/35Et/iKLnD3r+zoianzJo5CpzsmJRC4f5+DzpM+la/B35Ml hPD5x4yidH8XvyzwaFrDVC7YR4xv6gIMPDIq6MMCjKjFjYBo4m3QCOChonZ8aD6XCngf 65zqVfgqvSuQLgsazizGKcd8MnOw7RLugQCOE0T2km+TzA9JtbUsZRNbBNdyWt8/49SG 9xThvz+03WXN7XjgdnsgwI+19zxSamOTTdF9MGLhqaxUbrXjd+IJOiE0rKkIXN6OV1ye 9SklgUunEwV2A3z2y0MZ+/ZRuzdPpLY1fI6LgGkSnWKGoJgrRGgm3XUYr3wJtL0PkveR derg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636818; x=1782241618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=7LbqHsqIIDkdHZnHJlOZ0cciJwmdrPLtN8RdYZYIqwc=; b=Xazq5bfSMudIDZ5GCeJrVTo4PcLlrpRjJF67ysA9b/KFDz+TmUYONFEQ0JJaq74fG3 Pr120GNb/KVjymOO24Nx7nDQKIGZw/m48XFnoUJLYUekG6McTmfNB0i9PlSN48rhrTIR ifL9+g1wZxS8L1tsPUyCqwefFywOG7RYptF9OLSiSMiFo4qxMmKnQj8dQz/k529fctUJ 5Pubh/eYe+V5LQfg5H3F1NjE1RoygloK4F4OWBAximdTspzp/v1ycmkzH0uaNucGZhEP pYOVB6JaKUfZGL1/6cKB5Qb4wnQQLPSnBSkmiAKTDaevBvyesvHXnOmHRnWHYqoClSkv iReQ== X-Gm-Message-State: AOJu0YzE8QMvMk4P6dgxrHWPVs5alULSJIbn/k8ftHGKfSCILJO5hK+l c30CIx3oCwaOPCHsuuhrt8fVGltgXAihFyuFY+1HrmQ6IWid2VrpjQ+zl/MWoUyjsFXdKsZrpGj tHXlH X-Gm-Gg: Acq92OFbnecL0nOcfFiMYkpxtTHDqwggYZZ/xKyx56Aa/s3VRKksr5b4SkI5A9uWRwD UfeTTYuWRYAJe5kzIzUOyENs5+ScMEsKUSCBg/1yMCjDvrlV01iAGVssB/2+kyuAZlhO9BZniRn xfRuE1Qm5cEwQINGl8k6Vwpw84sEDCrnDoXT7j8gA6nMXoZFGL0lI25MEFM5gd/6CfJGu8DBaSC e9Bp64wGxGJBTK+jP390ligPvkbZwpvy3dP2efqvNw8jmLlKLMjXVP4ONwNcJkmIZOKtosjy21C KLMIqrJEorPHr87BGho1jYAuDQtggMoidaB8epWojLxVVpEzr4DbDfeNS9FOPITmeTRWVM6+Jzd hCAKHQ3uYWJCewW0Z6EoQoNfJxCBEH6xaC8Ytk4aRK8xjbuAkJ1597M2e/6m+6x85bFvAFSsnjY 9z3flyYnmEf1VoYfiaZ+nSPcfpjuBt7WzF4N4Vg/DngTM9FB0Q4WbDHyKZuaftFquwclyloyTp8 0cbyxN18E8tTeeTjPyPJLafnAULtFVK X-Received: by 2002:a05:600c:a305:b0:490:b629:286c with SMTP id 5b1f17b1804b1-492333aa59bmr10568175e9.12.1781636818497; Tue, 16 Jun 2026 12:06:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/61] backends/iommufd: Introduce iommufd_backend_viommu_mmap Date: Tue, 16 Jun 2026 20:05:51 +0100 Message-ID: <20260616190639.3462006-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636999448158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a backend helper to mmap hardware MMIO regions exposed via iommufd for a vIOMMU instance. This allows user space to access HW-accelerated MMIO pages provided by the vIOMMU. The caller is responsible for unmapping the returned region. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-5-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- backends/iommufd.c | 22 ++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 4 ++++ 3 files changed, 27 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 8eaaf456e8..440c1b82bc 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -580,6 +580,28 @@ bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be= , uint32_t viommu_id, return true; } =20 +/* + * Helper to mmap HW MMIO regions exposed via iommufd for a vIOMMU instanc= e. + * The caller is responsible for unmapping the mapped region. + */ +bool iommufd_backend_viommu_mmap(IOMMUFDBackend *be, uint32_t viommu_id, + uint64_t size, off_t offset, void **out_p= tr, + Error **errp) +{ + g_assert(viommu_id); + g_assert(out_ptr); + + *out_ptr =3D mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, be->= fd, + offset); + trace_iommufd_backend_viommu_mmap(be->fd, viommu_id, size, offset); + if (*out_ptr =3D=3D MAP_FAILED) { + error_setg_errno(errp, errno, "IOMMUFD vIOMMU mmap failed"); + return false; + } + + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index c5c1d95aad..b63420b73e 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -25,6 +25,7 @@ iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id= , uint32_t type, uint32 iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t q= ueue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id,= int ret) " iommufd=3D%d viommu_id=3D%u queue_type=3D%u index=3D%u addr=3D0= x%"PRIx64" size=3D0x%"PRIx64" queue_id=3D%u (%d)" +iommufd_backend_viommu_mmap(int iommufd, uint32_t viommu_id, uint64_t size= , uint64_t offset) " iommufd=3D%d viommu_id=3D%u size=3D0x%"PRIx64" offset= =3D0x%"PRIx64 =20 # igvm-cfg.c igvm_reset_enter(int type) "type=3D%u" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index c6f2e87a7e..bb8d5081d7 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -112,6 +112,10 @@ bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be= , uint32_t viommu_id, uint64_t addr, uint64_t length, uint32_t *out_hw_queue_id, Error **err= p); =20 +bool iommufd_backend_viommu_mmap(IOMMUFDBackend *be, uint32_t viommu_id, + uint64_t size, off_t offset, void **out_p= tr, + Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637388; cv=none; d=zohomail.com; s=zohoarc; b=TuM8+AwuZcPjc3aqz+MkXCwQirayp7jJ3GSUVue0UXmjwjWTQKS7QB16kQMIuesKLjpAjzcowE5HOQFbeV+tKrPTDgtvhu8n8oDSHPJ5REPqTmyz1w1vWd5+aUMx5X75Oek9SJ46tZM7Sd5Wb3DUtxgoKeXbsGo1PjkA8SQbNDw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637388; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Ic2bXL26/Yx4lR7wZIf6TWd/FeRNPNT75FGM1aR3uho=; b=I7LOd/9ThRXvGDskj6L0mRah0WQuQbTKJRvl1K4yqeDo5Kc1Z2UuqnA7byic5wOTBikWH/dSDFGt/laOf/UE6YyA/eAr3FBi/QymqA/KhNvW1Q6vFlgoAd4TzZblC8yxBd/l+C/snQGzLCOAeCLcwuhXI0IPug8AsPKGt4ziVwY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637388864511.7228497017567; Tue, 16 Jun 2026 12:16:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZDg-0003dT-T7; Tue, 16 Jun 2026 15:13:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8Z-0004ml-9W for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:53 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8U-0000xE-0M for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:50 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-460662fcb4eso3412767f8f.0 for ; Tue, 16 Jun 2026 12:07:00 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636820; x=1782241620; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ic2bXL26/Yx4lR7wZIf6TWd/FeRNPNT75FGM1aR3uho=; b=pE9Eo/YyY81zZimcpHK1d1fjQrPFghOaGtG3F10xqnZmiD2DcwhJzSZT4Jq6BFxNuk T8aIj11jUOejx4f7zeXjKT2E1W8NxMzU7IYxkY4yFfP1Xb40C53Nj4P4QvM+JYVfPHcL FPS1Vu3wx+UCYgQERek/fYgHMj9sQw+8SkYXtzconlNqX67QNjUcjde77pAbiEMClXs1 urjd9aPlz/5486eDXFu2osNRlK76wQ4kTe0QAjDS8mQTjxuBi1OaxgoVXZrL+IXqInpY xt7gctJM1lhVoFZ98YAoRoj/JNFEsYXGoiK7ofgNhpaz0f3RRd/+2heVxJpWj25E3tfn 37LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636820; x=1782241620; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Ic2bXL26/Yx4lR7wZIf6TWd/FeRNPNT75FGM1aR3uho=; b=Pd3+CrU4gRWxpPv1+bq0MCnQ6QYlC2lDqoztGhanq+DIMOle784ucwgkiVoaOXOqL5 nNBtDHrnmzCduwnfHtNpkGIunbf5nJ45Y6rTXyDwUQ7V7zFhydywG73XAZhEFCwBxvIO elj0ic7zI9JOFaKJbRpY7GAG/P2blwIXwcrlgXGaBU3oR/du/fK/lXoEdMFJe6ambiDc JmfN9RPjJNTefh27o03JtJ6QliJu0WlbgjWGH1xPKMgdeEAg7f6J9UY3/u5fdDKlhALM F0g0JPLrX63/CdXR2OkaWqynXGZKbClx4/p8lJTQ2MlCtU7gVoSzcnK4EdeXuXiwG3eM Yo1g== X-Gm-Message-State: AOJu0YysRMY3sD/kmwngs6jbtGhWj6wcJVi5VUGIbrkCgxPusqEjYmdA 00nZbc5sfLU/dHUQE2GJ6ugDSGgBsUvGe0xKDNQ97tCL3kL0RJLETPHFbKDyWT0TUgwQ7yZLmFn hNEVL X-Gm-Gg: Acq92OH6HpIQb9CAVL95Z+rKVI8kFAPUbQVERdXXJhHkv1/Ris6smSEWA8jwGzx5qJQ pFdiwkIMbrSuPHgLS2kIMbgb6FmwoUoPwAzVDNMB9j2LCi+sH+o+rcgnGNql4v5Zb5rcPfLVGn7 1qSp+1Zx3upV7lVEsFrfw0A8S/BC6TjaUWIXr/Z0P1IuCyn8W5wTIYZ6Thju0HyVRMHEtc+hlqY zX+9yT2dZ5c9pOM2oUO6Dhj/b1JWzFkGr9ahFy2+CPVgLbqBQSqCtnNsyWHQ5+7dOCpR4d9B8aY NGC8HZr50JOwJxcbmMxtXoYmwdIRMc2nZzMVeDvDDftEbPqr1/cdJ8JnQzvHTA1oE/+Rm6W1Hdo lyuAyAmhhou3bu+YKxmn/Udx+W/YeDudlQuBn+VsNrdUBe0tcch6hcN5erA+g0aWBAv6lq5sbqn bCcUwMUVJdvSZvnykKFI3uASYfCOccM0MAQCZlLChtcDtB0Fy2SqAsne+Te99D7Y0qfKfB8UVV2 gJa1sIi4tWX92BubMf3otTsRYo6qH8A X-Received: by 2002:a5d:45cc:0:b0:45e:945b:276 with SMTP id ffacd0b85a97d-46237d5b277mr950005f8f.20.1781636819589; Tue, 16 Jun 2026 12:06:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/61] system/iommufd: Remove unused viommu pointer from IOMMUFDVeventq Date: Tue, 16 Jun 2026 20:05:52 +0100 Message-ID: <20260616190639.3462006-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637389907158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum The viommu field is assigned but never used. Callers freeing the veventq already have access to the IOMMUFDViommu object through other references, so this field is redundant. Removing it also simplifies upcoming changes where veventq is allocated based on the viommu id before the IOMMUFDViommu object is created (e.g. vendor CMDQV-based veventq allocation). No functional change. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-6-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 1 - include/system/iommufd.h | 1 - 2 files changed, 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 4cef487679..70b2581c17 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -553,7 +553,6 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error *= *errp) veventq =3D g_new0(IOMMUFDVeventq, 1); veventq->veventq_id =3D veventq_id; veventq->veventq_fd =3D veventq_fd; - veventq->viommu =3D accel->viommu; accel->veventq =3D veventq; =20 /* Set up event handler for veventq fd */ diff --git a/include/system/iommufd.h b/include/system/iommufd.h index bb8d5081d7..da68ba0037 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -58,7 +58,6 @@ typedef struct IOMMUFDVdev { =20 /* Virtual event queue interface for a vIOMMU */ typedef struct IOMMUFDVeventq { - IOMMUFDViommu *viommu; uint32_t veventq_id; uint32_t veventq_fd; uint32_t last_event_seq; /* Sequence number of last processed event */ --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637077; cv=none; d=zohomail.com; s=zohoarc; b=iFSUSC9wLGkgmyydFSZPS7Wyrp13yaKAbgydMEtrOaIJCq1ylMxXQhUDKCWGoyY9c7URW5GuxHu1mRdQ9scZvk4D62hRWYoEsnHMzxYHZ1k/T/hkdCO9AZ4hGvp2ZlLQL/Arc3CUCmjPuXYvu5t1mJ3tXffjxaqdHtpbYMKggeQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637077; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=PYQ8HdK5SkU6BX/BtmWU/KoQEGIEXyhmRcW7vzpl7zc=; b=UkS9jAwoTGwgcmMyn6FwH8RSnOWsnP//gzIcIIkOThWQFYRJlMeSQcN9OALt0DXo5z3B0FE5Ej85eOh8hu82jQF+elbe4EVZSuaRg7uQcLJs2n7ev8G0snNMXo4JFrNqVNdPeVKmWtwPlEvKuKp8WITcpMSoNR5wcCZCF0jXK0g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637077016140.7741014195907; Tue, 16 Jun 2026 12:11:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAV-00075B-RD; Tue, 16 Jun 2026 15:09:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZQ-Li for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ87-0000xf-O3 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:28 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-490b12270b3so30451355e9.1 for ; Tue, 16 Jun 2026 12:07:01 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.06.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:06:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636821; x=1782241621; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PYQ8HdK5SkU6BX/BtmWU/KoQEGIEXyhmRcW7vzpl7zc=; b=h0wh+SBIXmiWKI/xi3nihv/iI16LPz8wcA0ssPDIYEqu5oQYQ1BJXe/bGwkDvdTq/m 4LxbWGG/P05Ftqs0uY9HaMsmp91BUjy4R1ActAk0EsDgLL46Xyqnh/3RLRcdXrESPfbK BH0f/zOGxTpCzGF9kPVIcAScQg/5LLM2lBsL7Ssp8ACPIbCehyEV/6vuoEynfo+onEG7 y+iKc4FEAvLU7Z/GqLNy/hLNpfNoB1cqpOjdk3/VwYXkBz3OSZgZVEjtfU33FzTHWkdS lKp91D4AghTm/H8fJ76ukJZdkyaVm7z1khGZ9aUUc3ZMk8o1fxPnN/SQZrB6OJ/rUybF tuvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636821; x=1782241621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=PYQ8HdK5SkU6BX/BtmWU/KoQEGIEXyhmRcW7vzpl7zc=; b=eeOgmsojduTASLpuxftS7lJAzRaryWvqzk+ahvR5xLSyHQ9MBzbjgNTx7VBnme3vJl k4cDYDcmay3jZTWG45Tbo4EwltQPJ8vi8BQrEcd1j5vCzjTHGKecQUdf93Lx7G18ol3U XwRzkV/9gr43kUuNcjgF66BPzR0ImHMmU8SuqIONAIqbt7hNfTkpYcIdJMfhv1yWi5PO TFdsIxlRnLJzGk+SMf7ZgdUsT1OZaCDX5pYYIfziyXbirXKbtXhR4g7P/c2lTekgKNi/ /hSAHGIpzlLtNL054VpaUdf5fE33WmnFaBpX0dURRCgLEvfgT2YsyNLA5huCAybSkK8H axxQ== X-Gm-Message-State: AOJu0Yw09IziPmAeIZHLkW0wloJFCHvdoqCgRzuGU0e8eETFcGA6CjEF HjxuMfAqaKgiqObFaqcDSKMUJSoVQgdHLfhZwKa7HmuA7E37OY/jSCXwwp3YRGAjJLd616lPA8x FNSxv X-Gm-Gg: Acq92OGZUSUDVTKu87cK7qCnUMfTONxWwR0JLwp2IJpRbXWKDqnOz8NdG9xLPD14lHm e+69Z5tqIJjWOa+JSl0fZGZJ9ROGT9Xv+0rMkrSlLaKJrqu2kdBgZSs/Uhvb9+VkbmLJ1IOV6bK HJ6AyXp4bXAIdYEY1CYEUGuaFYlY9DW6vixf+cu6QAivgSfvwGmoOkAp/ynhrKVdTsS9gM6FaJA fN07F3uMtEj/LvyPMXDnSUWydy5m9Vws7VhLoKz47lh79IZuHEmYERIlYeZ2slxrUuLktsG+DAT 1pfvDWx01VNpOONn1wgnb4/4XWglDmaLAZDoKhnoFNBGErs5fFFzh1yWyk0P9vREQ7RVrgEwNW2 H0xUrqHpd6AgNblSSKaIh6452ftbUV2SQN3NwKd46Dvw3kRMshcSqTTjljIUqoQdvGg5Gk7KYNI mYlSA/qKWqc9LjbiIh2HnNCNkAJsFXjXXwhpeqNZNnWJ0PDIA4y5+OTc4Cd4jpLlVChAbGqxPiD BHsaTJhdj7tYD+u3EPqqFrnM35uvCv1 X-Received: by 2002:a05:600c:3e8e:b0:490:ea8a:32da with SMTP id 5b1f17b1804b1-492333d6b3bmr11595385e9.26.1781636820743; Tue, 16 Jun 2026 12:07:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/61] hw/arm/smmuv3-accel: Introduce CMDQV ops interface Date: Tue, 16 Jun 2026 20:05:53 +0100 Message-ID: <20260616190639.3462006-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637077960158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Command Queue Virtualization (CMDQV) is a hardware extension available on certain platforms that allows the SMMUv3 command queue to be virtualized and passed through to a VM, improving performance. For example, NVIDIA Tegra241 implements CMDQV to support virtualization of multiple command queues (VCMDQs). The term CMDQV is used here generically to refer to any platform that provides hardware support to virtualize the SMMUv3 command queue. CMDQV support is a specialization of the IOMMUFD-backed accelerated SMMUv3 path. Introduce an ops interface to factor out CMDQV-specific probe, initialization, and vIOMMU allocation logic from the base implementation. The ops pointer and associated state are stored in the accelerated SMMUv3 state. This provides an extensible design to support future vendor-specific CMDQV implementations. No functional change. Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-7-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 87fecb5c68..b45f25ad03 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -10,11 +10,44 @@ #define HW_ARM_SMMUV3_ACCEL_H =20 #include "hw/arm/smmu-common.h" +#include "hw/arm/smmuv3.h" #include "system/iommufd.h" #ifdef CONFIG_LINUX #include #endif =20 +/* + * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to + * support multiple VCMDQs with virtualization capabilities. + * CMDQV specific behavior is factored behind this ops interface. + */ +typedef struct SMMUv3AccelCmdqvOps { + /** + * @probe: Mandatory. Vendor-specific device probing. + */ + bool (*probe)(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, Error **er= rp); + /** + * @init: Optional callback. Initialize CMDQV hardware. + */ + bool (*init)(SMMUv3State *s, Error **errp); + /** + * @alloc_viommu: Mandatory. Allocate CMDQV viommu resources. + */ + bool (*alloc_viommu)(SMMUv3State *s, + HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, + Error **errp); + /** + * @free_viommu: Optional callback. Free CMDQV viommu resources. + * If NULL, the viommu_id is freed directly via iommufd_backend_free_i= d(). + */ + void (*free_viommu)(SMMUv3State *s); + /** + * @reset: Optional callback. Reset CMDQV state. + */ + void (*reset)(SMMUv3State *s); +} SMMUv3AccelCmdqvOps; + /* * Represents an accelerated SMMU instance backed by an iommufd vIOMMU obj= ect. * Holds bypass and abort proxy HWPT IDs used for device attachment. @@ -27,6 +60,7 @@ typedef struct SMMUv3AccelState { QLIST_HEAD(, SMMUv3AccelDevice) device_list; bool auto_mode; bool auto_finalised; + const SMMUv3AccelCmdqvOps *cmdqv_ops; } SMMUv3AccelState; =20 typedef struct SMMUS1Hwpt { --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637004; cv=none; d=zohomail.com; s=zohoarc; b=jT2ZC/7A+9ExlDRKzJO5NYv2c3blvNr2ALOv0X3wkeourt1EuK9VLTV4xzXmCkTGVoRJN8AH+a37NG9G9j716zk6MzWfCUrBCbYEbhPUEm5Ftj1QwP0YVveyCi9eerXXqppEx5QKKNLQVJlTYNqcyKR7PTDmvBrCqQjdoGPcUiI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637004; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=8o5615QM/YZyebhfGAhf37s8TorbhzZ4P/CIGr3ijUc=; b=mPtokx8yd2/wZNfrVEUCKN7uEbRx3cJbqTNMiIH4Ln8s3IMibu46excQrRm+rWm6BpIlvGfvqnWhgCIt/CSD8CpmAsPgJKlw8LstJCpZWpp9XZ0gsSIrZqxrAAJuiiTJb4wIOJ5/LZb4P7VkIsYRMiOpadjvNkWb+6f509PFEC0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637004546894.8785436078385; Tue, 16 Jun 2026 12:10:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAH-0005y8-Fp; Tue, 16 Jun 2026 15:09:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ83-0004VV-6n for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:28 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7u-0000xv-JH for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:14 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-45eeea039ebso2830740f8f.1 for ; Tue, 16 Jun 2026 12:07:03 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636822; x=1782241622; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8o5615QM/YZyebhfGAhf37s8TorbhzZ4P/CIGr3ijUc=; b=nttykw5zU+pFLNd16gqCrA7WnlyTDvjCPEalZdmJpD7O+pcX0vbnsBukPFdMIOrZw2 Qm60jvyBYPFHoVPQNVks+zHOhx0CtfQWoyYc1oWTwCGd/BwHH31T3xeKq9WM1WRARngJ 8W218agvKJrs1GLhFLenWL2JRORiW/BZ2jOoCKtEjl9Z22Drwsw4SjJhZDNlR8da9Otg QI37BvxEehV9Wo5x9VyfGld5Vi1gtca6Ah7Tx3tS+xhnJVVcHXIXZspWJXhG26dZx8Xb oTwCr8Q3tuTqNDOr2hexbCPuHE4oQD2FyF4Znx3ppM3zCZOk7dWuRD34y6ulAZwJgUB8 q2Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636822; x=1782241622; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=8o5615QM/YZyebhfGAhf37s8TorbhzZ4P/CIGr3ijUc=; b=bKUWeSlus40847v1SVnlOQ54XiS65i3aoHZEiy7vU4q8UOwySBFai3FOHhoAEdho4O zSuVUk2P4FwVm1y6M9/k9v1Koi+06Rv/gQwyl/rR8UWMFpVt20Wfr39BHoJ+GXmylFvx kv0eyzJhYHsFm+awnRMemF/JFbTTgwZGva9LHQeduuzPIQyqE2UN4rodJSsY8c4bAn/+ zItCMgpWE8aYJBBNZeil9cES7JDIKn8J6U+R+13yWuFxDYJOOnuX/03vCgJ9WRDkYyzT /SutrTfAmMlspXBfEoKZ6fZU3KBAt4LyAFw4CZbOIaJxK5fjd6VTEJoDrgi605s+zjz+ B4eQ== X-Gm-Message-State: AOJu0YxIR473Inrq7usBnzDasTp1i/wyavG633YNM2qL//FrVRkVUIUU tbsW7cf/mH6vlPQZRQzJ5mP2r4WCB8FnqCwxtCBvIEFx96Sz6Ng9B4vsA7BAXJV2Vce2RQxoOyN vjBgx X-Gm-Gg: Acq92OHOPNz5La7PrsXrmRS7MQFIsQood2zz3U166lkIyfpyXlQG+bwJe9WTRfC8MrM rKdGgwgmF9YawqIs2mbeaPnumPW1WBtz+QqPwVwmWWsHIXhjSO2GWXF4W7icCOb3FqcowhaGZkD yR2QVM/GY8/3TlI+M7NSQxE2oKHqIO2QNReHzRT9Rxh6AdRTdlQPsCcT4RVM/BcnfQcx5ZV2VvA oc3TYvnXY0Dr5DSZbUi7C5esHwZmDgQwJFG1MJ3XpqricaxtrsAX7Z/Hkwv/tFd9RjQY5qyeqZG ARciDeDRwIneDU9+mXnGymt5qsd7TvHU3RGsHDZn4zNL2DPpnbGbdSoh6KWsdfVWqFCZEF8XxIB 6Q51HR7QIw3hqwFxLPE4SGDMY+dDu7UYoQxiYsIcmTlOSiQeIehrfi8rJij3ziIml1UyNLHpIC2 aGYKUnp+Zgl4IcTqvbbBMWgBh2UynFjteZelVp6KBE6hDvbWfVyrKTZImBd3oFMNQQ2jCfAYUiy WkP5MmJWjkVm1DsQDP1C9XHdGh2KcCT X-Received: by 2002:a05:6000:4023:b0:43c:fc5c:a9fe with SMTP id ffacd0b85a97d-46238ac9fc7mr1294621f8f.20.1781636821950; Tue, 16 Jun 2026 12:07:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/61] hw/arm/tegra241-cmdqv: Add Tegra241 CMDQV ops backend stub Date: Tue, 16 Jun 2026 20:05:54 +0100 Message-ID: <20260616190639.3462006-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637005458158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Introduce a Tegra241 CMDQV backend that plugs into the SMMUv3 accelerated CMDQV ops interface. This patch wires up the Tegra241 CMDQV backend and provides a stub implementation for CMDQV probe, initialization, vIOMMU allocation and reset handling. Functional CMDQV support is added in follow-up patches. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-8-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 5 ++++ hw/arm/meson.build | 2 ++ hw/arm/tegra241-cmdqv-stubs.c | 16 ++++++++++ hw/arm/tegra241-cmdqv.c | 56 +++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 15 ++++++++++ 5 files changed, 94 insertions(+) create mode 100644 hw/arm/tegra241-cmdqv-stubs.c create mode 100644 hw/arm/tegra241-cmdqv.c create mode 100644 hw/arm/tegra241-cmdqv.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index fb798ccbee..500bfdfe2a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -643,6 +643,10 @@ config FSL_IMX8MM_EVK depends on TCG select FSL_IMX8MM =20 +config TEGRA241_CMDQV + bool + depends on ARM_SMMUV3_ACCEL + config ARM_SMMUV3_ACCEL bool depends on ARM_SMMUV3 @@ -650,6 +654,7 @@ config ARM_SMMUV3_ACCEL config ARM_SMMUV3 bool select ARM_SMMUV3_ACCEL if IOMMUFD + imply TEGRA241_CMDQV =20 config FSL_IMX6UL bool diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 8f66a80e10..4233a800be 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -89,6 +89,8 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MM_EVK', if_true:= files('imx8mm-evk.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-= accel.c')) stub_ss.add(files('smmuv3-accel-stubs.c')) +arm_common_ss.add(when: 'CONFIG_TEGRA241_CMDQV', if_true: files('tegra241-= cmdqv.c')) +stub_ss.add(files('tegra241-cmdqv-stubs.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_common_ss.add(when: 'CONFIG_XEN', if_true: files( diff --git a/hw/arm/tegra241-cmdqv-stubs.c b/hw/arm/tegra241-cmdqv-stubs.c new file mode 100644 index 0000000000..4669f5c5f5 --- /dev/null +++ b/hw/arm/tegra241-cmdqv-stubs.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * + * Stubs for Tegra241 CMDQ-Virtualization extension for SMMUv3 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "smmuv3-accel.h" +#include "hw/arm/tegra241-cmdqv.h" + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void) +{ + return NULL; +} diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c new file mode 100644 index 0000000000..ad5a0d4611 --- /dev/null +++ b/hw/arm/tegra241-cmdqv.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" + +static void tegra241_cmdqv_free_viommu(SMMUv3State *s) +{ +} + +static bool +tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static void tegra241_cmdqv_reset(SMMUv3State *s) +{ +} + +static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, + Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D { + .probe =3D tegra241_cmdqv_probe, + .init =3D tegra241_cmdqv_init, + .alloc_viommu =3D tegra241_cmdqv_alloc_viommu, + .free_viommu =3D tegra241_cmdqv_free_viommu, + .reset =3D tegra241_cmdqv_reset, +}; + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void) +{ + return &tegra241_cmdqv_ops; +} diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h new file mode 100644 index 0000000000..74a6954017 --- /dev/null +++ b/hw/arm/tegra241-cmdqv.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_TEGRA241_CMDQV_H +#define HW_ARM_TEGRA241_CMDQV_H + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); + +#endif /* HW_ARM_TEGRA241_CMDQV_H */ --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637488; cv=none; d=zohomail.com; s=zohoarc; b=iVEcyqpYplh5mkd00AbRUxbI0iQVEj6pY1smlnTO68k897LVNDdLw5B4QupvS3A6PWr2Xy1GzXkN84FCyzo3HxuZxEaPJpgEtGDdWgmwiS0H1pvmADynjNJGJ7ntEq0tbnjjq+BuFO9cS64CoN6ypm8g4xGMq0Cz61Xf8T9SNLo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637488; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=G5wNENUz9ZKPTgkYLTujeqWRD9EO2XYzjjtZrcgsT3o=; b=GKp45Hpc9RiQLJhyaPLnrT4nVjvmuHDe14WeGuXKFqEgioSm/vtNEEAfOmDyhydGxmQZPTFZ9UGg5pxGy83/IGjwOEWY5bt1RkN9qJ2wy6Z1zHxVXkOaORgl8YM9kZAR6d6LApQb1hMd3JR6+VYEhH3Ii6GALCziiFxuloTsd04= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637488979160.01680601435942; Tue, 16 Jun 2026 12:18:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZBy-0001m5-KX; Tue, 16 Jun 2026 15:11:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZP-LT for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ87-0000yI-Nq for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:27 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4921eed3fa2so32653555e9.0 for ; Tue, 16 Jun 2026 12:07:05 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636823; x=1782241623; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=G5wNENUz9ZKPTgkYLTujeqWRD9EO2XYzjjtZrcgsT3o=; b=bcbgvn0SjfagWDTyBuo/cesNT2rmP/KyiQvwmCfJh8XMEKJ8nvgP7HAdvFFBkZCjAZ NwKCYdvSi+bL1d8WbZ5FRRfLoIDtyKtWBsNxfe5R6uCbw2kjp/tVZkiyA5KeVwjvkOWi 5Z2fh+iEOLDfl8vW5tWUrNrdX6Uh3hJ+DTyva6ebRAGHZoosY4o6wXe+/dK97DzdyoKh YSs0BxJIFHd0gA/If1ZwOyInYbr/WVY5E53IyH8cqqb3djGC6+GxYzb9ww8/1V1fYkMe adVTr2gfPR5qTBPNT9PQitOm5HccJYbWYkufN+k+5pA12CF89nQCth/8eiZqI8lpDfat N8dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636823; x=1782241623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=G5wNENUz9ZKPTgkYLTujeqWRD9EO2XYzjjtZrcgsT3o=; b=T47DPjWQW8dz5wsODA0qMWjMQKpbkEyYsW3fgQBBIcW7j1Yuj7cxT0TSd5bXKBRO5G ep+zmklJ+I9XSUFCb7VpOZph36e8MM+u7My13lXjIvsWm4fcrTg6i7Cc3Ojqqku7LyzC Pfn83gkWvjkRxs+Pi6/vR4OknT8JaC4c2HDeYirmwDbxH+esxKFuuDJQ1fPHa9A3KOTD SniOCLkMYjdRmONgteBI6t6wB2QeHQWaDqyMS9bO88MnKjwnLLUMLgsDFAWytWHlWR4+ b6r/xrAIscCjxkDJanmT43c4vZ81q4LZ+AXB7omJTehFa6mWxHDko6cij3Br0vrZ5W9V tEeQ== X-Gm-Message-State: AOJu0Yy8nlrM64w49Pa24BPduWA7yFwJUqVIA8pU/vPQBdQ+WVw1gGl9 MVgroGIVHDy/a+zA8py+pQfgDOWCjfrNbnFCqS8TqRDunEi5XJ6cliYQcqKb8zGDMnLw6QPu2qq 6OTys X-Gm-Gg: Acq92OHKw74/rgKC6EHdOrfL3N3QJ7IPICQPhVDUhFoVsFcr0Ob7tKG68PZLEqqLG05 VRs+dApEhX+Y8OJ0Mnw2BB/VjK2PjXRUnfylwZ5lsFkcNpWv00CyRyV92ui/JXLLfrdT49bOD2i wwwfIuXcFPoqjKe8PA1wK4yF602Z+E6bQMoy0vV7duPSPeg2xcHEdZtegtinmcpXCalaquoQGLM FqcWVUDgG1yqHNPjNA3Oju/vKvau9Njw4Qic2w34j5egEo3ipMiHJD7bB3L/oxLGepCORNUAzgz ODJIPWs+82x9n6vzcgy8CpesCjPArz43WnXa6y3IvhsbqNbV9jNlig0rLIbzSSj2gDygR9kW6Ig M0QPahK/6l+dwHVqrpCZxQO3XlSRg6rUVJZJiJuYiGDaVj4TVP9eYr7gWJ8Jb1SS4i6DkyxOXr7 yZwWb6q4Ey0sxTAO9S7rjCT1sWIjpuFX5dlhTgVGfWMGBIhZLmpSw2tK6YawRlJgz/dV6AIzFL1 q4MSXjk6fvDkmi/nQeaX1zKeSpw1vF7 X-Received: by 2002:a05:600c:19cb:b0:490:d354:d151 with SMTP id 5b1f17b1804b1-492333c8e6dmr12107195e9.18.1781636823122; Tue, 16 Jun 2026 12:07:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/61] hw/arm/smmuv3-accel: Wire CMDQV ops into accel lifecycle Date: Tue, 16 Jun 2026 20:05:55 +0100 Message-ID: <20260616190639.3462006-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637490655158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Add support for selecting and initializing a CMDQV backend based on the cmdqv OnOffAuto property. If set to OFF, CMDQV is not used and the default IOMMUFD-backed allocation path is taken. If set to AUTO, QEMU attempts to probe a CMDQV backend during device setup. If probing succeeds, the selected ops are stored in the accelerated SMMUv3 state and used. If probing fails, QEMU silently falls back to the default path. If set to ON, QEMU requires CMDQV support. Probing is performed during setup and failure results in an error. When a CMDQV backend is active, its callbacks are used for vIOMMU allocation, free, and reset handling. Otherwise, the base implementation is used. The current implementation wires up the Tegra241 CMDQV backend through the generic ops interface. Functional CMDQV behaviour is added in subsequent patches. No functional change. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-9-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 94 ++++++++++++++++++++++++++++++++++++++--- include/hw/arm/smmuv3.h | 2 + 2 files changed, 89 insertions(+), 7 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 70b2581c17..3ceca56a67 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -19,6 +19,7 @@ #include "smmuv3-internal.h" #include "smmuv3-accel.h" #include "system/system.h" +#include "tegra241-cmdqv.h" =20 /* * The root region aliases the global system memory, and shared_as_sysmem @@ -570,6 +571,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *hiodi, Error **errp) { SMMUv3AccelState *accel =3D s->s_accel; + const SMMUv3AccelCmdqvOps *cmdqv_ops =3D accel->cmdqv_ops; struct iommu_hwpt_arm_smmuv3 bypass_data =3D { .ste =3D { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL }, }; @@ -580,10 +582,17 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *hiodi, uint32_t viommu_id, hwpt_id; IOMMUFDViommu *viommu; =20 - if (!iommufd_backend_alloc_viommu(hiodi->iommufd, hiodi->devid, - IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwp= t_id, - NULL, 0, &viommu_id, errp)) { - return false; + if (cmdqv_ops) { + if (!cmdqv_ops->alloc_viommu(s, hiodi, &viommu_id, errp)) { + return false; + } + } else { + if (!iommufd_backend_alloc_viommu(hiodi->iommufd, hiodi->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, NULL, 0, &viommu_id, + errp)) { + return false; + } } =20 viommu =3D g_new0(IOMMUFDViommu, 1); @@ -629,12 +638,70 @@ free_bypass_hwpt: free_abort_hwpt: iommufd_backend_free_id(hiodi->iommufd, accel->abort_hwpt_id); free_viommu: - iommufd_backend_free_id(hiodi->iommufd, viommu->viommu_id); + if (cmdqv_ops && cmdqv_ops->free_viommu) { + cmdqv_ops->free_viommu(s); + } else { + iommufd_backend_free_id(hiodi->iommufd, viommu->viommu_id); + } g_free(viommu); accel->viommu =3D NULL; return false; } =20 +static const SMMUv3AccelCmdqvOps * +smmuv3_accel_probe_cmdqv(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + const SMMUv3AccelCmdqvOps *ops =3D tegra241_cmdqv_get_ops(); + + if (!ops) { + error_setg(errp, "No CMDQV ops found"); + return NULL; + } + g_assert(ops->probe); + g_assert(ops->alloc_viommu); + + if (!ops->probe(s, idev, errp)) { + return NULL; + } + return ops; +} + +static bool +smmuv3_accel_select_cmdqv(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + const SMMUv3AccelCmdqvOps *ops =3D NULL; + + if (s->s_accel->cmdqv_ops) { + return true; + } + + switch (s->cmdqv) { + case ON_OFF_AUTO_OFF: + s->s_accel->cmdqv_ops =3D NULL; + return true; + case ON_OFF_AUTO_AUTO: + ops =3D smmuv3_accel_probe_cmdqv(s, idev, NULL); + break; + case ON_OFF_AUTO_ON: + ops =3D smmuv3_accel_probe_cmdqv(s, idev, errp); + if (!ops) { + error_append_hint(errp, "CMDQV requested but not supported"); + return false; + } + break; + default: + g_assert_not_reached(); + } + + if (ops && ops->init && !ops->init(s, errp)) { + return false; + } + s->s_accel->cmdqv_ops =3D ops; + return true; +} + static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int d= evfn, HostIOMMUDevice *hiod, Error **e= rrp) { @@ -669,6 +736,10 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus,= void *opaque, int devfn, goto done; } =20 + if (!smmuv3_accel_select_cmdqv(s, hiodi, errp)) { + return false; + } + if (!smmuv3_accel_alloc_viommu(s, hiodi, errp)) { error_append_hint(errp, "Unable to alloc vIOMMU: hiodi devid 0x%x:= ", hiodi->devid); @@ -946,8 +1017,17 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Er= ror **errp) =20 void smmuv3_accel_reset(SMMUv3State *s) { - /* Attach a HWPT based on GBPA reset value */ - smmuv3_accel_attach_gbpa_hwpt(s, NULL); + SMMUv3AccelState *accel =3D s->s_accel; + + if (!accel) { + return; + } + /* Attach a HWPT based on GBPA reset value */ + smmuv3_accel_attach_gbpa_hwpt(s, NULL); + + if (accel->cmdqv_ops && accel->cmdqv_ops->reset) { + accel->cmdqv_ops->reset(s); + } } =20 static void smmuv3_accel_as_init(SMMUv3State *s) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 85be3d7467..34d0f65eaa 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -75,6 +75,8 @@ struct SMMUv3State { OnOffAuto ats; OasMode oas; SsidSizeMode ssidsize; + /* SMMU CMDQV extension */ + OnOffAuto cmdqv; =20 Notifier machine_done; }; --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637002; cv=none; d=zohomail.com; s=zohoarc; b=gQXzTY6SUqUrI1pCCXiKqkurScGOCmnDmkrb1zz4OuJ0HZJQR1LIn+1nLA8iA7AvMXDBYYr+2dvdrHgKwM5dShHkfgXIQXfFJZqMGFHwMRYaLgTvflyeiaWjEMG4UgcN416uU93h6yUklCsTpE80n/RMoLUJ7GX32eMJ54qBkJE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637002; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=pxe9Q4e15SUoztJVYM/EMV71jX5dkOv1tCM4I7rpjrE=; b=hhl88iCgXwSp82Wl6Hj4lKDAxKmdAyNmfduvciMGqXg//tRbJW47klIyYwBpGpMQo1RTc88skVPmICb6C0FLStInIQGqjLV99i/a4RM52IeoULRFj7QBgFkAKxeY6XLqQs2zNzWAPQcGfSH9a3xyEoM2eEHdY6MsjPpTQk5gQiY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637002526327.59012137704815; Tue, 16 Jun 2026 12:10:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAS-0006he-To; Tue, 16 Jun 2026 15:09:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ7z-0004V5-EU for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:28 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7t-0000yD-LD for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:12 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-490b613a17bso45362235e9.3 for ; Tue, 16 Jun 2026 12:07:05 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636824; x=1782241624; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=pxe9Q4e15SUoztJVYM/EMV71jX5dkOv1tCM4I7rpjrE=; b=hh3LJUPXnmI+2My+tO3jm0b2PVsjsXo1+RFKBnhzKPJGXbUCnvkhf8SV+l9FPGhNHR tQBzJmu+DoqD3k9b5vMdL0KRytMdJSQRTLhT7lzJTZ80KNFQeB7QfaqWKmM5rKTYw8kU 67mg6NNLK1Xw8MYlLFDz7JhyyD/Zu0dspL5r7BsLWJ80913vCJkBao9tuoX3qTzZZj0+ ucdkScMrLuhNpBMQGKCgIoowTLFqXsAQ0Nn+B7BTjaclL3iQJD+AylMOrocCWfVSJ9tg a3Eaw+sF54NCDcu6isCxYaBhD0Ngi/MHm5tHWZX/7QeBQ+oV2R+DBXwr3z+QzmyEsKdz CnQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636824; x=1782241624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=pxe9Q4e15SUoztJVYM/EMV71jX5dkOv1tCM4I7rpjrE=; b=sHTRnY4YpIj39YLPJvb1CoqYCg5zgf8EksqTretbAW/x9ErtYIkdU9MgI8gfAgh08m W3D0AWatlHqGCADCHdo79GJJcGC582oIRZnZLPcgdcTwKHHvoNESH7J+DILyoyjQSlsJ Na7+C9FZJ9m66prDfDoM9jK0PbGBd0iI0VV2HKMnzVo3kZ7NHhvp0/jBKhIj1psuyXB2 psxvTXFMEyelza1TWV4zyA4g4hujuWcYBG42i0d+OwbMKiUnJeA+w2LitHg0zFUcKUsa s5SXGKevPK46jlAeAcrAccw3v4zzlsM/w0RBDKasp5+IGDbP1yQdvUuoS5W8Hc6g23lG Ncsw== X-Gm-Message-State: AOJu0YzKx0FxSyccwPBqKZHeGpa7g0/ksgYFqWRmW8LRqhwQfiCwpJw7 BbM4e2d1IlaQ1K3xlU2d+c9P0tWcXmvEQqlwhg10FU7QJ3tevj7NNVKEuBPMuvT7CrEfFnmsmUC RHScB X-Gm-Gg: Acq92OEiqWr5TYtmMVVfpCl6fbh8RisTauByGc+x8PQOFlcFj9XqxOH5wzur5g3ecOl 7trpm4sH+aa0EG1x6JajjZIyE2S9t8e0K6ReOWVmcmwcwFzkXbt1K9WrXntxerEQAo3rhmbpHOu r7Rd83t1ehTPyFgoM6aEvs7nBowGGw+zJHqYNiJAPMD5acVe+cSUVHoiKU31YQhDy0B8OVeB7GV t6SIaMnQXaCyDUT75W/gfiNaPVO+jOGfYfH+A178T8UEaYazKWyUpNidYj5l/mz7QDhX2YOCrnZ fIsxDu4iXvX2kYow1N8ilIg3c9y9frrFJtgfKduREV6mSOVIy49rmNi1OwUEMUSkORokfMTK9Xw vXiqjoSUnZY6BxbcJArJA2bo+Sv/hir5LzTRYWSmTtATFfRp1l5uIl7kCpsDFUVitzm9sUvOtVT STWWvxZ/nRyhkvpBBqQGx2xV9bX6C8TDe54cz1WCzY8o+lqTe8lin5fnKf+kKnNdi0yZ5QCFQ1K /dgeRhIiDRiavHwnUBNICZxaygX98hT X-Received: by 2002:a05:600c:c094:b0:490:b642:ce2c with SMTP id 5b1f17b1804b1-492333af1b4mr11247535e9.14.1781636824066; Tue, 16 Jun 2026 12:07:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/61] hw/arm/virt: Use stored SMMUv3 device list for IORT build Date: Tue, 16 Jun 2026 20:05:56 +0100 Message-ID: <20260616190639.3462006-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637003488158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Introduce a GPtrArray in VirtMachineState to track all SMMUv3 devices created on the virt machine, and use it when building the IORT table instead of relying on object_child_foreach_recursive() walks of the object tree. This avoids recursive object traversal and provides a foundation for subsequent patches that need direct access to SMMUv3 instances for CMDQV-related handling. No functional change. No bios-tables qtest failures observed. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-10-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 70 ++++++++++++++++++---------------------- hw/arm/virt.c | 3 ++ include/hw/arm/virt.h | 1 + 3 files changed, 35 insertions(+), 39 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3f285ff6c7..b00f3477ca 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -392,49 +392,41 @@ static int smmuv3_dev_idmap_compare(gconstpointer a, = gconstpointer b) return map_a->input_base - map_b->input_base; } =20 -static int iort_smmuv3_devices(Object *obj, void *opaque) -{ - VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); - AcpiIortSMMUv3Dev sdev =3D {0}; - GArray *sdev_blob =3D opaque; - AcpiIortIdMapping idmap; - PlatformBusDevice *pbus; - int min_bus, max_bus; - SysBusDevice *sbdev; - PCIBus *bus; - - if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) { - return 0; - } - - bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); - sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); - sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); - pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); - sbdev =3D SYS_BUS_DEVICE(obj); - sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); - sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; - sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, 0); - sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; - sdev.irq +=3D ARM_SPI_BASE; - - pci_bus_range(bus, &min_bus, &max_bus); - sdev.rc_smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); - idmap.input_base =3D min_bus << 8, - idmap.id_count =3D (max_bus - min_bus + 1) << 8, - g_array_append_val(sdev.rc_smmu_idmaps, idmap); - g_array_append_val(sdev_blob, sdev); - return 0; -} - /* * Populate the struct AcpiIortSMMUv3Dev for all SMMUv3 devices and * return the total number of idmaps. */ -static int populate_smmuv3_dev(GArray *sdev_blob) +static int populate_smmuv3_dev(VirtMachineState *vms, GArray *sdev_blob) { - object_child_foreach_recursive(object_get_root(), - iort_smmuv3_devices, sdev_blob); + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + Object *obj =3D OBJECT(g_ptr_array_index(vms->smmuv3_devices, i)); + AcpiIortSMMUv3Dev sdev =3D {0}; + AcpiIortIdMapping idmap; + PlatformBusDevice *pbus; + int min_bus, max_bus; + SysBusDevice *sbdev; + PCIBus *bus; + + bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", + &error_abort)); + sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort= ); + sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + sdev.irq +=3D ARM_SPI_BASE; + + pci_bus_range(bus, &min_bus, &max_bus); + sdev.rc_smmu_idmaps =3D g_array_new(false, true, + sizeof(AcpiIortIdMapping)); + idmap.input_base =3D min_bus << 8; + idmap.id_count =3D (max_bus - min_bus + 1) << 8; + g_array_append_val(sdev.rc_smmu_idmaps, idmap); + g_array_append_val(sdev_blob, sdev); + } /* Sort the smmuv3 devices(if any) by smmu idmap input_base */ g_array_sort(sdev_blob, smmuv3_dev_idmap_compare); /* @@ -568,7 +560,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) if (vms->legacy_smmuv3_present) { rc_smmu_idmaps_len =3D populate_smmuv3_legacy_dev(smmuv3_devs); } else { - rc_smmu_idmaps_len =3D populate_smmuv3_dev(smmuv3_devs); + rc_smmu_idmaps_len =3D populate_smmuv3_dev(vms, smmuv3_devs); } =20 num_smmus =3D smmuv3_devs->len; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b090233893..ac0606fe87 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3865,6 +3865,7 @@ static void virt_machine_device_plug_cb(HotplugHandle= r *hotplug_dev, } =20 create_smmuv3_dev_dtb(vms, dev, bus, errp); + g_ptr_array_add(vms->smmuv3_devices, dev); } } =20 @@ -4319,6 +4320,8 @@ static void virt_instance_init(Object *obj) vms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); vms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); cxl_machine_init(obj, &vms->cxl_devices_state); + + vms->smmuv3_devices =3D g_ptr_array_new_with_free_func(NULL); } =20 static void virt_instance_finalize(Object *obj) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 3ba33b4bd2..171d44c644 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -207,6 +207,7 @@ struct VirtMachineState { MemoryRegion *sysmem; MemoryRegion *secure_sysmem; bool pci_preserve_config; + GPtrArray *smmuv3_devices; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636994; cv=none; d=zohomail.com; s=zohoarc; b=SA3ztUu/TkdYMjxu/8t1BNzYDiebxSj5mLfppe/AgV1WTor2Mq+uMvGIrsnyLz957gYl9DHbvYaXmrnYh3muLWK2iy+MbwlQY8LnXdH9hV8abnzC+1j7G/iKcgjMIqit828J93ISyb3VQZSPBY8+DgV7JaRsz13jK89QhqBOqwU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636994; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=U36QTOj3+WS8UfS+I/MVEAMSNS5LcHohAWyCMHmrQIo=; b=fk3orma04djNAcnq+W1jBobOKO7pStGyhuUeTkm4mSnn7QVVV674ywjfLgCjO5EK7SfxiNX/7guMFGWCHroqIXi0b3hslLWfHEiw5g1IQnsiA3aD1gzBtoVwlvyOF1XZHomoRTj57SWJ+2TkkBQV+I/M61LYbfyOUdNwMl1kHAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781636994509538.184309228706; Tue, 16 Jun 2026 12:09:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAR-0006Ud-B1; Tue, 16 Jun 2026 15:09:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8B-0004Ys-Fm for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ85-0000yS-UT for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:24 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-45ee5cdbd28so111972f8f.1 for ; Tue, 16 Jun 2026 12:07:06 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636825; x=1782241625; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=U36QTOj3+WS8UfS+I/MVEAMSNS5LcHohAWyCMHmrQIo=; b=uKGPzVvlagJ6Q5lPLIRUIqFGsBC0odeRQMMVWbWM8OTWnSlwS9U/exBOqQaRdAuTCr 96KoIO5vYN11HdA3t4O5bHnPmoIO8JUsqSBWVRmSwZECVCjGQ4kunTPBsNE2yKvZhwqB DbQjtcKmiviDqNQJ+uWJIHb+KRLGNru1Byo8lqlUCbC/d56FNimMVlnCnSs6U8OhReCp hacHCGi9iWK2Gd6y+SBv+oHSn9XTdhObS5pL+sU8OUjJYtVbaxgbJdUIeObTb0jwv6Xk jfx7aBmQFJUmgbmmX6EGsg0uXy2UKu+PTLtoCjsXBn6Z0aoeyWKxx4utMg77hBvBx4eN LnBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636825; x=1782241625; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=U36QTOj3+WS8UfS+I/MVEAMSNS5LcHohAWyCMHmrQIo=; b=RFMVAn1Tqy4WewGN+4TSCeszXB0w4/d9y0LbWBcnS2/zQixz520yI2ctCuhgXeFVmD XSQY48cCmzSBunmdEmwppr4buQbpQj5XQ8i8caSbSJ2HuaBZNjGQ6FcKQcN9VFp/01w/ 6LYmkdnP/0neMl5sNrkTyAMzy+eym4eK/1NQAMoYcdXbpUdnYtM/g+NUvi1ftPLvRjo6 FoMqQTa4QD6g3OnkVOCMfBmzuutwnL1dwoT/zcQ+UVvEdpxwzLqZYdyKGh2GwIIybPhj kLlp6BoCiet3/qCZ903VaLPbBK3xAl6kPVBqq4M4xxWg4wx8XSl1HsZjookFmeyMFFyx z/ug== X-Gm-Message-State: AOJu0Yx7d6qAtz5elRHmghVtL4EwPSiLXA58iGIh2mfQ3Vc+XxINyQ1M a8IJOLu7nd8SLfALKzpKBbw9ibXYcW5V1GtpmigDB8W+54WyZ/IkUxYaimRBC/CjvwxJiKOrJ1s LRCKx X-Gm-Gg: AfdE7ckyqfhyBw94qaHK/3SENPgOrihSvZZLnLh7gtUcLPSWEsae1OW7SEOu252TmBj QQyEOtk0FPg4T0cXnDj9gdlbVf+ab0zxv23sH+bjMPbzziztvicO3DBNsikNQfdVvIfdEdb84OO 2O4NXu7qDVGfr8tItZFpoM+Cz2h8Ci37WYpspZ7fpSAKGvp0AbrOkVVXn2408GSsqFWFxc20fza JwNHnnpyG0cTqIRP08K9EsXtJeUNzt19/az8maa6m2wITXKt94OgamnljqOV39Fm5wgrNfWjIM8 N8E+cTgTc3HsQUTuqkh8gZB6yl3X7q169brWgxCXav/9dp/Xn94krU34hykKrsUGBgrf8oqGzqy I1gUWTMcTuZUdDxXyfgwCbZCS4Uxb9g0552kZOa3uOll9pBhGm6jLlmf43Y5S/i4DvB8m+diNAz 4Hdgn900ayRcDDIeLZLEYckVJ0hIhMzL6z0k8rhZsvjzp6LRMxyKPvUgC1cZ0P/efmueiwgRXvc gzwUR5YNV/juhH8VQhoO34Qb0CZx3Kq X-Received: by 2002:a5d:5d05:0:b0:45e:e936:5e30 with SMTP id ffacd0b85a97d-462692f8590mr43249f8f.6.1781636825069; Tue, 16 Jun 2026 12:07:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/61] hw/arm/tegra241-cmdqv: Probe host Tegra241 CMDQV support Date: Tue, 16 Jun 2026 20:05:57 +0100 Message-ID: <20260616190639.3462006-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636995376158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Use IOMMU_GET_HW_INFO to query host support for Tegra241 CMDQV. Validate the returned data type, version, and minimum number of vCMDQs and SIDs per Tegra241 CMDQ Virtual Interface(VI). Fail the probe if the host does not meet these requirements. The QEMU model supports one Virtual Interface(VI) per VM with 2 vCMDQs and 16 SIDs per VI, so the probe ensures the host implementation is compatible with these limits. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-11-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 32 ++++++++++++++++++++++++++++++-- hw/arm/tegra241-cmdqv.h | 4 ++++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index ad5a0d4611..3a19a1af56 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -38,8 +38,36 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error **= errp) static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + uint32_t data_type =3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV; + struct iommu_hw_info_tegra241_cmdqv cmdqv_info; + uint64_t caps; + + if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, + &cmdqv_info, sizeof(cmdqv_info), = &caps, + NULL, errp)) { + return false; + } + if (data_type !=3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV) { + error_setg(errp, "Host CMDQV: unexpected data type %u (expected %u= )", + data_type, IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV); + return false; + } + if (cmdqv_info.version !=3D CMDQV_VER) { + error_setg(errp, "Host CMDQV: unsupported version %u (expected %u)= ", + cmdqv_info.version, CMDQV_VER); + return false; + } + if (cmdqv_info.log2vcmdqs < CMDQV_NUM_CMDQ_LOG2) { + error_setg(errp, "Host CMDQV: insufficient vCMDQs log2=3D%u (need = >=3D %u)", + cmdqv_info.log2vcmdqs, CMDQV_NUM_CMDQ_LOG2); + return false; + } + if (cmdqv_info.log2vsids < CMDQV_NUM_SID_PER_VI_LOG2) { + error_setg(errp, "Host CMDQV: insufficient SIDs log2=3D%u (need >= =3D %u)", + cmdqv_info.log2vsids, CMDQV_NUM_SID_PER_VI_LOG2); + return false; + } + return true; } =20 static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D { diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 74a6954017..38c8b27b4d 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -10,6 +10,10 @@ #ifndef HW_ARM_TEGRA241_CMDQV_H #define HW_ARM_TEGRA241_CMDQV_H =20 +#define CMDQV_VER 1 +#define CMDQV_NUM_CMDQ_LOG2 1 +#define CMDQV_NUM_SID_PER_VI_LOG2 4 + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637299; cv=none; d=zohomail.com; s=zohoarc; b=JJP8QysrllnPAbujT9pdspwWenhpJGJkSVWp5nPLgB7lUBPweitp/aQin8fLsqh//EEWSWUd1rQBC/U0aPtdfO/OV2fW7IMyvOFjHU8UgufFH2pba45yDbRu8sF55Z79tpSAEu8Qryii226JcONakRsV8VdqvHHXzIBYkmhNE7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637299; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=FXr9ylmZYOE7+E0t1jj2Ga4P2T/mevVY7GxsxYiycI4=; b=U3DKB4/6jJi8q4qug/3FeUoTd1q+Wd2Xdrzj3Dal0GXBiqgBWo10VMK+kS9t/2Q/K0GLlfGnsiBtWTszfZ4wKy1QZIIrk1Dw8iJudEyN8Tv2WlsR3AZ5p1Bb0G7OBDcDp09sXgluAlF8+m0j51PuFYMitdWRR2WOBEErRPc+ec0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17816372997411004.8409146033954; Tue, 16 Jun 2026 12:14:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAc-0007nP-Jt; Tue, 16 Jun 2026 15:09:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8W-0004jL-NS for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:51 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8S-0000yl-Ua for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:48 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-491b390f9e9so41835015e9.0 for ; Tue, 16 Jun 2026 12:07:07 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636826; x=1782241626; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FXr9ylmZYOE7+E0t1jj2Ga4P2T/mevVY7GxsxYiycI4=; b=LnntycusGZnhGD+yTaGRFpeqT9OX3dvinnLfqbleh7998F7l7ilKYEKTNP+eesRrin N0DGI6qzBwNiRPZGrQvGHiGobMxrCCC5OSJTwLUN5janXfzSChRj1yDGk9Xdcf4t/6sk u7la2HEfM/N1J41Khr2jJRoDPh84qjnzkgObrkPm3dJ/xU0tdhLorFOdsZQwS2VzOtKY FcGueP8eAFLjl9Fl9cn/G/qq3Sv2kT/sIc8v4mq3yd6o2O0x5AVpPWa1BsWmEfJ4Fluz DA4zMfAuAJ7kRQRIczxuaYshrWEgQeml4SznN+C7kZwg7rX6blKhsLIYTcwS5DyAvzsI Uplw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636826; x=1782241626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=FXr9ylmZYOE7+E0t1jj2Ga4P2T/mevVY7GxsxYiycI4=; b=Suj2MyAtwf+i5dARNn0lN2KgNpHUmFOVdn5zD1Tnib4F5wFwzF/EsiiHnqclQT1SRQ XxpJrnvCMDFoPzn9vHiW6hQdfy0jgw8i2gfWa7WAyVtqjWAsCjyPQOIGsT5ckSHeRM5M aeqzwazT7iJc+wLt36iwF3l8HGfx/Qpw19Sx8343GSICz3fhx/e3IV85Oe1B2zx2MYfH 8llDEYBvs0TGOWyFl7i1reMczVy8rwuTauhsjp9F1nzsSfDWPJXSlWFLczWuVZyUPwUu pFSuSdYSuVxB65UD/sUvqHL0GhNjC6CNWe1Q5xTjMEOJo/BHT2HiTG0OpfvwonULxFBH lOdg== X-Gm-Message-State: AOJu0Yx1QYL1GIzVXaoUvalUrqdxselTbVte+Gd+ToxIG6fzEOniXhRM x4az0iAX0xzytlZMzkpnIhPd5F1ljONcVSs/e8Y46/OVcYRWDndwr328y6qnTk2ry2RYpkhnZet viVrw X-Gm-Gg: Acq92OESghlezfQR+iTx+kksUsLQgoE/yuJPEYQCDZPD0+5vpYV5Wx1uB8sZOmZ4Gbo 1f9gOgTmoWnVONarStb02b/dc/LYI6xjIRg0hNM3jdgluipKni5/lvZomBROsfoTIIb40WumDon eFI7Mk8BViQTyYEBxb3DY7Zn98MjsYdRak9vRud+1o/30YZcIwXyRx281gLRyaEwcrL2KU4MTQf YW/ehckA9R4weF9eZsVKc40/kx3D9bweQT/EiLoYjMDDGHJ/hbN7/eVdJIf0rWvRTlvUDsTGD3X JPcXZq7toXLJWiOeYCVw3PyZO/e2aolgBIJL/UPJgDmYEiCRy5O4D244K6tIi0wsy9xD4bUuE26 lCm2RQnF0uFEhBEp7Bo7rvgRdCnH2yT6sCd05LACe3AE9/zSGpRXom0gftEiHRHGyvYArQPEKli bbClm9iCxtR33r6brUt3RikGklBbcx6coPihWd/oMae2PgnyS27gPwCd6qCfDL+6tatmAMH9k33 CIvbj9XJZ9PdbA8GITNW9a6HqnH8RTi X-Received: by 2002:a05:600c:3317:b0:492:1e36:552c with SMTP id 5b1f17b1804b1-492333e3b6amr8268905e9.37.1781636826209; Tue, 16 Jun 2026 12:07:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/61] hw/arm/tegra241-cmdqv: Implement CMDQV init Date: Tue, 16 Jun 2026 20:05:58 +0100 Message-ID: <20260616190639.3462006-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637301354158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Tegra241 CMDQV extends SMMUv3 with support for virtual command queues (VCMDQs) exposed via a CMDQV MMIO region. The CMDQV MMIO space is split into 64KB pages: 0x00000 (CMDQ-V Config page) 0x10000 (CMDQ-V CMDQ Page0) 0x20000 (CMDQ-V CMDQ Page1) 0x30000 (Virtual Interface Page0) 0x40000 (Virtual Interface Page1) This patch wires up the Tegra241 CMDQV init callback and allocates vendor-specific CMDQV state. The state pointer is stored in SMMUv3AccelState for use by subsequent CMDQV operations. The CMDQV MMIO region and a dedicated IRQ line are registered with the SMMUv3 device. The MMIO read/write handlers are currently stubs and will be implemented in later patches. The CMDQV interrupt is edge-triggered and indicates VCMDQ or VINTF error conditions. This patch only registers the IRQ line. Interrupt generation and propagation to the guest will be added in a subsequent patch. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260609112552.378999-12-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.h | 1 + hw/arm/tegra241-cmdqv.c | 40 ++++++++++++++++++++++++++++++++++++++-- hw/arm/tegra241-cmdqv.h | 20 ++++++++++++++++++++ 3 files changed, 59 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index b45f25ad03..e0bbec8581 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -61,6 +61,7 @@ typedef struct SMMUv3AccelState { bool auto_mode; bool auto_finalised; const SMMUv3AccelCmdqvOps *cmdqv_ops; + void *cmdqv; /* vendor specific CMDQV state */ } SMMUv3AccelState; =20 typedef struct SMMUS1Hwpt { diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 3a19a1af56..2875affc8d 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -13,6 +13,17 @@ #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 +static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset, + unsigned size) +{ + return 0; +} + +static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ +} + static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { } @@ -29,10 +40,35 @@ static void tegra241_cmdqv_reset(SMMUv3State *s) { } =20 +static const MemoryRegionOps mmio_cmdqv_ops =3D { + .read =3D tegra241_cmdqv_read_mmio, + .write =3D tegra241_cmdqv_write_mmio, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + }, +}; + static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(OBJECT(s)); + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv; + + cmdqv =3D g_new0(Tegra241CMDQV, 1); + cmdqv->cmdqv_data =3D g_new0(struct iommu_viommu_tegra241_cmdqv, 1); + memory_region_init_io(&cmdqv->mmio_cmdqv, OBJECT(s), &mmio_cmdqv_ops, = cmdqv, + "tegra241-cmdqv", TEGRA241_CMDQV_IO_LEN); + sysbus_init_mmio(sbd, &cmdqv->mmio_cmdqv); + sysbus_init_irq(sbd, &cmdqv->irq); + cmdqv->s_accel =3D accel; + accel->cmdqv =3D cmdqv; + return true; } =20 static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 38c8b27b4d..a5f65a8991 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -14,6 +14,26 @@ #define CMDQV_NUM_CMDQ_LOG2 1 #define CMDQV_NUM_SID_PER_VI_LOG2 4 =20 +/* + * Tegra241 CMDQV MMIO layout (64KB pages) + * + * 0x00000 (CMDQ-V Config page) + * 0x10000 (CMDQ-V CMDQ Page0) + * 0x20000 (CMDQ-V CMDQ Page1) + * 0x30000 (Virtual Interface Page0) + * 0x40000 (Virtual Interface Page1) + */ +#define TEGRA241_CMDQV_IO_LEN 0x50000 + +struct iommu_viommu_tegra241_cmdqv; + +typedef struct Tegra241CMDQV { + struct iommu_viommu_tegra241_cmdqv *cmdqv_data; + SMMUv3AccelState *s_accel; + MemoryRegion mmio_cmdqv; + qemu_irq irq; +} Tegra241CMDQV; + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637216; cv=none; d=zohomail.com; s=zohoarc; b=bPfUmRFaPsHyHk32Fad5ZBjW7+pL48i4aExBQJvsAHxielY2mc60rxtG/wx72PxLHONwlHRuSdG/88E1uHPzJi0scfhpK4VDuv8blXNAqCWG+bL0ZuIPfWcdau9E+jLAxKTK/swiZqDKArUbP3wo25xOxijan7i3wJy0xFgN2Ak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637216; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=dBnz57USTF4klnOD0F5S3F9sAeLT+jv8yGXcqqpiY2U=; b=dMpf2ZV/piO8L87UskOkOdpvG7NU2U/w6JQfxLN6TAMPFdasuLgkztE1YTtpGfibW4dNI3oyiM3iQh21q6xVNsHRsquaC4yaCRA9p7SsV1DE2E7wJALyG86h+QsaZET4smtikPfqAD1nii1vXE8DLKwqnUlByySKcBre/cHBq24= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637216722461.24826950081695; Tue, 16 Jun 2026 12:13:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAa-0007Wr-3l; Tue, 16 Jun 2026 15:09:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZM-Bs for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ87-0000yz-P8 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:26 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-490a76757e5so35888215e9.2 for ; Tue, 16 Jun 2026 12:07:08 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636827; x=1782241627; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dBnz57USTF4klnOD0F5S3F9sAeLT+jv8yGXcqqpiY2U=; b=UNWcdNGXWi559vcK1kduzSlD4DcmH4EwHnh3es6W0e6RzDNUcGLpbpiaebBO354D5R xBhz4/U0KgB/gaCXxBp7A2BYNiQFs2O4PZFrjDkd5QwktvCJbADy2LwAicM1fLO3ASjT T1gqgT8wvAvdiLOXHILZirgS9F86+RHBLv2C5puJPEnSoHIV13iDZgRPx3pfvgPYY+E/ X3StTYyfDmyfqwqzZ6yeosBzufw4rcnO+g9XWiwSqNVesamjIkavrdmAekiBHgpHw7e3 Jc3ZLHe1Jf4Dh7BnTFVbYnxoRaoElOMj07y6HKxuSpT7X9U+n2fErkT23/HD8o3bslV5 Lc/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636827; x=1782241627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dBnz57USTF4klnOD0F5S3F9sAeLT+jv8yGXcqqpiY2U=; b=BFOM+Qiil6ZWPPpMoehKVZ4EF1qQznV6BKVqkJDKDUHozxhm7pYrQREm+8GLirTL3E zVgWLbB9C1vK82DVlAjKP+IaXy+gum7Se0G4eBMzr+YyLSYCRX5KU0vnGEw4qc0jBcJi QlWscZIk0SC1DGPTezOVOUrQu4PBM6mP3oWmfQNrPSZEP5SYXjddfzh86lSaxw+ipKdb D/nGem3Qq1Winrkhyq1FICnk+RiCXdXtkPsgyjpH8HR0fmmS0+fh6W72GSe+Sr/Ywhzm QCuUAPhHYSxJYx7Tp1eugIKitZjRY28AVncz2jfqCcmQKQncptB277ITrIUffbx+/og1 Ttsg== X-Gm-Message-State: AOJu0YwrMYyrbnMyr1NrUTOytOAAyHKqXltV4FtFpTfiKekBbUpAqZkg rdjtpNgtXxqD0h1HOtc0Ftt5/FDRhfG/ChUA49tDm9+GfmWrC6Wx4ROcu9UW56eG6up6dgH/Y22 v3aZN X-Gm-Gg: Acq92OEJ8rVP9u5R4nJJvpCGmPUkLGJ/kxHtyeGmEoOM2GgaJvl+BbBBxib903SwOyt UJEAVB3CTSdBVkQF24TbNA2Se2HUKuKHFIO5LvVPdOH7YmI+APOTIO5iHnhGIz6CAmaGFk1tRpY rOn/Ijfg7GpRMD4rR5a0B3CfX7etznO6fD4hQDFmur661yWrUOW2fCH8vXzaLaJMXOwbRX6NKsD A1Kqb6Xzkjy0RWVt2HkvtrqKit9ZE9n7jSuEd/L7qETYC/u0jjWEW6k49bEfU5KLNOBLuieh+JU xSIzeb8CLo8kkCefVMWlmSSpBkmxNmS5iY9J6MpmqY40KF23IAA7MKeR4PZw3BspJNMgmkyFyw0 nUEOObn0UDcHWcUzCGtTQ7HUGtjocPpF5VxbYS0jHPjs87onNxneydXp6SKORcHCVeUKfLnXwWm FBKIAN8hgkHCerE5RlI72uqQlr0p/IbauTrDNPsna+uaxFJeckiLIewRfTf1GlcuZiyEi2wNihx tnuDjrjHw9pnzzocTrfbKhrg3OhLJZ/OFlEw/VaxU8= X-Received: by 2002:a05:600c:19ca:b0:492:1edf:9fbc with SMTP id 5b1f17b1804b1-492333ba2e3mr14447175e9.1.1781636827379; Tue, 16 Jun 2026 12:07:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/61] hw/arm/virt: Link SMMUv3 CMDQV resources to platform bus Date: Tue, 16 Jun 2026 20:05:59 +0100 Message-ID: <20260616190639.3462006-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637218838158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum SMMUv3 devices with acceleration may enable CMDQV extensions after device realize. In that case, additional MMIO regions and IRQ lines may be registered but not yet mapped to the platform bus. Ensure SMMUv3 device resources are linked to the platform bus during machine_done(). This is safe to do unconditionally since the platform bus helpers skip resources that are already mapped. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-13-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ac0606fe87..2add7401a1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2361,6 +2361,25 @@ static void virt_build_smbios(VirtMachineState *vms) } } =20 +/* + * SMMUv3 devices with acceleration may enable CMDQV extensions + * after device realize. In that case, additional MMIO regions and + * IRQ lines may be registered but not yet mapped to the platform bus. + * + * Ensure all resources are linked to the platform bus before final + * machine setup. + */ + +static void virt_smmuv3_dev_link_cmdqv(VirtMachineState *vms) +{ + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + DeviceState *dev =3D g_ptr_array_index(vms->smmuv3_devices, i); + + platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev= ), + SYS_BUS_DEVICE(dev)); + } +} + static void virt_machine_done(Notifier *notifier, void *data) { @@ -2377,6 +2396,9 @@ void virt_machine_done(Notifier *notifier, void *data) if (vms->cxl_devices_state.is_enabled) { cxl_fmws_link_targets(&error_fatal); } + + virt_smmuv3_dev_link_cmdqv(vms); + /* * If the user provided a dtb, we assume the dynamic sysbus nodes * already are integrated there. This corresponds to a use case where --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637278; cv=none; d=zohomail.com; s=zohoarc; b=Pz3Z47MOkG6aAcF/dxJWZ8CPhfuir/+M/il66oONBZUUaVNzZYeNPaxczG1/wOxKYBPxkOVAzr9yZLa+0h67wUev1ZJdab3NGk46qeiwiAJHNsA/Yv1kCd9z43OuX/NFS5POdFY5EXsopJSinlEPTzJKkpKr90KgxlNCZVGdBNw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637278; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ZfK0y90nu3Ld/r6Gi/P+At5Q9uLEC4IcCIzFZn+LBq8=; b=Bchiy3aGeh5WQ82k/2vzBMKPdRvKFNK6kqoNNZGjNGKW6V2goFy3xaaSQqX6BDK7LammBbwcjpbYj9c3qLwWTc9uCVfkZPB6j7qPvAj0UHSR6N4kgIUCv22dmCYrGraw+kwwK2uoYo+J5I7IiQfu/8FcneZS1Gp7ycMfY7DvwyY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637278291388.9177083183738; Tue, 16 Jun 2026 12:14:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZC7-00028W-9p; Tue, 16 Jun 2026 15:11:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZR-MD for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ87-0000zB-Rr for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:28 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-49230a567a9so6467395e9.0 for ; Tue, 16 Jun 2026 12:07:09 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636828; x=1782241628; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZfK0y90nu3Ld/r6Gi/P+At5Q9uLEC4IcCIzFZn+LBq8=; b=fvyVbCbdYcPWSMI1mFeafchv+WiTpBcOTVDQzhI+Cb/uCf+Y9crB75N6Xh04GSCTiE fSD4oqRhdEVfUw/ZurAc5Pq1yoPgL7U3VmBK3m4gxNIlHMN38bzJeRK0bC6avXBuUf6G 4Q3zGRL7VKO07eO2rH5G3lJ5LxEl2BnFq1BL3mgvRWRZnm/GioVXpNZfEyZ0zcU+sDKy yOFKfj4vtrPSMFAZW3HAaJLgCY2+8fHa7+PzyrL4aNLpHMGATviSi2KhjFo+h8iNwlqw 93eWIEXrucsMcrEZtnnpzIPq1yaXlKMCDK5x+xjZhQtnb/Fnf46DipPKs+brE43dA5cM QKbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636828; x=1782241628; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ZfK0y90nu3Ld/r6Gi/P+At5Q9uLEC4IcCIzFZn+LBq8=; b=GOc9euyICKA1OQExAErkiNUvYjiyxdNqHmTqKurfaLdVeU2pG94JwJsZGOuw/cMC8X C9XpnhKV+yp5mpv6xqwcvQo5OgxB3iPRDWNqddoSkt1L+MoBIzNg/qwY0f7OsifeSsdX ufWerVgiUtfHg94gLmLCYpT9KBoWN3IYxPLTS4vwMMOXsqDyjBQujEFFJ+0tX2+cd4ti k1fM9bGH3Mgfs42bY7oy/qLWYAZF4HA54qaOam6TmyPRZLHuoWkON4dreaAc6qv05ZbM OKnyC1iL7DSDOHr2nfRuIU0FDducjDTkWqtHUDmwpo+/Huqu6odu7eBj4iv/juKcS/5U x0fw== X-Gm-Message-State: AOJu0YyfEb0Sr2P5cAL3bFPRSfoGthxIv0lFMdJ+UJDFI0WNlYnBRbQO KmDRGdZh9JzEG6rEwi4xjFf4rbownk5Bp6okSrsWAZfGpQgcqgEXJIgfZ6/k0NqoFYqVU9fz2Tq c5enT X-Gm-Gg: Acq92OGeLhiKRYx+WYyAyCktgotFA0Dscug1GRJvgBX1mJWkg9+rkvbYn80K6u88sI8 74cdUGKON+lCiIy+SiCMPeK/3N1IBtsGt5U9qWOe03ttSry+ls6IIXTD0gjMrSAcMqdJ5OKQND7 nv3iXZm1QEYYzGyEStAJLFBRYNeGeG75ok2S0MgvsOnBoaczcrbhRLLQx1R4io0FBZvKepctKJe sBKQItALhK4u2eOwBDyAWUeDWeqYVE+b9JEqrCX3BQ+xhRardoD7w6iEZWOTiiq+M/O+VP1IvG6 G33hxmV0iQk8u3qByQO1rmBxBhvVCTObNtQV/Aurl0MW0vtw8n29JTUkobDJSH11r3NMABXazjZ RE+wIt96VlSAUNbkL8UvLo1TrT2/9S4hUG0flDxWAhTMHr1RaH7WyEqyNlJMZiv2Xy2ouRrBKUy CnTdAve3xPy0jnUZsDsAK62FS0vpM8D+VpM2Qy85xq2rlG4xrN4dUkJIL6G0+2LFWcGI0qZ43+y Q6NW62dlMaDVMN1rrqCoyBrL55iAxb3TFzhlkd4QuA= X-Received: by 2002:a05:600c:c096:b0:490:be9e:fd03 with SMTP id 5b1f17b1804b1-492333e8f1emr10480435e9.7.1781636828502; Tue, 16 Jun 2026 12:07:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/61] hw/arm/tegra241-cmdqv: Implement CMDQV vIOMMU alloc/free Date: Tue, 16 Jun 2026 20:06:00 +0100 Message-ID: <20260616190639.3462006-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637279230158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Replace the stub implementation with real vIOMMU allocation for Tegra241 CMDQV. Allocate a matching vEVENTQ together with the vIOMMU, since it is specific to the Tegra241 CMDQV vIOMMU and used to receive CMDQV events. Free both objects on teardown. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260609112552.378999-14-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 48 ++++++++++++++++++++++++++++++++++++++++- hw/arm/tegra241-cmdqv.h | 1 + 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 2875affc8d..c1351c8519 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/arm/smmuv3-common.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 @@ -26,13 +27,58 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwa= ddr offset, =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + IOMMUFDViommu *viommu =3D accel->viommu; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + IOMMUFDVeventq *veventq =3D cmdqv->veventq; + + if (!viommu) { + return; + } + if (veventq) { + close(veventq->veventq_fd); + iommufd_backend_free_id(viommu->iommufd, veventq->veventq_id); + g_free(veventq); + cmdqv->veventq =3D NULL; + } + iommufd_backend_free_id(viommu->iommufd, viommu->viommu_id); } =20 static bool tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, uint32_t *out_viommu_id, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + Tegra241CMDQV *cmdqv =3D s->s_accel->cmdqv; + uint32_t viommu_id, veventq_id, veventq_fd; + IOMMUFDVeventq *veventq; + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, + idev->hwpt_id, cmdqv->cmdqv_data, + sizeof(*cmdqv->cmdqv_data), &viommu_= id, + errp)) { + return false; + } + + if (!iommufd_backend_alloc_veventq(idev->iommufd, viommu_id, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + 1 << SMMU_EVENTQS, &veventq_id, + &veventq_fd, + errp)) { + error_append_hint(errp, "Tegra241 CMDQV: failed to alloc veventq"); + goto free_viommu; + } + + veventq =3D g_new(IOMMUFDVeventq, 1); + veventq->veventq_id =3D veventq_id; + veventq->veventq_fd =3D veventq_fd; + cmdqv->veventq =3D veventq; + + *out_viommu_id =3D viommu_id; + return true; + +free_viommu: + iommufd_backend_free_id(idev->iommufd, viommu_id); return false; } =20 diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index a5f65a8991..9fc720e96c 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -32,6 +32,7 @@ typedef struct Tegra241CMDQV { SMMUv3AccelState *s_accel; MemoryRegion mmio_cmdqv; qemu_irq irq; + IOMMUFDVeventq *veventq; } Tegra241CMDQV; =20 const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637363; cv=none; d=zohomail.com; s=zohoarc; b=EqS8sMWX+hlLrpathMXnL0o42syMn0VSSODm5nrIwwniozFSMgqSWNH/ygyFdQmGVUVxZoQj11ybD3p8AQJCzAzq7G0o+k5VvZEQIdYoGKq0G4UvdNfVUTLf5IoNIYog2Q7f+g8euqjxl3FnVJbQvGHA9Hp/PvrfOkEM60ojt+o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637363; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=CF2PjHRoqnkXEbIdrl1cHC73lx4B4AOTIM81CeISaZE=; b=S/I7dtUfFOzY/qrNKPbg/BCuBoHQbh3jfaLWr93sF8XT6ldoDFhLA86nRcruMPMrpQNW3jViTsz/Xgdn2gE7GsRCAOenJny9k0xLfL+yQdw42Cg/k4vL9H9sdf9BMSkpQlD7cgspR+9kcPJWdUB/J18aAD2N0xyBXUsxTJ14hgc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637363459436.59434795564994; Tue, 16 Jun 2026 12:16:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZEE-0004pO-N0; Tue, 16 Jun 2026 15:13:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8Y-0004lt-B0 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:52 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8T-0000zH-T6 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-490b1bbcf3aso37690415e9.1 for ; Tue, 16 Jun 2026 12:07:10 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636830; x=1782241630; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CF2PjHRoqnkXEbIdrl1cHC73lx4B4AOTIM81CeISaZE=; b=awNBaIKLrw2hY4X8VIN70HMZJqnCUYVYfxheYkYdS/zM8uGzJJlzP07dzXNTRtM2bh HD5ufXwRJ+7yVWVtzkXyaOxSjNEkM4UCWDzPlcTWOuh4oJ98SrmIYfX8usfeNT5NjIpK swSLxjnY4H3EUVWtJQyStxar7gmj3/n/C6hUVDbkGiwLDK3TU102pGoSCdpNAec3pOQJ JSNW2NbjhaVmuuRJIPnYgCRL6e5dd5Hdh124PkfAiyXYIAj5LeuWGUoDBjpxlkNf58jr s1P43lm7ryydOsInAt0CxtgcKMUI8cbPe/67Q4DLZ7Z2HkJguLAMlTTgJKqGuYd+synC daQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636830; x=1782241630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=CF2PjHRoqnkXEbIdrl1cHC73lx4B4AOTIM81CeISaZE=; b=Y95D7uSK5A4olD1GPKe17XlVdn0WnnSZ8hE5N5hKJLEmpuR9vVnbcGwZn5j8VOmWM+ YpKU0tqgcIbQnRmVyRICFfnpQxWwz1yMkWC3bcsK/3D+68CDlQyE4XQKS3knVAsj4UOn I7wwguSYGFZVQ+D5KNfXxzg4k74XMUQcvO8fIsFai36yc5cjP43DfcDB8ETV+Yyc9E0E eOg5da2v6/8FdCe8SNCDmcAPCtK6f/MuWOcHhvl3bH5viDU6ikVX5FHgyptW3fjsizC8 dteinkN5ow3NtIgSxYDpyPTcvmlnUe8AHNCsS7OkwWjHXTTgvqFcoCFpVZE93R1bHUXq 6bUQ== X-Gm-Message-State: AOJu0YxhHghHQt8HKaetuU/xJ1sjVv3TfBfott2OEhcI3wj1XbMS4F3O p8WYgX7FmbYyTkKR3Za5pMNE/y3J73wc8YDLRblyXRVus3z5/q23S/9AAXsOiuBUp0syqsHoc/q sZact X-Gm-Gg: Acq92OHlp1chZKbrnoVRDUJWheFZvcGtPTKdMNd2+QZSvsJ8YDWmnXtVyT6LBlfOUa+ dgVNFu43wjoTHe+PDTnEYqtWsxLO9p5u7X1+YxvsCEH6mmkj8KpZg8gQiPeaSwVAVeiUedyrkX9 ETwV7dMPraHexpopfstb+bm9pG4EgOmjJW9r2JCM3duZnDE2wIkSAm6ZZTOJBXqCJm9UImPXISG F7f230oqUVxb0vJGsx/3bOZ8scbdXd24iYu+q9WUbjttJaXADcuOF06F13a87LxIrxdYhz1NluJ 6qTaja/pJD+0kRHORImeN/F2QmNPackVU61w+jxsbRpS0i7MZXhLI9gVtzDzBhnZqQeZPIm8Sdy migGk4YUNAtqqR5xvGCd7oZXAZwqK8/U/ulTUZNhesKUtZtnZL1ZnKE9/CjQNgWMvUCiWovU55y pLPSZ+KEKXceSGm8CYOhJnyVGBn8g0hsBAUXyftQZhH7vylzy+Kghtw7uhqNxe65DjtRGLXCcbJ G7n8lBd06xXg+ZpvTplFRMgDA++NGJ8 X-Received: by 2002:a05:600c:818f:b0:490:b6a4:9f43 with SMTP id 5b1f17b1804b1-492333a5291mr15383805e9.7.1781636829660; Tue, 16 Jun 2026 12:07:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/61] hw/arm/tegra241-cmdqv: mmap host VINTF Page0 for CMDQV Date: Tue, 16 Jun 2026 20:06:01 +0100 Message-ID: <20260616190639.3462006-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637363808158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen The kernel currently exposes a single VINTF per emulated SMMUv3 instance. IOMMU_VIOMMU_ALLOC returns an mmap offset for the host VINTF Page0 allocated for this SMMU. However, VCMDQs only become bound to that VINTF after IOMMU_HW_QUEUE_ALLOC, so until then the mapped Page0 does not back any real VCMDQ state. mmap the host VINTF Page0 right after IOMMU_VIOMMU_ALLOC, as the host VINTF is already enabled at that point, and unmap it when the vIOMMU is freed. The mapping shares the vIOMMU's lifetime. This prepares the VINTF mapping in advance of subsequent patches that add VCMDQ allocation. Signed-off-by: Nicolin Chen Tested-by: Nicolin Chen Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Message-id: 20260609112552.378999-15-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 16 +++++++++++++++- hw/arm/tegra241-cmdqv.h | 3 +++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index c1351c8519..3eec6073a4 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -41,6 +41,10 @@ static void tegra241_cmdqv_free_viommu(SMMUv3State *s) g_free(veventq); cmdqv->veventq =3D NULL; } + if (cmdqv->vintf_page0) { + munmap(cmdqv->vintf_page0, VINTF_PAGE_SIZE); + cmdqv->vintf_page0 =3D NULL; + } iommufd_backend_free_id(viommu->iommufd, viommu->viommu_id); } =20 @@ -60,13 +64,20 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, return false; } =20 + if (!iommufd_backend_viommu_mmap(idev->iommufd, viommu_id, VINTF_PAGE_= SIZE, + cmdqv->cmdqv_data->out_vintf_mmap_off= set, + &cmdqv->vintf_page0, errp)) { + error_append_hint(errp, "Tegra241 CMDQV: failed to mmap VINTF page= 0"); + goto free_viommu; + } + if (!iommufd_backend_alloc_veventq(idev->iommufd, viommu_id, IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, 1 << SMMU_EVENTQS, &veventq_id, &veventq_fd, errp)) { error_append_hint(errp, "Tegra241 CMDQV: failed to alloc veventq"); - goto free_viommu; + goto munmap_page0; } =20 veventq =3D g_new(IOMMUFDVeventq, 1); @@ -77,6 +88,9 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *idev, *out_viommu_id =3D viommu_id; return true; =20 +munmap_page0: + munmap(cmdqv->vintf_page0, VINTF_PAGE_SIZE); + cmdqv->vintf_page0 =3D NULL; free_viommu: iommufd_backend_free_id(idev->iommufd, viommu_id); return false; diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 9fc720e96c..00c83b6186 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -25,6 +25,8 @@ */ #define TEGRA241_CMDQV_IO_LEN 0x50000 =20 +#define VINTF_PAGE_SIZE 0x10000 + struct iommu_viommu_tegra241_cmdqv; =20 typedef struct Tegra241CMDQV { @@ -33,6 +35,7 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; IOMMUFDVeventq *veventq; + void *vintf_page0; } Tegra241CMDQV; =20 const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636994; cv=none; d=zohomail.com; s=zohoarc; b=ieF8aaQqLd7kE8Im9+vuXjMQA65kVmE5u7pOY/POEVybpDzZU8fDib0eR5jWGSGM/+h0LU8Mo5eXEmfSQ8Jx45+I7pqpOFptvhoBXnIfWqqNEhTLEg25+yaDmjxuftEwxpN/lJYYy5M22T3aCR0ajv3qjBsD9kuSIereqOwHbDw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636994; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Uj8VsHdiz/VZVf8n44lPRhYIPhFT4loCUExswkW8++M=; b=BSVro6h8VVNd6sC1qamQVvd0ZNQ74dI0HZE2j/EKBcwVk5yn+aFAAS3tWLzzVOaoOCtyd7CYFNdmr4/r+0UNB+wP3O3Zd5LcRO8SHZsycvpLztYP1OacwLbvsim/m290Go8HQ50J1QlRMAa3FELXyc1ykZG4PnE0/qpiNO0dPRk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781636994104930.512982692499; Tue, 16 Jun 2026 12:09:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZ9I-0005JD-NT; Tue, 16 Jun 2026 15:08:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ86-0004VX-Rb for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:28 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ7z-0000zl-6M for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:20 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-490b9318997so36091055e9.2 for ; Tue, 16 Jun 2026 12:07:12 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636831; x=1782241631; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Uj8VsHdiz/VZVf8n44lPRhYIPhFT4loCUExswkW8++M=; b=nWcw2fcUFnnEqqOFVc9iySFB4vYhAss27QUKZAYUtxYAFwII5Y53fpHVVeIA6pYjk9 J5I/zTr6JhzdzJyUmDwTv1s+LoIz1z+iJK0wJ40NUa26M7Jjw9Uce7dOXB0dQpxUlNTt dO2IV95pd1Gg06wCJFQpzLPVaV3IhQoKwoMqq+sK7NEZeLh6WR7joXubm4Xxh+ZpnUVc CN95pBFLMav6noEaJp6UCybv8YBp4NNWJwxLiuRr93pjPmJzvjwYck1zV1pdKcUjJ2L0 pa4piJoE6t2NsyRLUT31fYAvqEEdSkdU6y5U12WO4GGb21fvjKvM6Lr/iex4d6SX0Y3L x97w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636831; x=1782241631; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Uj8VsHdiz/VZVf8n44lPRhYIPhFT4loCUExswkW8++M=; b=Dt/irfiGkEhllf9X+aBRmk7V1m9wuWLBdWGGU79GkIomQfU+uKGwfjJ+sVCrb2fRd+ F/zFZ/ZX3lRPBCkbhMvJSU3UWz5PoSddeW5IGbQ40PHMhu4I4v6K/595+xbXxCC7Rms+ 64MhAM9tCgJ1w/ennO3PSXZyRnCCDZtBsPbigCEq5ECaM0UrXUDw9KMf8VOP/gSzszDH mHjTOt0fj/9VCZSV8qwR5r2ddRnyYoX5wR22vdgq3k/UAMNusGad9+j9vfvpudf5WyF2 c+lxkcDyYMAvtFxtRVUuMDPAy8I0sd4pWK0HMcsrKks0S/Afs1L5bt2PKoTFBQF1p9y4 obzA== X-Gm-Message-State: AOJu0YyIeYlY9pyqqyLJp+hiT9hJ3mAdtRicpJk6sAFNJuu5g/SVpPxb rfu1lDuSgc4okBNNIV5zmJWALUiigOBvZxIW6vXTp6BCMLZG8FZL3gWK44+i1stBQjSBZi8SF30 V5Gd1 X-Gm-Gg: Acq92OGIknx0hcmrXLtEnRRtpg15Zp9vanXM81SzYoKaLJ2saiKUYR3mc19r2/1tyU/ PfoBxMRHWRSP1PSUhWBN/bc7UUCKpCQ/AlHoNcQVZSbp7QmqNbcNo3HLaiYOLjhsUQgCTS/aWvK Eyo5kJxlByMUgMg880cpIdFCZwvEWGdZWyapPL1kBudAOHuNrzI1PUn2yTYEQqO9KioSH68wGs2 UT33eFEP1zs/k/LXN2xbvgce9rYmjodLZixyFIjmuwGoPyILgxzZx+gdZ7nJtCooftCpRXuCZ2l n0xGaq79oLEFi5CvxTXCztA3R4+ZG63CH+fv1BVW9tcI/J7fLEJikHFSI7Du4vGCRVxAh6w62AN Rc0zhKydjBxRZoTT3XIwqMd+M7443BGAyxOV5Y9SerTVAyx0RUNX+8yYopAnjCORK86hM2LR/10 Lp28QMSSGtWpALUcm4281GN304SwQRpi/zqHbCf72z2hwvHbHGUwtdqDyZs2YUlODXg+cLIET26 bf1sBXHfpWi+l0ynm3k+wDp4aBPafau X-Received: by 2002:a05:600c:e547:20b0:492:1eed:3e67 with SMTP id 5b1f17b1804b1-492333d6cadmr9248505e9.26.1781636830905; Tue, 16 Jun 2026 12:07:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/61] hw/arm/tegra241-cmdqv: Emulate CMDQ-V Config region Date: Tue, 16 Jun 2026 20:06:02 +0100 Message-ID: <20260616190639.3462006-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636995468158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Tegra241 CMDQV exposes control and status registers in the CMDQ-V Config page (offset [0x0, 0x10000)) used to configure virtual command queue allocation and interrupt behavior. Add read/write emulation for the CMDQ-V Config region ([CMDQV_BASE, CMDQV_CMDQ_BASE]), backed by a simple register cache. This includes CONFIG, PARAM, STATUS, VI error and interrupt maps, CMDQ allocation map and the VINTF0 related registers defined in the CMDQ-V Config space. Only VINTF0 is supported; VINTF1-63 are not. Dispatch writes on access size: Introduced writel_mmio for 4-byte and writell_mmio for 8-byte. Reads need no split as the MMIO framework masks the returned value to the access size. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260609112552.378999-16-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 181 +++++++++++++++++++++++++++++++++++++++- hw/arm/tegra241-cmdqv.h | 110 ++++++++++++++++++++++++ hw/arm/trace-events | 4 + 3 files changed, 294 insertions(+), 1 deletion(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 3eec6073a4..8950d5153b 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -8,21 +8,200 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" =20 #include "hw/arm/smmuv3.h" #include "hw/arm/smmuv3-common.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" +#include "trace.h" + +static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv, + hwaddr offset) +{ + int i; + + switch (offset) { + case A_VINTF0_CONFIG: + return cmdqv->vintf_config; + case A_VINTF0_STATUS: + return cmdqv->vintf_status; + case A_VINTF0_SID_MATCH_0 ... A_VINTF0_SID_MATCH_15: + i =3D (offset - A_VINTF0_SID_MATCH_0) / 4; + return cmdqv->vintf_sid_match[i]; + case A_VINTF0_SID_REPLACE_0 ... A_VINTF0_SID_REPLACE_15: + i =3D (offset - A_VINTF0_SID_REPLACE_0) / 4; + return cmdqv->vintf_sid_replace[i]; + case A_VINTF0_LVCMDQ_ERR_MAP_0 ... A_VINTF0_LVCMDQ_ERR_MAP_3: + i =3D (offset - A_VINTF0_LVCMDQ_ERR_MAP_0) / 4; + return cmdqv->vintf_cmdq_err_map[i]; + default: + /* + * GLB_FILT_CFG_0 (offset 0xC) and GLB_FILT_DATA_0 (offset 0x10) a= re + * filter config and filter data registers. They are not required = for + * normal VINTF operation and are not emulated. + */ + qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", + __func__, offset); + return 0; + } +} + +static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv, + hwaddr offset, uint64_t valu= e) +{ + int i; + + switch (offset) { + case A_VINTF0_CONFIG: + /* + * Mask out HYP_OWN on guest writes. This bit selects Hypervisor (= 1) vs + * Guest (0) ownership of the CMDQ. Force it to 0 so the VINTF alw= ays + * remains guest-owned. + */ + value &=3D ~R_VINTF0_CONFIG_HYP_OWN_MASK; + + cmdqv->vintf_config =3D value; + if (value & R_VINTF0_CONFIG_ENABLE_MASK) { + cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + } else { + cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; + } + break; + case A_VINTF0_SID_MATCH_0 ... A_VINTF0_SID_MATCH_15: + i =3D (offset - A_VINTF0_SID_MATCH_0) / 4; + cmdqv->vintf_sid_match[i] =3D value; + break; + case A_VINTF0_SID_REPLACE_0 ... A_VINTF0_SID_REPLACE_15: + i =3D (offset - A_VINTF0_SID_REPLACE_0) / 4; + cmdqv->vintf_sid_replace[i] =3D value; + break; + default: + /* + * GLB_FILT_CFG_0 (offset 0xC) and GLB_FILT_DATA_0 (offset 0x10) a= re + * filter config and filter data registers. They are not required = for + * normal VINTF operation and are not emulated. + */ + qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", + __func__, offset); + return; + } +} =20 static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset, unsigned size) { - return 0; + Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + uint64_t val =3D 0; + + if (offset >=3D TEGRA241_CMDQV_IO_LEN) { + qemu_log_mask(LOG_UNIMP, + "%s offset 0x%" PRIx64 " off limit (0x%x)\n", __func= __, + offset, TEGRA241_CMDQV_IO_LEN); + goto out; + } + + switch (offset) { + case A_CONFIG: + val =3D cmdqv->config; + break; + case A_PARAM: + val =3D cmdqv->param; + break; + case A_STATUS: + val =3D cmdqv->status; + break; + case A_VI_ERR_MAP_0 ... A_VI_ERR_MAP_1: + val =3D cmdqv->vi_err_map[(offset - A_VI_ERR_MAP_0) / 4]; + break; + case A_VI_INT_MASK_0 ... A_VI_INT_MASK_1: + val =3D cmdqv->vi_int_mask[(offset - A_VI_INT_MASK_0) / 4]; + break; + case A_CMDQ_ERR_MAP_0 ... A_CMDQ_ERR_MAP_3: + val =3D cmdqv->cmdq_err_map[(offset - A_CMDQ_ERR_MAP_0) / 4]; + break; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: + val =3D cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4]; + break; + case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: + val =3D tegra241_cmdqv_config_vintf_read(cmdqv, offset); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", + __func__, offset); + } + +out: + trace_tegra241_cmdqv_read_mmio(offset, val, size); + return val; +} + +/* 4-byte MMIO write handler. */ +static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *cmdqv, hwaddr offset, + uint32_t value) +{ + switch (offset) { + case A_CONFIG: + cmdqv->config =3D value; + if (value & R_CONFIG_CMDQV_EN_MASK) { + cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; + } else { + cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; + } + break; + case A_VI_INT_MASK_0 ... A_VI_INT_MASK_1: + cmdqv->vi_int_mask[(offset - A_VI_INT_MASK_0) / 4] =3D value; + break; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: + cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] =3D value; + break; + case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: + tegra241_cmdqv_config_vintf_write(cmdqv, offset, value); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", + __func__, offset); + } +} + +/* + * 8-byte MMIO write handler. + */ +static void tegra241_cmdqv_writell_mmio(Tegra241CMDQV *cmdqv, hwaddr offse= t, + uint64_t value) +{ + qemu_log_mask(LOG_UNIMP, + "%s unhandled 64-bit write at 0x%" PRIx64 " (WI)\n", + __func__, offset); } =20 static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, uint64_t value, unsigned size) { + Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + + if (offset >=3D TEGRA241_CMDQV_IO_LEN) { + qemu_log_mask(LOG_UNIMP, + "%s offset 0x%" PRIx64 " off limit (0x%x)\n", __func= __, + offset, TEGRA241_CMDQV_IO_LEN); + goto out; + } + + switch (size) { + case 4: + tegra241_cmdqv_writel_mmio(cmdqv, offset, value); + break; + case 8: + tegra241_cmdqv_writell_mmio(cmdqv, offset, value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s bad write size %u at 0x%" PRIx64 "\n", + __func__, size, offset); + } + +out: + trace_tegra241_cmdqv_write_mmio(offset, value, size); } =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 00c83b6186..d49fa42cd5 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -10,10 +10,15 @@ #ifndef HW_ARM_TEGRA241_CMDQV_H #define HW_ARM_TEGRA241_CMDQV_H =20 +#include "hw/core/registerfields.h" + #define CMDQV_VER 1 #define CMDQV_NUM_CMDQ_LOG2 1 #define CMDQV_NUM_SID_PER_VI_LOG2 4 =20 +#define TEGRA241_CMDQV_MAX_CMDQ (1U << CMDQV_NUM_CMDQ_LOG2) +#define TEGRA241_CMDQV_MAX_NUM_SID (1U << CMDQV_NUM_SID_PER_VI_LOG2) + /* * Tegra241 CMDQV MMIO layout (64KB pages) * @@ -36,8 +41,113 @@ typedef struct Tegra241CMDQV { qemu_irq irq; IOMMUFDVeventq *veventq; void *vintf_page0; + + /* CMDQ-V Config page register cache */ + uint32_t config; + uint32_t param; + uint32_t status; + uint32_t vi_err_map[2]; + uint32_t vi_int_mask[2]; + uint32_t cmdq_err_map[4]; + uint32_t cmdq_alloc_map[TEGRA241_CMDQV_MAX_CMDQ]; + + /* VINTF0 register cache (within CMDQ-V Config page) */ + uint32_t vintf_config; + uint32_t vintf_status; + uint32_t vintf_sid_match[TEGRA241_CMDQV_MAX_NUM_SID]; + uint32_t vintf_sid_replace[TEGRA241_CMDQV_MAX_NUM_SID]; + uint32_t vintf_cmdq_err_map[4]; } Tegra241CMDQV; =20 +/* CMDQ-V Config page registers (offset 0x00000) */ +REG32(CONFIG, 0x0) +FIELD(CONFIG, CMDQV_EN, 0, 1) +FIELD(CONFIG, CMDQV_PER_CMD_OFFSET, 1, 3) +FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) +FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) +FIELD(CONFIG, CONS_DRAM_EN, 20, 1) + +REG32(PARAM, 0x4) +FIELD(PARAM, CMDQV_VER, 0, 4) +FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) +FIELD(PARAM, CMDQV_NUM_VI_LOG2, 8, 4) +FIELD(PARAM, CMDQV_NUM_SID_PER_VI_LOG2, 12, 4) + +REG32(STATUS, 0x8) +FIELD(STATUS, CMDQV_ENABLED, 0, 1) + +/* SMMU_CMDQV_VI_ERR_MAP_0/1 definitions */ +#define A_VI_ERR_MAP_0 0x14 +#define A_VI_ERR_MAP_1 0x18 +#define V_VI_ERR_MAP_NO_ERROR (0) +#define V_VI_ERR_MAP_ERROR (1) + +/* SMMU_CMDQV_VI_INT_MASK_0/1 definitions */ +#define A_VI_INT_MASK_0 0x1c +#define A_VI_INT_MASK_1 0x20 +#define V_VI_INT_MASK_NOT_MASKED (0) +#define V_VI_INT_MASK_MASKED (1) + +/* SMMU_CMDQV_CMDQ_ERR_MAP_0-3 definitions */ +#define A_CMDQ_ERR_MAP_0 0x24 +#define A_CMDQ_ERR_MAP_1 0x28 +#define A_CMDQ_ERR_MAP_2 0x2c +#define A_CMDQ_ERR_MAP_3 0x30 + +/* + * CMDQ_ALLOC_MAP: one entry per physical VCMDQ. Hardware supports up to 1= 28 + * entries (CMDQV_NUM_CMDQ_LOG2=3D7), but QEMU only exposes + * TEGRA241_CMDQV_MAX_CMDQ (=3D2) VCMDQs per VM so only entries 0 and 1 are + * defined here. + */ +/* 2 identical register entries */ +#define SMMU_CMDQV_CMDQ_ALLOC_MAP_(i) \ + REG32(CMDQ_ALLOC_MAP_##i, 0x200 + i * 4) \ + FIELD(CMDQ_ALLOC_MAP_##i, ALLOC, 0, 1) \ + FIELD(CMDQ_ALLOC_MAP_##i, LVCMDQ, 1, 7) \ + FIELD(CMDQ_ALLOC_MAP_##i, VIRT_INTF_INDX, 15, 6) + +SMMU_CMDQV_CMDQ_ALLOC_MAP_(0) +SMMU_CMDQV_CMDQ_ALLOC_MAP_(1) + +/* SMMU_CMDQV_VINTF0 registers (only VINTF0 is exposed to the guest) */ +REG32(VINTF0_CONFIG, 0x1000) +FIELD(VINTF0_CONFIG, ENABLE, 0, 1) +FIELD(VINTF0_CONFIG, VMID, 1, 16) +FIELD(VINTF0_CONFIG, HYP_OWN, 17, 1) + +REG32(VINTF0_STATUS, 0x1004) +FIELD(VINTF0_STATUS, ENABLE_OK, 0, 1) +FIELD(VINTF0_STATUS, STATUS, 1, 3) +FIELD(VINTF0_STATUS, VI_NUM_LVCMDQ, 16, 8) + +#define V_VINTF_STATUS_NO_ERROR (0 << 1) +#define V_VINTF_STATUS_VCMDQ_ERROR (1 << 1) + +/* + * SMMU_CMDQV_VINTF0_SID_MATCH/_REPLACE: 16 entries per VINTF + * (CMDQV_NUM_SID_PER_VI_LOG2=3D4). Only _0 and _15 are defined, + * used as switch case range bounds. + */ +REG32(VINTF0_SID_MATCH_0, 0x1040) +FIELD(VINTF0_SID_MATCH_0, ENABLE, 0, 1) +FIELD(VINTF0_SID_MATCH_0, VIRT_SID, 1, 20) +#define A_VINTF0_SID_MATCH_15 (A_VINTF0_SID_MATCH_0 + 15 * 4) + +REG32(VINTF0_SID_REPLACE_0, 0x1080) +FIELD(VINTF0_SID_REPLACE_0, PHYS_SID, 0, 20) +#define A_VINTF0_SID_REPLACE_15 (A_VINTF0_SID_REPLACE_0 + 15 * 4) + +/* + * SMMU_CMDQV_VINTF0_LVCMDQ_ERR_MAP: 4 registers per VINTF covering 32 log= ical + * VCMDQs each. With TEGRA241_CMDQV_MAX_CMDQ=3D2, only MAP_0 bits [1:0] ca= rry + * error state. MAP_1..MAP_3 always read as 0. Only _0 and _3 are defined, + * used as switch case range bounds. + */ +REG32(VINTF0_LVCMDQ_ERR_MAP_0, 0x10c0) +FIELD(VINTF0_LVCMDQ_ERR_MAP_0, LVCMDQ_ERR_MAP, 0, 32) +#define A_VINTF0_LVCMDQ_ERR_MAP_3 (A_VINTF0_LVCMDQ_ERR_MAP_0 + 3 * 4) + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 3457536fb0..8c61d66a26 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -72,6 +72,10 @@ smmuv3_accel_unset_iommu_device(int devfn, uint32_t devi= d) "devfn=3D0x%x (idev dev smmuv3_accel_translate_ste(uint32_t vsid, uint32_t hwpt_id, uint64_t ste_1= , uint64_t ste_0) "vSID=3D0x%x hwpt_id=3D0x%x ste=3D%"PRIx64":%"PRIx64 smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_i= d) "vSID=3D0x%x ste type=3D%s hwpt_id=3D0x%x" =20 +# tegra241-cmdqv +tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" +tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637367; cv=none; d=zohomail.com; s=zohoarc; b=KtrZ9bVUlAgFqB/VvG3TbgoUaIVcam2HSZ1n1kWT+Fte4KrK0sVyW3SttTofw9c1rBdR4wRFOqqDIKFFsQbn79pQM8w1oOfy4HT0BBMVhZmAZlfQ1ceNp7zc1WLJ1wMQ7aO3SJ7/cLWPtelFgM5JK1eqFYCy+vvOUBVKKnkIDps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637367; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=vR7RdlNMPx/THnmWhCmFbMG80mzKu4YDqpbpGpKx+mQ=; b=SMFAQcfw+IWb1T6jn+RLDJTrpvIzWj93FcVJYaglVruf37UQSxVnHYXiY3D7rFTDZT0ui5XChcZtvFSiL2bxdki9NvMCeKJPqbGp2X2tlAMT+jMd/ZDMUjikJrM94yqvmaJjJ2U1m8iAXQLZMDiX8JmUChha3fH79YJZSG0dJ+s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637367511996.6797014769613; Tue, 16 Jun 2026 12:16:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZDr-0004JR-CZ; Tue, 16 Jun 2026 15:13:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8A-0004Yq-3v for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:36 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ83-000102-Af for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:24 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-45ef4223be7so2869945f8f.2 for ; Tue, 16 Jun 2026 12:07:13 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636832; x=1782241632; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vR7RdlNMPx/THnmWhCmFbMG80mzKu4YDqpbpGpKx+mQ=; b=CXp54FtCrABpfDNIRro+6DQgjZAKdrWEzsBpa24WJQ+cryz1j8HhJqPd2k85bZROS2 0Jcn0TE9phqKim6VaU9TdgkHHr3vifqnzEpZ2XzGSpc4XXPZu1CBxal7FCPRQLlI+Oe1 0jzODH33wnd0dTVZcMnjfQfyW8FxuwPOzpBRtdaWTRzin482TYVBRHA46ZL9RqtLa6vH a+21YExxWFm16qLiCkqmaOWXUjTJ8gSX4J4d+H3bfK8gVOzFkGJe4SX+/JVwfIiHHs+t r/8p521h8T8SmEup+SYC0Ux09GQGNWr+FKejuMlo3yNu/8GxKtQetTQWLVdrA/7pwsvr c0uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636832; x=1782241632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=vR7RdlNMPx/THnmWhCmFbMG80mzKu4YDqpbpGpKx+mQ=; b=HdS/5lQ8pKfgivzXkUlv+OFzI8GIOs5lapn5c4j2jukjXBgKPsu2uv+QqCGPK52tOV zslxQz1RDasENZ6hjNNUBVLELGJS/Kw8al2/zEm31ith0xCFGMRAiQRYQ50g4xk6RJyh GkVenDB/T4tGLbAdtEFI4pPoQQtgLuq5HHtqSnP2sJTvArXA6PW2LyLH3bIEgEqWwNC7 ffONKSMNGPKGthP0D5B+LkXso11TriZ8YXjjyAEgKcgScCPJYFxWrwk3Sjwe5GqE8ubd zvp+m2wHuzSFUcl0cMUYauYNc6SwcOhE4Tq2RL6mj8z4udtvf+Etw+ZtXLojGYJGMRPq IYtA== X-Gm-Message-State: AOJu0YwCw/nhFU+3g1rUHpZAR/E1HgoSRj9TroIWsFofk+MkRRg+d7TN +82uJqwBF5pKJzjWmQ3HXJ0YGX4hVds4RMco/T3J9WhtxnNLjso9d7SVlZbB3lzt/IXqBo0Yy6V LSA/X X-Gm-Gg: Acq92OFOI21zeNYrWwgOA7jKfVrw6gtg/FEFiX6Dbw95tbFxauVU+EMI5R8W2jDaFiL h822ZqYVToRzhJsxWBrzlcMar8W24a9k9AD7l+Yj+FP28pDZWkGn2tzjRFDPTiFyt+i4ux/Q2l0 dA0r3uXsbCzgIq4FAADHYxJyyj2eBLHn+aEJydiMUn5PkT4KedG9mu2dyUEH5ACwpOwjb3B/wps ACwJYRIpw2eaaQPTGy1WQHv49TwObTzRIoM/qkHfrCI6GZGpM35gDt5Melqzmx8JMYcPPcZ0xa0 BOtHq3Wd/4Sddyf4KLCESbBdUvwgg0W9d36w91zd6LB/gHJgc/8qU7ZcC0c+vQxOxf2qHroRFs7 gbBI+N/sSGo3en1HZ8/qaRdIBPWd6PEsUV9CeiWiL01NhtkFjoQHb10dMDqEq53p1luAywVGDmC rho9XnkQO+Ye/fzLE9Gar6c30Z12BFl0aIrSurlnoqpfkDQyRLR3Jd2frZX+phpkU6yAqtzjOxs O9WedDtOx1BS3S4R6H0teHjumM2lXZ7 X-Received: by 2002:a5d:5d81:0:b0:460:3233:beef with SMTP id ffacd0b85a97d-4623936ca7bmr1200408f8f.43.1781636831887; Tue, 16 Jun 2026 12:07:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/61] hw/arm/tegra241-cmdqv: Emulate VCMDQ register reads Date: Tue, 16 Jun 2026 20:06:03 +0100 Message-ID: <20260616190639.3462006-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637367915158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Tegra241 CMDQV exposes per-VCMDQ register windows through two MMIO apertures: Direct VCMDQ aperture (0x10000/0x20000): VCMDQ Page0/Page1 VINTF logical aperture (0x30000/0x40000): VINTF0 LVCMDQ Page0/Page1 Both apertures are hardware aliases of the same underlying registers: Page 0 (control/status): CONS_INDX, PROD_INDX, CONFIG, STATUS, GERROR, GERRORN Page 1 (base/DRAM): BASE_L/H, CONS_INDX_BASE_DRAM_L/H The direct aperture Page 0 is programmable at any time so long as CMDQV_EN is enabled. The VINTF (logical) aperture Page 0 is programmable only once SW has mapped a VCMDQ to a VINTF; the "logical" view is local to that VINTF. Add read emulation for both apertures, backed by a single per-VCMDQ register cache. VINTF aperture reads are translated to their equivalent direct-aperture offset and served from the same cached state. Per the CMDQV architecture, a VCMDQ must be allocated to a Virtual Interface before it is used to send commands to the SMMU. Until that allocation happens, reads return cached register state with no HW interaction. Subsequent patches wire up IOMMU_HW_QUEUE_ALLOC, mmap the host VINTF Page 0, and install it into guest MMIO; after that, Page 0 reads from either aperture are served from the hardware-backed mmap'd page instead of the cache. Page 1 is also a hardware alias, but the kernel only exposes mmap for Page 0, so Page 1 reads always trap to QEMU and are served from cache. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260609112552.378999-17-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 103 +++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 216 ++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 2 + 3 files changed, 321 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 8950d5153b..2dfd377ee9 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -16,6 +16,79 @@ #include "tegra241-cmdqv.h" #include "trace.h" =20 +/* + * Read a VCMDQ Page 0 register (control/status) using VCMDQ0_* offsets. + * + * The caller normalizes the MMIO offset such that @offset0 always refers + * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + */ +static uint64_t tegra241_cmdqv_read_vcmdq_page0(Tegra241CMDQV *cmdqv, + hwaddr offset0, int index, + bool direct) +{ + uint64_t val =3D 0; + + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + val =3D cmdqv->vcmdq_cons_indx[index]; + break; + case A_VCMDQ0_PROD_INDX: + val =3D cmdqv->vcmdq_prod_indx[index]; + break; + case A_VCMDQ0_CONFIG: + val =3D cmdqv->vcmdq_config[index]; + break; + case A_VCMDQ0_STATUS: + val =3D cmdqv->vcmdq_status[index]; + break; + case A_VCMDQ0_GERROR: + val =3D cmdqv->vcmdq_gerror[index]; + break; + case A_VCMDQ0_GERRORN: + val =3D cmdqv->vcmdq_gerrorn[index]; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled read access at 0x%" PRIx64 "\n", + __func__, offset0); + } + trace_tegra241_cmdqv_read_vcmdq_page0(index, direct ? "direct" : "vi", + offset0, val); + return val; +} + +/* + * Read a VCMDQ Page 1 register (base / DRAM address) using VCMDQ0_* offse= ts. + */ +static uint64_t tegra241_cmdqv_read_vcmdq_page1(Tegra241CMDQV *cmdqv, + hwaddr offset0, int index, + bool direct) +{ + uint64_t val =3D 0; + + switch (offset0) { + case A_VCMDQ0_BASE_L: + val =3D cmdqv->vcmdq_base[index]; + break; + case A_VCMDQ0_BASE_H: + val =3D cmdqv->vcmdq_base[index] >> 32; + break; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + val =3D cmdqv->vcmdq_cons_indx_base[index]; + break; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_H: + val =3D cmdqv->vcmdq_cons_indx_base[index] >> 32; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled read access at 0x%" PRIx64 "\n", + __func__, offset0); + } + trace_tegra241_cmdqv_read_vcmdq_page1(index, direct ? "direct" : "vi", + offset0, val); + return val; +} + static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv, hwaddr offset) { @@ -93,6 +166,7 @@ static uint64_t tegra241_cmdqv_read_mmio(void *opaque, h= waddr offset, { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; uint64_t val =3D 0; + int index; =20 if (offset >=3D TEGRA241_CMDQV_IO_LEN) { qemu_log_mask(LOG_UNIMP, @@ -126,6 +200,35 @@ static uint64_t tegra241_cmdqv_read_mmio(void *opaque,= hwaddr offset, case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: val =3D tegra241_cmdqv_config_vintf_read(cmdqv, offset); break; + case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: + /* + * VINTF Page0 registers are hardware aliases of VCMDQ Page0 regis= ters. + * Translate the VINTF aperture offset to its VCMDQ Page0 equivale= nt + * before dispatching to the Page 0 helper. + */ + offset -=3D CMDQV_VINTF_PAGE0_BASE - CMDQV_VCMDQ_PAGE0_BASE; + index =3D (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE; + return tegra241_cmdqv_read_vcmdq_page0(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, false); + case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN: + /* + * Decode a per-VCMDQ Page 0 access. Each VCMDQ occupies a + * CMDQV_VCMDQ_STRIDE-byte window; extract the index and normalize + * to the VCMDQ0_* offset before calling the Page 0 helper. + */ + index =3D (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE; + return tegra241_cmdqv_read_vcmdq_page0(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, true); + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above. */ + offset -=3D CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE; + index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; + return tegra241_cmdqv_read_vcmdq_page1(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, false); + case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: + index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; + return tegra241_cmdqv_read_vcmdq_page1(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, true); default: qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", __func__, offset); diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index d49fa42cd5..c4d327a9a5 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -30,6 +30,13 @@ */ #define TEGRA241_CMDQV_IO_LEN 0x50000 =20 +/* CMDQV MMIO aperture bases and VCMDQ stride */ +#define CMDQV_VCMDQ_PAGE0_BASE 0x10000 /* CMDQV_CMDQ_BASE */ +#define CMDQV_VCMDQ_PAGE1_BASE 0x20000 +#define CMDQV_VINTF_PAGE0_BASE 0x30000 /* CMDQV_VI_CMDQ_BASE */ +#define CMDQV_VINTF_PAGE1_BASE 0x40000 +#define CMDQV_VCMDQ_STRIDE 0x80 + #define VINTF_PAGE_SIZE 0x10000 =20 struct iommu_viommu_tegra241_cmdqv; @@ -57,6 +64,19 @@ typedef struct Tegra241CMDQV { uint32_t vintf_sid_match[TEGRA241_CMDQV_MAX_NUM_SID]; uint32_t vintf_sid_replace[TEGRA241_CMDQV_MAX_NUM_SID]; uint32_t vintf_cmdq_err_map[4]; + /* + * VCMDQ register cache. The direct (VCMDQ aperture) and logical + * (VINTF aperture) views are hardware aliases; both are served from + * this single cached copy. + */ + uint32_t vcmdq_cons_indx[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_prod_indx[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_config[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_status[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_gerror[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_gerrorn[TEGRA241_CMDQV_MAX_CMDQ]; + uint64_t vcmdq_base[TEGRA241_CMDQV_MAX_CMDQ]; + uint64_t vcmdq_cons_indx_base[TEGRA241_CMDQV_MAX_CMDQ]; } Tegra241CMDQV; =20 /* CMDQ-V Config page registers (offset 0x00000) */ @@ -148,6 +168,202 @@ REG32(VINTF0_LVCMDQ_ERR_MAP_0, 0x10c0) FIELD(VINTF0_LVCMDQ_ERR_MAP_0, LVCMDQ_ERR_MAP, 0, 32) #define A_VINTF0_LVCMDQ_ERR_MAP_3 (A_VINTF0_LVCMDQ_ERR_MAP_0 + 3 * 4) =20 +/* + * Direct VCMDQ aperture register windows. + * + * Page 0 @ CMDQV_VCMDQ_PAGE0_BASE: VCMDQ control and status registers. + * Page 1 @ CMDQV_VCMDQ_PAGE1_BASE: VCMDQ base and DRAM address registers. + * + * Each VCMDQ occupies a CMDQV_VCMDQ_STRIDE-byte slot within its page. + */ + +/* --- Page 0 register macros --- */ +#define SMMU_CMDQV_VCMDQi_CONS_INDX_(i) \ + REG32(VCMDQ##i##_CONS_INDX, \ + CMDQV_VCMDQ_PAGE0_BASE + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_CONS_INDX, RD, 0, 20) \ + FIELD(VCMDQ##i##_CONS_INDX, ERR, 24, 7) + +#define V_VCMDQ_CONS_INDX_ERR_CERROR_NONE 0 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_OPCODE 1 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ABT 2 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ATC_INV_SYNC 3 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_ACCESS 4 + +#define SMMU_CMDQV_VCMDQi_PROD_INDX_(i) \ + REG32(VCMDQ##i##_PROD_INDX, \ + CMDQV_VCMDQ_PAGE0_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_PROD_INDX, WR, 0, 20) + +#define SMMU_CMDQV_VCMDQi_CONFIG_(i) \ + REG32(VCMDQ##i##_CONFIG, \ + CMDQV_VCMDQ_PAGE0_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) + +#define SMMU_CMDQV_VCMDQi_STATUS_(i) \ + REG32(VCMDQ##i##_STATUS, \ + CMDQV_VCMDQ_PAGE0_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) + +#define SMMU_CMDQV_VCMDQi_GERROR_(i) \ + REG32(VCMDQ##i##_GERROR, \ + CMDQV_VCMDQ_PAGE0_BASE + 0x10 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ + FIELD(VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) + +#define SMMU_CMDQV_VCMDQi_GERRORN_(i) \ + REG32(VCMDQ##i##_GERRORN, \ + CMDQV_VCMDQ_PAGE0_BASE + 0x14 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ + FIELD(VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) + +/* Page 0 layout: VCMDQ0 */ +SMMU_CMDQV_VCMDQi_CONS_INDX_(0) +SMMU_CMDQV_VCMDQi_PROD_INDX_(0) +SMMU_CMDQV_VCMDQi_CONFIG_(0) +SMMU_CMDQV_VCMDQi_STATUS_(0) +SMMU_CMDQV_VCMDQi_GERROR_(0) +SMMU_CMDQV_VCMDQi_GERRORN_(0) + +/* Page 0 layout: VCMDQ1 */ +SMMU_CMDQV_VCMDQi_CONS_INDX_(1) +SMMU_CMDQV_VCMDQi_PROD_INDX_(1) +SMMU_CMDQV_VCMDQi_CONFIG_(1) +SMMU_CMDQV_VCMDQi_STATUS_(1) +SMMU_CMDQV_VCMDQi_GERROR_(1) +SMMU_CMDQV_VCMDQi_GERRORN_(1) + +/* --- Page 1 register macros --- */ +#define SMMU_CMDQV_VCMDQi_BASE_L_(i) = \ + REG32(VCMDQ##i##_BASE_L, CMDQV_VCMDQ_PAGE1_BASE + i * CMDQV_VCMDQ_STRI= DE) \ + FIELD(VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) = \ + FIELD(VCMDQ##i##_BASE_L, ADDR, 5, 27) + +#define SMMU_CMDQV_VCMDQi_BASE_H_(i) \ + REG32(VCMDQ##i##_BASE_H, \ + CMDQV_VCMDQ_PAGE1_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_BASE_H, ADDR, 0, 16) + +#define SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(i) \ + REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, \ + CMDQV_VCMDQ_PAGE1_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) + +#define SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(i) \ + REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, \ + CMDQV_VCMDQ_PAGE1_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) + +/* Page 1 layout: VCMDQ0 */ +SMMU_CMDQV_VCMDQi_BASE_L_(0) +SMMU_CMDQV_VCMDQi_BASE_H_(0) +SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(0) +SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(0) + +/* Page 1 layout: VCMDQ1 */ +SMMU_CMDQV_VCMDQi_BASE_L_(1) +SMMU_CMDQV_VCMDQi_BASE_H_(1) +SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(1) +SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(1) + +/* + * VINTF0 logical VCMDQ aperture register windows. + * + * Page 0 @ CMDQV_VINTF_PAGE0_BASE: VCMDQ control and status registers. + * Page 1 @ CMDQV_VINTF_PAGE1_BASE: VCMDQ base and DRAM address registers. + * + * VCMDQs mapped via VINTF are accessed through this aperture as + * hardware aliases of the direct VCMDQ aperture above. + */ + +/* --- Page 0 register macros --- */ +#define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX, \ + CMDQV_VINTF_PAGE0_BASE + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_CONS_INDX, RD, 0, 20) \ + FIELD(VI_VCMDQ##i##_CONS_INDX, ERR, 24, 7) + +#define SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(i) \ + REG32(VI_VCMDQ##i##_PROD_INDX, \ + CMDQV_VINTF_PAGE0_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_PROD_INDX, WR, 0, 20) + +#define SMMU_CMDQV_VI_VCMDQi_CONFIG_(i) \ + REG32(VI_VCMDQ##i##_CONFIG, \ + CMDQV_VINTF_PAGE0_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) + +#define SMMU_CMDQV_VI_VCMDQi_STATUS_(i) \ + REG32(VI_VCMDQ##i##_STATUS, \ + CMDQV_VINTF_PAGE0_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) + +#define SMMU_CMDQV_VI_VCMDQi_GERROR_(i) \ + REG32(VI_VCMDQ##i##_GERROR, \ + CMDQV_VINTF_PAGE0_BASE + 0x10 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ + FIELD(VI_VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VI_VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) + +#define SMMU_CMDQV_VI_VCMDQi_GERRORN_(i) \ + REG32(VI_VCMDQ##i##_GERRORN, \ + CMDQV_VINTF_PAGE0_BASE + 0x14 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ + FIELD(VI_VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) + +/* Page 0 layout: VCMDQ0 */ +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(0) +SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(0) +SMMU_CMDQV_VI_VCMDQi_CONFIG_(0) +SMMU_CMDQV_VI_VCMDQi_STATUS_(0) +SMMU_CMDQV_VI_VCMDQi_GERROR_(0) +SMMU_CMDQV_VI_VCMDQi_GERRORN_(0) + +/* Page 0 layout: VCMDQ1 */ +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(1) +SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(1) +SMMU_CMDQV_VI_VCMDQi_CONFIG_(1) +SMMU_CMDQV_VI_VCMDQi_STATUS_(1) +SMMU_CMDQV_VI_VCMDQi_GERROR_(1) +SMMU_CMDQV_VI_VCMDQi_GERRORN_(1) + +/* --- Page 1 register macros --- */ +#define SMMU_CMDQV_VI_VCMDQi_BASE_L_(i) \ + REG32(VI_VCMDQ##i##_BASE_L, \ + CMDQV_VINTF_PAGE1_BASE + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \ + FIELD(VI_VCMDQ##i##_BASE_L, ADDR, 5, 27) + +#define SMMU_CMDQV_VI_VCMDQi_BASE_H_(i) \ + REG32(VI_VCMDQ##i##_BASE_H, \ + CMDQV_VINTF_PAGE1_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_BASE_H, ADDR, 0, 16) + +#define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, \ + CMDQV_VINTF_PAGE1_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) + +#define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, \ + CMDQV_VINTF_PAGE1_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) + +/* Page 1 layout: VCMDQ0 */ +SMMU_CMDQV_VI_VCMDQi_BASE_L_(0) +SMMU_CMDQV_VI_VCMDQi_BASE_H_(0) +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(0) +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(0) + +/* Page 1 layout: VCMDQ1 */ +SMMU_CMDQV_VI_VCMDQi_BASE_L_(1) +SMMU_CMDQV_VI_VCMDQi_BASE_H_(1) +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(1) +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(1) + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 8c61d66a26..5156604228 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -75,6 +75,8 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS # tegra241-cmdqv tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" +tegra241_cmdqv_read_vcmdq_page0(int index, const char *aperture, uint64_t = offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 +tegra241_cmdqv_read_vcmdq_page1(int index, const char *aperture, uint64_t = offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637365; cv=none; d=zohomail.com; s=zohoarc; b=Qab5/rOkS49smZ31o95fCQ9379rqqKrDh5BQowy2L0B7qbdbSFsF3zHiMXn/cTXnZeuoz03HwaL76eo0O9M1StELncO9D3ss60CwJqYTFgcoOPhkZZvZA0mROBPXmSSPO3iLDr7tp8lOzj0w4SvwFoBFKjCgBqO6icZRFaw99DE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637365; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=y0U9XSoqZ7NscbSwIzDuis0V8cuLT6uo3vwbdLjQW14=; b=EEE7GuLSa1YnjqTKKKkWVVfuOuiEACnSVQnn1LorXbbzdGVsT0fbpZCPJs+nz0EbkcpCk7Xbjhx99TUpvilkHt+krAs6EYWDsHYVIC2leJFGaCxk5HTgy4R8d8PfjFFwKsfnRsxdeJ0CZS4U/l9y86ois8RBqIxLhiZ0WE4sgBI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637365353497.30688005858997; Tue, 16 Jun 2026 12:16:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZBg-0001HM-U6; Tue, 16 Jun 2026 15:11:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8S-0004iC-Mf for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8M-00010U-C3 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:43 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-490cf3000f0so49704245e9.1 for ; Tue, 16 Jun 2026 12:07:14 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636833; x=1782241633; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=y0U9XSoqZ7NscbSwIzDuis0V8cuLT6uo3vwbdLjQW14=; b=bACIDaHvjXhlUUu77RvNDnTw8hQ/XaiTbFLrlN/3KZTHN1jTYjQakFLNSeJgTisV5/ 1f7zCePfsGDwlnnyDR5opSYISpfhxGhF9YCbB/F01yMaHVa7ibYWhWo0gwV3SEobfj8J w2e7su69ZSeHVNx4vTQZRs5bSubmzO907WwefCVeLY/bXVVSmchkTTggyRjbjd3f15I7 qFCj+CT7HtkJnuHJuPD32RTMuOxOFYfqmJSlK8ripifn94dcULWC9ZrYv0LhpG2A8UZp 8XNGuBhc9wfUEJ7rBM1fvP9e29mSgy7xL0v7h9ra65ywJ5WnscsLVJKXpR85ULRT5gfn arIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636833; x=1782241633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=y0U9XSoqZ7NscbSwIzDuis0V8cuLT6uo3vwbdLjQW14=; b=kDVJiampqovLT//2ZF0PTsYBBbpeVD8qoS0Hp796Ar+Z9XgkpGPIBKL1AMz4DUCr02 earSlH+HcTB/i2MZCwcpSugpm6hRB/QCIbdpB5knNUUjT8wVmyoKYiGyKaQeI3wAxG7G jH1swuvdms7nL4OzL27k0VlGpQ0GMB1yvI0EIgY49kxP02DEy885yAEoyHIcQ8jrNlHu UspEaDgNAHxZulbHRpUyGFRRCCkBFeqHoj5ljzm0cLnAdFGfatmneI0+Cjvx0zSdA0lz 49orz4nLyh5fQobWAJu9GLiu3U2NbcSUiZrLiePt5k4HIxSGRwoSVkAlFBGKeDxvYfVn jO1Q== X-Gm-Message-State: AOJu0YwLPOzcidMQIvj5OKnCYtgYIjoMGvXsLYRuh2rYoEFYzZ1niBzO wB6deqKU9ot8Fw0VcvcuGw6dV5VWs1gK8nDOsleb5NnlUdE7Au7++TD5aH59Rh9H/RJdGwuP188 TE7R4 X-Gm-Gg: Acq92OHNw485FPRmztaCrFu2LLLaB6rIIXi2pWZ6PrNTeYKIQxByUY5UCo4AdIZz+k+ VjEz3XKB4nn2dZ1ofwghlyObvpKfNoBTi4xgaYhqSavsDOFYIUJGy9jvluYV+cpvgN+qDDeX7pz UcTj7vpqtSTvltYwG/p6nILzfnhbKNqpKYW5amXLiSzfCCXW9rS6i3vlYxQKX3eb0MWqEjc+vS+ 3SGPWYiYcI4BxNvsZbv+n4V4+tylIheqLeMjcObCm9amTc2oatXJxJnGN+X3KrXxwdZNimhKjbu h14CPiCc7J2j+oK/UOGwMbH8AY9RnLYiC5ilCvk2ILIjivlsClbRq+ohpDanEJTl4kdDy8ss90l osde/lYG/vtIwB3QK5pQHb4GDLfF7sLxTugX8bmYmgENkJTEwIzSGw2kSVaCQ9XZn1/jOuBY2+O 6jjh5f95nJgS3JNtr3Rbp+RFbg6SKq/4u5F/uG8z+fKYxleEKMgZOMl1r8lZWOul1EEFsrF5qpG XA40iVxRTVNtIJ/65ja5CSnEC2OC8+c X-Received: by 2002:a05:600c:8184:b0:490:625e:bb68 with SMTP id 5b1f17b1804b1-4923339f885mr15021255e9.3.1781636832885; Tue, 16 Jun 2026 12:07:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/61] hw/arm/tegra241-cmdqv: Emulate VCMDQ register writes Date: Tue, 16 Jun 2026 20:06:04 +0100 Message-ID: <20260616190639.3462006-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637365862158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen This is the write side counterpart of the VCMDQ read emulation. Add write handling for both the direct VCMDQ aperture and the VINTF logical aperture using the same index decoding and VINTF-to-VCMDQ translation logic as the read path. VINTF aperture writes are translated to their direct-aperture equivalent and update the same cached state. Page 1 registers (BASE, CONS_INDX_BASE) always update the cache. Per the CMDQV architecture, a VCMDQ must be allocated to a Virtual Interface before it is used to send commands to the SMMU. Until that allocation happens, MMIO writes only update cached register state - no command consumption, error handling, or interrupt activity is driven from these writes. Subsequent patches wire up IOMMU_HW_QUEUE_ALLOC, mmap the host VINTF Page 0, and install it into guest MMIO; after that, Page 0 writes from either aperture reach the hardware-backed mmap'd page instead of just the cache. Signed-off-by: Nicolin Chen Tested-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260609112552.378999-18-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 159 +++++++++++++++++++++++++++++++++++++++- hw/arm/trace-events | 2 + 2 files changed, 159 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 2dfd377ee9..1f3d883cfe 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -120,6 +120,104 @@ static uint64_t tegra241_cmdqv_config_vintf_read(Tegr= a241CMDQV *cmdqv, } } =20 +/* + * Write a VCMDQ Page 0 register (control/status) using VCMDQ0_* offsets. + * + * The caller normalizes the MMIO offset such that @offset0 always refers + * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + * + * Page 0 registers are all 32-bit; this helper is only called for 4-byte + * writes. + */ +static void tegra241_cmdqv_write_vcmdq_page0(Tegra241CMDQV *cmdqv, + hwaddr offset0, int index, + uint32_t value, bool direct) +{ + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + cmdqv->vcmdq_cons_indx[index] =3D value; + break; + case A_VCMDQ0_PROD_INDX: + /* VCMDQ is functional only once allocated to a VINTF; cache only.= */ + cmdqv->vcmdq_prod_indx[index] =3D value; + break; + case A_VCMDQ0_CONFIG: + if (value & R_VCMDQ0_CONFIG_CMDQ_EN_MASK) { + cmdqv->vcmdq_status[index] |=3D R_VCMDQ0_STATUS_CMDQ_EN_OK_MAS= K; + } else { + cmdqv->vcmdq_status[index] &=3D ~R_VCMDQ0_STATUS_CMDQ_EN_OK_MA= SK; + } + cmdqv->vcmdq_config[index] =3D value; + break; + case A_VCMDQ0_GERRORN: + /* VCMDQ is functional only once allocated to a VINTF; cache only.= */ + cmdqv->vcmdq_gerrorn[index] =3D value; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled write access at 0x%" PRIx64 "\n", + __func__, offset0); + } + trace_tegra241_cmdqv_write_vcmdq_page0(index, direct ? "direct" : "vi", + offset0, value); +} + +/* + * Write a VCMDQ Page 1 register (base / DRAM address) - 4-byte access. + */ +static void tegra241_cmdqv_write_vcmdq_page1(Tegra241CMDQV *cmdqv, + hwaddr offset0, int index, + uint32_t value, bool direct) +{ + switch (offset0) { + case A_VCMDQ0_BASE_L: + cmdqv->vcmdq_base[index] =3D + deposit64(cmdqv->vcmdq_base[index], 0, 32, value); + break; + case A_VCMDQ0_BASE_H: + cmdqv->vcmdq_base[index] =3D + deposit64(cmdqv->vcmdq_base[index], 32, 32, value); + break; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + cmdqv->vcmdq_cons_indx_base[index] =3D + deposit64(cmdqv->vcmdq_cons_indx_base[index], 0, 32, value); + break; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_H: + cmdqv->vcmdq_cons_indx_base[index] =3D + deposit64(cmdqv->vcmdq_cons_indx_base[index], 32, 32, value); + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled write access at 0x%" PRIx64 "\n", + __func__, offset0); + } + trace_tegra241_cmdqv_write_vcmdq_page1(index, direct ? "direct" : "vi", + offset0, value); +} + +/* + * Write a VCMDQ Page 1 register - 8-byte access at BASE_L or DRAM_L. + */ +static void tegra241_cmdqv_write_vcmdq_page1_64(Tegra241CMDQV *cmdqv, + hwaddr offset0, int index, + uint64_t value, bool direc= t) +{ + switch (offset0) { + case A_VCMDQ0_BASE_L: + cmdqv->vcmdq_base[index] =3D value; + break; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + cmdqv->vcmdq_cons_indx_base[index] =3D value; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled 64-bit write at 0x%" PRIx64 "\n", + __func__, offset0); + } + trace_tegra241_cmdqv_write_vcmdq_page1(index, direct ? "direct" : "vi", + offset0, value); +} + static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv, hwaddr offset, uint64_t valu= e) { @@ -243,6 +341,8 @@ out: static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *cmdqv, hwaddr offset, uint32_t value) { + int index; + switch (offset) { case A_CONFIG: cmdqv->config =3D value; @@ -261,6 +361,39 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *= cmdqv, hwaddr offset, case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: tegra241_cmdqv_config_vintf_write(cmdqv, offset, value); break; + case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: + /* + * VINTF Page0 registers are hardware aliases of VCMDQ Page0 regis= ters. + * Translate the VINTF aperture offset to its VCMDQ Page0 equivale= nt + * before dispatching to the Page 0 helper. + */ + offset -=3D CMDQV_VINTF_PAGE0_BASE - CMDQV_VCMDQ_PAGE0_BASE; + index =3D (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE; + tegra241_cmdqv_write_vcmdq_page0(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, value, false); + break; + case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN: + /* + * Decode a per-VCMDQ Page 0 access. Each VCMDQ occupies a + * CMDQV_VCMDQ_STRIDE-byte window; extract the index and normalize + * to the VCMDQ0_* offset before calling the Page 0 helper. + */ + index =3D (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE; + tegra241_cmdqv_write_vcmdq_page0(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, value, true); + break; + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above. */ + offset -=3D CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE; + index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; + tegra241_cmdqv_write_vcmdq_page1(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, value, false); + break; + case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: + index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; + tegra241_cmdqv_write_vcmdq_page1(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, value, true); + break; default: qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", __func__, offset); @@ -268,14 +401,36 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV = *cmdqv, hwaddr offset, } =20 /* - * 8-byte MMIO write handler. + * 8-byte MMIO write handler. Only Page 1 BASE / CONS_INDX_BASE_DRAM accept + * full 64-bit writes; other offsets are write-ignored. */ static void tegra241_cmdqv_writell_mmio(Tegra241CMDQV *cmdqv, hwaddr offse= t, uint64_t value) { - qemu_log_mask(LOG_UNIMP, + int index; + + switch (offset) { + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* + * VINTF Page1 registers are hardware aliases of VCMDQ Page1 regis= ters. + * Translate the VINTF aperture offset to its VCMDQ Page1 equivale= nt + * before dispatching to the Page 1 helper. + */ + offset -=3D CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE; + index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; + tegra241_cmdqv_write_vcmdq_page1_64(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, value, false); + break; + case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: + index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; + tegra241_cmdqv_write_vcmdq_page1_64(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, value, true); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled 64-bit write at 0x%" PRIx64 " (WI)\n", __func__, offset); + } } =20 static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 5156604228..666967dc5e 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -77,6 +77,8 @@ tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, u= nsigned size) "offset: tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_read_vcmdq_page0(int index, const char *aperture, uint64_t = offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_read_vcmdq_page1(int index, const char *aperture, uint64_t = offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 +tegra241_cmdqv_write_vcmdq_page0(int index, const char *aperture, uint64_t= offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 +tegra241_cmdqv_write_vcmdq_page1(int index, const char *aperture, uint64_t= offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637316; cv=none; d=zohomail.com; s=zohoarc; b=CeW5BUEzGEOa9cw1XyhaCo3EBWpgFhoxhkrV513cpOaASNzSZ6nw2qFrw8GL1+562jYc63dfwoGoUJCnDTNjXuM9jmP7rmdfocVOxcP63NRLKqeSse42RNdjNz46cnqLLfTYE0KJYgYmcIbofjnFF5gvpGC1sX7wfRzvsb24QSc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637316; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=m4Z8534aNzEYzyGhBE2zpgXQN+xhbZIG8IL744vqSUI=; b=JRqiZ7WhFoKkXQkTfWHJt8FZY3jQ6bN1rZX+3AQ7InNlmJlN9CNMKrqTHseTrzxFwV+to7Fzex73SaIk7bMtQ8akRjOW4Pd0rVj7oDAMIvvIamPq2+Ojem3grOd/dtGo4BB8DBJ+PF5Lm3Zah120YQ43SuKFEHGyoFaoi9lIC+U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637316799255.7465175539877; Tue, 16 Jun 2026 12:15:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAW-0007Es-Rc; Tue, 16 Jun 2026 15:09:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZS-Mh for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ87-00010o-Oi for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:27 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-461a15bb819so939187f8f.3 for ; Tue, 16 Jun 2026 12:07:15 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636834; x=1782241634; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=m4Z8534aNzEYzyGhBE2zpgXQN+xhbZIG8IL744vqSUI=; b=MVIBgNHNMsrkpgDUHmEOjcbspbzKIxm6l1YZEjIWSayqzSAWu+IH8PVvA5VPXVPT31 hqpfGYNWT7lXQO6H464Dcbpb6EQUnAFLtJwgTxtcf6FrfL4U+9DRDLfshp/M2LROT3+F Lf+Z4hperJEZKrAureQhytb1nrddKTWn4+mc9vGHJMGxNT+IL1TCfLyeYFdzuGM826Ej fOy0yP8KR8qX/aTIzIrSwQ6xFmR9Ps6h6kXaCfpXwwZ/RshfsHl44NLrjSCh6KcKIs9O l3JykZML5bMVTq4imowJ3g9xDW+mdjCQZa53VgjAzCFA2d7e4FVHfqGFEaggic+5aO5N uJhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636834; x=1782241634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=m4Z8534aNzEYzyGhBE2zpgXQN+xhbZIG8IL744vqSUI=; b=gGhXsxKhoKQB9BaLQCn79SzMze/mMqU2D1kwrMYYwqXjlrbI+9Wo7706/YRNuk8I9B /ndS5GTDFsyqO85+BoW8xYg619N5TIDs+n/67ljF0IAr/EZx3fuNZBCAm953WbiMZJ5C qAqQeivNv5qFEbVIRLgpKW2tviMlI/X4lLLFGQC/yebEFFOXkSLusPW08OM3OgU5QihK bJMAjxoRtcNHkFd+rsRsg9owe4K7pnMsT8uzoflJLIBuSXPRWLvJ0Eh4JrN+kYNgEQG9 sW/+NTv7CBWXaNkZHsJtRU+WIAwghkhAA12hdypPJq6iRBOMLJb1SiyLcE1ioaKamjF+ Fq8Q== X-Gm-Message-State: AOJu0YyMVOZWTk+gpjidecAB9M7M2hQpYwQSF2fms0BQGe8oMDoN1kJv sWGFUnTMG4XxKuhAaVY1cnN054fFRxUtJKbjZ77v84gVe+uA58JvFhcKHrRONMbW/QworCa84vl /rId4 X-Gm-Gg: Acq92OHrYqrtk2BsEDx9jo1eYO8StmTHHi/SkZyM3A6pU9hroCKz4W9ERCIw1BGtBCG P20B8hRkWdejL5vq6J2tjVbGU7+NalVtCqoEoZYvEGzDqXRZo2lP4Wqp6Ayu4Y1LuhEo/Idl2Gg gPrneV4jap78aYcd5sSLUlrAn8uxX5kA7SWJxpWyWbhKNozDYY6NQVPUuPsD7PYNjbWbpNdqFGF bcjDw9fsqWIGvqdz3NMabAu+JuPnn5NjJJUPOIHGvlcrkon93iGRIHmNvBt0Puzzylz2/K625ds V7dDbQ8u4Vx321pWQRrhlAwNZEWP2GVoFKlSOiwv7iEQ9ie4cAhoh/gfAV5IbigUASR8isOI41w XOFWPdJuTsrxtcyf7FaK6zSlily/d1DuaXxEL1EpYvK7lJ6PYHptz1gCJtfwAW1BaHlSnwVTHFV iazYOumgfEtHbN2N6Mz0SFohKeVHH+g2odrvXs4xzdVZgvkLyi6bumXYajDNAN56kwS7c2JkjSr rbhee3t56KfVlxBUL3s19b5f/n7epA+ X-Received: by 2002:a05:6000:22c4:b0:45e:fb69:f02b with SMTP id ffacd0b85a97d-4623f2e7641mr941982f8f.1.1781636833814; Tue, 16 Jun 2026 12:07:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/61] hw/arm/tegra241-cmdqv: Allocate HW VCMDQs once configured Date: Tue, 16 Jun 2026 20:06:05 +0100 Message-ID: <20260616190639.3462006-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637317599158500 From: Nicolin Chen Add support for allocating IOMMUFD hardware queues when the guest programs the VCMDQ BASE registers. VCMDQ_EN lives in VCMDQ_CONFIG, which is on the VINTF Page0 region that a later patch installs into guest MMIO =E2=80=94 so QEMU won't trap its writes. Allocate the hardware queue instead once all of these are set: BASE programmed, CMDQ_ALLOC_MAP.ALLOC, and CMDQV / VINTF enabled. Each precondition write retries the allocation, so the guest may program them in any order. iommufd_backend_alloc_hw_queue() needs the guest physical address of the VCMDQ ring buffer, so allocation is deferred until the guest has populated BASE. If a hardware queue was previously allocated for the same VCMDQ, free it before reallocation. All allocated VCMDQs are freed when CMDQV or VINTF is disabled, when the ALLOC bit is cleared, or on reset. On allocation failure, set CMDQ_INIT_ERR and clear CMDQ_EN_OK in the cache so trapped guest reads see the failure rather than a queue that looks live. Clear them on a later successful allocation. A guest CMDQ_EN write then sets CMDQ_EN_OK only if CMDQ_INIT_ERR is clear. Signed-off-by: Nicolin Chen Tested-by: Nicolin Chen Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Message-id: 20260609112552.378999-19-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 171 +++++++++++++++++++++++++++++++++++++--- hw/arm/tegra241-cmdqv.h | 11 +++ 2 files changed, 171 insertions(+), 11 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 1f3d883cfe..8cb39e87c4 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -16,6 +16,96 @@ #include "tegra241-cmdqv.h" #include "trace.h" =20 +static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index) +{ + IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; + IOMMUFDHWqueue *vcmdq =3D cmdqv->vcmdq[index]; + + if (!vcmdq) { + return; + } + iommufd_backend_free_id(viommu->iommufd, vcmdq->hw_queue_id); + g_free(vcmdq); + cmdqv->vcmdq[index] =3D NULL; +} + +/* + * A VCMDQ's HW queue can be allocated once the guest has programmed: + * - VCMDQ_BASE (ring buffer GPA and size). This only checks that BASE is + * non-zero, not that both the _L and _H halves have been written; a + * half-written BASE may pass here, but the write of the second half + * re-runs setup and reallocates with the complete address. + * - the VINTF mapping (CMDQ_ALLOC_MAP.ALLOC). + * - both the CMDQV global enable and the VINTF enable. + */ +static bool tegra241_cmdqv_vcmdq_ready_to_alloc(Tegra241CMDQV *cmdqv, int = index) +{ + return cmdqv->vcmdq_base[index] && + (cmdqv->cmdq_alloc_map[index] & R_CMDQ_ALLOC_MAP_0_ALLOC_MASK) = && + tegra241_cmdqv_enabled(cmdqv) && tegra241_vintf_enabled(cmdqv); +} + +/* + * Allocate a host HW VCMDQ from the current cached BASE / size for @index. + * No-op (returns true) until the VCMDQ is ready to be allocated. + */ +static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index, + Error **errp) +{ + SMMUv3AccelState *accel =3D cmdqv->s_accel; + uint64_t base_mask =3D (uint64_t)R_VCMDQ0_BASE_L_ADDR_MASK | + (uint64_t)R_VCMDQ0_BASE_H_ADDR_MASK << 32; + uint64_t addr =3D cmdqv->vcmdq_base[index] & base_mask; + uint64_t log2 =3D cmdqv->vcmdq_base[index] & R_VCMDQ0_BASE_L_LOG2SIZE_= MASK; + uint64_t size =3D 1ULL << (log2 + 4); + IOMMUFDViommu *viommu =3D accel->viommu; + IOMMUFDHWqueue *hw_queue; + uint32_t hw_queue_id; + + if (!tegra241_cmdqv_vcmdq_ready_to_alloc(cmdqv, index)) { + return true; + } + + tegra241_cmdqv_free_vcmdq(cmdqv, index); + + if (!iommufd_backend_alloc_hw_queue(viommu->iommufd, viommu->viommu_id, + IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV, + index, addr, size, &hw_queue_id, + errp)) { + /* Record the failure in the cache. */ + cmdqv->vcmdq_gerror[index] |=3D R_VCMDQ0_GERROR_CMDQ_INIT_ERR_MASK; + cmdqv->vcmdq_status[index] &=3D ~R_VCMDQ0_STATUS_CMDQ_EN_OK_MASK; + return false; + } + hw_queue =3D g_new(IOMMUFDHWqueue, 1); + hw_queue->hw_queue_id =3D hw_queue_id; + hw_queue->viommu =3D viommu; + cmdqv->vcmdq[index] =3D hw_queue; + + cmdqv->vcmdq_gerror[index] &=3D ~R_VCMDQ0_GERROR_CMDQ_INIT_ERR_MASK; + cmdqv->vcmdq_status[index] |=3D R_VCMDQ0_STATUS_CMDQ_EN_OK_MASK; + + return true; +} + +static void tegra241_cmdqv_free_all_vcmdq(Tegra241CMDQV *cmdqv) +{ + /* uapi/linux/iommufd.h: hw_queue destroy must be in descending @index= . */ + for (int i =3D (TEGRA241_CMDQV_MAX_CMDQ - 1); i >=3D 0; i--) { + tegra241_cmdqv_free_vcmdq(cmdqv, i); + } +} + +static void tegra241_cmdqv_setup_all_vcmdq(Tegra241CMDQV *cmdqv, + Error **errp) +{ + for (int i =3D 0; i < TEGRA241_CMDQV_MAX_CMDQ; i++) { + if (!tegra241_cmdqv_setup_vcmdq(cmdqv, i, errp)) { + return; + } + } +} + /* * Read a VCMDQ Page 0 register (control/status) using VCMDQ0_* offsets. * @@ -143,7 +233,12 @@ static void tegra241_cmdqv_write_vcmdq_page0(Tegra241C= MDQV *cmdqv, break; case A_VCMDQ0_CONFIG: if (value & R_VCMDQ0_CONFIG_CMDQ_EN_MASK) { - cmdqv->vcmdq_status[index] |=3D R_VCMDQ0_STATUS_CMDQ_EN_OK_MAS= K; + /* Report init error if any. */ + if (!(cmdqv->vcmdq_gerror[index] & + R_VCMDQ0_GERROR_CMDQ_INIT_ERR_MASK)) { + cmdqv->vcmdq_status[index] |=3D + R_VCMDQ0_STATUS_CMDQ_EN_OK_MASK; + } } else { cmdqv->vcmdq_status[index] &=3D ~R_VCMDQ0_STATUS_CMDQ_EN_OK_MA= SK; } @@ -167,16 +262,19 @@ static void tegra241_cmdqv_write_vcmdq_page0(Tegra241= CMDQV *cmdqv, */ static void tegra241_cmdqv_write_vcmdq_page1(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, - uint32_t value, bool direct) + uint32_t value, bool direct, + Error **errp) { switch (offset0) { case A_VCMDQ0_BASE_L: cmdqv->vcmdq_base[index] =3D deposit64(cmdqv->vcmdq_base[index], 0, 32, value); + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); break; case A_VCMDQ0_BASE_H: cmdqv->vcmdq_base[index] =3D deposit64(cmdqv->vcmdq_base[index], 32, 32, value); + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); break; case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: cmdqv->vcmdq_cons_indx_base[index] =3D @@ -200,11 +298,13 @@ static void tegra241_cmdqv_write_vcmdq_page1(Tegra241= CMDQV *cmdqv, */ static void tegra241_cmdqv_write_vcmdq_page1_64(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, - uint64_t value, bool direc= t) + uint64_t value, bool direc= t, + Error **errp) { switch (offset0) { case A_VCMDQ0_BASE_L: cmdqv->vcmdq_base[index] =3D value; + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); break; case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: cmdqv->vcmdq_cons_indx_base[index] =3D value; @@ -219,7 +319,8 @@ static void tegra241_cmdqv_write_vcmdq_page1_64(Tegra24= 1CMDQV *cmdqv, } =20 static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv, - hwaddr offset, uint64_t valu= e) + hwaddr offset, uint64_t valu= e, + Error **errp) { int i; =20 @@ -235,7 +336,13 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241= CMDQV *cmdqv, cmdqv->vintf_config =3D value; if (value & R_VINTF0_CONFIG_ENABLE_MASK) { cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + /* + * VCMDQs whose BASE was programmed before VINTF was + * enabled need their hw_queue allocated now. + */ + tegra241_cmdqv_setup_all_vcmdq(cmdqv, errp); } else { + tegra241_cmdqv_free_all_vcmdq(cmdqv); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; } break; @@ -341,6 +448,7 @@ out: static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *cmdqv, hwaddr offset, uint32_t value) { + Error *local_err =3D NULL; int index; =20 switch (offset) { @@ -348,18 +456,39 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV = *cmdqv, hwaddr offset, cmdqv->config =3D value; if (value & R_CONFIG_CMDQV_EN_MASK) { cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; + /* + * VCMDQs whose BASE was programmed before CMDQV was enabled + * need their hw_queue allocated now. + */ + tegra241_cmdqv_setup_all_vcmdq(cmdqv, &local_err); } else { + tegra241_cmdqv_free_all_vcmdq(cmdqv); cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; } break; case A_VI_INT_MASK_0 ... A_VI_INT_MASK_1: cmdqv->vi_int_mask[(offset - A_VI_INT_MASK_0) / 4] =3D value; break; - case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: - cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] =3D value; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: { + int idx =3D (offset - A_CMDQ_ALLOC_MAP_0) / 4; + bool was_alloc =3D cmdqv->cmdq_alloc_map[idx] & + R_CMDQ_ALLOC_MAP_0_ALLOC_MASK; + bool now_alloc =3D value & R_CMDQ_ALLOC_MAP_0_ALLOC_MASK; + + cmdqv->cmdq_alloc_map[idx] =3D value; + /* + * If the VCMDQ was already programmed (BASE) before mapping, fire + * setup on the ALLOC 0->1 transition; tear down on 1->0. + */ + if (!was_alloc && now_alloc) { + tegra241_cmdqv_setup_vcmdq(cmdqv, idx, &local_err); + } else if (was_alloc && !now_alloc) { + tegra241_cmdqv_free_vcmdq(cmdqv, idx); + } break; + } case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: - tegra241_cmdqv_config_vintf_write(cmdqv, offset, value); + tegra241_cmdqv_config_vintf_write(cmdqv, offset, value, &local_err= ); break; case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: /* @@ -387,17 +516,23 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV = *cmdqv, hwaddr offset, offset -=3D CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE; index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; tegra241_cmdqv_write_vcmdq_page1(cmdqv, - offset - index * CMDQV_VCMDQ_STRIDE, index, value, false); + offset - index * CMDQV_VCMDQ_STRIDE, index, value, false, + &local_err); break; case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; tegra241_cmdqv_write_vcmdq_page1(cmdqv, - offset - index * CMDQV_VCMDQ_STRIDE, index, value, true); + offset - index * CMDQV_VCMDQ_STRIDE, index, value, true, + &local_err); break; default: qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", __func__, offset); } + + if (local_err) { + error_report_err(local_err); + } } =20 /* @@ -407,6 +542,7 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *c= mdqv, hwaddr offset, static void tegra241_cmdqv_writell_mmio(Tegra241CMDQV *cmdqv, hwaddr offse= t, uint64_t value) { + Error *local_err =3D NULL; int index; =20 switch (offset) { @@ -419,18 +555,24 @@ static void tegra241_cmdqv_writell_mmio(Tegra241CMDQV= *cmdqv, hwaddr offset, offset -=3D CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE; index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; tegra241_cmdqv_write_vcmdq_page1_64(cmdqv, - offset - index * CMDQV_VCMDQ_STRIDE, index, value, false); + offset - index * CMDQV_VCMDQ_STRIDE, index, value, false, + &local_err); break; case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; tegra241_cmdqv_write_vcmdq_page1_64(cmdqv, - offset - index * CMDQV_VCMDQ_STRIDE, index, value, true); + offset - index * CMDQV_VCMDQ_STRIDE, index, value, true, + &local_err); break; default: qemu_log_mask(LOG_UNIMP, "%s unhandled 64-bit write at 0x%" PRIx64 " (WI)\n", __func__, offset); } + + if (local_err) { + error_report_err(local_err); + } } =20 static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, @@ -535,6 +677,13 @@ free_viommu: =20 static void tegra241_cmdqv_reset(SMMUv3State *s) { + Tegra241CMDQV *cmdqv =3D s->s_accel->cmdqv; + + if (!cmdqv) { + return; + } + + tegra241_cmdqv_free_all_vcmdq(cmdqv); } =20 static const MemoryRegionOps mmio_cmdqv_ops =3D { diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index c4d327a9a5..84499b840d 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -47,6 +47,7 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; IOMMUFDVeventq *veventq; + IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ]; void *vintf_page0; =20 /* CMDQ-V Config page register cache */ @@ -364,6 +365,16 @@ SMMU_CMDQV_VI_VCMDQi_BASE_H_(1) SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(1) SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(1) =20 +static inline bool tegra241_cmdqv_enabled(Tegra241CMDQV *cmdqv) +{ + return cmdqv->status & R_STATUS_CMDQV_ENABLED_MASK; +} + +static inline bool tegra241_vintf_enabled(Tegra241CMDQV *cmdqv) +{ + return cmdqv->vintf_status & R_VINTF0_STATUS_ENABLE_OK_MASK; +} + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781636925; cv=none; d=zohomail.com; s=zohoarc; b=khYYg4JNHm15PBnPeltlIMVBYh9xe1cpm1E/UACVD3qQR1+/BotemhTGkBxf1jEocW+1l5C5UXLCVY45zMDfjNDQQNzT4PRiLDAyICXacnaBgyU04iGjX+uweTGk9li0wSMJJMLuNT/FXsuS6aLHwKYE3QS7pTp8/BlAjzrrTkA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781636925; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=t/Eu9EnnFiSkjhm7/fYfR3ltbAVADI4vo+xpn1ePMDs=; b=H/HuzZp+Yuntf4KW+KwVgFAGY1rI381Qtazc/oumch4MGPodRgSfS/GLEAfUBYz6mN7o5Dv5tzWO1HLAKYoMJF+9IN6XqR2+qleWp3cdlTgJnbmmwr8p4dxdObkiathQpJGMt5sQ6CDdJ2J5vZrRjwBo5HrxOg/UAQPrW9eiDMM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781636925493924.5645796277844; Tue, 16 Jun 2026 12:08:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZ9J-0005L2-NX; Tue, 16 Jun 2026 15:08:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZO-KR for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ87-00010z-Pk for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:27 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-45f3cf907ceso2636686f8f.2 for ; Tue, 16 Jun 2026 12:07:15 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636835; x=1782241635; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=t/Eu9EnnFiSkjhm7/fYfR3ltbAVADI4vo+xpn1ePMDs=; b=oPiQ/H1AX1xNfXN8YQcAOtQb9Sqi2Wl9b5PWuK9y4ut5otSz3GR5syydtBUt21Jc+v PVIBAMLS4J9Ky1Y3Vi0QdDVblQcIlW0gKygBZ3x+npdmWaYYyzoVkO4c+FKpIEgV3DmW xBSu2r6kC2a7J9vzhIE1lt/HsKr8Ed3uj3o81Vt6DOjbLeUq/8RtrHjkw6+aASuqdXI6 PDgcQK3CNiSlh80hde/j6gMP1ej+2dO+YKIWzQQB4VZz2dPtljrHOByAOC0oGMCqXG4m 81YDGvpumhStfVj86IOkjOvOvV2ulfacPUW7XLRQ81j0a/bg43sgyY6Oc/xMhrtN4AEO J8Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636835; x=1782241635; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=t/Eu9EnnFiSkjhm7/fYfR3ltbAVADI4vo+xpn1ePMDs=; b=sVibGlYBs84EScf73GBMJp380Mf8sC/z1zRObrh4qcyBgbEeVFNqlr8VUq2ULwLCVR DzeFyaZPJKU8Gp5GNDZ1JcXnxpJOyH+Bh+HnTJ1WBbO21I+CPSRZPD8/wZxnmpciPA/M V2wX7kRAytGN8/V9Rlp4W6QP47g7fMDIe/FgjJhaUXWwSWg1tO3BHUS+N0eXlIy8UE0j qywVuOycdWDG9TMb/LoD2gXqD/VINWrQqb/MnZZ0L3npAt5HjqcR6lwlzxI7IgM7kBLV +eHSFm/QiGPulquqcxjA4D4/Kcpqijpwj6mhmom80IwUX9kwWkxCgcBsCPJ9BkrI35WD 5uKQ== X-Gm-Message-State: AOJu0YyL7UWFBYEYtKDXMKUtoN3l6MF4B8oeQDfWryiEnofmBNZn5wt/ sCjHNz5SSIDXiXQhvSvnNuLZ33an8KrEgv71aVRbRDd0qeNunvBPIa1CPpauf5lwkF7W/9Z5P9E 0fOci X-Gm-Gg: Acq92OHVX1HmLlVtn2lCaVCwpajiIgyM2QgU9XH1LUzrK1dLZaconJxbxusRB/SrXK3 xXbu/pdXUF4Z+qlzUdrGbREJwnlJn/LO3pcBDwvpL9zsnVky4tZM5XUwlAv/oyDglJmuZjm/7RH DBmTP1vkV4FkEr0al3Y9qZno+yrawzaOpVFK0lzpJ61xLICUbz/URQvoMm/DBDzwciMuHSWvy1n yWGc1k65qt640bDCKX0WuuArPnX68PKvtWObo0npu8gprrXMwfXqQ+9hw86pLVz/+Mh5SgQVI/M 6meo5fDFDEPwkCQNvig8pVy8MEaEQwWrV5YFAiM1ALB9HSmP+g2oJzyE/PygqyEK7j9YUn1zbii ToJgkMeUs0QyTqM7Jcw9LchMXL+NSFqvRmrYBRp5UxyzTnB4eigoU0UYqYi3hjPQvnQrM0amFQI eVibMFPm6zXFloMiVIfY4fK7wvd90tloN1/yMG2ncLUUkjmWOBKxFFcgTppbGi3ru6Lm0EQi6o4 Sn5UAgWtGDSTMAMf3UBEZmB+pEEtr/q X-Received: by 2002:a05:6000:a8d:b0:461:a16c:d88d with SMTP id ffacd0b85a97d-46237d5b74amr893724f8f.26.1781636834844; Tue, 16 Jun 2026 12:07:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/61] hw/arm/tegra241-cmdqv: Route allocated VCMDQ Page0 accesses to the mmap'd host VINTF page0 Date: Tue, 16 Jun 2026 20:06:06 +0100 Message-ID: <20260616190639.3462006-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781636927062158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Introduce tegra241_cmdqv_vintf_lvcmdq_ptr() to route VCMDQ Page 0 register accesses through the mmap'd host VINTF Page 0 backing once a hardware queue has been allocated for the VCMDQ. The two QEMU-trapped Page 0 apertures (direct at 0x10000, VINTF at 0x30000) are hardware aliases of the same underlying registers. A subsequent patch installs the VINTF aperture as a RAM-device into guest MMIO; in this patch both remain QEMU-trapped. The direct VCMDQ aperture stays QEMU-trapped (rather than aliased to the VINTF mmap) so that writes to an unallocated VCMDQ remain well-defined. The CMDQV architecture allows software to program a VCMDQ through the direct aperture without first allocating it to a VINTF; aliasing to the VINTF mmap would route those writes into unallocated logical slots where the hardware silently drops them. A VCMDQ Page 0 access is served from one of two sources: - Cache-backed: no hw_queue is allocated for the VCMDQ (HW_QUEUE_ALLOC has not yet succeeded). Both apertures use QEMU's register cache. - HW-backed: HW_QUEUE_ALLOC has succeeded. Both apertures access the registers directly through the mmap'd host VINTF Page 0. tegra241_cmdqv_sync_vcmdq() copies any cached writes (CONS_INDX, PROD_INDX, CONFIG, GERRORN) into the mmap'd page on the cache-to-HW transition so the guest's earlier register state survives. Freeing a VCMDQ clears the cached Page0 registers. Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Message-id: 20260609112552.378999-20-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 89 +++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 4 +- 2 files changed, 91 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 8cb39e87c4..63fe0ac681 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -16,6 +16,16 @@ #include "tegra241-cmdqv.h" #include "trace.h" =20 +static void tegra241_cmdqv_reset_vcmdq_cache(Tegra241CMDQV *cmdqv, int ind= ex) +{ + cmdqv->vcmdq_cons_indx[index] =3D 0; + cmdqv->vcmdq_prod_indx[index] =3D 0; + cmdqv->vcmdq_config[index] =3D 0; + cmdqv->vcmdq_status[index] =3D 0; + cmdqv->vcmdq_gerror[index] =3D 0; + cmdqv->vcmdq_gerrorn[index] =3D 0; +} + static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index) { IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; @@ -27,6 +37,7 @@ static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdq= v, int index) iommufd_backend_free_id(viommu->iommufd, vcmdq->hw_queue_id); g_free(vcmdq); cmdqv->vcmdq[index] =3D NULL; + tegra241_cmdqv_reset_vcmdq_cache(cmdqv, index); } =20 /* @@ -45,6 +56,47 @@ static bool tegra241_cmdqv_vcmdq_ready_to_alloc(Tegra241= CMDQV *cmdqv, int index) tegra241_cmdqv_enabled(cmdqv) && tegra241_vintf_enabled(cmdqv); } =20 +/* + * Return a pointer into the mmap'd VINTF page0 for the VCMDQ Page 0 + * register at @offset0 in VCMDQ slot @index, or NULL when the VCMDQ + * has no hw_queue allocated or the host VINTF page0 is not mmap'd. + */ +static inline uint32_t *tegra241_cmdqv_vintf_lvcmdq_ptr(Tegra241CMDQV *cmd= qv, + int index, hwaddr offset0) +{ + if (!cmdqv->vcmdq[index] || !cmdqv->vintf_page0) { + return NULL; + } + return (uint32_t *)(cmdqv->vintf_page0 + + (index * CMDQV_VCMDQ_STRIDE) + + (offset0 - CMDQV_VCMDQ_PAGE0_BASE)); +} + +/* + * Flush cached register writes into the mmap'd host VINTF page0 after a + * successful HW_QUEUE_ALLOC, so the guest's earlier writes survive + * the cache-to-hardware transition. + */ +static void tegra241_cmdqv_sync_vcmdq(Tegra241CMDQV *cmdqv, int index) +{ + uint32_t *ptr; + + ptr =3D tegra241_cmdqv_vintf_lvcmdq_ptr(cmdqv, index, A_VCMDQ0_CONS_IN= DX); + if (!ptr) { + return; + } + *ptr =3D cmdqv->vcmdq_cons_indx[index]; + + ptr =3D tegra241_cmdqv_vintf_lvcmdq_ptr(cmdqv, index, A_VCMDQ0_PROD_IN= DX); + *ptr =3D cmdqv->vcmdq_prod_indx[index]; + + ptr =3D tegra241_cmdqv_vintf_lvcmdq_ptr(cmdqv, index, A_VCMDQ0_CONFIG); + *ptr =3D cmdqv->vcmdq_config[index]; + + ptr =3D tegra241_cmdqv_vintf_lvcmdq_ptr(cmdqv, index, A_VCMDQ0_GERRORN= ); + *ptr =3D cmdqv->vcmdq_gerrorn[index]; +} + /* * Allocate a host HW VCMDQ from the current cached BASE / size for @index. * No-op (returns true) until the VCMDQ is ready to be allocated. @@ -85,6 +137,9 @@ static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cm= dqv, int index, cmdqv->vcmdq_gerror[index] &=3D ~R_VCMDQ0_GERROR_CMDQ_INIT_ERR_MASK; cmdqv->vcmdq_status[index] |=3D R_VCMDQ0_STATUS_CMDQ_EN_OK_MASK; =20 + /* Push cached writes to HW; freeing resets the cache. */ + tegra241_cmdqv_sync_vcmdq(cmdqv, index); + return true; } =20 @@ -111,13 +166,23 @@ static void tegra241_cmdqv_setup_all_vcmdq(Tegra241CM= DQV *cmdqv, * * The caller normalizes the MMIO offset such that @offset0 always refers * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + * + * If the VCMDQ is allocated and the host VINTF page0 is mmap'd, read + * directly from the host VINTF page0 backing. Otherwise, fall back to + * the cache. */ static uint64_t tegra241_cmdqv_read_vcmdq_page0(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, bool direct) { + uint32_t *ptr =3D tegra241_cmdqv_vintf_lvcmdq_ptr(cmdqv, index, offset= 0); uint64_t val =3D 0; =20 + if (ptr) { + val =3D *ptr; + goto out; + } + switch (offset0) { case A_VCMDQ0_CONS_INDX: val =3D cmdqv->vcmdq_cons_indx[index]; @@ -142,7 +207,9 @@ static uint64_t tegra241_cmdqv_read_vcmdq_page0(Tegra24= 1CMDQV *cmdqv, "%s unhandled read access at 0x%" PRIx64 "\n", __func__, offset0); } +out: trace_tegra241_cmdqv_read_vcmdq_page0(index, direct ? "direct" : "vi", + ptr ? "hw" : "cache", offset0, val); return val; } @@ -218,11 +285,31 @@ static uint64_t tegra241_cmdqv_config_vintf_read(Tegr= a241CMDQV *cmdqv, * * Page 0 registers are all 32-bit; this helper is only called for 4-byte * writes. + * + * If the VCMDQ is allocated and the host VINTF page0 is mmap'd, write + * directly to the VINTF page0 backing. Otherwise, update the cache. */ static void tegra241_cmdqv_write_vcmdq_page0(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, uint32_t value, bool direct) { + uint32_t *ptr =3D tegra241_cmdqv_vintf_lvcmdq_ptr(cmdqv, index, offset= 0); + bool hw =3D false; + + if (ptr) { + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + case A_VCMDQ0_PROD_INDX: + case A_VCMDQ0_CONFIG: + case A_VCMDQ0_GERRORN: + *ptr =3D value; + hw =3D true; + goto out; + default: + break; + } + } + switch (offset0) { case A_VCMDQ0_CONS_INDX: cmdqv->vcmdq_cons_indx[index] =3D value; @@ -253,7 +340,9 @@ static void tegra241_cmdqv_write_vcmdq_page0(Tegra241CM= DQV *cmdqv, "%s unhandled write access at 0x%" PRIx64 "\n", __func__, offset0); } +out: trace_tegra241_cmdqv_write_vcmdq_page0(index, direct ? "direct" : "vi", + hw ? "hw" : "cache", offset0, value); } =20 diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 666967dc5e..a8dcbc82db 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -75,9 +75,9 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS # tegra241-cmdqv tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" -tegra241_cmdqv_read_vcmdq_page0(int index, const char *aperture, uint64_t = offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 +tegra241_cmdqv_read_vcmdq_page0(int index, const char *aperture, const cha= r *backing, uint64_t offset0, uint64_t val) "vcmdq[%d] %s (%s) offset0: 0x%= "PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_read_vcmdq_page1(int index, const char *aperture, uint64_t = offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 -tegra241_cmdqv_write_vcmdq_page0(int index, const char *aperture, uint64_t= offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 +tegra241_cmdqv_write_vcmdq_page0(int index, const char *aperture, const ch= ar *backing, uint64_t offset0, uint64_t val) "vcmdq[%d] %s (%s) offset0: 0x= %"PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_write_vcmdq_page1(int index, const char *aperture, uint64_t= offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 =20 # strongarm.c --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637078; cv=none; d=zohomail.com; s=zohoarc; b=bxdF5KLYn/hwnEvtdnvsmeFZ5ekH++ivwBh33eKzgzcoU1j5LD4dTEv7npUhYaUYfoW/G2og7Gk0go55MY0fnmjtrZr0ycNrkud4xIERXceLjoTCFw5V2L3thJKcj8CYCahyuE8PhlQ0QhPR1bonmg2d2D597qWCy7NR1jCI3GY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637078; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=TSml+C+o8e5g2HzgYLSNK9fnxCmPI3ITde5GKhyWgGw=; b=VMirCz7/kD9unGHkbHsnYa5DLoXVr7UtFnEGwDhjIBewB9HIVLVEblYKMUYGOePoxDY/T0qKK+ouJTRe9WdEiQqHpuaskoJQ0aSW1R6JMdSWc5cEJn7LXV+bN0X9tCIunbcXyvmtczkiLcHMrJpJUcGm8OkUoFi00Lam/F374Es= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637078275330.8483847445782; Tue, 16 Jun 2026 12:11:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAS-0006fO-JY; Tue, 16 Jun 2026 15:09:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8I-0004Zx-Kb for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8A-00011M-V4 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:30 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-460166910e6so2632984f8f.2 for ; Tue, 16 Jun 2026 12:07:16 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636836; x=1782241636; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TSml+C+o8e5g2HzgYLSNK9fnxCmPI3ITde5GKhyWgGw=; b=PhffYPtyJBLuMMtTqftR8gkA+/EWR7mklMP4jPie6wtJL7dbeOU6iOz3bP/wIR4Y9r aOMTP6XBRMDLaAa8sezzY06VHn0UAXFybxmjQiEZwNz+RdMAOAY071DxKr3/wI9H42nT VZEG32vtC93V1Rfk1pzlfmRssk17lBlKwOfCr2HIa9cJwoyCip6lXKC8KYmcE1qqJRnW KH/iXFXJi8apno/4Y2WOEJ9qdbJxUHGPynFPwQS4Q4GPTakjFxz7H4Eae7zd+UdmoYLs 9tHz8A08Yk+0/VcDt6ZGTunCQajOxB6/HtwFo3LtCO9qGE41y+mo2aeR4pxBajSouDgO FQfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636836; x=1782241636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=TSml+C+o8e5g2HzgYLSNK9fnxCmPI3ITde5GKhyWgGw=; b=aWmckgjAEyYoSWj4cJ8WDNvz2WK6lHopBuA5nh2+jAGLIO3oegKROdrtv+2UCaZCah AgmkgwzgdnmLHXYLKkQXXATD9nolw0gP7ElARDKrplDFPYc7BK3FHoVjBB4hguClbBvq 7sweTTthJIEEWzL6D+brITlaSE87l1w98hkvuLT5sZpI7dDWnLviGiGnIXaxZfqk9/IK QQI1Sq1fmAXwNYwJ0lEx35DR3Xos/5ylrAd75FnwYK2V4jTHocv2jc/DmeqK4O6oC5Bw OfrSkxcGBUBKdAa56RDDvk4k9KdMx4B0mjHv5WaFfGDt1l6Cmwcccir157aDpw47IQV0 X9MA== X-Gm-Message-State: AOJu0YyWN3TEjc4+38KcVFVNZABt1mT95eaEKjbTO8A6sCGTFPq4MXQu k/hOsyRfKwHVj4CB9IKX2faGW15XUnKu4WtVeHnlW+4it1HmvDtrYrXwvz4ugXrhq2SCPu+G65e c8Rla X-Gm-Gg: Acq92OG4hgwxKMnl3acf/z+WqrS81ytsR3xHeirudGwenHkiBUPa2BoM/010CnC9llj fOH7yxUYmzHCGqwBE3VsUc3LlT7fUtn/uSLKzrJZn+dxe2v+cGui09LQZRBQtfT4yNMNYIPys9w OWJOENYuBaEbIPQyJRxBHOGehwmCKwbiB6sCHiNaRBzrb8Vd6H4FJ0stqiOvzbu8iQQZD8LJsZX gbM+NqHIIL85kpbKlNftzb8aLGyW6RaxihocsAWYOlGY6OT7S+BJQoMSV9VA0dEHMxCrYm/0BFx S1unwkcF/Bajpa2ZCvK8RV76pVbgNojbjzyBMDRO1sxuftvv8PUg6yv1qbhFZVtrKm6axEzyE/G Z/elasiebxNEzAnoGnsn45A8o60UFQHCwutheg5xdwuQHOzK5KxWqB9CkIcMT2SksX+/VVDbpG4 fzYGAM/WXLyuFdHXEOUiEcUaGYbvjT3AYNqGS9t3oLlFWSpi0U9JrPE5ZHJFpuqQpKnuEIhLseD S9GWebt/oWphmUSu64ndfjOTHjhRL9a X-Received: by 2002:a05:6000:2404:b0:45e:6518:3299 with SMTP id ffacd0b85a97d-46236930430mr1298944f8f.5.1781636835767; Tue, 16 Jun 2026 12:07:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/61] memory: Allow RAM device regions to skip IOMMU mapping Date: Tue, 16 Jun 2026 20:06:07 +0100 Message-ID: <20260616190639.3462006-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637079990158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Some RAM device regions created with memory_region_init_ram_device_ptr() are not intended to be P2P DMA targets. The VFIO listener currently treats all RAM device regions as DMA capable and attempts to map them into the IOMMU. For regions without dma-buf backing this fails and prints warnings such as: IOMMU_IOAS_MAP failed: Bad address, PCI BAR? Introduce a MemoryRegion flag (ram_device_skip_iommu_map) to mark RAM device regions that should not be IOMMU mapped, paired with memory_region_skip_iommu_map() / memory_region_set_skip_iommu_map() accessors. When the flag is set, the VFIO listener skips DMA mapping for that region. Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Message-id: 20260609112552.378999-21-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/vfio/listener.c | 6 ++++++ hw/vfio/trace-events | 1 + include/system/memory.h | 21 +++++++++++++++++++++ system/memory.c | 10 ++++++++++ 4 files changed, 38 insertions(+) diff --git a/hw/vfio/listener.c b/hw/vfio/listener.c index 0b72a2cf5e..14cca678ae 100644 --- a/hw/vfio/listener.c +++ b/hw/vfio/listener.c @@ -610,6 +610,12 @@ void vfio_container_region_add(VFIOContainer *bcontain= er, } } =20 + if (memory_region_skip_iommu_map(section->mr)) { + trace_vfio_listener_region_skip_dma_map(memory_region_name(section= ->mr), + iova, int128_get64(llsize)= ); + return; + } + ret =3D vfio_container_dma_map(bcontainer, iova, int128_get64(llsize), vaddr, section->readonly, section->mr); if (ret) { diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events index 2049159015..70c5aa1bcc 100644 --- a/hw/vfio/trace-events +++ b/hw/vfio/trace-events @@ -100,6 +100,7 @@ vfio_listener_region_del_iommu(const char *name) "regio= n_del [iommu] %s" vfio_listener_region_add_ram(uint64_t iova_start, uint64_t iova_end, void = *vaddr) "region_add [ram] 0x%"PRIx64" - 0x%"PRIx64" [%p]" vfio_known_safe_misalignment(const char *name, uint64_t iova, uint64_t off= set_within_region, uintptr_t page_size) "Region \"%s\" iova=3D0x%"PRIx64" o= ffset_within_region=3D0x%"PRIx64" qemu_real_host_page_size=3D0x%"PRIxPTR vfio_listener_region_add_no_dma_map(const char *name, uint64_t iova, uint6= 4_t size, uint64_t page_size) "Region \"%s\" 0x%"PRIx64" size=3D0x%"PRIx64"= is not aligned to 0x%"PRIx64" and cannot be mapped for DMA" +vfio_listener_region_skip_dma_map(const char *name, uint64_t iova, uint64_= t size) "Region \"%s\" 0x%"PRIx64" size=3D0x%"PRIx64" marked to skip IOMMU = mapping" vfio_listener_region_del(uint64_t start, uint64_t end) "region_del 0x%"PRI= x64" - 0x%"PRIx64 vfio_device_dirty_tracking_update(uint64_t start, uint64_t end, uint64_t m= in, uint64_t max) "section 0x%"PRIx64" - 0x%"PRIx64" -> update [0x%"PRIx64"= - 0x%"PRIx64"]" vfio_device_dirty_tracking_start(int nr_ranges, uint64_t min32, uint64_t m= ax32, uint64_t min64, uint64_t max64, uint64_t minpci, uint64_t maxpci) "nr= _ranges %d 32:[0x%"PRIx64" - 0x%"PRIx64"], 64:[0x%"PRIx64" - 0x%"PRIx64"], = pci64:[0x%"PRIx64" - 0x%"PRIx64"]" diff --git a/include/system/memory.h b/include/system/memory.h index 1417132f6d..4560809013 100644 --- a/include/system/memory.h +++ b/include/system/memory.h @@ -864,6 +864,8 @@ struct MemoryRegion { =20 /* For devices designed to perform re-entrant IO into their own IO MRs= */ bool disable_reentrancy_guard; + /* RAM device region that does not require IOMMU mapping for P2P */ + bool ram_device_skip_iommu_map; }; =20 struct IOMMUMemoryRegion { @@ -1743,6 +1745,25 @@ static inline bool memory_region_is_romd(const Memor= yRegion *mr) */ bool memory_region_is_protected(const MemoryRegion *mr); =20 +/** + * memory_region_skip_iommu_map: check whether a memory region is excluded + * from IOMMU mapping + * + * Returns %true if @mr is a RAM device region marked to skip IOMMU mappin= g. + * + * @mr: the memory region being queried + */ +bool memory_region_skip_iommu_map(const MemoryRegion *mr); + +/** + * memory_region_set_skip_iommu_map: mark a RAM device region to skip IOMMU + * mapping + * + * @mr: the memory region being modified + * @skip: %true to skip IOMMU mapping, %false to allow it + */ +void memory_region_set_skip_iommu_map(MemoryRegion *mr, bool skip); + /** * memory_region_has_guest_memfd: check whether a memory region has guest_= memfd * associated diff --git a/system/memory.c b/system/memory.c index 739ba11da6..48245fd01b 100644 --- a/system/memory.c +++ b/system/memory.c @@ -1814,6 +1814,16 @@ bool memory_region_is_protected(const MemoryRegion *= mr) return mr->ram && (mr->ram_block->flags & RAM_PROTECTED); } =20 +bool memory_region_skip_iommu_map(const MemoryRegion *mr) +{ + return memory_region_is_ram_device(mr) && mr->ram_device_skip_iommu_ma= p; +} + +void memory_region_set_skip_iommu_map(MemoryRegion *mr, bool skip) +{ + mr->ram_device_skip_iommu_map =3D skip; +} + bool memory_region_has_guest_memfd(const MemoryRegion *mr) { return mr->ram_block && mr->ram_block->guest_memfd >=3D 0; --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637471; cv=none; d=zohomail.com; s=zohoarc; b=YDxJR2JjTuXiHHZwmDQHvilhHRJ9+GtlhWga7Zwv9omfF+Noqm9PKmedNjxwtDfCXcDGTtVeRyklJRtvS0NYHNuFHeHMe9NGB5hIu/FazM9/P6sNU7ZqCUiGVZ9tc56GXHZXV0NuHYRoxp40WCMRQqKwwaPY3MeTPhzBpioT0ww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637471; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=03cexD1Fz809DC5BukV1ykiIrCk3MZqLYcCjBMj80NM=; b=CdpfgCxrG8kOLv6QJz4T9+V6pb3QglczLMvw1wQnxROS4M2w6gKhm6bMgCV3FNkp4kaRoBNPcqds4N4zE8G+E/gSAid+iDDvpwLx9YCr0SVOtcoiyPlimglH3JKzchwm2xioJNSyOZgEb1aRiKhUXTOyTY9z0GeCJLumBJxtzK4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637471013529.4904397258794; Tue, 16 Jun 2026 12:17:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAX-0007Iu-RK; Tue, 16 Jun 2026 15:09:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZL-Ax for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ85-00011X-Ji for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:25 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-45ef1198766so125051f8f.0 for ; Tue, 16 Jun 2026 12:07:18 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636837; x=1782241637; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=03cexD1Fz809DC5BukV1ykiIrCk3MZqLYcCjBMj80NM=; b=Iz2kt8p/kMhlvmYHmLuWu28z33JSlXop0hUh+ZfiqVj36I9FR6BBCk+DF21dg3xsJh WvVcJ9XC/QfcnyoH8AkEF2vIOL6bRKUsz3WeGSPqAGckwygsSqJOBcvAQ2bgfs4P76DY 0YxJ+WlseH1lDJwvzEd12I6h1MO8GkvXC/Y9Ozh6FlgVeo+wY6nzXKK2irN0r7ONHVI8 Utpb/2JvDJcyHK05WYxTZ0aRbR2x+O+nNtGis2SINsX1/j6qR77N9NEYyoKgTqxUvhoW 9BgSKd9g7G5OY+NGZBbK43x1/I1U9N+bzzwP0bbm+culNHeHSipYgUOoBYIVHBoFHGCU 7RNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636837; x=1782241637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=03cexD1Fz809DC5BukV1ykiIrCk3MZqLYcCjBMj80NM=; b=AHxsy60SG8Hq3M2PAZ8swH4gSYOn9mwY5+74mlJpbGit1Rvfy3V4d7EAOo13a/kZxL DxHLAKUce8MjRDElTCv+gGSQti3BRrRmsWQrZMY969+2zlckMtIu5nF5Ry2g13+ipyix 6kicPlRaOim2q/rWZIW7jTHMBzmgAFYpItrg2gsDnj3tHYxEg46KCrr4IzHJuhs3IEhu j1G2T1XQNaqMbZxtQxpBHL68vtk/AwZRG5MbFK4hCB+vjCVJksEynADdGPugCl0cDMP2 qbayp73a+zlL2leJSlgV9e7kG7AZeX4T6dYd0tTPKr0QM1+iM6ObYVMNCTWmdnSM5cUn gPNQ== X-Gm-Message-State: AOJu0YyeQwOWHAFUjHiq4DqPC8gbkMsTnTc0OM/GZgzfPezR6xekuubO fmtWF8H2Nn/uuif+nfhI5U3IxfkWrS3AujvIOZ4+DOpQMl7O7Met2E1BndjEer4isn9x1oR7A3p ueffz X-Gm-Gg: AfdE7cnvLlZ9yvjcLgnoC1gxsMCRiGfHfUxAY+yUtfiIynucCzMEgKGnrLSnwMQ3/q9 XQKQYRjx9ri6COISPylWlwghKR1rOfWTAQV5Yx/DGaWoHrmsFi+/8tG5wlDmcmtO+k8vvmFXoYy C3HMDQ7913Bct1AQiIBdKAsQ8vf/sSxjheXWrZBEPb59TC6+/k7TkL0JwWN2PLT0TKvCMRpWMu9 M9opQnY/fWRGuYWViEbfDEfEljuKpRIJGTGZaRgG1eGpssuLRWS6wb42yjw5gfaSGInXR9xt9iV 6DsyPVoIaI11lGl0yvxau4xOCqvsLD3z5nkEAKTi/RbU5ZfLL06XGsdkwDacXS15pXTtpP5i57W rIlLHvdqRN2S6AjsdXXWIpcbkgCtUmwY9QZHZHGJF6rHXJM6QIUmAWyfJcEB5O7/6om2Edg3NHF Sag8bKVR1yLmxehe7mVURZRYY2NdyV1+78lv7rZMMa+uESscT5aadcdrP7xUEclOe19/1VIS6TU rR3hTRumezzxyaBviJ+Vn/RfDme88b9 X-Received: by 2002:a05:6000:2411:b0:461:a169:fdbd with SMTP id ffacd0b85a97d-46269aa5b38mr20688f8f.13.1781636836600; Tue, 16 Jun 2026 12:07:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/61] hw/arm/tegra241-cmdqv: Use mmap'd host VINTF page0 for virtual VINTF page0 Date: Tue, 16 Jun 2026 20:06:08 +0100 Message-ID: <20260616190639.3462006-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637472548158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Install the mmap'd host VINTF page0 as a RAM-device MemoryRegion backing the guest's virtual VINTF Page 0 aperture (guest MMIO offset 0x30000) when VINTF is enabled, and remove it on VINTF disable or reset. This eliminates QEMU trapping for hot-path CONS/PROD index updates via that aperture. After this patch, the two VCMDQ Page 0 apertures use different access paths: the direct aperture (0x10000) remains QEMU-trapped, while the VINTF aperture (0x30000) is a guest-direct RAM mapping. The direct aperture is intentionally kept trapped (not aliased to the host VINTF mmap) so that writes to an unallocated VCMDQ remain well-defined. The CMDQV architecture allows software to program a VCMDQ through the direct aperture without first allocating it to a VINTF; aliasing would route those writes to unallocated logical slots in the VINTF page, where the hardware silently drops them. Signed-off-by: Nicolin Chen Tested-by: Nicolin Chen Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Message-id: 20260609112552.378999-22-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 37 +++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 1 + 2 files changed, 38 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 63fe0ac681..7264b4bfa9 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -26,6 +26,40 @@ static void tegra241_cmdqv_reset_vcmdq_cache(Tegra241CMD= QV *cmdqv, int index) cmdqv->vcmdq_gerrorn[index] =3D 0; } =20 +static void tegra241_cmdqv_guest_unmap_vintf_page0(Tegra241CMDQV *cmdqv) +{ + if (!cmdqv->mr_vintf_page0) { + return; + } + + memory_region_del_subregion(&cmdqv->mmio_cmdqv, cmdqv->mr_vintf_page0); + object_unparent(OBJECT(cmdqv->mr_vintf_page0)); + g_free(cmdqv->mr_vintf_page0); + cmdqv->mr_vintf_page0 =3D NULL; +} + +static void tegra241_cmdqv_guest_map_vintf_page0(Tegra241CMDQV *cmdqv) +{ + char *name; + + if (cmdqv->mr_vintf_page0) { + return; + } + + name =3D g_strdup_printf("%s vintf-page0", + memory_region_name(&cmdqv->mmio_cmdqv)); + cmdqv->mr_vintf_page0 =3D g_malloc0(sizeof(*cmdqv->mr_vintf_page0)); + memory_region_init_ram_device_ptr(cmdqv->mr_vintf_page0, + memory_region_owner(&cmdqv->mmio_cmd= qv), + name, VINTF_PAGE_SIZE, + cmdqv->vintf_page0); + memory_region_set_skip_iommu_map(cmdqv->mr_vintf_page0, true); + memory_region_add_subregion_overlap(&cmdqv->mmio_cmdqv, + CMDQV_VINTF_PAGE0_BASE, + cmdqv->mr_vintf_page0, 1); + g_free(name); +} + static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index) { IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; @@ -430,7 +464,9 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241C= MDQV *cmdqv, * enabled need their hw_queue allocated now. */ tegra241_cmdqv_setup_all_vcmdq(cmdqv, errp); + tegra241_cmdqv_guest_map_vintf_page0(cmdqv); } else { + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); tegra241_cmdqv_free_all_vcmdq(cmdqv); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; } @@ -772,6 +808,7 @@ static void tegra241_cmdqv_reset(SMMUv3State *s) return; } =20 + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); tegra241_cmdqv_free_all_vcmdq(cmdqv); } =20 diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 84499b840d..01cd6af97d 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -49,6 +49,7 @@ typedef struct Tegra241CMDQV { IOMMUFDVeventq *veventq; IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ]; void *vintf_page0; + MemoryRegion *mr_vintf_page0; =20 /* CMDQ-V Config page register cache */ uint32_t config; --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637281; cv=none; d=zohomail.com; s=zohoarc; b=kKy1IllwanKd7IIaxkHkLYrge1jSUj+zUZN1GFlUKiDR4rm8RC21OezDLOFON2dqHF+773Hi4eNW/rutcS6HmMZicJAEzWveOxqcCgh0OPJ1CmzuS13Mxox9S/YZZ2X5OxaFkXShj/z1XdwOXZS7fbbtXhMTIMY3AXGaUXrZMoU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637281; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=UcXYR0u9XO6butqPyE33f491+UF5RjAaf8RWRVOWwfM=; b=BUTPBz7pdywIdkF8cgKiSG7qz39+oBZ/6XCOsuEgbb25cYwobOx+kTHtcEYX1rEtldDGyrV0+WP1+2V7tH9ySVhPGfYXsKFZDsqYJkoUSmkjKELwHl8Wr0qjXEjCl8qf832427Ct6bsApG8zEvlyKyW0UdMMz0+9zthUHm2XDe4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637281662575.1940133972128; Tue, 16 Jun 2026 12:14:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZDj-00040E-Oj; Tue, 16 Jun 2026 15:13:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8L-0004bK-Eb for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:41 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8F-00011f-1J for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:35 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-45ef616daf6so5640606f8f.3 for ; Tue, 16 Jun 2026 12:07:18 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636838; x=1782241638; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UcXYR0u9XO6butqPyE33f491+UF5RjAaf8RWRVOWwfM=; b=X+hIlhQcJNn5fkYad6lZQOYdWhAB3hBfWJhRNxSg/olIGjzavl0IEAWa7CCRd1uB2b SalWKQKTRNaF8BYyB4d208N0Ry+HjqsVrs/BeaIV7NGvo+JQjCoEoehDjiB1agmsrtpJ w6Cxz9qd79Sx5iYY7W7wP/EWsq46QPuZf0xWGG9E1bCFDP6bZDu7zs2uN25ANFzdpbBr W3GbOlqYDk/VBl13J4j+zXhwR5/3znUBsyEg9SQJNW1Ujwnz/rvccs24HxLg/l3z8nJ6 VkbZoBmRVh+P51L0xRgskWVkHWCinkcaDOg3/etW2AUEtBS5xHfEhDvPZJ75cvprg8uS srZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636838; x=1782241638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=UcXYR0u9XO6butqPyE33f491+UF5RjAaf8RWRVOWwfM=; b=FIcgutT/OZpQhRhmBFWJYiAkWm8Z95cRbhLKh2VT1U7g1cuImQvMKaXbAd44w4WPzZ dC3Zxd0f1d1z9YECF4IFZtn9usvXGG41ouPkZNSEDJrKY1348cy2DFzXacz/9HTmjo25 nAkkSF7IUWZhaG6UOUVBGnOZHAQdRC9ygSVeC2hcGJoMi01c1NEXnTAdXTpJxQOhekNU fNaRA5xF758Iz28k9R42jUvZY6tmnrZEiL49ifBW/foCV8UsMxPD6yFQ7VmuGrdi9teo +P09uSJE6BqbmxSytlPXczGvlzt7zOW9xQ+O0OMYgPoD0Vrq8d5f0kswD5CgrqI87cg3 K6bA== X-Gm-Message-State: AOJu0Yzc3ZR66oqPssl5Ec1T6/yqk0dYbh/H28jGCr/bEk5PTOyWfV8B iIETarUEN8FalasBfZ3edsmSds9dG4fI/g5qUkMCQHtpBt0tZQ5dNO6H/Olo9k629foeb3npvLb 5Db6b X-Gm-Gg: Acq92OEwrvdetfFzF17lJw4T6helWpEzhfaz1+ZUKP/vBdLQB3B/L+Sd8D+6JbGYIyf Z07ISwaHoaKZL1vx1cmdRKm6B574jeASOO5nCoLTzWbwTWb16KiLZwQNVCj2jjVjvnLSFhH00h0 NyBWVU6WsxT1LcNVmBulUfgwoe6he5KNSbejkKgf5uEjr6UXwvwtyMcQCAScw0Jaw1AiIY+8kGZ 5s/ZwFLJcHHuKaiqKMXStoivt4xE7qc03HYpSeVFjSQwYFge03r5/xaSbAbRGuqRFOj2WnLQT9A b38NUdX7E7IpxZaiWQ1wwwjSAxzcKwP+XZU6u+uXru9aqgq+Ggu025oVi58MAH11aUR17KbT+Kh 931qyFto0HZeHo2CYtqgQJw+hBtlEVRnBWLT6Z5XCuID1UDVJmX1l+G6bUM1NU+MesFPNmWxjXX NWm8P2CMn4vf2hLp5BPLzWFJ7GAu3g/KBumrcV3V2RS7aVEItmw0dYfEqwhjLnabNnCRff2/t0Z MtaIGGIJ7Jqt5BPn9QmQfzhm/dJcT13 X-Received: by 2002:a05:6000:43c6:20b0:460:6a8f:5d36 with SMTP id ffacd0b85a97d-46238acb5ebmr1101385f8f.22.1781636837660; Tue, 16 Jun 2026 12:07:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/61] hw/arm/smmuv3-accel: Introduce common helper for veventq read Date: Tue, 16 Jun 2026 20:06:09 +0100 Message-ID: <20260616190639.3462006-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637283392158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Move the vEVENTQ read and validation logic into a common helper smmuv3_accel_event_read_validate(). The helper performs the read(), checks for overflow and short reads, validates the sequence number, and updates the sequence state. This helper can be reused for Tegra241 CMDQV vEVENTQ support in a subsequent patch. Error handling is slightly adjusted: instead of reporting errors directly in the read handler, the helper now returns errors via Error **. Sequence gaps are reported as warnings. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-23-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel-stubs.c | 7 ++++ hw/arm/smmuv3-accel.c | 73 ++++++++++++++++++++++--------------- hw/arm/smmuv3-accel.h | 2 + 3 files changed, 52 insertions(+), 30 deletions(-) diff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c index 70cef66966..9e6c44a282 100644 --- a/hw/arm/smmuv3-accel-stubs.c +++ b/hw/arm/smmuv3-accel-stubs.c @@ -47,6 +47,13 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **= errp) return true; } =20 +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp) +{ + return true; +} + + void smmuv3_accel_reset(SMMUv3State *s) { } diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 3ceca56a67..c1c2a67c97 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -440,6 +440,44 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void = *cmd, SMMUDevice *sdev, sizeof(Cmd), &entry_num, cmd, errp); } =20 +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp) +{ + uint32_t last_seq =3D veventq->last_event_seq; + uint32_t id =3D veventq->veventq_id; + struct iommufd_vevent_header *hdr; + ssize_t bytes; + + bytes =3D read(veventq->veventq_fd, buf, size); + if (bytes <=3D 0) { + if (errno =3D=3D EAGAIN || errno =3D=3D EINTR) { + return true; + } + error_setg(errp, "vEVENTQ(type %u id %u): read failed (%m)", type,= id); + return false; + } + hdr =3D (struct iommufd_vevent_header *)buf; + if (bytes =3D=3D sizeof(*hdr) && + (hdr->flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) { + error_setg(errp, "vEVENTQ(type %u id %u): overflowed", type, id); + veventq->event_start =3D false; + return false; + } + if (bytes < size) { + error_setg(errp, "vEVENTQ(type %u id %u): short read(%zd/%zd bytes= )", + type, id, bytes, size); + return false; + } + /* Check sequence in hdr for lost events if any */ + if (veventq->event_start && (hdr->sequence - last_seq !=3D 1)) { + warn_report("vEVENTQ(type %u id %u): lost %u event(s)", + type, id, hdr->sequence - last_seq - 1); + } + veventq->last_event_seq =3D hdr->sequence; + veventq->event_start =3D true; + return true; +} + static void smmuv3_accel_event_read(void *opaque) { SMMUv3State *s =3D opaque; @@ -448,39 +486,14 @@ static void smmuv3_accel_event_read(void *opaque) struct iommufd_vevent_header hdr; struct iommu_vevent_arm_smmuv3 vevent; } buf; - enum iommu_veventq_type type =3D IOMMU_VEVENTQ_TYPE_ARM_SMMUV3; - uint32_t id =3D veventq->veventq_id; - uint32_t last_seq =3D veventq->last_event_seq; - ssize_t bytes; + Error *local_err =3D NULL; =20 - bytes =3D read(veventq->veventq_fd, &buf, sizeof(buf)); - if (bytes <=3D 0) { - if (errno =3D=3D EAGAIN || errno =3D=3D EINTR) { - return; - } - error_report_once("vEVENTQ(type %u id %u): read failed (%m)", type= , id); + if (!smmuv3_accel_event_read_validate(veventq, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3, &= buf, + sizeof(buf), &local_err)) { + warn_report_err_once(local_err); return; } - - if (bytes =3D=3D sizeof(buf.hdr) && - (buf.hdr.flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) { - error_report_once("vEVENTQ(type %u id %u): overflowed", type, id); - veventq->event_start =3D false; - return; - } - if (bytes < sizeof(buf)) { - error_report_once("vEVENTQ(type %u id %u): short read(%zd/%zd byte= s)", - type, id, bytes, sizeof(buf)); - return; - } - - /* Check sequence in hdr for lost events if any */ - if (veventq->event_start && (buf.hdr.sequence - last_seq !=3D 1)) { - error_report_once("vEVENTQ(type %u id %u): lost %u event(s)", - type, id, buf.hdr.sequence - last_seq - 1); - } - veventq->last_event_seq =3D buf.hdr.sequence; - veventq->event_start =3D true; smmuv3_propagate_event(s, (Evt *)&buf.vevent); } =20 diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index e0bbec8581..8d0f636338 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -87,6 +87,8 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd= , SMMUDevice *sdev, Error **errp); void smmuv3_accel_idr_override(SMMUv3State *s); bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp); +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp= ); void smmuv3_accel_reset(SMMUv3State *s); =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637006; cv=none; d=zohomail.com; s=zohoarc; b=EEaAoEnx1+VcXVbJmGa/iQQaOSZJ3Xw/zPhwwk8li0dEusb59wnL+TN/SHPUn4wVcvT6KoSgQAEPwx3BD1bRzpk27pA3NkKBlIKkME4X+W0RwixzqNfOVWCZm8r4Uxsr05m1ACJSQq/KID4SpsUj2Wcogwon9SN1DoEK2KmZKxQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637006; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=v/w08YsGzSbVzz3Gzi7V2p2Sw+AOEyN59cWjZhnh21E=; b=Hs+fbppRjaF5lfXUQP0dPLWxFWGZZsJMlrbSMVdK5MvJG49+PNROKl9JLLSw5NvzMKVc34duFEU2wppUUH/tCep1N05DtuyEARcKU1ou2kSGxTCRN8rym17NJuzyHYUJgiExsdIlKnFF6JGdnx8roGzSY5sBT2zaJtNFasdRSik= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178163700615293.04665879958009; Tue, 16 Jun 2026 12:10:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAP-0006AI-8Q; Tue, 16 Jun 2026 15:09:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZJ-C0 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ86-00012A-KI for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:25 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-490b1bbcf3aso37691395e9.1 for ; Tue, 16 Jun 2026 12:07:19 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636839; x=1782241639; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=v/w08YsGzSbVzz3Gzi7V2p2Sw+AOEyN59cWjZhnh21E=; b=LtAR3SC9CP8D9Pf0vSKvFcF2KxzPiL+5r3m/xu5G+l2muPyWWYtio+FHokRpQ6OHI+ NCTQkniS4GQ3INsSm/GjTO1W3DULJYr1JPsDmwjDcZ5cfc+Jp6TwtTE2CLAbCPQYDWzF jJqS/kRGMO/FhEHxDFCCE5XW8pPMpGxGi0i2B3wEG624MFNNMXLrpvKQ8gOyHVJXjg6A 6MJZ0Nf2j/xdHaC9NdzAA+0lR/4pE9dMwquEkhIZr/ZZJR878vGHmOfApX12J/0xUa03 CcXCVSGgCDWWDFO2Emw7ay9BDlNcGNqXxHMq6fKHiw/tqzesEiWmXwhSxe331bVeLf3D +cdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636839; x=1782241639; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=v/w08YsGzSbVzz3Gzi7V2p2Sw+AOEyN59cWjZhnh21E=; b=LSTybbUTX3nJazQ3Sx+ZSOGVud4GY208x7vaQtZFlyUzmFcUJVuZ9ZhAYtdn8CFf6N iQBMR/o9IAMHiET6DfGpznlKt095d+P0Mmmp/eRj5QXQaI4M/6mIQQmJXikv4tT3dBs4 3RjFhvx7dCnBBzTqdHaD1Rr2o8vJSkDVhNrgy8lt7ld7cN5YACzcGcT3p50iuwbK3rAK 2bwkqulma/NWYV8x2FRLHhXMDov4FyS7/4cUIbLjDC9VVb6B5kBWMI4TBc9kDSz8Fb83 EkFeD8zUg8ivuHRO6UfrYf5Y4xcqxYsWMM3/GG53m7bxHGVsxg0ipVSNT+a0n312sZ8w XPnQ== X-Gm-Message-State: AOJu0YzZMnIxwWHWGZCWpC4EKoTlfqJNv5brD/1zpotZHRLaaKlWriKG LjSaC+ck7H3GHf0rfiTVIbRkXKqm7kla6qtD6yrzhW4M1SutDGSRYcwTBei/cyHQ8FCmXOxqFrU n4t32 X-Gm-Gg: Acq92OGcw2E7x7pd22ORgmoHQhTpVjVh9ukNNAw0N7gjzl6U1B5l14RpqCArMLeadwv 7S4nzajX1C0eq8sR+/y5/5mUNoOBQWC0dQBLGU94iStHgPv++D9eUizVVvGwdoazwjWZgy6Zzop +dHAjkRfhbOsgqhxT5LFSDQY4eOFlWj9n9AQ3QTs6aD5Qjlo3mwqj8dQQvjITPuvNnQHU6WrRFT gKZCHv/wRhSTvO8RuAwCG31sm9Xyz+f7hbt79sj8fU7FJDsYeUrtmzDcaNUGKUOdT++PSzLGABh JpqQWwWQXLNsHN+dRDL5zkpfZuwuIP5UYtdgkv0n9ozr8gjGKvVO542jjY2gYNidE4jalWjnpBb B7I9nWBRpXhxpJDrTpiKiIstjMV2r9IFRXwptw1ACyQM5I7A8gKk91s5lCloz28FJzLz2Cyaoq0 EdNjErqhPaviPxvmp5c2N/IryZIqh5kuYOELxBenaZcASt26qCvA/eTde+yAJFRDhsztJlLjdY6 PAV9/2Z01jk+R+Dls8CqdvDYlsTUcN3 X-Received: by 2002:a05:600c:6308:b0:492:1e36:8c72 with SMTP id 5b1f17b1804b1-492333e2433mr11717775e9.37.1781636838897; Tue, 16 Jun 2026 12:07:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/61] hw/arm/tegra241-cmdqv: Read and propagate Tegra241 CMDQV errors Date: Tue, 16 Jun 2026 20:06:10 +0100 Message-ID: <20260616190639.3462006-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637007390158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Install an event handler on the CMDQV vEVENTQ fd to read and propagate host received CMDQV errors to the guest. The handler runs in QEMU's main loop, using a non-blocking fd registered via qemu_set_fd_handler(). Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-24-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 63 +++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + 2 files changed, 64 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 7264b4bfa9..ff0fcd1e66 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -12,6 +12,7 @@ =20 #include "hw/arm/smmuv3.h" #include "hw/arm/smmuv3-common.h" +#include "hw/core/irq.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" #include "trace.h" @@ -729,6 +730,51 @@ out: trace_tegra241_cmdqv_write_mmio(offset, value, size); } =20 +static void tegra241_cmdqv_event_read(void *opaque) +{ + Tegra241CMDQV *cmdqv =3D opaque; + IOMMUFDVeventq *veventq =3D cmdqv->veventq; + struct { + struct iommufd_vevent_header hdr; + struct iommu_vevent_tegra241_cmdqv vevent; + } buf; + Error *local_err =3D NULL; + + if (!smmuv3_accel_event_read_validate(veventq, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQ= V, + &buf, sizeof(buf), &local_err)) { + warn_report_err_once(local_err); + return; + } + + if (buf.vevent.lvcmdq_err_map[0] || buf.vevent.lvcmdq_err_map[1]) { + cmdqv->vintf_cmdq_err_map[0] =3D + extract64(buf.vevent.lvcmdq_err_map[0], 0, 32); + cmdqv->vintf_cmdq_err_map[1] =3D + extract64(buf.vevent.lvcmdq_err_map[0], 32, 32); + cmdqv->vintf_cmdq_err_map[2] =3D + extract64(buf.vevent.lvcmdq_err_map[1], 0, 32); + cmdqv->vintf_cmdq_err_map[3] =3D + extract64(buf.vevent.lvcmdq_err_map[1], 32, 32); + /* + * CMDQV_CMDQ_ERR_MAP and VINTF0_LVCMDQ_ERR_MAP are distinct + * registers (different MMIO offsets). With only VINTF0 exposed + * they carry the same data, so mirror. + */ + for (int i =3D 0; i < 4; i++) { + cmdqv->cmdq_err_map[i] =3D cmdqv->vintf_cmdq_err_map[i]; + } + /* Set the VINTF0 bit in VI_ERR_MAP_0 (only VINTF0 is exposed). */ + cmdqv->vi_err_map[0] |=3D BIT(0); + if (!(cmdqv->vi_int_mask[0] & BIT(0))) { + qemu_irq_pulse(cmdqv->irq); + } + trace_tegra241_cmdqv_err_map( + cmdqv->vintf_cmdq_err_map[3], cmdqv->vintf_cmdq_err_map[2], + cmdqv->vintf_cmdq_err_map[1], cmdqv->vintf_cmdq_err_map[0]); + } +} + static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { SMMUv3AccelState *accel =3D s->s_accel; @@ -740,6 +786,7 @@ static void tegra241_cmdqv_free_viommu(SMMUv3State *s) return; } if (veventq) { + qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL); close(veventq->veventq_fd); iommufd_backend_free_id(viommu->iommufd, veventq->veventq_id); g_free(veventq); @@ -759,6 +806,7 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, Tegra241CMDQV *cmdqv =3D s->s_accel->cmdqv; uint32_t viommu_id, veventq_id, veventq_fd; IOMMUFDVeventq *veventq; + int flags; =20 if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, @@ -784,14 +832,29 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMU= DeviceIOMMUFD *idev, goto munmap_page0; } =20 + flags =3D fcntl(veventq_fd, F_GETFL); + if (flags < 0) { + error_setg(errp, "Failed to get flags for vEVENTQ fd"); + goto free_veventq; + } + if (fcntl(veventq_fd, F_SETFL, O_NONBLOCK | flags) < 0) { + error_setg(errp, "Failed to set O_NONBLOCK on vEVENTQ fd"); + goto free_veventq; + } + veventq =3D g_new(IOMMUFDVeventq, 1); veventq->veventq_id =3D veventq_id; veventq->veventq_fd =3D veventq_fd; cmdqv->veventq =3D veventq; =20 + /* Set up event handler for veventq fd */ + qemu_set_fd_handler(veventq_fd, tegra241_cmdqv_event_read, NULL, cmdqv= ); *out_viommu_id =3D viommu_id; return true; =20 +free_veventq: + close(veventq_fd); + iommufd_backend_free_id(idev->iommufd, veventq_id); munmap_page0: munmap(cmdqv->vintf_page0, VINTF_PAGE_SIZE); cmdqv->vintf_page0 =3D NULL; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index a8dcbc82db..dbed00afbb 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -75,6 +75,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS # tegra241-cmdqv tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" +tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" tegra241_cmdqv_read_vcmdq_page0(int index, const char *aperture, const cha= r *backing, uint64_t offset0, uint64_t val) "vcmdq[%d] %s (%s) offset0: 0x%= "PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_read_vcmdq_page1(int index, const char *aperture, uint64_t = offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_write_vcmdq_page0(int index, const char *aperture, const ch= ar *backing, uint64_t offset0, uint64_t val) "vcmdq[%d] %s (%s) offset0: 0x= %"PRIx64" val: 0x%"PRIx64 --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637381; cv=none; d=zohomail.com; s=zohoarc; b=FBpTWFyr2t79ckNsor1t9zhf6L0n9FDXrcpjSLkL7l5WsQMolLUzqdfFbe91KWC+jdrwTci2dqtz5HM//bA2z1Uw51RmDzbilulgEyMgK6TcMaF+3PB2znCWSSiLhfArnTPY4IWhbGiqFMetePlk2p86R4ssGxh08RYO5Nv6vXg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637381; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=cW2zQrTmtXwLACpSm411lB+wI1Su9/wjqYscnJrEuVc=; b=lljTXXCiAXymUQx7jdvtPrMNjvCZ0jh45muJ9/py70rGXSXxzom91R8YayuF+GS7yNylVaRQpJ5hJV5+tvWhuTBtwoaJMQLNNwjgwxcmjF70yLYCkeuFny1joRaEST4vKFJHsGOFxAZNwkJlAt+8+/TVAkQPwSoLc9ALJMHTrV4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637381761150.0393918788526; Tue, 16 Jun 2026 12:16:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZF3-0005dR-NX; Tue, 16 Jun 2026 15:14:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8X-0004jZ-Uc for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:52 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8T-00012J-Od for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-461a15bb819so939266f8f.3 for ; Tue, 16 Jun 2026 12:07:20 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636840; x=1782241640; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cW2zQrTmtXwLACpSm411lB+wI1Su9/wjqYscnJrEuVc=; b=WVAGmlytn9DpQoFREQYE6nYN8HmhawhvawDjhd4LHoKYXL/G22D60M0fmEvMhc5etj gmerVvVU8bkSAczWd5pBB+7KkIuhyijlUBbGv2PCHfuWUKw6mqh0UKBE+V1oZbkOaQHr RHjl173N1syqH0cBMIyKUq8ZWmR/m7zOJiYXvT6Y605bo4vZJr7beyEAPyT1OVVDePat HsijOEM2knBxNDRWvKgw4NzNGFntZxFTuZv5c1o3bM2xOCLHZ0mftZDnRifFhG2bB+Le S7UgSVaxE8pWDDH+utalIRjkZ/VuMigvDVfQuV2T7YcicQ5Q9YjMflUxJh/53pNB6IWZ Sc8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636840; x=1782241640; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=cW2zQrTmtXwLACpSm411lB+wI1Su9/wjqYscnJrEuVc=; b=cWBigTOY4uqk1XhhoIaovhEUu11N2VKUQdc8IS2H0DAmggNXjNMv9zwRWn9C7uren6 r26s0CY3ammoXf6zidGx/timTy/VOLbtG0F6bx4+z0PjohYaWHXaXXeWsi6hb4/bVFP0 z8TT3ixoWdMB9QZ4ztfBt5mJEuR9cNf2HC8D0xiKB4SRToXVcfe0IX75rqbzZtehQwXZ 8v7Gsveu9KBVfotwRyvZdcIM+NYyH/F1OeDCuuDd8UhAV4Zfwvl3JzzqricFrPYCSWs6 vQJ3i1soouxw4VXGZmCxy3lsPeqsm0AvZJn489kx15UULmWlu/9YefKJ/YyEkuxau5H4 8Onw== X-Gm-Message-State: AOJu0YwjTGb8TVh9j2Tzil3NB2xJG8ykBS4gyF0OkhyoWzdvfN/RhJzb vgEeM3BeWoj2WuC3XwF9xdrb6HTPfg1PTJZNO4sJwYaIISZ1SF6UP/f+E2s43RuBMTFfHgVSclI hcJtf X-Gm-Gg: Acq92OHSYqmXxVlj+nVea5dvIQAYk6WdG7rlQ4JhaNXLjmQaTEkER1+yS7aPORcN3nr J5nWzw1WgSBPfTeI0hR085NGSwlTUK10Wxd8DUUTOjZQz0klAaqK1tc/MSr1x75kLGGAjZcAo1+ ltQTaJdC7q1jvPVxyBe5Hnm7eeUbWQdtxCAf/LFvZKMcnxxjCtluZ8cJ5RxMoJV8Dy6b0JVcTbP +rhK9zilB5I+4+OX7mb4kAH6icChpkUDgWqZR8lj0NRswR6E/RyFkHT0Lal+muVQdqA+Ha0NyrI te8drpvTASGqjJhHcqKfZ4ykyBNgBo8enERgVF5lsYA90+2U2qhYA1aCn2sFOygdUQQuY88WTsg CoSRR6Dch+hm4cnkAh/1Ql6eroQ3m9gnUEYvvP/KvWyumhU8yQO3pn/hVIf9ThGYWdUy3VOJC2x gnqXMN8faoMsA/XFWFMQCD1Tlauaa/dInIvcWteLIUdVonFrEk/PSrlg9k8n86CH2Xcnush6Ttx 0sZAyPUvyfisks7cqATYIaO6BHye6AH X-Received: by 2002:a05:6000:41e3:b0:461:9459:874c with SMTP id ffacd0b85a97d-4623fe7ddfdmr952455f8f.19.1781636839838; Tue, 16 Jun 2026 12:07:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/61] hw/arm/tegra241-cmdqv: Initialize register state on reset Date: Tue, 16 Jun 2026 20:06:11 +0100 Message-ID: <20260616190639.3462006-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637383901158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Initialize the Tegra241 CMDQV register state in the reset handler. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-25-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 38 ++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 3 +++ hw/arm/trace-events | 1 + 3 files changed, 42 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index ff0fcd1e66..0ed2a03612 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -863,6 +863,42 @@ free_viommu: return false; } =20 +static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) +{ + int i; + + cmdqv->config =3D V_CONFIG_RESET; + cmdqv->param =3D FIELD_DP32(0, PARAM, CMDQV_VER, CMDQV_VER); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_CMDQ_LOG2, + CMDQV_NUM_CMDQ_LOG2); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_SID_PER_VI_= LOG2, + CMDQV_NUM_SID_PER_VI_LOG2); + trace_tegra241_cmdqv_init_regs(cmdqv->param); + cmdqv->status =3D R_STATUS_CMDQV_ENABLED_MASK; + + for (i =3D 0; i < 2; i++) { + cmdqv->vi_err_map[i] =3D 0; + cmdqv->vi_int_mask[i] =3D 0; + } + for (i =3D 0; i < 4; i++) { + cmdqv->cmdq_err_map[i] =3D 0; + cmdqv->vintf_cmdq_err_map[i] =3D 0; + } + cmdqv->vintf_config =3D 0; + cmdqv->vintf_status =3D 0; + for (i =3D 0; i < TEGRA241_CMDQV_MAX_CMDQ; i++) { + cmdqv->cmdq_alloc_map[i] =3D 0; + cmdqv->vcmdq_cons_indx[i] =3D 0; + cmdqv->vcmdq_prod_indx[i] =3D 0; + cmdqv->vcmdq_config[i] =3D 0; + cmdqv->vcmdq_status[i] =3D 0; + cmdqv->vcmdq_gerror[i] =3D 0; + cmdqv->vcmdq_gerrorn[i] =3D 0; + cmdqv->vcmdq_base[i] =3D 0; + cmdqv->vcmdq_cons_indx_base[i] =3D 0; + } +} + static void tegra241_cmdqv_reset(SMMUv3State *s) { Tegra241CMDQV *cmdqv =3D s->s_accel->cmdqv; @@ -873,6 +909,8 @@ static void tegra241_cmdqv_reset(SMMUv3State *s) =20 tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); tegra241_cmdqv_free_all_vcmdq(cmdqv); + + tegra241_cmdqv_init_regs(s, cmdqv); } =20 static const MemoryRegionOps mmio_cmdqv_ops =3D { diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 01cd6af97d..de4c1e5335 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -89,6 +89,9 @@ FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) FIELD(CONFIG, CONS_DRAM_EN, 20, 1) =20 +/* CMDQV_EN=3D1, PER_CMD_OFFSET=3D16B, CLK_BATCH=3D256, CMD_BATCH=3D32. */ +#define V_CONFIG_RESET 0x00020083 + REG32(PARAM, 0x4) FIELD(PARAM, CMDQV_VER, 0, 4) FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index dbed00afbb..0bd718b1ab 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -76,6 +76,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" +tegra241_cmdqv_init_regs(uint32_t param) "register init, param=3D0x%08X" tegra241_cmdqv_read_vcmdq_page0(int index, const char *aperture, const cha= r *backing, uint64_t offset0, uint64_t val) "vcmdq[%d] %s (%s) offset0: 0x%= "PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_read_vcmdq_page1(int index, const char *aperture, uint64_t = offset0, uint64_t val) "vcmdq[%d] %s offset0: 0x%"PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_write_vcmdq_page0(int index, const char *aperture, const ch= ar *backing, uint64_t offset0, uint64_t val) "vcmdq[%d] %s (%s) offset0: 0x= %"PRIx64" val: 0x%"PRIx64 --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637323; cv=none; d=zohomail.com; s=zohoarc; b=jAwkuZaspQELT9hZSTZkKYxWUsxq8jRzH1dPelLCVKzwykfBShJZTR4Upiw+YDF/KNPZ255vooqPO8mSv+b0Elq/Yflkax8/vTlxm4TrqLHUW6D+5nmfMVQAY9lVNIMDOke4XxiNWXvl5F9vHJBIHzOxaXvElgneOuXCsAZZVcg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637323; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=2/1GUAAh//nPT3HEYKqYiftP4JHRiGntoWcmixhZGfs=; b=Nuhbo1lEBdgwUXvjLtWr4RomQJCR/Zb9OG+5sTEFMSBBNmgYEOPpD5PtcAZ4Cv2/kTcsSfUf74EtYgh4bRQ9+YvioxE04IbMHERCBLGxG9SyB80iC092Uxt0bENHRVyxeQLtSnmtVxfOtyt0fOUiZYS7lsh4mUbMmouQ/e0Iknc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637323295337.99146243191865; Tue, 16 Jun 2026 12:15:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAd-0007xf-J8; Tue, 16 Jun 2026 15:10:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8E-0004ZK-Ai for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:37 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ87-00012V-Mk for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:25 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-461a15bb819so939283f8f.3 for ; Tue, 16 Jun 2026 12:07:22 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636841; x=1782241641; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2/1GUAAh//nPT3HEYKqYiftP4JHRiGntoWcmixhZGfs=; b=vX4BkK7kUz2Qvd6lnOTan3iKK7wlK08zzrU36Z5KJCFXzn7azh1UBr4WXh7srewi/Q j5Axj5pQfNYTuKG6ttDsoqVE5RVk+uMTzzw4M226BtH862RwTkqlM7lVOaGxNSYFO/zz irOZN09gKymYYq+M/VC2M/ySqpdyBEQxFkh0lNDfOOJDqq/iZ119Xcm9vgsJezdr10lu ZKC6X21UG/jp8k6kkjn0979dmDuLLOZ6vYKNuxg1EIF6zSyckXHxBg9afcn55S6CgOvE AnT0665MbwKDGfIFmRPKavfq4MnN2o68xZgybWxSixj9v7gIWt7cbu1T0DgOLLx+el7b hvOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636841; x=1782241641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2/1GUAAh//nPT3HEYKqYiftP4JHRiGntoWcmixhZGfs=; b=OwlIJ2aHRCS1vteKX8EY+XJyNL7ygv6ca/3st+glnjRk1DBg37zKt7nsnuoCvHul6K 83Nc94nMKZADG+VGWA2Xqat+7pUgNH5mfkuTmv3pxK8086cxKWT5oN/l8Uu0JIL9o/gI f+s5TgaorGLrl1jQHQO5f94NaR80klxf6o6XW2Ms7eBjMTedmkFRKIbGx4iMoNoU2wBE D7m77YTAcEGk7m8JpXDXbOyaoORFe2z/wAwDOCDIDbv5VAijs2QJrGYS+6Yngg1f5woX fI8j3YSb/iBBRr+9Vfim7u/sImd4Z10PAqN/Mpj9K9BqjJPzVQFdfeLjfEbOwL6EOi5T O/YQ== X-Gm-Message-State: AOJu0YwIl42PeDHUk5Bt6IzT9/Cs/8JGJ0poq7fTOrPLcklNw7DWepgB 4g428jEc/bndreUcrQxztbOE1oNw8GlOPzvQ8qdsnqG7VjYo2b/6XVcXOuIIH6Ql6fSKInJKNi9 xYOle X-Gm-Gg: Acq92OHZDoFvIu8zs/MhLZAa17svW5Jpj5Dv2CvQ/CWNTrEYVFGGwlteNcPybMrkRt0 xrueA4TPPjbTiRuT96epbQOlm4KhxBN/XTo1iim/smFlSCCEgheZVw2lJ9RDv5SNlywmvZO3VBW lfQAHjT+9bRaSRWbATpMnDHAvW5qzzta4hR/gLav08FIqGiIONxYn6bSmJWA3zN6lfqDbySDXzS 1+kgr26WPFXElNV+dyeEgITXtOK/IPrU0WSwzrrCUNnEU1+q2FST67sJybT60xEYybtGQ5vQ43p XAN7j96rg+rNzDaSAweUr2ymkyKy0eBKxtmPjBNo5OopXgRhfKJQ4XQQ//GiTOxofQq/YgSgQRO isNeuuHpu/eHcQXg4Q8vaGF4FMEvX0DUGwBsgdfvr93rrB2VW4NDqekvC30/xkfyqdth8+iSV52 q55yommj2doZEP71r4QGY52zwfAxLmpnJCt4sACR3NPZ7OgGzRKAeVv4hJQFCiubMDmahVXoJ56 RJKJntvUvXW4COkrX5P6d3TuFfEIeND X-Received: by 2002:a05:6000:40df:b0:461:a15f:6b31 with SMTP id ffacd0b85a97d-4623f2e766dmr968329f8f.3.1781636841101; Tue, 16 Jun 2026 12:07:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/61] hw/arm/tegra241-cmdqv: Limit queue size based on backend page size Date: Tue, 16 Jun 2026 20:06:12 +0100 Message-ID: <20260616190639.3462006-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637323579158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen CMDQV HW performs DMA accesses to guest queue memory by its host physical address set up via IOMMUFD. This requires the guest queue to be contiguous in both guest PA and host PA space. With Tegra241 CMDQV enabled, we must only advertise a command queue size (CMDQS) that the host can safely back with physically contiguous memory. Allowing a queue size larger than the host page size could cause the hardware to DMA across page boundaries, leading to faults. Use qemu_minrampagesize() to find the smallest memory-backend page size in use, then cap IDR1.CMDQS so the guest cannot configure a command queue that exceeds that contiguous backing. Note this is done at SMMUv3 init, before any guest queue GPA is known, so the cap is conservative. Maximum queue size is 8MiB; it is recommended to back the VM with hugepage sizes large enough so CMDQS stays at the HW maximum. Smaller backing pages reduce CMDQS accordingly. Signed-off-by: Nicolin Chen Tested-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-26-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 0ed2a03612..4b8f8b15c7 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -14,6 +14,8 @@ #include "hw/arm/smmuv3-common.h" #include "hw/core/irq.h" #include "smmuv3-accel.h" +#include "smmuv3-internal.h" +#include "system/hostmem.h" #include "tegra241-cmdqv.h" #include "trace.h" =20 @@ -866,6 +868,8 @@ free_viommu: static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) { int i; + long pgsize; + uint32_t val; =20 cmdqv->config =3D V_CONFIG_RESET; cmdqv->param =3D FIELD_DP32(0, PARAM, CMDQV_VER, CMDQV_VER); @@ -897,6 +901,22 @@ static void tegra241_cmdqv_init_regs(SMMUv3State *s, T= egra241CMDQV *cmdqv) cmdqv->vcmdq_base[i] =3D 0; cmdqv->vcmdq_cons_indx_base[i] =3D 0; } + + /* + * CMDQ must not cross a physical RAM backend page. Adjust CMDQS so the + * queue fits entirely within the smallest backend page size, ensuring + * the command queue is physically contiguous in host memory. + * + * IDR1.CMDQS =3D log2(max_qsz) - entry_shift + * + * where entry_shift =3D 4 (each CMDQ entry is 16 bytes =3D 2^4). + */ + pgsize =3D qemu_minrampagesize(); + if (pgsize =3D=3D LONG_MAX) { + pgsize =3D qemu_real_host_page_size(); + } + val =3D FIELD_EX32(s->idr[1], IDR1, CMDQS); + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, MIN(ctz64(pgsize) - 4= , val)); } =20 static void tegra241_cmdqv_reset(SMMUv3State *s) --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637212; cv=none; d=zohomail.com; s=zohoarc; b=YYB/V+RYDUt25oWHPR3dtk3o9oLnoiAzinT3jPxYU1K8QsRDF56GF8flvX9JjxI9kJbdPBpEJn3gpTMlsQRQAA+ghaoSIACmWUHgPnY18gq5SOmiOm2X52LZr71W9eAlq0BAxCXIgor7uWng9q3UA82ZWzc62Zr+RBwkMG7uXFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637212; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=fPpiudd5fPqHqruORX0t6CTsOwaDw0XajqAXoTO5iOk=; b=WIdGqKpuPnKVTxYlVlL0cDknqXFkITZRTePnZY9cAYu9Kmf6nWjeC6NfMqJo2L6i6xafjH7vCBeFdVXxJYXa9K6kZ/p/Hid5R4aBFQzchJj9FEZ5NV+JxavDYFCcqY4+Uw70I5RKGLKu/PDhdQVhHpJmyAHoydSCynnoc5nEw3Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637212470947.3475336182822; Tue, 16 Jun 2026 12:13:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAW-00079l-NA; Tue, 16 Jun 2026 15:09:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8S-0004iD-NF for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8L-00012q-49 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:41 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-490b7866869so50207435e9.2 for ; Tue, 16 Jun 2026 12:07:23 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636842; x=1782241642; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fPpiudd5fPqHqruORX0t6CTsOwaDw0XajqAXoTO5iOk=; b=G7eNjsgp53lDwJPVzNLOb0kOJkFh4GeWM5oD5u2QMjRByffWHoX7i0wKPnbk6NUSAL jfKEOyQOdAD7IOEyHrVbwlIPh8re9HpMyC7VL46mdbrfobxvOk1lsvVSHjAWvfkW2RkZ ZOd6H2fEF3x6iuliAONIN3cinT/S6c27sta4woVHtn4Qldib9WYVRJwso/kdt6hupKxn hGCngnetyN+QljW2uAl30If5uJdl3GGXoyoGsKUVAig2M6XPY8QX3n6Ki+2SRlB0U3X1 5Fmjlp2pjJMuEDjs28vPHs4xlxCZLIvy6fw2pkVONUSjGiabRyhorcZQillT94boS8WN iXGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636842; x=1782241642; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=fPpiudd5fPqHqruORX0t6CTsOwaDw0XajqAXoTO5iOk=; b=a2EZ38BDk9tExZH0euFRM/dIaexgxU4b+tchN0f5te9A0uzMjGD6xCCCdbBRMthqRr EfULj+BqH6KrlTkdtBp6Vja9eCdVzGe1OrGUoNOecd/n9I5g7kGeZqyVCW08z/M7SW+u 9vSHWjL1o8zip5r4+pGcBbJRmayeiWbVB3xEvOgfdzW5RLeYjMX/MxpfV3ykfch9WvYE agFS5DjShLMzE3iuSvj285T/ifrhu45TCePGbSW0Kcsfdeuxf/qsCIxjytruxVMpdnwj 7aY2IipzWE7W/lASivKBu54UkwknexhsXCyirAkvNdEz63XcA0IUMJRN0L/0F1A3GTOh sceg== X-Gm-Message-State: AOJu0YzmMZ0axTWqCmU/gwSoydsvNEdnUBTrBYZ3Kd5oIypFBiywSrnc UswYytUuvg58U4HDJawh5LIHpO7Uwcq/sS7lv1IFd6JZD5pShDveAI/s9hgKaBGOPvqM3vwVthR r4lEq X-Gm-Gg: Acq92OHSQXWzHt41gezMOIrsQ+kdx4Ooa7hUsny/5ksEm7JKZ0PboCepEmbIqfK1AP2 iHnhO1zNn3MM5W2CtVR5HfZlIyysuiV/X+IebfCB+N8zZHU1ymUOIAJi8E9vfqLY2joYi3X2cNY i6HVm2qrqstE7o95nh7HXftpGufcmSx1rjIPffx8K3+rfXghvYE/Bt5QKdP0LOeOOKFgG6uulTS 9Vo1eYFb8jo/f7HhkFIVlPDC6JNtbVE6vpaAx83e3YB5i18CCWBpgBayIsCcGpZv0Pwk8W8ERcv sJTRRFSDiPUwUvwBTjJNUZyncSa4KYhD3TwdPYO6FOq/5i92pwWms1zefHvn6L0Q+0CtnqAZCEe xejRlLPCYzH39su1l8pEnOnMZtm5vweOlZbpfr9lyQRN8mX3L4vcsWyUrip7q4xvBm87xlHehG1 svcLGMmdNbpsZui5hVgF97xVxCSFXzuQkD4PbME7Fh8JNngyV+O5KM8Q/UJ6Us9D2ozbSC6IHWc ku8Dk1SMUV2+7tJU1XBX6A2G4gaoIOq X-Received: by 2002:a05:600c:4747:b0:492:1e36:bafc with SMTP id 5b1f17b1804b1-492333df104mr11337985e9.36.1781636842267; Tue, 16 Jun 2026 12:07:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/61] hw/arm/smmuv3: Add per-device identifier property Date: Tue, 16 Jun 2026 20:06:13 +0100 Message-ID: <20260616190639.3462006-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637212905158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Add an "identifier" property to the SMMUv3 device and use it when building the ACPI IORT SMMUv3 node Identifier field. This avoids relying on device enumeration order and provides a stable per-device identifier. A subsequent patch will use the same identifier when generating the DSDT description for Tegra241 CMDQV, ensuring that the IORT and DSDT entries refer to the same SMMUv3 instance. The identifier is assigned at pre-plug time, accounting for the ITS Group node that build_iort() places before SMMUv3 nodes in the IORT table, so that identifiers are globally unique across all IORT nodes. No functional change: IORT blob content for bios-tables qtest is identical to before. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-27-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 2 ++ hw/arm/virt-acpi-build.c | 5 ++++- hw/arm/virt.c | 12 ++++++++++++ include/hw/arm/smmuv3.h | 1 + 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 83fa6468fd..a8fb10e531 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2126,6 +2126,8 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + /* Identifier used for ACPI IORT SMMUv3 (and DSDT for CMDQV) generatio= n */ + DEFINE_PROP_UINT8("identifier", SMMUv3State, identifier, 0), DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index b00f3477ca..9d05982137 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -349,6 +349,7 @@ static int iort_idmap_compare(gconstpointer a, gconstpo= inter b) typedef struct AcpiIortSMMUv3Dev { int irq; hwaddr base; + uint8_t id; GArray *rc_smmu_idmaps; /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ size_t offset; @@ -411,6 +412,7 @@ static int populate_smmuv3_dev(VirtMachineState *vms, G= Array *sdev_blob) &error_abort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort= ); sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); + sdev.id =3D object_property_get_uint(obj, "identifier", &error_abo= rt); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -637,7 +639,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count); build_append_int_noprefix(table_data, node_size, 2); /* Length */ build_append_int_noprefix(table_data, 4, 1); /* Revision */ - build_append_int_noprefix(table_data, id++, 4); /* Identifier */ + build_append_int_noprefix(table_data, sdev->id, 4); /* Identifier = */ + id++; /* advance shared counter for RC/RMR node uniqueness */ /* Number of ID mappings */ build_append_int_noprefix(table_data, smmu_mapping_count, 4); /* Reference to ID Array */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 2add7401a1..d8d27f2ef6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -254,6 +254,9 @@ static MemMapEntry extended_memmap[] =3D { /* Any CXL Fixed memory windows come here */ }; =20 +/* Counts SMMUv3 devices plugged; used to assign stable IORT identifiers */ +static uint8_t smmuv3_dev_id; + static const int a15irqmap[] =3D { [VIRT_UART0] =3D 1, [VIRT_RTC] =3D 2, @@ -3830,6 +3833,15 @@ static void virt_machine_device_pre_plug_cb(HotplugH= andler *hotplug_dev, OBJECT(vms->sysmem), NULL); object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(vms->secure_sysmem), NULL); + /* + * In build_iort(), the ITS node(id=3D0) precedes SMMUv3 nodes + * when present. Account for it so this SMMUv3's identifier + * is globally unique across all IORT nodes. + */ + uint8_t its_offset =3D (vms->msi_controller =3D=3D VIRT_MSI_CT= RL_ITS) + ? 1 : 0; + object_property_set_uint(OBJECT(dev), "identifier", + its_offset + smmuv3_dev_id++, NULL); } if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { hwaddr db_start =3D 0; diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 34d0f65eaa..d39fe8850b 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -65,6 +65,7 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; char *stage; + uint8_t identifier; =20 /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637470; cv=none; d=zohomail.com; s=zohoarc; b=ZoSu4HnR9cm8sVcwCew1scKTl3Cy2hkeoYx7eFPD09fibK3EA1PB/mrptL1dVAo8TUjMxOM7J69/maXBmKRP4NOodLJKhj6zlp0KOtE2lRk6R758+jYEXD34ZyZsdQlgwUraqLnf3VfKgcXBgnsS+XhOQY4DINKQe0AtUpyAiWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637470; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=KEUPHZb5YuT1h0BGZ3M+7qfyPu+oA13cs/eRBK1qjto=; b=dops/tVCAJzoq1fr9ZH21Tgvlm2zqHAYrboMqJYlFuKrhFyJ7lEJJ+/IJzr6F8F32cRi5zimCQF5MjuxbLhr1V7wZGicUJbbKI6BaJGFPrgWcC4fjlU57WPVYm+IzPpXtMIN2EI2FiBrEQk5EeweLEdo1JZteJOdGjX1WW8LdAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637470583120.90763841730961; Tue, 16 Jun 2026 12:17:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAc-0007mx-9s; Tue, 16 Jun 2026 15:09:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8Y-0004ja-18 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:52 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8T-000130-OE for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-4624c1409c9so80163f8f.3 for ; Tue, 16 Jun 2026 12:07:24 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636843; x=1782241643; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=KEUPHZb5YuT1h0BGZ3M+7qfyPu+oA13cs/eRBK1qjto=; b=dgXWkuV/avch0Ovrr8shPMUxLQzkAzKFrL2cdkT6fT00ct77Zd7KW9kWF4tDgQ9HSW E7FoSXaOYMZ3jIIdw/AHZ0ixt5ll0/S91I/b++f5Lwj3wKzUSlj/MmSyxTz5SJKCDoZK rela/VRDr+fstOSPNmxwodgDSRC7RlmVQiU+tMz3EXtcND0uI3nq3cm+NJGjAh31CNV+ bzy2/6+zMo5C7hW3PU2Kpjl3b+YQBngxM2+npCskAyePPFjYG1NG72eXvOLCB+LGU8hr SxxFPkVQAJR4oMnnuJljdudv5UUqQBWfYHPszEvHY09imMZ3z0N0Dk/5P7YcEuU0fctk JFHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636843; x=1782241643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=KEUPHZb5YuT1h0BGZ3M+7qfyPu+oA13cs/eRBK1qjto=; b=tOBZbWuc1cD6rfuvqHX4HUipioJKeIxsaut3ZtmAohiz1p4mKK+u3SDTa1/0a6usL4 fATYcQnSnqJNNugBf+r0X92siYla8K/CPruCKUZoDun0K98naG+JNkhy2tlphoK3HaNn RPtDBPcXWgpDrmutBEQlA5RTBAX3iBv1X+adqFTkxV5ib18aPaR8aQs9+FlkuMITZY+S 71MDCaZZVcay94HLdM0Aph7GSoqPeRsKaby2XIOIWVHqDj4wRzTQdmo2zWmodZ/zTnkj u1tNoKgV1TS+ZVEXc+4G6j1fZxoClZEkog3LLO3hg5RJ5D6keMmfHYek6f56qQYKDw1g jsrg== X-Gm-Message-State: AOJu0Yy4v/8uwzuVWTvmoRR/j42io9New0KKamsEcwR7zK0U/f80pubq q78c3id7vxXziXJKX3NFIqpXHh2kAXv14/fH16xo88QaZp0kjvbqrCkYIgcvCE92MPJd7AMGDoM KUVBZ X-Gm-Gg: Acq92OHOvzd/wtff+xrGi84AUYCO5JW29kUd5fO1dwwqkCXMg93CD9jk1l/KHX0fKMe OGu24/DKlfDRTkgylp47/7eZgnFKFRSioz/XtqJiuOPR52j4tflxcjQs9mECFRyZzA1w/782dpp GCah/3GiG1WYBF6vZKRApQlzZfBGQng9HOdTwNAvZcN95lhoZunKqY2yt3BsDfZerqUq6sEHG9E 9FQVw9AIwBAX26QwxBzASf5itxb2UjoVMSfmppktEyLEMcGOdxbuNTF4ZGNzSZE7kdEFdKc8BKX B6EQDQ6SMJA1wdfgymLvNJXRQ1zfkFOc0hShp4nWLucBkOzss1WJgr1VjhIrho+Ozi3BwjfW+P7 90ZmrxTZYv/3vUtm7fuC4La16MeCj9fS0pfryYedvK0MRHetCEYEFEoqti3ZH0qAUcJfrb1WGW9 BVWVDLWUIZY/jb3ePjINvUQxaGnH2RvtnWwlORniQvDNXq7Vvww3usHevsLTtfK8KxlTMJsjquP KoXaXgY3uweDIwX2Om7q/v8mVvwr5bcJQ8zw+iDyCs= X-Received: by 2002:a05:6000:1204:b0:45e:fa7b:a7d2 with SMTP id ffacd0b85a97d-46235caf3e4mr1023486f8f.7.1781636843170; Tue, 16 Jun 2026 12:07:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/61] hw/arm/smmuv3-accel: Introduce helper to query CMDQV type Date: Tue, 16 Jun 2026 20:06:14 +0100 Message-ID: <20260616190639.3462006-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637472479158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Introduce a SMMUv3AccelCmdqvType enum and a helper to query the CMDQV implementation type associated with an accelerated SMMUv3 instance. A subsequent patch will use this helper when generating the Tegra241 CMDQV DSDT. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-28-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel-stubs.c | 5 +++++ hw/arm/smmuv3-accel.c | 12 ++++++++++++ hw/arm/smmuv3-accel.h | 10 ++++++++++ hw/arm/tegra241-cmdqv.c | 6 ++++++ 4 files changed, 33 insertions(+) diff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c index 9e6c44a282..147ae06163 100644 --- a/hw/arm/smmuv3-accel-stubs.c +++ b/hw/arm/smmuv3-accel-stubs.c @@ -57,3 +57,8 @@ bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *vev= entq, uint32_t type, void smmuv3_accel_reset(SMMUv3State *s) { } + +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj) +{ + return SMMUV3_CMDQV_NONE; +} diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index c1c2a67c97..9c3bd4413d 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -1060,6 +1060,18 @@ static void smmuv3_accel_as_init(SMMUv3State *s) address_space_init(shared_as_sysmem, &root, "smmuv3-accel-as-sysmem"); } =20 +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj) +{ + SMMUv3State *s =3D ARM_SMMUV3(obj); + SMMUv3AccelState *accel =3D s->s_accel; + + if (!accel || !accel->cmdqv_ops || !accel->cmdqv_ops->get_type) { + return SMMUV3_CMDQV_NONE; + } + + return accel->cmdqv_ops->get_type(); +} + static void smmuv3_accel_machine_done(Notifier *notifier, void *data) { SMMUv3State *s =3D container_of(notifier, SMMUv3State, machine_done); diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 8d0f636338..5fc85fb89d 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -16,6 +16,11 @@ #include #endif =20 +typedef enum SMMUv3AccelCmdqvType { + SMMUV3_CMDQV_NONE =3D 0, + SMMUV3_CMDQV_TEGRA241, +} SMMUv3AccelCmdqvType; + /* * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to * support multiple VCMDQs with virtualization capabilities. @@ -42,6 +47,10 @@ typedef struct SMMUv3AccelCmdqvOps { * If NULL, the viommu_id is freed directly via iommufd_backend_free_i= d(). */ void (*free_viommu)(SMMUv3State *s); + /** + * @get_type: Optional callback. Return the CMDQV implementation type. + */ + SMMUv3AccelCmdqvType (*get_type)(void); /** * @reset: Optional callback. Reset CMDQV state. */ @@ -90,5 +99,6 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **e= rrp); bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, void *buf, size_t size, Error **errp= ); void smmuv3_accel_reset(SMMUv3State *s); +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj); =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 4b8f8b15c7..d821eafca1 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -964,6 +964,11 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error = **errp) return true; } =20 +static SMMUv3AccelCmdqvType tegra241_cmdqv_get_type(void) +{ + return SMMUV3_CMDQV_TEGRA241; +} + static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, Error **errp) { @@ -1004,6 +1009,7 @@ static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops = =3D { .init =3D tegra241_cmdqv_init, .alloc_viommu =3D tegra241_cmdqv_alloc_viommu, .free_viommu =3D tegra241_cmdqv_free_viommu, + .get_type =3D tegra241_cmdqv_get_type, .reset =3D tegra241_cmdqv_reset, }; =20 --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637327; cv=none; d=zohomail.com; s=zohoarc; b=MrYcPNmFAlZ2cpDLhXBXWGydJRz3QpJ/Hk9z0+pQJpnK5eAGNErmgFb9mjhclO8HQ1/G3xFZTVNkrv18DmffHlErLw6ZcfkXHuaAL2RRhELJfqIXj+kWuuO0EZJ+ag+NwMvaE4akckYuUUWSFasFN0Qjb7r2M+jgOOz9uQ22dPg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637327; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=VDaWMEHLJlGMMFHNhVRPokbxg5QakMSEfI8x6+01vJo=; b=bQnOCj6mJpjw+LHgFNgGYI1pK/EQWNKbxTTEnBc7Qm25Yz7age0OevUY9S2wB1AR+Liuv+lXCD2n1zfI8MvbkaJ2aE9yyqokQMIUJLfNBufJ2lxzOu63etnErtSvrZ/igXEFPc8euE/jSZKGBWSuECyqJfQ1hYJz9Uu0ap1S5KU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637327389473.77447030595886; Tue, 16 Jun 2026 12:15:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAf-0008F1-Nv; Tue, 16 Jun 2026 15:10:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8T-0004iJ-UV for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8P-00013O-5a for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:45 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-45ee5cdbd28so112099f8f.1 for ; Tue, 16 Jun 2026 12:07:25 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636844; x=1782241644; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VDaWMEHLJlGMMFHNhVRPokbxg5QakMSEfI8x6+01vJo=; b=gRzkby7Raiskkdykg47Ba0BP9w7FG1keRbEvDeLZFs3cJyQFySVRE95tUtha53vSeS 8xubBGFN0DmmBWHKK+XYl/CIoFdUAkLJoyTxlOfSfgP82VzJsEik/gO3wS1F3u6AdXy2 4zlIUBp7PRP2r/xlR7osl494I+wVD2h8AePhz6+IiganEkIZLBF1GSSfRi/XBaRszuMJ 5U6s7lWt9fnd91NBFL7PQpXxFFXAZbKkIDEKAmNXQoK27BXoJWMgLbY4Fu1gXx7nOeZc mDLHVxvUWh7S3C/EfRBtQsEZ17pkeKvSGWYUy3SJdjJGNxeuKEt3BoPcsCxos3+f9CUV wJEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636844; x=1782241644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=VDaWMEHLJlGMMFHNhVRPokbxg5QakMSEfI8x6+01vJo=; b=lPSGbeltksSZFTuvXGVRExogZwsXRuDyKXub/94pBLr3urIHS0rCR78bqjOpeIMLk4 N53cPz+iVyo3MtiDeZ77adKLeVaqzJz6UOa/qiEkDJcnOBZ9SRDYGdycK18f9Hn2zMan G33EutEVmDabnI9Gh2TjrqT9i/H4RL23GatUNfAOOJLDSFKWzlDnz6zoeQWOpVNg3tW0 QoToLeMv66YU9CXPlWGoYpsjiSIQrS+sBHOFTAnsKxrJ/gfexn+DGmVnh/NuM09KuJRj gO4OUwSZJyLBESUZr4iGjpg+Bb4TneJqJRtkf4puGMZgJhqAUtgQu/GgvJHQUB5Gzyc1 NPNg== X-Gm-Message-State: AOJu0YxhXL5xH6tGGA4ZptEMMEK28kyzU0q4Tgv3EZi4a8OffiwF1Wql dzl0NcUSZVwKk1M2mLOUwc00tOicFAnFxUjom0CE4Ws7eC99gRfnRQe6viqJXXhldRhq+/5v2Ry bV1QD X-Gm-Gg: AfdE7cmtLiq04uJWZB97iNS3Ezd083X/Qrn+1Q1jXPqS0LsXVyBRGKudt9BLqabufFD +Q4nHIZmPM7q5TtnTivIVNH42jaRMj0OznZAXx4wZvpxyteiD4Apq2OTLsZbsnEbZXLTJeqTNiJ Omph+dBWkxkw5nYlM4w74DSuMMxeDym0JYEy3TIPoJNviO35beBzpR1FZsM1PlxSSH0oPiZ/g1s VY8s+VtttZLdjbLeZmp9/TgnzE05lLQPHeykyyjOwMeIou/IxxQsla8hWqmAVfi489gocJm53fi QYSxExFi0aY3NnveCoMxTYvmzMurWf/541cUNsUPtELMidElDrranZGATJbRgjcog5ImygNhVag FCGPkNR++SR35YKxQE88fvO7njpHaL/MER9jyBgSlIL44IhA4AiMDDrGzu1JJUy1m9q/uxxm/0T naYlryPW9MEc5w4V5mo+doSjDIzZtIhVGYBbULoItkli9SxdTCcHxHjRdTjPYRpgvjSSy4PDVor //dY+j36yAlmFs8r0ifOTYFJz7/lKFZ X-Received: by 2002:a05:6000:1ac8:b0:45e:dd32:92fa with SMTP id ffacd0b85a97d-462699af50fmr28173f8f.12.1781636844271; Tue, 16 Jun 2026 12:07:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/61] hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT Date: Tue, 16 Jun 2026 20:06:15 +0100 Message-ID: <20260616190639.3462006-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637329648158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add ACPI DSDT support for Tegra241 CMDQV when the SMMUv3 instance is created with tegra241-cmdqv. For each accelerated SMMUv3 instance, add a Tegra241 CMDQV device object under the DSDT \_SB namespace, with HID "NVDA200C" and a UID that matches the Identifier of the corresponding SMMUv3 IORT node, so the guest OS can associate the DSDT device with the right SMMU. The _CRS covers the CMDQV MMIO aperture plus its interrupt, and _CCA declares I/O cache coherency. See ACPI Specification 6.5, Section 6 (Device Configuration) for _HID/_UID/_CCA/_CRS. Generated DSDT entry for a CMDQV instance paired with SMMUv3 Identifier=3D1: ... Device (CV01) { Name (_HID, "NVDA200C") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cac= heable, ReadWrite, 0x0000000000000000, // Granularity 0x000000000C080000, // Range Minimum 0x000000000C0CFFFF, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000000000050000, // Length ,, , AddressRangeMemory, TypeStatic) Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) { 0x00000094, } }) } ... Generated IORT SMMUv3 node (Identifier =3D 1): ... [048h 0072 001h] Type : 04 [049h 0073 002h] Length : 0058 [04Bh 0075 001h] Revision : 04 [04Ch 0076 004h] Identifier : 00000001 [050h 0080 004h] Mapping Count : 00000001 [054h 0084 004h] Mapping Offset : 00000044 ... Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260609112552.378999-29-skolothumtho@nvidia.com Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/trace-events | 1 + hw/arm/virt-acpi-build.c | 52 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 0bd718b1ab..1b16f710fe 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -9,6 +9,7 @@ omap1_lpg_led(const char *onoff) "omap1 LPG: LED is %s" =20 # virt-acpi-build.c virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out." +virt_acpi_dsdt_tegra241_cmdqv(int smmu_id, uint64_t base, uint32_t irq) "D= SDT: add cmdqv node for (id=3D%d), base=3D0x%" PRIx64 ", irq=3D%d" =20 # smmu-common.c smmu_add_mr(const char *name) "%s" diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9d05982137..99490aa7b1 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -65,6 +65,9 @@ #include "target/arm/cpu.h" #include "target/arm/multiprocessing.h" =20 +#include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" + #define ARM_SPI_BASE 32 =20 #define ACPI_BUILD_TABLE_SIZE 0x20000 @@ -1121,6 +1124,51 @@ static void build_fadt_rev6(GArray *table_data, BIOS= Linker *linker, build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); } =20 +static void acpi_dsdt_add_tegra241_cmdqv(Aml *scope, VirtMachineState *vms) +{ + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + Object *obj =3D OBJECT(g_ptr_array_index(vms->smmuv3_devices, i)); + PlatformBusDevice *pbus; + Aml *dev, *crs, *addr; + SysBusDevice *sbdev; + hwaddr base; + uint32_t id; + int irq; + + if (smmuv3_accel_cmdqv_type(obj) !=3D SMMUV3_CMDQV_TEGRA241) { + continue; + } + id =3D object_property_get_uint(obj, "identifier", &error_abort); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + base =3D platform_bus_get_mmio_addr(pbus, sbdev, 1); + base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + irq =3D platform_bus_get_irqn(pbus, sbdev, NUM_SMMU_IRQS); + irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + irq +=3D ARM_SPI_BASE; + + dev =3D aml_device("CV%.02u", id); + aml_append(dev, aml_name_decl("_HID", aml_string("NVDA200C"))); + aml_append(dev, aml_name_decl("_UID", aml_int(id))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + crs =3D aml_resource_template(); + addr =3D aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_F= IXED, + AML_CACHEABLE, AML_READ_WRITE, 0x0, base, + base + TEGRA241_CMDQV_IO_LEN - 0x1, 0x0, + TEGRA241_CMDQV_IO_LEN); + aml_append(crs, addr); + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_EDGE, + AML_ACTIVE_HIGH, AML_EXCLUSIVE, + (uint32_t *)&irq, 1)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + aml_append(scope, dev); + + trace_virt_acpi_dsdt_tegra241_cmdqv(id, base, irq); + } +} + /* DSDT */ static void build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) @@ -1185,6 +1233,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, V= irtMachineState *vms) acpi_dsdt_add_tpm(scope, vms); #endif =20 + if (!vms->legacy_smmuv3_present) { + acpi_dsdt_add_tegra241_cmdqv(scope, vms); + } + aml_append(dsdt, scope); =20 pci0_scope =3D aml_scope("\\_SB.PCI0"); --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637327; cv=none; d=zohomail.com; s=zohoarc; b=gC3v6vuoag52Htn4J6LNM0xVkJDY2CuL47AKYvY0Q2+MVABe5Av0dTmtmINiVpRRRAVDMnHBdqZOG1iGzFZZw6xAZ6oHk6cV56KESO1se4qUoo9tRU9fmxbAh+gta14VVNQ3QbnUFdFPradCOZHc6TwGZaWRAaccW302MnFnXdc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637327; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DW5PvP0d6kR8ug90l3JDujZwID8eIhrnAyO6bY33H8Q=; b=cBMSDehYsb7W9sNkrroE6gsPyvaSVr9SgNxa1qS/grDc8Y1E153qILnum/0iQaQ5Hl7YF2t9BJbJE2EPoVsmXq/EgAy2RfpIbYVycX4vps1MPj65hS1iCnrVsDpJ/fOblrsgVxjRmfoK9pEiu39F3CMBq2u0j/bku7feufOCNqg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637327894670.0362609196931; Tue, 16 Jun 2026 12:15:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZFM-0006Dm-L5; Tue, 16 Jun 2026 15:14:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8Y-0004l2-88 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:52 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8T-00013e-Q4 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-490c0c92cffso32558095e9.2 for ; Tue, 16 Jun 2026 12:07:26 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636845; x=1782241645; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DW5PvP0d6kR8ug90l3JDujZwID8eIhrnAyO6bY33H8Q=; b=fYvKZYqPdeZLd7bxXw1I+qsBPYALD/cSQmD9wjut0/ZyLMPzKhZeiBXoSbELFHJE8a PL0xb3PHmPEfZdgO51VC7XxWYHYF/KWousjKrlwXsTdEx+FF65GbNHceHhbOvOFH9nBC RGCjLJ86yQ6E49dB1mYg8IWmlwbgRiBVq7kNh1SmnETjfIrGC/aHqZpWCL4rNe/D7vU8 8KekzIbKtdFWR4sSIHef+oxyRALizZZXvKmq2TiCzX9IIVo1lPTfuj51w6cI0diAyyjr z69S03R1USuFpuNr9ltzBhi8F/c9zQXGa8xdew7fFnd7ZTT1r7F3Rain2W/X2f4L9fnt Ng2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636845; x=1782241645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=DW5PvP0d6kR8ug90l3JDujZwID8eIhrnAyO6bY33H8Q=; b=Iat6QiWXFCFsICGn6QHIdiMtyzJ40iwpH6zld+Xbr6EYlBgns2V4tvIpdzWiVsktVS A9NzP1zq1u2PJTydua/3h0kl7BQFwAp4dOt5P7iHou0rUcPciK7ecVlizf8qoKNTXeRI YeXZGS9loX+J/Nnmqnb3S6oV/vfToPckcf4IVLi5QlmVMXU3OAAvWn6ua985sRAfkNuk ZYTScchTWtB0AawxIL2B0go24BhRcIbFaN1dQ3kNAec6vKCZfYDBM7yiuq5kmDjuZzSt TuDj1KsVmQoeg2Y0EHJ2HYnZGF+LPAnEYZaBw4W7rBEVUQRQ+93m+mILDvp4YD0VyM/t 8yOQ== X-Gm-Message-State: AOJu0Yx/qeDyqXAhlfshEUoYVCLKZ7gsN5qIRUdk9KgKTHI5YcQZM/fH BGbE2Lh/M+0qR2pjh1ftdzxiWeYKCdcvxbxpXdEhZoliT85onjbNBweTPP/OUwF/ZAiBX9fuhhe z3wms X-Gm-Gg: Acq92OHyLJTR3e8YO7Cwr6QZbh3rPKSlHU80ZFxMxUDCmQvn86Uo/lNsYF48EHoq8E8 +g/hOHZP4j7Do8Eqqy7UJB/L80c3wju2Onhi5WHBxsIA0bZNwfcss8oDT3La4jNbppJ5WL41OnX nW8ldov/vTzFDIAXlIKC3FsG/iQZ8mGHhjjT27KnvCMogG0Ii9xfPHl4+wEIoIikap7lw8i0s3/ W6TLkamenJl7D5+DWXdMwB8Dq9g/9suxI7k3oUg/GGYvl8tRd7h8SHXuZz+GIkAweuO4ZnI3HeN xDr8Qv77hf/F4leIzEbYwdWBEzhWtBE74b9eblElUGEUl40RlyU7Zdzm/W4uwABMiSIju4yQXYY Bz8SYBR/wmUwjQs8l7nrTbXPca7tVUrfiHH2NIweOroF7Q15VasKseHHS1qiTLdRpcGBkj2FlKt NdL4UgtxEOB0NUI80s+i/Xa2OLWItneZmkDU8QxmtWMgX0G044ogn0OQCvisWRHdkbrNpr46MPb aBKJtB6UskraZhg/BM6bohrb/UbuRtb X-Received: by 2002:a7b:cc8e:0:b0:490:bd66:db49 with SMTP id 5b1f17b1804b1-492333f5ff0mr7076835e9.12.1781636845236; Tue, 16 Jun 2026 12:07:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/61] hw/arm/smmuv3-accel: Enforce viommu association when CMDQV is active Date: Tue, 16 Jun 2026 20:06:16 +0100 Message-ID: <20260616190639.3462006-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637329624158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum When CMDQV is active, the first cold-plugged VFIO device establishes the viommu to host SMMUv3 association, and the guest's boot-time CMDQV configuration (VINTFs, VCMDQs) is built on top of that association. Hot-unplugging that device would release the viommu and tear down all CMDQV state. Hot-plugging another device behind a different host SMMUv3+CMDQV would then re-bind the same vSMMUv3 to new host hardware, while the guest keeps using its boot-time configuration and ends up issuing commands to the wrong host. Block hot-unplug of the establishing device to avoid this; retaining the binding across unplug is non-trivial and not required by any current use case. Also abort at machine_done if cmdqv=3Don is requested but no cold-plugged VFIO device was present to initialize it. Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-30-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 18 ++++++++++++++++++ hw/arm/smmuv3-accel.h | 1 + 2 files changed, 19 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 9c3bd4413d..80900c2521 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -759,6 +759,18 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus,= void *opaque, int devfn, return false; } =20 + /* + * CMDQV is active: block hot-unplug of the device that established the + * viommu association. Removing it would cause the vIOMMU to host SMMU= v3 + * association be changed via device hot-plug. + */ + if (s->s_accel->cmdqv_ops) { + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); + error_setg(&accel_dev->unplug_blocker, + "CMDQV is active: removing the device that established = the " + "viommu association would break the guest CMDQV"); + qdev_add_unplug_blocker(DEVICE(pdev), accel_dev->unplug_blocker); + } done: accel_dev->hiodi =3D hiodi; accel_dev->s_accel =3D s->s_accel; @@ -1082,6 +1094,12 @@ static void smmuv3_accel_machine_done(Notifier *noti= fier, void *data) "at least one cold-plugged VFIO device"); exit(1); } + + if (s->cmdqv =3D=3D ON_OFF_AUTO_ON && !accel->cmdqv) { + error_report("arm-smmuv3 cmdqv=3Don requires at least one cold-plu= gged " + "VFIO device"); + exit(1); + } } =20 bool smmuv3_accel_init(SMMUv3State *s, Error **errp) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 5fc85fb89d..dd755c394d 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -84,6 +84,7 @@ typedef struct SMMUv3AccelDevice { IOMMUFDVdev *vdev; QLIST_ENTRY(SMMUv3AccelDevice) next; SMMUv3AccelState *s_accel; + Error *unplug_blocker; /* set when CMDQV is active to block hot-unplug= */ } SMMUv3AccelDevice; =20 bool smmuv3_accel_init(SMMUv3State *s, Error **errp); --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637114; cv=none; d=zohomail.com; s=zohoarc; b=ExNrm1gfMlkZhDbZokxHRjia6E7M0vFuteJuuX9COKEW/NkYgGrfsQ08xjJq0L+Ku3E/MzfR//EQFWJWnXJNhtYxZ3m7sbzYsh5+Dv0aIR0On56qS/iqMlq+Wzb72r9BGIkNXmknwiygFx3oxBrD9OeIOBjHY1UKmA/YNPqk9Mg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637114; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=lXTnLo9AYMynqhYOAlIEHSPGTicUDN6Avwxqc5XliDA=; b=CiNclBBpRdDUVIWw7lmyMuwNRZvvZi11wam00i+CC3f0i8T75AjJJlFBxAQxq0a+fUm3LM/vStfu5CohVDbQpxagfGJc5o2BNLMYsFKjcR1XXoBxKpdWYYrT6XL5z9RQSKRb+Fw5oLcaQaKH1fpG/bd2LEYjYRMW80YgoqT3ggI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178163711411831.738432129779426; Tue, 16 Jun 2026 12:11:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAP-00068Z-1q; Tue, 16 Jun 2026 15:09:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8L-0004b0-EA for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:41 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8G-00013t-35 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:35 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-490b211ee6aso37313495e9.3 for ; Tue, 16 Jun 2026 12:07:27 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636846; x=1782241646; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lXTnLo9AYMynqhYOAlIEHSPGTicUDN6Avwxqc5XliDA=; b=cT8M3iET7T18YC1KcYN2E+iQXQ/dTDyxYqxDkdQxUAE2pE5ZXD/5Hkn21NJNjqUeO9 V+Gv55s2BBdxU5gO/yg1nmOTFM83rzHJ95FPzgr7a/e0yCxzG2eoj1JN6PkUUcRAmU8A oeS2uEvzD+0cRwdc153HAXy4jAnRW6kMR1WFdJss1X4TqA+SKfFpzLxhXGh306nybyFj RkYPd3xkFQKYTZEgNavJhmiM9SzVj3RRIHTBJmVzhH+CIy69X4ghMQ1gOvpCsOvpWo7/ Pfbz25PQC5VaMye84CjDu1sGWgT+byFycuSDrZIrEQuPvyboQZukYVnsWgkWcl6XF/5X jPXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636846; x=1782241646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=lXTnLo9AYMynqhYOAlIEHSPGTicUDN6Avwxqc5XliDA=; b=FDC4LlI0CKnPwRM7L/fFHAHVVnjPFNuO5WlC56Kpv3cdrfTx0vIFticcFfsjih+x2D XZFLV4GLwRAhZCHpPtE09YN0eemMei4h1X0+PYA4Q8vaNQqAOZPO4wMtIgQayg5ujUeJ LAPZmHppqR74g9XTXp7fxSi1cWFxnN36eJPn0bSz/bhVuX6ACBPRll/LmHfvRpHzQZoK 6cTaGu0+B/gtFk8fajnj6U/3nYcKLfkv1d7H/es7Azp40jPpSmEp7Bh5i2TYSWyjbjOU x+bwFfOH75fKH/WNKbosm3yX34zEx7lxiKChtnnUtAFRWHH7EI7FKX/MZ++/t/jtueGH 86tg== X-Gm-Message-State: AOJu0YwrRdS4rsJ+syopVB97MdaKbk6MyrSyTJwmNbFIzYrYLVqvWI/S fFrVKa7aFQusM5NMDlL7gRtjPWJkkT4aECBii4WWzt9OlOxL+mlDdJTzJpsOyJrlkQc1FcPzNty kajIv X-Gm-Gg: Acq92OHaOXzHwvuedTwnPao4XCSP9Be9SBQbtdCN4Gr68wxJvqfTJ1XhDsk//PHe2Q+ 5dd4OxKQlxQKY85l0KHFg0AnPROESNKUVgqfkLTU+ODrC07DylkP3dRMpl0AfFdNEtMSC2ZAH8M R2DTueHYVpb41rbCjJoIcBHlT6C52KLRzIEHQEzD9l7kARW026dWOyS6MhgMbf6NH1w6RskYAET P6mVMqAbaXPAhcpHR+F0JsMjL9uQhbAw+kbH8M766NsJ5OOmQrCjj/z+1s238BpGiAKQAQhtaLQ h67+DT+6zb2rp+N093zFlUiLdAx5OgAqoXY5/32+u1Qkmg+rL84SYzcw2h11xVvDyB9ATYu750E klEc9b2uCBeMk7v+jnNTR8kzuMmX+Vi1uuQgMLaSGMSNXCa4VhHf59MR9qM+KsrYm2Zx7jfa7J6 wkQNHXAF/H8mMkA/AYKWDkApue9V5B4HytgcYwQ+swvBJnZ1bqzU1oJfcdwUQ3ULQFH537TKrkn 8ZYfmOhC8Msvxf0gDw9U1HCabv2FNX25J8xpmsXDjU= X-Received: by 2002:a05:600c:19cb:b0:490:bb45:79f0 with SMTP id 5b1f17b1804b1-492333ba306mr13126225e9.3.1781636846123; Tue, 16 Jun 2026 12:07:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/61] hw/arm/tegra241-cmdqv: Document the CMDQV design and lifecycle Date: Tue, 16 Jun 2026 20:06:17 +0100 Message-ID: <20260616190639.3462006-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637116293158501 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Add an overview describing the Tegra241 CMDQV passthrough model, MMIO layout, guest-driven lifecycle, and per-VM isolation. Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Message-id: 20260609112552.378999-31-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/tegra241-cmdqv.c | 100 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index d821eafca1..29c488e0e4 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -7,6 +7,106 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ =20 +/* + * Tegra241 CMDQV - overview + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + * + * NVIDIA Tegra241 extends SMMUv3 with a Command Queue Virtualization (CMD= Q-V) + * block. It lets a guest issue SMMU invalidation commands directly to + * dedicated hardware queues (vCMDQs) without trapping into the hypervisor= on + * the fast path. vCMDQs are exclusively allocated to Virtual Interfaces + * (VINTFs); the host kernel allocates one VINTF per emulated SMMUv3 insta= nce + * via iommufd. QEMU emulates the CMDQV MMIO region and drives the host ke= rnel + * calls (VIOMMU_ALLOC, HW_QUEUE_ALLOC, mmap); the actual command processi= ng + * happens on real hardware. + * + * A vCMDQ becomes functional only once allocated to the host VINTF; until= then + * no command processing happens, and trapped register accesses fall back = to a + * QEMU-side cache. After allocation, the cached register state is migrate= d to + * the hardware and command processing runs on the host; guest accesses to= the + * live control/status registers then bypass QEMU and reach the host direc= tly. + * + * MMIO layout (64KB pages, total TEGRA241_CMDQV_IO_LEN) + * ----------------------------------------------------- + * 0x00000 CMDQV Config page: QEMU-trapped. + * 0x10000 Direct vCMDQ Page 0 (control/status): QEMU-trapped and routed + * to either the mmap'd host VINTF Page 0 (if the vCMDQ has been + * allocated to a VINTF) or a per-vCMDQ register cache (otherwi= se). + * 0x20000 Direct vCMDQ Page 1 (BASE / DRAM addresses): QEMU-trapped. + * 0x30000 VINTF Page 0 (per-VINTF control/status): the guest's virtual + * VINTF Page 0 aperture, backed by the host VINTF Page 0 (mmap= 'd + * via iommufd) and installed into guest MMIO as a RAM-device + * subregion when VINTF is enabled; subsequent accesses bypass = QEMU. + * 0x40000 VINTF Page 1 (per-VINTF BASE): QEMU-trapped. Although this is + * a HW alias of the direct Page 1, the kernel only exposes mmap + * for the host VINTF Page 0; the host VINTF Page 1 is not mmap= 'd + * and stays trapped. + * + * The direct vCMDQ apertures (0x10000/0x20000) are HW aliases of the VINTF + * apertures (0x30000/0x40000); they expose the same per-vCMDQ register sl= ots + * under different addressing. + * + * The direct vCMDQ Page 0 stays trapped rather than aliased to the host V= INTF + * Page 0 mmap. The CMDQV architecture allows software to program a vCMDQ + * through the direct aperture before allocating it to a VINTF; aliasing to + * the host VINTF Page 0 mmap would route those accesses into unallocated + * logical slots where the hardware silently drops them, so trapping keeps + * accesses well-defined for an unallocated vCMDQ. + * + * Lifecycle (driven by guest events) + * ---------------------------------- + * 1. First vfio-pci device attach (.set_iommu_device) triggers: + * - tegra241_cmdqv_probe(): IOMMU_GET_HW_INFO confirms host CMDQV supp= ort. + * - IOMMU_VIOMMU_ALLOC: the kernel allocates and enables a VINTF for t= his + * VM, configures the VM's VMID (from its stage-2 HWPT) in VINTF_CONF= IG, + * forces HYP_OWN=3D0, and returns the mmap offset/length for the host + * VINTF Page 0, which QEMU then mmap()s. + * + * 2. Guest writes VINTF_CONFIG.ENABLE =3D 1: + * QEMU installs the mmap'd host VINTF Page 0 into guest MMIO as the gu= est's + * virtual VINTF Page 0 aperture (a RAM-device subregion) and reports + * STATUS.ENABLE_OK =3D 1. The aperture is now a direct window onto the= host + * page, so accesses no longer trap into QEMU; a vCMDQ within it operat= es as + * a real command queue only once it has been allocated (step 3). + * + * 3. Guest completes vCMDQ setup (BASE, CMDQ_ALLOC_MAP.ALLOC, CMDQV_EN, + * VINTF.ENABLE, in any order; each precondition write retries the HW q= ueue + * allocation): + * IOMMU_HW_QUEUE_ALLOC grants the guest a new host vCMDQ in this VM's + * VINTF, binding the guest BASE GPA (translated through stage-2 and pi= nned + * by the kernel) to it. + * + * 4. Guest SMMU driver programs a Stream Table Entry for a passthrough + * device: IOMMU_VDEVICE_ALLOC programs SID_MATCH/SID_REPLACE in this V= M's + * VINTF so that the HW translates the device's guest vSID into its host + * pSID. Commands referencing unmapped SIDs are rejected by HW. + * + * This reflects the current accel SMMUv3 design, which allocates the + * vDEVICE when the guest programs the STE. + * + * Per-VM isolation + * ---------------- + * - Each VM has its own iommufd FD; all iommufd objects (VINTF, vdevices, + * hw_queues, mmap regions) belong to that FD. Cross-FD lookups fail, so + * one VM cannot reach another VM's IDs. + * - IOMMU_VIOMMU_ALLOC configures the VM's VMID in VINTF_CONFIG; the CMDQV + * hardware substitutes / checks VMID on every command the guest issues. + * - The kernel allocates the VINTF with HYP_OWN =3D 0, which restricts the + * guest to a safe subset of commands. + * - IOMMU_VDEVICE_ALLOC populates SID_MATCH/SID_REPLACE so invalidations + * only reach the host StreamIDs assigned to this VM (see step 4). + * - IOMMU_HW_QUEUE_ALLOC binds each vCMDQ to a single VINTF, so a guest + * cannot reach a vCMDQ that belongs to another VM. + * + * Limits exposed to the guest + * --------------------------- + * One VINTF per emulated SMMUv3 and two vCMDQs per VINTF. The HW maximum + * vCMDQ size is 8MiB, but the size QEMU exposes to the guest may be small= er. + * The queue must be physically contiguous in host memory, so QEMU caps the + * exposed size to the host memory-backend page size. Use hugepage backing= to + * reach the 8MiB maximum. + */ + #include "qemu/osdep.h" #include "qemu/log.h" =20 --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637328; cv=none; d=zohomail.com; s=zohoarc; b=k48/Ht8041I4PoDNiAWyZyiBrCn4rKmrALyUIjZFxGWmuyNaxYi3gZxezTFxT0TMNb0EN4f+SvwUaBUyvqFfBvKqncFZ+T7Y2S74ALf+W9VXCAfdE9b/sTMA3KnqfSg3sDSRhJGhFSltTEkMJu50TIEQIfh4E9E4RUKRIs/Ft4M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637328; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=9wCLOkdT45lh5ipdi99zooqwQLCwa4nSMaUr+Wnmkc0=; b=fckMTicQctvlSCimp/nxDN6KxrtM8Z56C2k+mlvScjbjiftGgi4/1V4TpGPlogaR54JQM82cndLV9ixkKdrs5NORY85QPEFTyM2LqNMX892HasUZL6gkSHRXlFzQ1zD8IMhcBvrmtnVOKahgis171hhQPfdFzZqCo6AQ6d1pUnk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637328250368.5234669196159; Tue, 16 Jun 2026 12:15:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAU-0006t5-I3; Tue, 16 Jun 2026 15:09:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8S-0004iE-Mz for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8L-00014J-59 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:41 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-46066e640easo3025122f8f.1 for ; Tue, 16 Jun 2026 12:07:28 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636847; x=1782241647; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=9wCLOkdT45lh5ipdi99zooqwQLCwa4nSMaUr+Wnmkc0=; b=E6Gjt4EHh7nBWAJmuvABI0o6XBM6rckFr2Q1OKsKqD7lK4UCSxgxF4YqTu33hUwKmk 4bbcTxmmIhzzqLaqLYNijeYp+O39WTzSjtS+Yeq2PXP+Mf2e9/jf+AUJc9/EyNFtcMt6 QXUMNZWlAwt64Fyi242We86LrKboG32/MQM5aC1dGFdUnId7RBtfqUTqSSkKqKWLiYXM UmBlyO5jlaw4k3EAEq/750MdVNW3p0cVWGgszgX/QOS+AjCuOgA+TwXt+P3MtAPHMZd6 wBACC4ryzHBeK1DeJwnpuVGWSQ6bIDq597PAaVxHUBNvAP4nzbrG2dvmbUOJuP4oEWeG t1Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636847; x=1782241647; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=9wCLOkdT45lh5ipdi99zooqwQLCwa4nSMaUr+Wnmkc0=; b=LIEl0HNKN2TKKEb96qTx7nOziRGL6PaacDjMlPAk1/3z888dvo51UIDVLMFKW9EmvC I7DooBxRrrfW5IC9ZHjncFKNpqm4ADR/eZFLtlSxA7V4Nah43jWiTUdYLXtFXQIU4M08 OeRYe7MqzOT9QAETqWdi/HPxCXMPtiALE3QoiZsrB4z9jBb1OiY1ToUBhfX7AmV81USM EmG84VRZ8Hka71nwLdW3xfm9jRj32Isd52IBsA5l5YNj6/JzzuDqpUim/QjXhlCbYna/ FkO/rh44IUbu0nzmKyBuoUhHYg1clQ3ngF3aZ7w0LWS0AsOI3dXkGtXDZAy/DTF4PGNn jGTg== X-Gm-Message-State: AOJu0YxdmLoxCy6lYuNxoLvBUfym9It6YgZdI+T801+kB9XE8zn5APKP MlWW58ntQfT6NMemtd5MmCKecgaDm99IMMjBKuxxXwkjr/nkOrXRR46/33iSEJbGaFt+VHIDdUV 1Tzdo X-Gm-Gg: Acq92OF1uAltI8k65Po6U+jWfQRvGMAxGuoHkhKUDSVdx6n55n5p7YnYfvehO/5OZoD 38MNB7VF8+HIQgNsYzbLMQfidrf+SLUT7+KtjGBdNfKuAeo9X9QSNk9uomUFBsXCCgn0OfdSUvD UKBvOeOTgtAK7uH4JUZxEpGLDrxCmKfnNcB4cSKhwqvbkkSMUD4eef9EfzhmqOYL9DzB0vuaKqQ oiftC9MOaub9xFNKVGD5NNkQwTVl/jbLFdFQYGt1AP2pttf7rBMZUimHbphH+Z27uPRZEOnW0MX qGefM+UV6koGPv5C/w6G1+LVwR25U+dUzFSFnQTe0YTyq+zk/EPBf0/CFXJXq9GCLyQQQxaMOOg zjQBIW37EQfNVwcSao7aEdJfHs76VA/ipvzW/W91BLwBtGIx8dg7A82ebaQIuWJF0/32o//Y24s GMpi2hdFPeFthUNfc/NwIag4WuKctqbq++LB1kxTdZbi+mIOcsEiElW8wPHRlWAgCWDJWk2KyF9 J5DNiDgxki9LUcSwRM3gnqNWvRa3hlP X-Received: by 2002:a05:6000:18a3:b0:45e:f271:5019 with SMTP id ffacd0b85a97d-46236276630mr1427244f8f.14.1781636847245; Tue, 16 Jun 2026 12:07:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/61] hw/arm/smmuv3: Add cmdqv property for SMMUv3 device Date: Tue, 16 Jun 2026 20:06:18 +0100 Message-ID: <20260616190639.3462006-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637329567158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Introduce a "cmdqv" property to enable Tegra241 CMDQV support. This is only enabled for accelerated SMMUv3 devices. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Nicolin Chen Signed-off-by: Shameer Kolothum Tested-by: Eric Auger Message-id: 20260609112552.378999-32-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 8 ++++++++ qemu-options.hx | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index a8fb10e531..5e5a6a960c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1994,6 +1994,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) "bits if accel=3Don"); return false; } + if (s->cmdqv =3D=3D ON_OFF_AUTO_ON) { + error_setg(errp, "cmdqv can only be enabled if accel=3Don"); + return false; + } return true; } =20 @@ -2144,6 +2148,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_AUTO), DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, SSID_SIZE_MODE_AUTO), + DEFINE_PROP_ON_OFF_AUTO("cmdqv", SMMUv3State, cmdqv, ON_OFF_AUTO_AUTO), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2194,6 +2199,9 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "than 0 is required to enable PASID support." "Please ensure the value does not exceed the maximum " "SubstreamID size supported by the host platform."); + object_class_property_set_description(klass, "cmdqv", + "Enable/disable CMDQV support (for accel=3Don). " + "Valid values are on, off, and auto. Defaults to auto."); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/qemu-options.hx b/qemu-options.hx index a5979d0a5b..c799286153 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1329,6 +1329,14 @@ SRST =20 - With accel=3Doff, auto is resolved to 0. =20 + ``cmdqv=3Don|off|auto`` (default: auto) + Enable hardware Command Queue Virtualization (CMDQV) for the + SMMUv3 command queue. Currently only the NVIDIA Tegra241 CMDQV + implementation is supported. + + - With accel=3Don, auto means the value is automatically derived f= rom the host SMMU. + - With accel=3Doff, auto is resolved to 'off'. + ``-device amd-iommu[,option=3D...]`` Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). Only available with ``-machine q35``, it supports the following option= s: --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637184; cv=none; d=zohomail.com; s=zohoarc; b=Hamn+YA/eof3hLxYgU/+r1eR8sMdE66upGUOPLdhG+lDbwwVwRyxpE9NQYLh7CLsPEoLnIo/H7VafT/S8lIM6JXZoeQQOW31dAhNUi4D7ByaPOx65MLTe1/MzqjsZA4iy+6MoWlAJI7VmSxqDUlaW98VNIbfsE5rDyaI5Bf0SL0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637184; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=kMc87tQ2ULiuGMs7LUUhtdlm3P0nrGr1QZBHW/A68sk=; b=ATvFRZz0Q18khKq9u+iB2njVHWkg24OmBXzgCAFptw+bpDMpjc3GYkD1KvxKO80mV/n/ApKWOy0kWiTNPc4+VAiB3Py3gkxXBOfNF/dbdIy2sOXpMFICwRHKNAU9ACqZU2u04kQVmsOitPRG938pWh79gvOA2qU/C2cWJWW2RCs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637184751528.2103144075688; Tue, 16 Jun 2026 12:13:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZBQ-00010M-Rl; Tue, 16 Jun 2026 15:10:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8S-0004iG-NU for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8L-00014e-2u for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:41 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-45ef189aa1cso3364954f8f.0 for ; Tue, 16 Jun 2026 12:07:30 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636849; x=1782241649; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kMc87tQ2ULiuGMs7LUUhtdlm3P0nrGr1QZBHW/A68sk=; b=DkBd5DBkNynmQ2IUD1LN7scgHopP8+4h8gNy0yPnlz623kay9vCxPW6Ab24/gxj3cH TlbHD9Ik3Xslq8A0VabHU4L4/5XlRC0tM78sNTThInNYIdlGDRmYKotS/9XYc7oukVHs V3JBhevXoiYdbP9Nbw6OncVW3AczaUbxKYAZpKjWZN+wksJo7/Wk9RQPAiMjourcE8To HOExz+BJu0/lENsS2gKXGrzXFnpex3baEIBGxYlhpixB7tczFvhgeq7XzLzm3rsry9Nm ssjDeK3k+1p0Uuu3AQViHzuPsom4Cbr6lb4zcqBwRC+a+paNnA+S+9wSHub1YDFLjjOk DcFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636849; x=1782241649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kMc87tQ2ULiuGMs7LUUhtdlm3P0nrGr1QZBHW/A68sk=; b=U/sdRx4PJorLR9e79g8f5ws6vWScyWgyGX9XyMyPixwkZ41on1ItquqV7+S3/B0mvG RfwIKuR31SfZBb3lSsNmOp/D/8+9UlOBHJL36Nx3/knDI+qbWLw6dWHtp52lBp7tVugk QVWGU3IAQ++Eie6LM0nVVbjf17IIuK6YczwMYLq0lptgz4bFWN2NptIm9+SMTzdb5mdU D893qGfogcv0XZG3S2nxPkzyAr2/twertqS+aGlpYgb0WrdTNdR/ajw9w6Uly3xeg+qX oDcllMO+N9SIpYQy7OokDSB5WM/zTotcxdGK8LTexJnIEVVVD/9ZzH6TBptlELPwpuYe rm9w== X-Gm-Message-State: AOJu0Yw1AgX4v5dqbqBc+uWufVyrFY0jVe3pvjHeobhLTkrW7aiqpKbh /X38K3UydkCfO2SV4hFS9i4a/ybvhgmysms1BbqjA/mNDvdYw09o8oMZ127lsRpHce+TTKW8yjr 1ru1R X-Gm-Gg: Acq92OHuKSJTqYPwyKTznrAMO/+38IujRq/CTrc/ESQRLZGdPdSRfW4VJoDMe2ZnICF EV90h7yZnQlLceI5SwdQPoVM1C43LxXOjDQ8lgtaOX4SmPv2lLSmrb8eQbRxWyzzpHOPBqWX8A1 7uzzFFHE5mLo2UMHBTy91D54u3myzLMRzTkkPqmgFZ7TKNwtJsuGhepSqFXHA+01GJBCX2kSN1J 7v/WnsADIlzyQjndLEcMcwso4IzQLO4Q7xoGPGYdS18AjEdINOtOM06imIcbuU72g/onji7xg22 jiVDGs/95mVF6IQyu5zLuoE8maeR7sNzwLw2znDE6qNfAdHN+tx7lWbg1dBsidvSL3PqGvRrZRx SoojNn3o79m38IJlCJtvnKc/tUzn6+DqaCaGUX3kCQZ663vu0Ysns4g3J/WeEgQTuySc6WOZOAT KBOA2ed3WWT0l4ZOcDKvpvUvyrXJFSDlPtjfxLEC8Ky4SM3ulfVpl/VZAzOKEnalBuJvLM4C0SN unJlGblMVrTZD/CDBxPVfp/UnaLM46F X-Received: by 2002:a05:6000:270b:b0:462:2636:2b39 with SMTP id ffacd0b85a97d-46236462425mr901749f8f.14.1781636848972; Tue, 16 Jun 2026 12:07:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/61] target/arm: honour CCR.BFHFNMIGN for probed data BusFaults Date: Tue, 16 Jun 2026 20:06:19 +0100 Message-ID: <20260616190639.3462006-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637186693158500 Content-Type: text/plain; charset="utf-8" From: Kyle Fox M-profile CCR.BFHFNMIGN lets software executing at a negative execution priority (in HardFault/NMI, or with FAULTMASK set) suppress precise data BusFaults caused by load/store instructions: the access completes returning UNKNOWN data, the fault status is recorded in BFSR/BFAR, but no BusFault exception is taken. Software uses this to probe for the presence of a device. QEMU stored CCR.BFHFNMIGN but never consumed it: arm_cpu_do_transaction_ failed() always raised the external abort, which arm_v7m_cpu_do_interrupt() pended as a BusFault and then escalated to a HardFault it could not take at priority -1, aborting the VM with "Lockup: can't escalate 3 to HardFault". Honour the bit in arm_cpu_do_transaction_failed(): when the access is a data access from M-profile code at negative priority with BFHFNMIGN set, record PRECISERR/BFARVALID and BFAR and return without raising, so the faulting instruction completes instead of re-faulting forever. Instruction fetches are unaffected, since BFHFNMIGN applies only to data accesses. The SG instruction's stack-word load is also an AccType_NORMAL data access that must honour BFHFNMIGN, but QEMU performs it manually in v7m_read_sg_stack_word() (outside the TCG TLB, so it never reaches arm_cpu_do_transaction_failed()). Apply the same suppression there: on a BusFault, record the status and, when BFHFNMIGN is set at negative priority, return the UNKNOWN data instead of pending ARMV7M_EXCP_BUS. The remaining manual EXCP_BUS sites (vector-table loads, stacking, unstacking) are AccType_VECTABLE/STACK/UNSTACK and are not required to honour the bit, so they are left unchanged. This surfaced running the real NXP i.MX 95 System Manager firmware on the emulated Cortex-M33: its SystemMemoryProbe() (set BFHFNMIGN + FAULTMASK, do the access, test CFSR.BFARVALID) locked up the VM. With this change the SM's debug-monitor memory-probe commands run and recover correctly. Signed-off-by: Kyle Fox Reviewed-by: Peter Maydell [PMM: minor tweak to v7m_read_sg_stack_word() code] Signed-off-by: Peter Maydell --- target/arm/tcg/m_helper.c | 16 ++++++++++++++-- target/arm/tcg/tlb_helper.c | 24 ++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index c5a553a5d4..f4ba93b291 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -2086,8 +2086,20 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMM= MUIdx mmu_idx, env->v7m.cfsr[M_REG_NS] |=3D (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); env->v7m.bfar =3D addr; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); - return false; + /* + * The SG instruction's stack-word load is an AccType_NORMAL data + * access, so CCR.BFHFNMIGN applies: at negative execution priority + * with BFHFNMIGN set, the BusFault is suppressed -- the access + * completes returning UNKNOWN data (status recorded above), with = no + * BusFault exception pended. + */ + if (!((env->v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK) && + armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure))) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); + return false; + } + /* BusFault suppressed; data value is UNKNOWN, we choose 0 */ + value =3D 0; } =20 *spdata =3D value; diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index f90765cb59..cbef9cb03e 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -10,6 +10,7 @@ #include "helper.h" #include "internals.h" #include "cpu-features.h" +#include "hw/intc/armv7m_nvic.h" =20 /* * Returns true if the stage 1 translation regime is using LPAE format page @@ -318,8 +319,31 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, MemTxResult response, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; ARMMMUFaultInfo fi =3D {}; =20 + /* + * For M-profile, CCR.BFHFNMIGN lets software executing at a negative + * priority (in HardFault/NMI, or with FAULTMASK set) suppress precise + * data BusFaults from load/store instructions: the access completes + * returning UNKNOWN data (the store is dropped), the fault status is + * recorded in BFSR/BFAR, but no BusFault exception is taken. This is + * the mechanism software uses to probe for the presence of a device + * (e.g. the NXP System Manager's SystemMemoryProbe). Honour it by + * recording the status and returning without raising, so the faulting + * instruction completes rather than re-faulting forever. BFHFNMIGN + * applies only to data accesses, so instruction fetches are unaffecte= d. + */ + if (arm_feature(env, ARM_FEATURE_M) && + access_type !=3D MMU_INST_FETCH && + (env->v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK) && + armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) { + env->v7m.cfsr[M_REG_NS] |=3D + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); + env->v7m.bfar =3D addr; + return; + } + /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr); =20 --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637472; cv=none; d=zohomail.com; s=zohoarc; b=hOnzr+V1nzXhkSo6oTFBFOccHmcp41o/iXnwReJL3GlQqr38fmnx5g9PM+uyIvqQ8XIBK4YHFdNicuMhLH7MzC50HGoXLw+Eck2jwItDgq2Osae26LJ59VRKqHOJl4Oyhj35XxUa3XVOOcGYPyCNW7BgiW7UwyB8Bry7O5uOCTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637472; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DDFEDfApovF7jVMAHqKHtDSTTw1A8a353M/NBq8GCgA=; b=IZU1FuhjQSnvpobiKrTfrikGRIKkx9VDN5SwRZpsjQGTcX+Mzdi8ISj1PGHrSUAX9DXX2v+GJo/r3JCQH43Tg7sql2+bzGXdn4Mp/JLGdkOTfMs89DhHkJgOiotimdVdduLBbVP4ApIZNFo6TAjjcwn/Bw7vz+qXK0CnMCRF5Yk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637472372186.17711147732348; Tue, 16 Jun 2026 12:17:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZFG-0005zF-R4; Tue, 16 Jun 2026 15:14:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8R-0004hq-VY for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:46 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8L-00015k-6u for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:40 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-46019edc13dso2389662f8f.1 for ; Tue, 16 Jun 2026 12:07:31 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636850; x=1782241650; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DDFEDfApovF7jVMAHqKHtDSTTw1A8a353M/NBq8GCgA=; b=zXQH8tgmHKux/vaqd51tvBaNn1iLMjVEgPs6xL6d6g1CPSHyBMnPhfJx749T1jNK1n GFe2PkVvgbBZsfLRr9EHlgGT9dlW6gsFVq1oollGahDxb3xnzxyS8Q4GBC2VMFvrTzqr AMri4VkYpElxw3VzjJ05/wSvljnuNGmm0loGayAIiVXYf8n9Y+SsTIhx0iismcgxi2Q0 TE69/03kzqOX+TqPgi3aqfWIHvzlXKuDA8DR2d0NKiw++DDDsugCPtcV1oWCJGhKBK5T 8/lgQNNXtSjDKbFakl5YN6WBuF7dNxP3pYlK7rb3aJyXV6wbakZMdGBVBHb0kTUYmjR4 aTkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636850; x=1782241650; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=DDFEDfApovF7jVMAHqKHtDSTTw1A8a353M/NBq8GCgA=; b=T5h1rSsb+CrSMOrKdH4cOl8pxWU59pBtJ4MSx9x4BX3LUIjpT9WGE/oRKOEOApPdPa dOdzyk/dqxVp2FJsMkXxyjRmE+OJr+04YF5VLCnjIJpPRY6ECzeMC6eQYDvdZMHdfJiV MpXaySxOMVE6ui3jzNtPsmH8DdYqHL0EjHv+1Azfjko2Y5mxvS+jHN3BS96GYPKjxt29 eJ3nWEguHN1SH/EPwN9XvkAxDhx6AjR4RYdjSRfxgtTToxVvMSO6nqIM7OHhREKEpQP5 9BC3CMvDx8u5FTkYz8rnEobmlvp6Ry6xEjDqg6PGbzb5Z0kzxaiVrPmeWkwNPlpR3i+3 eDgw== X-Gm-Message-State: AOJu0Ywnhz+dwmPC/Qn3t4qGk2lPpbTlkU050tvvBQoHToAhwaouS+IW PvLB/Oy2rk3s5n8SaG+hMKrbEIFbismZm+Ic1qpbdhL6j4pSB7jFlfzOKgEiEhsiP2uHaputoq6 p98Yj X-Gm-Gg: Acq92OEmCNiXPMutNYU86ZUokXCLMhFNBtezY5bWy9ehaAwHvZatdb3KRatHgKNN4kF yOqp77vhKlMCUxD0mOrp44wL95V85Lu7xL9P26kwQeXKxm+aJtmL72bIzCRMXNy2vftrg4Q/p6l CjixoQ6Pp5C5CrXVmNO3LaDez6pGiG5eqcvBkX4723VO2cEUUCyZwG8tuWm3QlaOI913v8MYggC zyykO6vE/v/po4winc9TkXg720rVdQKmn5nHJwlOETbaUCNsWwaGI2b37HMcF6hSLgo+mjcpT5B ucNm65J2w03evVLxi57FF5DhFLZPnURhXo7v3Sc6x1smVIenpCtohwEHhf2o9iPgD5eZb30zwLb 4i8MdlMboxLQRfT88wi6TzAf6jl3OYYyIndVJ9EvS9Y5xaYrQJx4rVTjaDYKpwBUAtn8sEYg19L ShftDwTmBW2jRdi1qBps370K3u4gjhAkTtck0dqfJ2OR9D3vIRrCi5et+YcaYFp0vuDMYonheT6 XpazaY2wsgaXKx+P/qonQfTRKXBo9B+ X-Received: by 2002:a05:6000:4007:b0:45e:f3b2:122a with SMTP id ffacd0b85a97d-46240cf969emr1017103f8f.26.1781636850116; Tue, 16 Jun 2026 12:07:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/61] hw/arm/bcm2838: Route I2C interrupts to GIC Date: Tue, 16 Jun 2026 20:06:20 +0100 Message-ID: <20260616190639.3462006-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637474514158500 From: Nicholas Righi The I2C interrupts are only routed to the legacy interrupt controller. This= means that for modern device trees that use the GIC, the interrupts don't work. T= his patch adds a splitter to route the I2C interrupt to both the legacy interrupt con= troller and the GIC. Testing Add these lines to QEMU invocation -drive if=3Dnone,id=3Di2c_storage,format=3Draw,file=3Deeprom.bin \ -device at24c-eeprom,bus=3Di2c-bus.1,address=3D0x50,drive=3Di2c_storage,rom= -size=3D4096 \ note: eeprom.bin is all zeros Before this change, running i2c get to read from EEPROM would result in this i2cget -y 1 0x50 Error: Read failed After this change, running i2c to read from EEPROM results in this i2cget -y 1 0x50 0x00 The eeprom can now also be enabled in the device tree. Before the eeprom driver load would fail due to the read failing ls -l /sys/bus/i2c/devices/i2c-1/1-0050/ | grep -i eeprom -rw------- 1 root root 4096 May 17 16:57 eeprom Signed-off-by: Nicholas Righi Message-id: 20260609024027.22140-1-nicholasrighi@gmail.com Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- hw/arm/bcm2835_peripherals.c | 9 +++++++++ hw/arm/bcm2838.c | 4 ++++ include/hw/arm/bcm2835_peripherals.h | 2 ++ include/hw/arm/bcm2838_peripherals.h | 1 + 4 files changed, 16 insertions(+) diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 8a1e72dfab..558c180df9 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -179,6 +179,8 @@ static void raspi_peripherals_base_init(Object *obj) &s->orgated_i2c_irq, TYPE_OR_IRQ); object_property_set_int(OBJECT(&s->orgated_i2c_irq), "num-lines", ORGATED_I2C_IRQ_COUNT, &error_abort); + object_initialize_child(obj, "orgated-i2c-irq-splitter", + &s->orgated_i2c_irq_splitter, TYPE_SPLIT_IRQ); } =20 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) @@ -504,7 +506,14 @@ void bcm_soc_peripherals_common_realize(DeviceState *d= ev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[n]), 0, qdev_get_gpio_in(DEVICE(&s->orgated_i2c_irq), n= )); } + + qdev_prop_set_uint32(DEVICE(&s->orgated_i2c_irq_splitter), "num-lines"= , 2); + if (!qdev_realize(DEVICE(&s->orgated_i2c_irq_splitter), NULL, errp)) { + return; + } qdev_connect_gpio_out(DEVICE(&s->orgated_i2c_irq), 0, + qdev_get_gpio_in(DEVICE(&s->orgated_i2c_irq_spli= tter), 0)); + qdev_connect_gpio_out(DEVICE(&s->orgated_i2c_irq_splitter), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_I2C)); diff --git a/hw/arm/bcm2838.c b/hw/arm/bcm2838.c index c14a854046..089af412a3 100644 --- a/hw/arm/bcm2838.c +++ b/hw/arm/bcm2838.c @@ -184,6 +184,10 @@ static void bcm2838_realize(DeviceState *dev, Error **= errp) sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->aux), 0, qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_AUX_UART= 1)); =20 + /* Connect the I2C interrupt to the interrupt controller */ + qdev_connect_gpio_out(DEVICE(&ps_base->orgated_i2c_irq_splitter), 1, + qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_I2C)); + /* Connect VC mailbox to the interrupt controller */ sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->mboxes), 0, qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_MBOX)); diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_= peripherals.h index bf35bb18e5..4f356f4643 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -33,6 +33,7 @@ #include "hw/usb/hcd-dwc2.h" #include "hw/ssi/bcm2835_spi.h" #include "hw/i2c/bcm2835_i2c.h" +#include "hw/core/split-irq.h" #include "hw/nvram/bcm2835_otp.h" #include "hw/misc/unimp.h" #include "qom/object.h" @@ -72,6 +73,7 @@ struct BCMSocPeripheralBaseState { BCM2835SPIState spi[1]; BCM2835I2CState i2c[3]; OrIRQState orgated_i2c_irq; + SplitIRQ orgated_i2c_irq_splitter; BCM2835OTPState otp; UnimplementedDeviceState dbus; UnimplementedDeviceState ave0; diff --git a/include/hw/arm/bcm2838_peripherals.h b/include/hw/arm/bcm2838_= peripherals.h index 7ee1bd066f..0be97e67c7 100644 --- a/include/hw/arm/bcm2838_peripherals.h +++ b/include/hw/arm/bcm2838_peripherals.h @@ -22,6 +22,7 @@ #define GIC_SPI_INTERRUPT_DMA_7_8 87 #define GIC_SPI_INTERRUPT_DMA_9_10 88 #define GIC_SPI_INTERRUPT_AUX_UART1 93 +#define GIC_SPI_INTERRUPT_I2C 117 #define GIC_SPI_INTERRUPT_SDHOST 120 #define GIC_SPI_INTERRUPT_UART0 121 #define GIC_SPI_INTERRUPT_RNG200 125 --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637477; cv=none; d=zohomail.com; s=zohoarc; b=L409MkCAYQpt99PMqUdbR8A+txXd48yODXp5SB6VLGW1/BxaH5E9EqgWKvNOVBKw5CDnQpFsYIVluLv4SHDODEUr02p1YPIZ8Pa1evBFeRyPygk3/aqvzUTmKzcd2ZghpokLbFiCBb5MflZlE9f2ndWrS5Ejv/OScJ/hRQ0hZXU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637477; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ghI20RlhSwol2c5KJyoQIvx6SEEjO2aKn93WrShChRM=; b=ntb+MLmvXECPXV5YVQErQ4Mg8aW5SYv8P7fiH87P3z42E3FDyOztkTLYLdgD9zddXemy17DAfXSYmfxIwZwSOVwBFOouRiJdA2MBQbFFhQqw5Su73qfIT915tbGvAhNRMxHcipvrrkH9SEFxNVvNy9X2HdsfQhCWYVhRcOG3tKI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637477245955.9513217885944; Tue, 16 Jun 2026 12:17:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZBy-0001kJ-L0; Tue, 16 Jun 2026 15:11:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8P-0004dX-OM for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:43 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8J-00017P-Fj for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:38 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-45ef56d9b67so4212628f8f.2 for ; Tue, 16 Jun 2026 12:07:32 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636851; x=1782241651; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ghI20RlhSwol2c5KJyoQIvx6SEEjO2aKn93WrShChRM=; b=kg0yBfP9G/m9i+4ls4qefKIahNEiYKHb2LRluNaSOqwXrfv3Nzhd+wsv/VAicyzB/u iGI4Gz8wo1OzTt7JfJaYP+u4RzSvWRA4GrlesenP2X42hpbgUl8Sv8amCkDHQpgssJoZ CllIV4y5utLyxcBdZP98DLy+TeX09y+JBKj4Vbin9zDnpQA/7+NZw2I7D7v3Kh51IVHt 2jaq2vGXDEaKFbEpMfrRF4EsXKaq7VzU0rDLRjfTdSQrpvinz2ENHumoy2suvfpU8k+q LkheDyXh1i3tWvjIEG863+UpyU5C6SsDg1RMolO7DuvLDlykxmv1OfK8B8X7bw66HbWW erog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636851; x=1782241651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ghI20RlhSwol2c5KJyoQIvx6SEEjO2aKn93WrShChRM=; b=a3BDTGUipBdeiCbxa2qlyoaYH5OaB+TGro+rlTFtotGzaE07N3fXBljn0DTeMryEl0 atwoCNHXYkAvdNdqyqG4LaXruEUsWL919PUGMbT7qw+WNUOaX/jORCs++1yKXT6KMB49 zJ88ixNgvPDdaKoRGoiSTVD6SGyCkKLoJv3tEEz34SDtpT0sGdFxTbHOUXXa6KM5EZ/K OVc3REQ9ocXt6vMxf3LUe16RcuI/H1O5AAzPeKyUoRVzghG1id8AGYMOgtt48mb5to7f LWviuLTftCOddOu3t92i2YXjTZLrcEkk4NeYa+wfe/KfSBCzDOptD76BMAxSy12k/+mp kR6w== X-Gm-Message-State: AOJu0YxaXeNMLlpL7xlHFCTxGoli/6Njzef8u6DgjFJXfmenlKdxLv2q USZ3wk68PsKEU/mj9edSTFCLP0IAqdv8m/rRfnMxnrwQYzYALNwrjBCuzM5Kpg7/V/aQ+832zkI X3poF X-Gm-Gg: Acq92OFi+m2ntFaFX8HavdIBSgyWQNHhnIk9fbgMyh88EPgk6g92gXY3G2TjFV6BWMA +t/efZBS2Olc/e+5JCwpi5YDVl4jh1m4Umc5YOMdcOiePlyl1s1byX93xV20XOfU9XW9ClHbG4S yP3dC3P/i6iHE5kThMqaJGIoLWJsSvaXzhivzDwutZay58P/7tgiG6z332om70nMUFJzh5e6zhN pYI/rftc8EhOLOEG+cMuDtn0tNORiOoef3C37v1DpXbmNXANAMFmtYGXO8u9uHPCG/1++5sk9BB Kh1xONIBrlN8zEgb9Al0GLvvZfJ0Ykrc3D1b8ZdwLuVhXHtvsAQzwhFCGXxtUz69prhRG+Q5MCQ /UQuGWxlx2CVlRIL6Vxwzp2YDgt4zLdV6isk5via26lGTDZtyJ86FjG7ICZZYep7gDsyq7M2S4b as5D+DvRlqUBSDCLCtCF0/25UVK+ap/Tq2Ku87lmVe8IEtEVtvH9h8xtlniEZnbF6CL/FB1/SZE qjI0oC503EMMOOMUsz3vMlNSoHuj0Ug X-Received: by 2002:a5d:5e8e:0:b0:45e:7997:8b7a with SMTP id ffacd0b85a97d-462356ec3ccmr1101595f8f.16.1781636851175; Tue, 16 Jun 2026 12:07:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/61] target/arm: Add feature predicates for SVE2.2 and SME2.2 Date: Tue, 16 Jun 2026 20:06:21 +0100 Message-ID: <20260616190639.3462006-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637478590158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 9e70d30964..a80b251589 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1516,7 +1516,12 @@ static inline bool isar_feature_aa64_sve2(const ARMI= SARegisters *id) =20 static inline bool isar_feature_aa64_sve2p1(const ARMISARegisters *id) { - return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >=3D2; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >=3D 2; +} + +static inline bool isar_feature_aa64_sve2p2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >=3D 3; } =20 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) @@ -1625,6 +1630,11 @@ static inline bool isar_feature_aa64_sme2p1(const AR= MISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) >=3D 2; } =20 +static inline bool isar_feature_aa64_sme2p2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) >=3D 3; +} + static inline bool isar_feature_aa64_f8cvt(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8CVT); @@ -1688,6 +1698,11 @@ static inline bool isar_feature_aa64_sme2p1_or_sve2p= 1(const ARMISARegisters *id) return isar_feature_aa64_sme2p1(id) || isar_feature_aa64_sve2p1(id); } =20 +static inline bool isar_feature_aa64_sme2p2_or_sve2p2(const ARMISARegister= s *id) +{ + return isar_feature_aa64_sme2p2(id) || isar_feature_aa64_sve2p2(id); +} + static inline bool isar_feature_aa64_sme2_i16i64(const ARMISARegisters *id) { return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_i16i64(id); --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637104; cv=none; d=zohomail.com; s=zohoarc; b=Tgl5ATU/oglnkSeHRegcfBNMP333SxHwLDn404eiwGIvv/snnZZ9pByMjjk4E76VAvqE97oYFGPghMchBrBY0mEtGqR0BH9EP6EIP7XHSed0ADHRGnubnEYXG80+qvhey/Jz3ae4x7yBFo7JDIzoBl7OPvVUp/yPUgdaj9lpxVI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637104; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Ah0CRDAJN/ATHeQbNI5Cn7/twLVIaLzn6NT18+EPD/Q=; b=HcyOoDNn4x/mO6jeBPpDrcnUzufKKxz8FGU7jOZUIn7vnBwM8/QT2YotouoFzBVCcRzyCFtRDwbhY0I88kJvqMIsi2CJWBsMigMCzPwMzL0LUgU5n+04avoY3is9+aSRcmQL57YgDN3h3jMIqK17fADachSHYwMmDycOpS2gY3E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637104640749.1958273153704; Tue, 16 Jun 2026 12:11:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZC7-00028m-Gv; Tue, 16 Jun 2026 15:11:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8S-0004iF-NQ for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8L-00019a-5C for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:43 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-490ac357c55so46760535e9.1 for ; Tue, 16 Jun 2026 12:07:33 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636852; x=1782241652; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ah0CRDAJN/ATHeQbNI5Cn7/twLVIaLzn6NT18+EPD/Q=; b=tsdJf5Nl/qF3Cd279Hruk4rqet3YSYutrK+bSGMVA1uhRWLKI/qtz08pXsTRWbtSgX vfo2vAdS6xupOm/NiTfDNA3gofbT6b4B1tvBBt1mplKdcS76JRA3ydgTp9kphk1AiaRs IjiRYw98AkUP6LyJ8UO9DMRbMHYze9g8Wvb8a0U6eEaI74T3G7HfVrFbXyvpDTRWEYMj /2eywn9EfsOvF2UIw4LVk1yXN9qfJ9s+7mNu4ddszsdCQaAbyBSyxePjYpD9QpYZk8Zl E9jjNPpqTJwv9DMKAo02FzoO6wEyI/nBmoOk0+bwDZMpUKkecuBOCQQRoJJPSnBo0H8v iOzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636852; x=1782241652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Ah0CRDAJN/ATHeQbNI5Cn7/twLVIaLzn6NT18+EPD/Q=; b=ZJg4zthh9TDkjxN6duLviBcZtVlXU5owb/DJkSlv30QH7+L63UY2jWH72X0cdj9nTj wvwGfPtrmBFYU/JvrYtmFNTQQvx19DxmvjdGJMeG0omh7bNL03hCSCAp+O7ffawwqhmr BAheH+j6BJrO0ZKb1qQ3aPocZCIRunpbX/JlA/lCu7O/5eUunmlDlMedg3873MJND+fM F5KX/blPggtQGGddZsq2nWjVGVeJyPV57az0ItXjlIxvFqafvmP0Gr3yAD+nAqLNTeaR K987XCz3u6QV9hhqoM4jNulUgvyDqnGL3irWBnBLd6mjhB87nWgAbJ4iz6ZwW2398ZO0 sZBA== X-Gm-Message-State: AOJu0YyyiIMBM1nXGmrNsr9BeS9/voUfThmi0Oke1WuNMzZAKMTrCYRA pl57kaBX4n6srnUbowdjKOpsPmXfoCkGnW6dpMbut5TvNZI9rxL/ekY3cBqpe59WWZQwW+R5WGF 9JeQA X-Gm-Gg: Acq92OGEfQcxQvpls0/OsGV3JVTJFUeJV52RwFRMDWjRr/Jt+htR3H4wjkCUtcgdQrl Ktle9hhjp6HyVXjJ6UubeWASsXfKflhJmFv2jWBVxku7y5+/JxxK1JrGAHgcRXTi08/wJKpAnvp Ui2/Ue0ilkPvlQibCImXCrJ/XKbhjmshguFbBLrjW4igdTzLRDKldjvPV02AFygGjmyPD20ruYR 0IQGrukFlFfnxeUBbRaLHOeGXgjpEajTKL0gKBZUgI90ZPgxhmbgSoF3iOMgZwbS5Crp2GmNlwP 5zSV5C/123HlYekjH0uN13TZQF5yuaJjXj0n7PPr2oIhiFUyhUE3HCWwIKuK0rc/xhEngntzJNa tA6GJTDnYK1bYxkDkg1C7VTcvmdVwGHrtMdXNWZ0Qxv6ahNS5AiADzYicHX/Uy9XU9i6yAyKd5H DNC2P4mDLhDxAzmUP9Zk4y+ICWBQaY6wyQRfKL0e/cKYgRI+X/LYi2JjPnG0JkYr/xHP2Bt0qkL 1ksZb81xLpJqS7G3R09R+gLZV1GV7ZuSRXCtrF7cqE= X-Received: by 2002:a05:600c:a105:b0:490:cb90:3e00 with SMTP id 5b1f17b1804b1-492333aaf90mr15981385e9.14.1781636852183; Tue, 16 Jun 2026 12:07:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/61] target/arm: Rename sve unary predicated patterns Date: Tue, 16 Jun 2026 20:06:22 +0100 Message-ID: <20260616190639.3462006-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637106263158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Add an "_m" suffix to indicate merging, in preparation for adding new predicated zeroing instructions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 152 ++++++++++++++--------------- target/arm/tcg/translate-sve.c | 169 +++++++++++++++++---------------- 2 files changed, 165 insertions(+), 156 deletions(-) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index b53fe6a58f..c7e633ec4f 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -392,24 +392,24 @@ LSL_zpzw 00000100 .. 011 011 100 ... ..... ...= .. @rdn_pg_rm =20 # SVE unary bit operations (predicated) # Note esz !=3D 0 for FABS and FNEG. -CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn -CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn -CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn -CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn -NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn -FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn -FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn +CLS_m 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn +CLZ_m 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn +CNT_zpz_m 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn +CNOT_m 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn +NOT_zpz_m 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn +FABS_m 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn +FNEG_m 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn =20 # SVE integer unary operations (predicated) # Note esz > original size for extensions. -ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn -NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn -SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn -UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn -SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn -UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn -SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn -UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn +ABS_m 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn +NEG_m 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn +SXTB_m 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn +UXTB_m 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn +SXTH_m 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn +UXTH_m 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn +SXTW_m 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn +UXTW_m 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn =20 ### SVE Floating Point Compare - Vectors Group =20 @@ -707,11 +707,11 @@ CPY_m_r 00000101 .. 101000 101 ... ..... ....= . @rd_pg_rn =20 # SVE reverse within elements # Note esz >=3D operation size -REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn -REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn -REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn -RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn -REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_= e0 +REVB_m 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn +REVH_m 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn +REVW_m 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn +RBIT_m 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn +REVD_m 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_= e0 =20 # SVE vector splice (predicated, destructive) SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm @@ -1184,59 +1184,59 @@ FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... .= .... @rdn_pg_rm_ra ### SVE FP Unary Operations Predicated Group =20 # SVE floating-point convert precision -FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_= e0 -FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_= e0 -BFCVT 01100101 10 0010 10 101 ... ..... ..... @rd_pg_rn_= e0 -FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_= e0 -FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_= e0 -FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_= e0 -FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_= e0 +FCVT_sh_m 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_= e0 +FCVT_hs_m 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_= e0 +BFCVT_m 01100101 10 0010 10 101 ... ..... ..... @rd_pg_rn_= e0 +FCVT_dh_m 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_= e0 +FCVT_hd_m 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_= e0 +FCVT_ds_m 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_= e0 +FCVT_sd_m 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_= e0 =20 # SVE floating-point convert to integer -FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_= e0 -FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_hh_m 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_hh_m 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_hs_m 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_hs_m 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_hd_m 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_hd_m 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_ss_m 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_ss_m 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_ds_m 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_ds_m 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_sd_m 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_sd_m 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_dd_m 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_dd_m 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_= e0 =20 # SVE floating-point round to integral value -FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn -FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn -FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn -FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn -FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn -FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn -FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn +FRINTN_m 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn +FRINTP_m 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn +FRINTM_m 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn +FRINTZ_m 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn +FRINTA_m 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn +FRINTX_m 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn +FRINTI_m 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn =20 # SVE floating-point unary operations -FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn -FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn +FRECPX_m 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn +FSQRT_m 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn =20 # SVE integer convert to floating-point -SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_= e0 -SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_= e0 -SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_= e0 -SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_= e0 -SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_= e0 -SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_= e0 -SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_hh_m 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_sh_m 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_dh_m 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_ss_m 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_sd_m 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_ds_m 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_dd_m 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_= e0 =20 -UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_= e0 -UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_= e0 -UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_= e0 -UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_= e0 -UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_= e0 -UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_= e0 -UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_hh_m 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_sh_m 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_dh_m 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_ss_m 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_sd_m 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_ds_m 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_dd_m 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_= e0 =20 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group =20 @@ -1517,10 +1517,10 @@ UADALP_zpzz 01000100 .. 000 101 101 ... ..... .= .... @rdm_pg_rn =20 ### SVE2 integer unary operations (predicated) =20 -URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn -URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn -SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn -SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn +URECPE_m 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn +URSQRTE_m 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn +SQABS_m 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn +SQNEG_m 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn =20 ### SVE2 saturating/rounding bitwise shift left (predicated) =20 @@ -1847,16 +1847,16 @@ SM4EKEY 01000101 00 1 ..... 11110 0 ..... .= .... @rd_rn_rm_e0 RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 =20 ### SVE2 floating-point convert precision odd elements -FCVTXNT_ds 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 -FCVTX_ds 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 -FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 -BFCVTNT 01100100 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 -FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 -FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 -FCVTLT_sd 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 +FCVTXNT_ds_m 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 +FCVTX_ds_m 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 +FCVTNT_sh_m 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 +BFCVTNT_m 01100100 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 +FCVTLT_hs_m 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 +FCVTNT_ds_m 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 +FCVTLT_sd_m 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 =20 ### SVE2 floating-point convert to integer -FLOGB 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz +FLOGB_m 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz =20 ### SVE2 floating-point multiply-add long (vectors) FMLALB_zzzw 01100100 10 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex e= sz=3D2 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index a85558bdaa..4fd17905d5 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -783,14 +783,14 @@ TRANS_FEAT(SEL_zpzz, aa64_sme_or_sve, do_sel_z, a->rd= , a->rn, a->rm, a->pg, a->e }; \ TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0) =20 -DO_ZPZ(CLS, aa64_sme_or_sve, sve_cls) -DO_ZPZ(CLZ, aa64_sme_or_sve, sve_clz) -DO_ZPZ(CNT_zpz, aa64_sme_or_sve, sve_cnt_zpz) -DO_ZPZ(CNOT, aa64_sme_or_sve, sve_cnot) -DO_ZPZ(NOT_zpz, aa64_sme_or_sve, sve_not_zpz) -DO_ZPZ(ABS, aa64_sme_or_sve, sve_abs) -DO_ZPZ(NEG, aa64_sme_or_sve, sve_neg) -DO_ZPZ(RBIT, aa64_sme_or_sve, sve_rbit) +DO_ZPZ(CLS_m, aa64_sme_or_sve, sve_cls) +DO_ZPZ(CLZ_m, aa64_sme_or_sve, sve_clz) +DO_ZPZ(CNT_zpz_m, aa64_sme_or_sve, sve_cnt_zpz) +DO_ZPZ(CNOT_m, aa64_sme_or_sve, sve_cnot) +DO_ZPZ(NOT_zpz_m, aa64_sme_or_sve, sve_not_zpz) +DO_ZPZ(ABS_m, aa64_sme_or_sve, sve_abs) +DO_ZPZ(NEG_m, aa64_sme_or_sve, sve_neg) +DO_ZPZ(RBIT_m, aa64_sme_or_sve, sve_rbit) DO_ZPZ(ORQV, aa64_sme2p1_or_sve2p1, sve2p1_orqv) DO_ZPZ(EORQV, aa64_sme2p1_or_sve2p1, sve2p1_eorqv) DO_ZPZ(ANDQV, aa64_sme2p1_or_sve2p1, sve2p1_andqv) @@ -803,7 +803,7 @@ static gen_helper_gvec_3 * const fabs_ah_fns[4] =3D { NULL, gen_helper_sve_ah_fabs_h, gen_helper_sve_ah_fabs_s, gen_helper_sve_ah_fabs_d, }; -TRANS_FEAT(FABS, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(FABS_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, s->fpcr_ah ? fabs_ah_fns[a->esz] : fabs_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const fneg_fns[4] =3D { @@ -814,34 +814,38 @@ static gen_helper_gvec_3 * const fneg_ah_fns[4] =3D { NULL, gen_helper_sve_ah_fneg_h, gen_helper_sve_ah_fneg_s, gen_helper_sve_ah_fneg_d, }; -TRANS_FEAT(FNEG, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(FNEG_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, s->fpcr_ah ? fneg_ah_fns[a->esz] : fneg_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const sxtb_fns[4] =3D { NULL, gen_helper_sve_sxtb_h, gen_helper_sve_sxtb_s, gen_helper_sve_sxtb_d, }; -TRANS_FEAT(SXTB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], = a, 0) +TRANS_FEAT(SXTB_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + sxtb_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const uxtb_fns[4] =3D { NULL, gen_helper_sve_uxtb_h, gen_helper_sve_uxtb_s, gen_helper_sve_uxtb_d, }; -TRANS_FEAT(UXTB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], = a, 0) +TRANS_FEAT(UXTB_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + uxtb_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const sxth_fns[4] =3D { NULL, NULL, gen_helper_sve_sxth_s, gen_helper_sve_sxth_d }; -TRANS_FEAT(SXTH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], = a, 0) +TRANS_FEAT(SXTH_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + sxth_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const uxth_fns[4] =3D { NULL, NULL, gen_helper_sve_uxth_s, gen_helper_sve_uxth_d }; -TRANS_FEAT(UXTH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], = a, 0) +TRANS_FEAT(UXTH_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + uxth_fns[a->esz], a, 0) =20 -TRANS_FEAT(SXTW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(SXTW_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_sxtw_d : NULL, a, 0) -TRANS_FEAT(UXTW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(UXTW_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_uxtw_d : NULL, a, 0) =20 static gen_helper_gvec_3 * const addqv_fns[4] =3D { @@ -2984,17 +2988,19 @@ static gen_helper_gvec_3 * const revb_fns[4] =3D { NULL, gen_helper_sve_revb_h, gen_helper_sve_revb_s, gen_helper_sve_revb_d, }; -TRANS_FEAT(REVB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], = a, 0) +TRANS_FEAT(REVB_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + revb_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const revh_fns[4] =3D { NULL, NULL, gen_helper_sve_revh_s, gen_helper_sve_revh_d, }; -TRANS_FEAT(REVH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], = a, 0) +TRANS_FEAT(REVH_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + revh_fns[a->esz], a, 0) =20 -TRANS_FEAT(REVW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(REVW_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_revw_d : NULL, a, 0) =20 -TRANS_FEAT(REVD, aa64_sme_or_sve2p1, gen_gvec_ool_arg_zpz, +TRANS_FEAT(REVD_m, aa64_sme_or_sve2p1, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a, 0) =20 TRANS_FEAT(SPLICE, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz, @@ -4491,53 +4497,53 @@ TRANS_FEAT(FCMLA_zzxz, aa64_sme_or_sve, gen_gvec_fp= st_zzzz, fcmla_idx_fns[a->esz *** SVE Floating Point Unary Operations Predicated Group */ =20 -TRANS_FEAT(FCVT_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_sh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sh, a, 0, FPST_A64) -TRANS_FEAT(FCVT_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_hs_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(BFCVT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(BFCVT_m, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 -TRANS_FEAT(FCVT_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_dh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_dh, a, 0, FPST_A64) -TRANS_FEAT(FCVT_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_hd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hd, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVT_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_ds, a, 0, FPST_A64) -TRANS_FEAT(FCVT_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sd, a, 0, FPST_A64) =20 -TRANS_FEAT(FCVTZS_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZU_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZS_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_hs_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hs, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZU_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_hs_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_hs, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZS_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_hd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hd, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZU_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_hd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_hd, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(FCVTZS_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_ss_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_ss, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_ss_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_ss, a, 0, FPST_A64) -TRANS_FEAT(FCVTZS_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_sd, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_sd, a, 0, FPST_A64) -TRANS_FEAT(FCVTZS_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_ds, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_ds, a, 0, FPST_A64) =20 -TRANS_FEAT(FCVTZS_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_dd, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_dd, a, 0, FPST_A64) =20 static gen_helper_gvec_3_ptr * const frint_fns[] =3D { @@ -4546,8 +4552,9 @@ static gen_helper_gvec_3_ptr * const frint_fns[] =3D { gen_helper_sve_frint_s, gen_helper_sve_frint_d }; -TRANS_FEAT(FRINTI, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->es= z], - a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) +TRANS_FEAT(FRINTI_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, + frint_fns[a->esz], a, 0, + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static gen_helper_gvec_3_ptr * const frintx_fns[] =3D { NULL, @@ -4555,8 +4562,9 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] =3D= { gen_helper_sve_frintx_s, gen_helper_sve_frintx_d }; -TRANS_FEAT(FRINTX, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->e= sz], - a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); +TRANS_FEAT(FRINTX_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, + frintx_fns[a->esz], a, 0, + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); =20 static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, ARMFPRounding mode, gen_helper_gvec_3_ptr *fn) @@ -4585,63 +4593,64 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_= esz *a, return true; } =20 -TRANS_FEAT(FRINTN, aa64_sme_or_sve, do_frint_mode, a, +TRANS_FEAT(FRINTN_m, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_TIEEVEN, frint_fns[a->esz]) -TRANS_FEAT(FRINTP, aa64_sme_or_sve, do_frint_mode, a, +TRANS_FEAT(FRINTP_m, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_POSINF, frint_fns[a->esz]) -TRANS_FEAT(FRINTM, aa64_sme_or_sve, do_frint_mode, a, +TRANS_FEAT(FRINTM_m, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_NEGINF, frint_fns[a->esz]) -TRANS_FEAT(FRINTZ, aa64_sme_or_sve, do_frint_mode, a, +TRANS_FEAT(FRINTZ_m, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_ZERO, frint_fns[a->esz]) -TRANS_FEAT(FRINTA, aa64_sme_or_sve, do_frint_mode, a, +TRANS_FEAT(FRINTA_m, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_TIEAWAY, frint_fns[a->esz]) =20 static gen_helper_gvec_3_ptr * const frecpx_fns[] =3D { NULL, gen_helper_sve_frecpx_h, gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d, }; -TRANS_FEAT(FRECPX, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->e= sz], - a, 0, select_ah_fpst(s, a->esz)) +TRANS_FEAT(FRECPX_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, + frecpx_fns[a->esz], a, 0, select_ah_fpst(s, a->esz)) =20 static gen_helper_gvec_3_ptr * const fsqrt_fns[] =3D { NULL, gen_helper_sve_fsqrt_h, gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d, }; -TRANS_FEAT(FSQRT, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz= ], - a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) +TRANS_FEAT(FSQRT_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, + fsqrt_fns[a->esz], a, 0, + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 -TRANS_FEAT(SCVTF_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(SCVTF_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_sh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_sh, a, 0, FPST_A64_F16) -TRANS_FEAT(SCVTF_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_dh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_dh, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(SCVTF_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_ss_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_ss, a, 0, FPST_A64) -TRANS_FEAT(SCVTF_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_ds, a, 0, FPST_A64) =20 -TRANS_FEAT(SCVTF_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_sd, a, 0, FPST_A64) -TRANS_FEAT(SCVTF_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_dd, a, 0, FPST_A64) =20 -TRANS_FEAT(UCVTF_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(UCVTF_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_sh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_sh, a, 0, FPST_A64_F16) -TRANS_FEAT(UCVTF_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_dh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_dh, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(UCVTF_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_ss_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_ss, a, 0, FPST_A64) -TRANS_FEAT(UCVTF_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_ds, a, 0, FPST_A64) -TRANS_FEAT(UCVTF_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_sd, a, 0, FPST_A64) =20 -TRANS_FEAT(UCVTF_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_dd, a, 0, FPST_A64) =20 /* @@ -6691,23 +6700,23 @@ TRANS_FEAT(UADALP_zpzz, aa64_sme_or_sve2, gen_gvec_= ool_arg_zpzz, * SVE2 integer unary operations (predicated) */ =20 -TRANS_FEAT(URECPE, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, +TRANS_FEAT(URECPE_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, a->esz =3D=3D 2 ? gen_helper_sve2_urecpe_s : NULL, a, 0) =20 -TRANS_FEAT(URSQRTE, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, +TRANS_FEAT(URSQRTE_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, a->esz =3D=3D 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 0) =20 static gen_helper_gvec_3 * const sqabs_fns[4] =3D { gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h, gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d, }; -TRANS_FEAT(SQABS, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz= ], a, 0) +TRANS_FEAT(SQABS_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->e= sz], a, 0) =20 static gen_helper_gvec_3 * const sqneg_fns[4] =3D { gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h, gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d, }; -TRANS_FEAT(SQNEG, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz= ], a, 0) +TRANS_FEAT(SQNEG_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->e= sz], a, 0) =20 DO_ZPZZ(SQSHL, aa64_sme_or_sve2, sve2_sqshl) DO_ZPZZ(SQRSHL, aa64_sme_or_sve2, sve2_sqrshl) @@ -7879,30 +7888,30 @@ static bool trans_RAX1(DisasContext *s, arg_RAX1 *a) return gen_gvec_fn_arg_zzz(s, gen_gvec_rax1, a); } =20 -TRANS_FEAT(FCVTNT_sh, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) -TRANS_FEAT(FCVTNT_ds, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTNT_ds_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64) =20 -TRANS_FEAT(BFCVTNT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(BFCVTNT_m, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvtnt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 -TRANS_FEAT(FCVTLT_hs, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTLT_hs_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTLT_sd, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTLT_sd_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64) =20 -TRANS_FEAT(FCVTX_ds, aa64_sme_or_sve2, do_frint_mode, a, +TRANS_FEAT(FCVTX_ds_m, aa64_sme_or_sve2, do_frint_mode, a, FPROUNDING_ODD, gen_helper_sve_fcvt_ds) -TRANS_FEAT(FCVTXNT_ds, aa64_sme_or_sve2, do_frint_mode, a, +TRANS_FEAT(FCVTXNT_ds_m, aa64_sme_or_sve2, do_frint_mode, a, FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds) =20 static gen_helper_gvec_3_ptr * const flogb_fns[] =3D { NULL, gen_helper_flogb_h, gen_helper_flogb_s, gen_helper_flogb_d }; -TRANS_FEAT(FLOGB, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->es= z], +TRANS_FEAT(FLOGB_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->= esz], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool= sel) --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637463; cv=none; d=zohomail.com; s=zohoarc; b=lYzpD0rbQW1kQBkRRSaCRcVcc3aT4WP3cVYvz07VcxBYuW3pdpBga5Da31iAibEaesT9v1UfvXsRssL8/zns77+QbbPl/XAFC3JubPN+mXjjTTEjcF2h/K5A3Jh2JC6jdJe6UVCtanDEDaON4QWkPnzIfT/Wd9P+k0HPZgOfCl8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637463; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=va+Qk8Dozw43WMNLNX2dHO7L1LT7PhC4dtXopinZQmE=; b=GAVeKYKxZNlAalQUNcDHdl1VPX53uOvBKg3pIGBxa0lGsvSqf6C3nXjE4B4cAcOrSnUHO0txNwm0BFY0o4HT6J/DeFlQLk7t5/QwfpS6/jlFLKUaxP3bmX+0SuGbpJ5iClOjzggqrRflMqIHQis4GHMNgXxL9gU1Prgo2IkMdRI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178163746380319.84542090586035; Tue, 16 Jun 2026 12:17:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZFI-00066V-K2; Tue, 16 Jun 2026 15:14:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8R-0004hi-S1 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:46 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8L-0001AZ-2P for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:40 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-4624c1409c9so80241f8f.3 for ; Tue, 16 Jun 2026 12:07:35 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636853; x=1782241653; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=va+Qk8Dozw43WMNLNX2dHO7L1LT7PhC4dtXopinZQmE=; b=cK3y/W0UD47twVhzMTm2TnWpUxXbUfGhJJ3byYkvwj9ijbA4YLceDApjdJwXwJtr5D TvnyQ5nZnZaTDc9VpHoM7fTfktOJAiAoFw9HXcHzKLcttn+9y1eyNh6AX5A+Ww4lH1JP 9vfB8TmdmdzE3N2+H7ApKc3NPFj1NQs0zPQU3ZztM43zYZjEMV1n79d19T9htAxX/3rp CJ/t+vSkjJYDtFEaZwuDz1QxUgX9fIBvrGZyCUw02a34HN/lgfLCZC2RPQaEvUJVjDPt v5heHwAR9qLEZ5uZcfaO2c0myeTGAISZ8lMpQd8ZsWB29vgzkh0Ugq6OnHwtUbqU3u1x 6bag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636853; x=1782241653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=va+Qk8Dozw43WMNLNX2dHO7L1LT7PhC4dtXopinZQmE=; b=XF1s3+CudBs7/9Cd4PuA4d+9sm3/exexGJZdMNsR/PMy0SGqcPQCreg8RjLBfCln3Y NvYjFLYcHSzGUtzte7cF82pK0M+9XA470uiE09Un9prdhSd9oBipOtqrwupgjaUPunMi aer6sPyOwH9lsxw/LLJJ0SATDhq0BfCyWJPGe4sSHVNgDt6TevoAOKv+t7qowl7xwedc 1bT6rekUryFkRaAG/LtOoWNV18TaaAbxcoAPJYjJozllViRq8W5aOfJsOXVO05ZlRTcO uf3343vIxxH6utndhNyIXjGPsor52ChfCdJFr8DIeCdGpLiO93AnnWm9XzpYX3mfHo96 25ZA== X-Gm-Message-State: AOJu0Yz7xbtcUNHDnmc8ZwG2j/BB5NFLbciWm5EBy7+vm59+LZkJDItU wK4f7bVtmvRIEg3QCynGTJS36Nm1EvNEe4yQUVwBivQYgF4gX28os9kOgBRe/OjJyZ+1yvKCqOL X3aM1 X-Gm-Gg: Acq92OGIezFJ/jG43buUeCi7vlXRsy619S373QqRecna5ZVds73gfxBHQZuVOozO+RN wUQiISf+OySDLfnTWxnFqDSE9CSVua1SjPBgXK7NXXj//vzKXvkxBSm3r99vdpibliB4r/cKjzZ qd38/A3SJmXdaakkb0HaEPb+bYpl6viJwTfEbhALFlSuNN3Za64ZE4crS/g9r12/YWt12O1Bhub tZkFZB67T4apD8C5e1SdirkHGDLgtA3kbVXH7nKOSNtLTlkUsncF3oscW9ukZeDQz8fN+oibl95 FptmRWaxbutm/VW7BcUbFNfstczAIK93m5u869DqDMTE1ynj8qLMiMfk6ZHEiqYYJny5Usrcoob LEejytL9ILvVtuPEs0Nl3jP+JFvzg+Q0cDDHMamL63loOKvVuv72fi8QubepKHhlbBQmhuR4uLW TZnObXp8388g2t2BrbUmrdtFdP+2Ogor7pKD9kliaKj5Sqlcpr+SBjTY3d/k+6E+7JD0y8qJ0ye 2izy5gXvcGvaC18Cbq4cnjndYhv2K76 X-Received: by 2002:a5d:68d0:0:b0:460:3233:beed with SMTP id ffacd0b85a97d-4623908e2fbmr997333f8f.41.1781636853170; Tue, 16 Jun 2026 12:07:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/61] target/arm: Enable zeroing in DO_ZPZ macros in sve_helper.c Date: Tue, 16 Jun 2026 20:06:23 +0100 Message-ID: <20260616190639.3462006-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637464478158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use the low bit of simd_data to hold a 'zeroing' bit. The simd_data field is currently unused and always 0. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_helper.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index d05d8addfd..9634517925 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -823,18 +823,20 @@ DO_ZPZW(sve_lsl_zpzw_s, uint32_t, uint64_t, H1_4, DO_= LSL) =20 #undef DO_ZPZW =20 -/* Fully general two-operand expander, controlled by a predicate. - */ +/* Fully general two-operand expander, controlled by a predicate. */ #define DO_ZPZ(NAME, TYPE, H, OP) \ void HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \ { \ intptr_t i, opr_sz =3D simd_oprsz(desc); \ + bool zeroing =3D simd_data(desc) & 1; \ for (i =3D 0; i < opr_sz; ) { \ uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ do { \ if (pg & 1) { \ TYPE nn =3D *(TYPE *)(vn + H(i)); \ *(TYPE *)(vd + H(i)) =3D OP(nn); \ + } else if (zeroing) { \ + *(TYPE *)(vd + H(i)) =3D 0; \ } \ i +=3D sizeof(TYPE), pg >>=3D sizeof(TYPE); \ } while (i & 15); \ @@ -846,12 +848,15 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, uint3= 2_t desc) \ void HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \ { \ intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; \ + bool zeroing =3D simd_data(desc) & 1; \ TYPE *d =3D vd, *n =3D vn; \ uint8_t *pg =3D vg; \ for (i =3D 0; i < opr_sz; i +=3D 1) { \ if (pg[H1(i)] & 1) { \ TYPE nn =3D n[i]; \ d[i] =3D OP(nn); \ + } else if (zeroing) { \ + d[i] =3D 0; \ } \ } \ } @@ -4831,7 +4836,8 @@ DO_ZPZS_FP(sve_ah_fmins_h, float16, H1_2, helper_vfp_= ah_minh) DO_ZPZS_FP(sve_ah_fmins_s, float32, H1_4, helper_vfp_ah_mins) DO_ZPZS_FP(sve_ah_fmins_d, float64, H1_8, helper_vfp_ah_mind) =20 -/* Fully general two-operand expander, controlled by a predicate, +/* + * Fully general two-operand expander, controlled by a predicate, * With the extra float_status parameter. */ #define DO_ZPZ_FP(NAME, TYPE, H, OP) \ @@ -4839,6 +4845,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, = \ float_status *status, uint32_t desc) \ { \ intptr_t i =3D simd_oprsz(desc); \ + bool zeroing =3D simd_data(desc) & 1; \ uint64_t *g =3D vg; \ do { \ uint64_t pg =3D g[(i - 1) >> 6]; \ @@ -4847,6 +4854,8 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, = \ if (likely((pg >> (i & 63)) & 1)) { \ TYPE nn =3D *(TYPE *)(vn + H(i)); \ *(TYPE *)(vd + H(i)) =3D OP(nn, status); \ + } else if (zeroing) { \ + *(TYPE *)(vd + H(i)) =3D 0; \ } \ } while (i & 63); \ } while (i !=3D 0); \ --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637340; cv=none; d=zohomail.com; s=zohoarc; b=WgmcVVKbpQySCNcN2D+ShlpJjEjQ58EwnihLeS2+hzmXygIYrur+MZYMnoOkhFCBxnzkVwmPeErVeYUqgQk8wLEDrlaWJAmolgJgr7uKImnzcq9BNhlSIDtesU8Dc/I/ZMAJWw7nN7xwGT/GFlJB9uMn18OrCP6IGOuwhM36oyY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637340; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=JXl9aM3YjYB0IaDfx/Jq49OoS0qkx8Ry7BVlhdhFJ5k=; b=nC1mMZfaKZWbPFkdXOUUqsesDrk4rY2q0Ybwp71jfZrr73s4SoEGLwafS2p3IZptrQBA1oczjcN5pIpjdlIoptBUJzVdXaGH9/Mhd8fk/C0WBXUKN3jO4D93335YCeACvDX2f/vp14D1rDu1JguwkNE6iqvJ9VvCCGLaMoJ1UFY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637340430980.5454081711257; Tue, 16 Jun 2026 12:15:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZFK-0006A1-0s; Tue, 16 Jun 2026 15:14:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8Q-0004dj-1A for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:44 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8K-0001Aa-Vt for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:38 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-461a15bb819so939451f8f.3 for ; Tue, 16 Jun 2026 12:07:35 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636854; x=1782241654; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JXl9aM3YjYB0IaDfx/Jq49OoS0qkx8Ry7BVlhdhFJ5k=; b=x6TH0RjTXW5yNJ5O0mRns8SusjeUzDgZxlU+vjnud/39kLCXxFtdWOvQW6OtJuaZdm pl/HUsock7sva5GhrTpmn9yFxrW7oFFPmBjK4TuSmrBj5dnZ3GKzyjTWQZ+26nJkDYER IsMpg8VJFFDtWKbOvkkqsfVl2hl7vy/kX9UURm4aWccRTOKpm9vrkAt/TEU9mK3mO8My HrPGic47hryU3DdDa4XtBqqzYvbYcsTYs+y6P+sPANxzyDjGIefY5DKB+IYHcISXhTh/ u8rjfjSBfWZZd/qj8IA9SQGl2s5wHEf9Y6Wr9dHWo6NNZ6kx3PUbMOW0jb3W6BC9WK34 eq6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636854; x=1782241654; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=JXl9aM3YjYB0IaDfx/Jq49OoS0qkx8Ry7BVlhdhFJ5k=; b=IfnsUICn3SbdmKriA1s8b0Q7OExLGghb/Yq7QSQobEhYuWYPtRYbd3rNYsCbktm1mh nfgZooqffWq+XhG2Rc0cpLNHXhXnaPWYkdIteN7wRMx1wVdIPAgVCX7smlE8VHO5Tu/a 5tLuoDL3j2QbacWpq0UpTLlB67gTcrDxuKw5dyIxTG7aCQH72KA2yDT7VdicplfMU3Hy chxCCqGuln1FBCvWGChVa6nrOLFfr+FrKpEE2aeseCnfFFJwwZedmnvSgmG1pHXQjOXp c7cwsNQUtg18ASmxaYES6PNI2eETSpOVLdl6dXEnuMa//FLZg+8uCaZDWMPVSxpU99cp szsA== X-Gm-Message-State: AOJu0YxXph/r1utQGbNTRD42FWpSnOxy52d8aOb4IQNQ0eC/Cix8V4Z/ RbAa7ZL5pRzmALRG+CSvm0FRMZULx8YBAhwbDmvpniQ63ZTPevqGM41C4+ZN4Wm2CA7rjlcNUf7 pNLKr X-Gm-Gg: Acq92OGWzEvNvuxDDr27sqvrZEsYAQoI1QVXcedHQ+035AGMXfVRlpDf2Zj/ZlMCG1b pDCFDPtiVXwOl9d4NRmIVYykPbMvPrwTI/EMtpdvcXeUOLjhMKQ0xIaP1e5qYKU0xELH9uTo1yQ A7YZYEiixe9ufzYo31bvzyujwcgow4jxalYuQgj+yZTdiAoChtqqOWmcB/rKf478CpHc0H7wJLn s7F5yF63flC7Xy0fox4DeSeRqkD9VhkjUVe9yk66E2uIIOrkQ209krI/lr5vozAz/VNj+GthFRu mb7ahY+kUpCvJsV3uYa10MzraXlxkK9rEU9lpadU9+ctswZkpWC/UtJS/ERVWFDBrZi4mabTxyU /3DLpyxK7LD285OaoPOVYkjJscy01GBsDWMmR0Rb0+Kxow6ANFfBl7qPQKPrHkO5R+k7mJROl0Q FvMzDtILLGWuMzHBxef6Mg0kw6k4tzOQg15xIiWjzXF8RcBA61mAEjfrySA9h0hC4KBiEFVCTaq cY/HeacmIreKZCnGJaxkZV0xl6uqz7e X-Received: by 2002:a05:6000:22c4:b0:45e:fb69:f02b with SMTP id ffacd0b85a97d-4623f2e7641mr943955f8f.1.1781636854169; Tue, 16 Jun 2026 12:07:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 47/61] target/arm: Expand DO_ZPZ in translate-sve.c Date: Tue, 16 Jun 2026 20:06:24 +0100 Message-ID: <20260616190639.3462006-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637341673158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Prepare for adding zeroing instructions for some of these. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-sve.c | 84 +++++++++++++++++++++++++++------- 1 file changed, 67 insertions(+), 17 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 4fd17905d5..8ab4526468 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -776,24 +776,74 @@ TRANS_FEAT(SEL_zpzz, aa64_sme_or_sve, do_sel_z, a->rd= , a->rn, a->rm, a->pg, a->e *** SVE Integer Arithmetic - Unary Predicated Group */ =20 -#define DO_ZPZ(NAME, FEAT, name) \ - static gen_helper_gvec_3 * const name##_fns[4] =3D { \ - gen_helper_##name##_b, gen_helper_##name##_h, \ - gen_helper_##name##_s, gen_helper_##name##_d, \ - }; \ - TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0) +static gen_helper_gvec_3 * const sve_cls_fns[4] =3D { + gen_helper_sve_cls_b, gen_helper_sve_cls_h, + gen_helper_sve_cls_s, gen_helper_sve_cls_d, +}; +TRANS_FEAT(CLS_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_cls_fns[a->es= z], a, 0) =20 -DO_ZPZ(CLS_m, aa64_sme_or_sve, sve_cls) -DO_ZPZ(CLZ_m, aa64_sme_or_sve, sve_clz) -DO_ZPZ(CNT_zpz_m, aa64_sme_or_sve, sve_cnt_zpz) -DO_ZPZ(CNOT_m, aa64_sme_or_sve, sve_cnot) -DO_ZPZ(NOT_zpz_m, aa64_sme_or_sve, sve_not_zpz) -DO_ZPZ(ABS_m, aa64_sme_or_sve, sve_abs) -DO_ZPZ(NEG_m, aa64_sme_or_sve, sve_neg) -DO_ZPZ(RBIT_m, aa64_sme_or_sve, sve_rbit) -DO_ZPZ(ORQV, aa64_sme2p1_or_sve2p1, sve2p1_orqv) -DO_ZPZ(EORQV, aa64_sme2p1_or_sve2p1, sve2p1_eorqv) -DO_ZPZ(ANDQV, aa64_sme2p1_or_sve2p1, sve2p1_andqv) +static gen_helper_gvec_3 * const sve_clz_fns[4] =3D { + gen_helper_sve_clz_b, gen_helper_sve_clz_h, + gen_helper_sve_clz_s, gen_helper_sve_clz_d, +}; +TRANS_FEAT(CLZ_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_clz_fns[a->es= z], a, 0) + +static gen_helper_gvec_3 * const sve_cnt_zpz_fns[4] =3D { + gen_helper_sve_cnt_zpz_b, gen_helper_sve_cnt_zpz_h, + gen_helper_sve_cnt_zpz_s, gen_helper_sve_cnt_zpz_d, +}; +TRANS_FEAT(CNT_zpz_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_cnt_zpz_f= ns[a->esz], a, 0) + +static gen_helper_gvec_3 * const sve_cnot_fns[4] =3D { + gen_helper_sve_cnot_b, gen_helper_sve_cnot_h, + gen_helper_sve_cnot_s, gen_helper_sve_cnot_d, +}; +TRANS_FEAT(CNOT_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_cnot_fns[a->= esz], a, 0) + +static gen_helper_gvec_3 * const sve_not_zpz_fns[4] =3D { + gen_helper_sve_not_zpz_b, gen_helper_sve_not_zpz_h, + gen_helper_sve_not_zpz_s, gen_helper_sve_not_zpz_d, +}; +TRANS_FEAT(NOT_zpz_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_not_zpz_f= ns[a->esz], a, 0) + +static gen_helper_gvec_3 * const sve_abs_fns[4] =3D { + gen_helper_sve_abs_b, gen_helper_sve_abs_h, + gen_helper_sve_abs_s, gen_helper_sve_abs_d, +}; +TRANS_FEAT(ABS_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_abs_fns[a->es= z], a, 0) + +static gen_helper_gvec_3 * const sve_neg_fns[4] =3D { + gen_helper_sve_neg_b, gen_helper_sve_neg_h, + gen_helper_sve_neg_s, gen_helper_sve_neg_d, +}; +TRANS_FEAT(NEG_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_neg_fns[a->es= z], a, 0) + +static gen_helper_gvec_3 * const sve_rbit_fns[4] =3D { + gen_helper_sve_rbit_b, gen_helper_sve_rbit_h, + gen_helper_sve_rbit_s, gen_helper_sve_rbit_d, +}; +TRANS_FEAT(RBIT_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_rbit_fns[a->= esz], a, 0) + +static gen_helper_gvec_3 * const sve2p1_orqv_fns[4] =3D { + gen_helper_sve2p1_orqv_b, gen_helper_sve2p1_orqv_h, + gen_helper_sve2p1_orqv_s, gen_helper_sve2p1_orqv_d, +}; +TRANS_FEAT(ORQV, aa64_sme2p1_or_sve2p1, gen_gvec_ool_arg_zpz, + sve2p1_orqv_fns[a->esz], a, 0) + +static gen_helper_gvec_3 * const sve2p1_eorqv_fns[4] =3D { + gen_helper_sve2p1_eorqv_b, gen_helper_sve2p1_eorqv_h, + gen_helper_sve2p1_eorqv_s, gen_helper_sve2p1_eorqv_d, +}; +TRANS_FEAT(EORQV, aa64_sme2p1_or_sve2p1, gen_gvec_ool_arg_zpz, + sve2p1_eorqv_fns[a->esz], a, 0) + +static gen_helper_gvec_3 * const sve2p1_andqv_fns[4] =3D { + gen_helper_sve2p1_andqv_b, gen_helper_sve2p1_andqv_h, + gen_helper_sve2p1_andqv_s, gen_helper_sve2p1_andqv_d, +}; +TRANS_FEAT(ANDQV, aa64_sme2p1_or_sve2p1, gen_gvec_ool_arg_zpz, + sve2p1_andqv_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const fabs_fns[4] =3D { NULL, gen_helper_sve_fabs_h, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637372; cv=none; d=zohomail.com; s=zohoarc; b=jquojfYz3c/NZ0Zd08HB4Yfr4Uj3YUz5msvJVLj6AVhhqKrcHNkwGz9FZzYhppX2YlA2M3F4VvrnPLE9jd1Mb6W+2yB1WBOAvkiUV2V4LcJ6Z9yFKxaqswIca8M5tJ/3uZVSRbT/CF1MLx+C4M47bFKSHnAjFfPhAUj+vgWUPr0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637372; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7tdeWQqQChrKXEqNhu7cV02uqUE7ISdKHK1ikUIyuf0=; b=EQ0UJU0pXoC67CBKMWQPYF54bNSSLmgjrTXH91/L/Ljn0++18g4RHjikHKcv1g3+F3PxaJs0+sQWAO+L2swozdn/KhFj5hWeot1x5fwihFXaypc7MYX9laBJhWAffFPWTGde+1ujL5h1gktIWDgiyKigCtFq8F7DHdq29Df23rY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637372775383.31455283774346; Tue, 16 Jun 2026 12:16:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZEB-0004iE-2k; Tue, 16 Jun 2026 15:13:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8S-0004iB-M5 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8L-0001Ar-3V for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:41 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-45eee266c6cso4364790f8f.1 for ; Tue, 16 Jun 2026 12:07:36 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636855; x=1782241655; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7tdeWQqQChrKXEqNhu7cV02uqUE7ISdKHK1ikUIyuf0=; b=E0TbNX8VUfSdRhygmJW5B47rV3xc/f/acEezlvob1eehNyeKtzPClPZ9aZqLMXTWEh dSJ9ZYOFgYRw4XMBjq1b/xICVfu0ESW0XD3EW6bQ98ttMuZ6Epm3NmU4jEZhkW5DH7US MPoUMxkXhIWitTxJopa8fJUlgiqryUqRSZELRIXHaUv9ILQiVRyQVdQ87TAWR1GbKBhg WqNJFW8/zirJo+rKbAPIy69kzDpM73moBNjx049Nb8/YjMubUs73lZETnxzdLJkJtqUa fyzmJlw8mSnTdBjWUj3kdea3yC6/mXEPFLTsTgN+ngM2nGTh6GA8zXvZYu4V97Cc2bOa NaQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636855; x=1782241655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=7tdeWQqQChrKXEqNhu7cV02uqUE7ISdKHK1ikUIyuf0=; b=Jtbb+StHsZthXl+ry//E07y0aVEA2zKYhJxAPxtxswXe4vYSrnSt5/58jUJSKFicc1 A58zEQrEQ5ZXKPYlYCk3eYftg8vhnCSI3mEP9NAjwJ+mn3v2gIsMIRdA+OuIFh65B6mb C7LD3rwlZrd47Z3AmTG8Bz24k06hmN3rCtPGR01ON2cd9iutanypyeVcQupWts202IyQ +VkP86j6r7VKGphQSN8e/6rS2Cx1BK0/jiV12uV8jLq2E0241soKVbTzQtQm6Z1BCX59 Lps5rZfbpZNzkyRg1DaGVcj3Mio/6WuqwfhRJSKjZiBIgwAGCVALIOL5Gnp0WYkJOynI aEaA== X-Gm-Message-State: AOJu0Yxw67F3dzc6LciFFajBtVwuT59VTp/o3VEJTftVGE5Q38UyPoMd ueNLEqf7l7dRATtsWS8bWpVf2EpsIv9zUEg044RhAqsDxglcNIyek5Rcts+pA0clGZRAuFYGIjN YZpHG X-Gm-Gg: Acq92OHvxxWPbGkgav6YE29BWD7Z2BvsvyjsfaJ/hKNWboqPKoy7AcK7J8g0Z6khYM+ ZQnSDARxoaFv19YwX+9y/cjQEvrMiMRZAPHinZkH7gFb627hspRwLE0yGBFaFXB3JlTArfxy08l iuOl8sTriyex7bPgqC3vJKQ/LsmefICDRK6kQaS8C310R83MKFw6Jwn09YeuafLDldQKEseAe0k zisMoEV6CyY6Z8GfuBveSoHYn5XkhVb60Z6CC3GwNbPPgmo7QJm4TbRaSKR0v1YUB3smTsR3CfM Ps2T0rkrJjIR8L5BlobfOlYE/qJ6u9TOcs6+cfcZHlqqQwY3zph2QtyMLSyyTk84I6fsAO4Tr+H BfVpP8bDET31leLk3uv8nV9AUz/ROHuZRApPfFlNnGpzdMa5TruYSR2kz07cbQpcZV7QRhAiask LJqpXffCsWGUmtpC0lcWbPzO17EMCPajy6VRR/creUWjXu7QxMa3yZOyb3nTswUfOcK9JRFFZGj +Ml7ZLzNToG8kGo/jrLhKU7SdO0dT/M X-Received: by 2002:a05:6000:4619:b0:43f:e934:50ac with SMTP id ffacd0b85a97d-4623521c5f7mr1356068f8f.7.1781636855073; Tue, 16 Jun 2026 12:07:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 48/61] target/arm: Implement SVE integer unary operations (predicated, zeroing) Date: Tue, 16 Jun 2026 20:06:25 +0100 Message-ID: <20260616190639.3462006-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637373797158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This includes ABS, NEG, SXT{B,H,W}. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 9 +++++++++ target/arm/tcg/translate-sve.c | 15 +++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index c7e633ec4f..31b65fab1b 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -411,6 +411,15 @@ UXTH_m 00000100 .. 010 011 101 ... ..... ....= . @rd_pg_rn SXTW_m 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn UXTW_m 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn =20 +ABS_z 00000100 .. 000 110 101 ... ..... ..... @rd_pg_rn +NEG_z 00000100 .. 000 111 101 ... ..... ..... @rd_pg_rn +SXTB_z 00000100 .. 000 000 101 ... ..... ..... @rd_pg_rn +UXTB_z 00000100 .. 000 001 101 ... ..... ..... @rd_pg_rn +SXTH_z 00000100 .. 000 010 101 ... ..... ..... @rd_pg_rn +UXTH_z 00000100 .. 000 011 101 ... ..... ..... @rd_pg_rn +SXTW_z 00000100 .. 000 100 101 ... ..... ..... @rd_pg_rn +UXTW_z 00000100 .. 000 101 101 ... ..... ..... @rd_pg_rn + ### SVE Floating Point Compare - Vectors Group =20 # SVE floating-point compare vectors diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 8ab4526468..afbed77ec3 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -811,12 +811,14 @@ static gen_helper_gvec_3 * const sve_abs_fns[4] =3D { gen_helper_sve_abs_s, gen_helper_sve_abs_d, }; TRANS_FEAT(ABS_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_abs_fns[a->es= z], a, 0) +TRANS_FEAT(ABS_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, sve_abs_fns= [a->esz], a, 1) =20 static gen_helper_gvec_3 * const sve_neg_fns[4] =3D { gen_helper_sve_neg_b, gen_helper_sve_neg_h, gen_helper_sve_neg_s, gen_helper_sve_neg_d, }; TRANS_FEAT(NEG_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_neg_fns[a->es= z], a, 0) +TRANS_FEAT(NEG_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, sve_neg_fns= [a->esz], a, 1) =20 static gen_helper_gvec_3 * const sve_rbit_fns[4] =3D { gen_helper_sve_rbit_b, gen_helper_sve_rbit_h, @@ -873,6 +875,8 @@ static gen_helper_gvec_3 * const sxtb_fns[4] =3D { }; TRANS_FEAT(SXTB_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], a, 0) +TRANS_FEAT(SXTB_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + sxtb_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const uxtb_fns[4] =3D { NULL, gen_helper_sve_uxtb_h, @@ -880,23 +884,34 @@ static gen_helper_gvec_3 * const uxtb_fns[4] =3D { }; TRANS_FEAT(UXTB_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], a, 0) +TRANS_FEAT(UXTB_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + uxtb_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const sxth_fns[4] =3D { NULL, NULL, gen_helper_sve_sxth_s, gen_helper_sve_sxth_d }; TRANS_FEAT(SXTH_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], a, 0) +TRANS_FEAT(SXTH_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + sxth_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const uxth_fns[4] =3D { NULL, NULL, gen_helper_sve_uxth_s, gen_helper_sve_uxth_d }; TRANS_FEAT(UXTH_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], a, 0) +TRANS_FEAT(UXTH_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + uxth_fns[a->esz], a, 1) =20 TRANS_FEAT(SXTW_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_sxtw_d : NULL, a, 0) +TRANS_FEAT(SXTW_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + a->esz =3D=3D 3 ? gen_helper_sve_sxtw_d : NULL, a, 1) + TRANS_FEAT(UXTW_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_uxtw_d : NULL, a, 0) +TRANS_FEAT(UXTW_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + a->esz =3D=3D 3 ? gen_helper_sve_uxtw_d : NULL, a, 1) =20 static gen_helper_gvec_3 * const addqv_fns[4] =3D { gen_helper_sve2p1_addqv_b, gen_helper_sve2p1_addqv_h, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637020; cv=none; d=zohomail.com; s=zohoarc; b=cJW8sHt8K6C5vW7/dzpwrCh6ot0SpOPTvEdjIn12nhS7bburLp0nQr/bdt9byUKtLWhhF99p+Wp9GddmLcCuO5ov/lRyMkth8IlYLB5/0uDdkFF2rMwChLEEhL6+BT46VAS8SvlUyaKMccuwg2O694l/mm5/9X3ztr8uup15r+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637020; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=mhyD5aUR+rlm/Tn1MIb7omoW4yLbGARIJaHm5kA7KoY=; b=LMQTRUDLphV8/Vs7qHAaZQzD1fVPBiOLKo34Uq3UiSlWWxmlGrKZMc0W5H+LoZ2opoNfAZLtp75cV3y656m/ryn50d8HrIV1LHaJZLimaooO7tpC1zriWSXI8TJcESqdBfaIO7EhWAvT0cU1ooNpFog/c41/s33ApkYL5CJbEv4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637020091987.1364426760098; Tue, 16 Jun 2026 12:10:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAh-0000AU-Tn; Tue, 16 Jun 2026 15:10:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8T-0004iK-WD for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:49 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8O-0001B4-77 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:45 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-490aaeabdb4so34649045e9.1 for ; Tue, 16 Jun 2026 12:07:37 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636856; x=1782241656; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mhyD5aUR+rlm/Tn1MIb7omoW4yLbGARIJaHm5kA7KoY=; b=j7i2pNBnIhdS5EbAfcI13sqnyR18zqGH2IGclCPKTnpdCK4/Fet/fM3WwfkpAHEAFR ZafZiPoneMSlMf4LKuKS1C14TTeYNeyrSDjMvNv2rDTYIzhKwA1qLIHxAk2xD8tIOUuD +uy/gOORCQ4XT6ch7nVfWcBeBD/455vvcVxsI617rJl61SyQTomkpaiVpKFuI9VD8muI hHvpknB4zyuhmFWL6hqk03w9l1prPm6Z+zA8F3/b0e+jdbVSeyenDglUIfuynugj36xh M4/4CDChfICvmoWJJEb1vlzRO4QLM6SNBv/5iGkxsU6K4dlPdiWP4WbFR2Owb5zdhe1a QCsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636856; x=1782241656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=mhyD5aUR+rlm/Tn1MIb7omoW4yLbGARIJaHm5kA7KoY=; b=PLiimICeKMm/I2XRHiEx0daMMxbaf3mxbHLM9K0+2yLT6/Fe4ZBiEkJ7v6dmNckGY+ CL+KB5okScuTSIXjeUuXbnP43i1wIUn+BgJeMP77IVRd+gJFeEwWKJgAktUjfq+vXjr8 nFvAIMOrwJ2gmuy6145GwwJqVnnfT0CTYbi/TS8PTOOTJgYEy9QV7RX5KpR/ASCjx4pS iWIW0OobtKZXQtUeWIPeyzgZw8LU7KbsRYYAgXd+TIjeU3eLmEXAA2cQItDnkbjL0d5V Vuh02P9kGLVwPa5xOi3YgRtewspjMLnLq6r5WyyNGMwv6yhk2VSLA8cN7jX4xvbOUd+9 bp2g== X-Gm-Message-State: AOJu0Yy7lVom/1L1MlhJ4ll3sp1StaVRkS7wNTy+MORAONiuS+Oyw4Op 9yboFmShdH6jANXWjduK6rOjMgsT8CQFft6t0AFjJ18FRUKXjDu2MJzg59y++ZqUWsI/pLeRO8E NfTLE X-Gm-Gg: Acq92OHt+Kvv4HSWS45tPFcFZS5yhh5WzAnd5lLrib3MMjLVZK47ozyUC+xYYi9Qq6k ZaWPpeAsFOpF0pD8gxvqoLa2xUzcLG2uoY5BSyY7aV3qSGXev6HtXBx3sQU5Kxd6Y2U5YHCTi23 bkit2hNJtRDbXIdCe/8CTLkZKQDW9GL2Jg7yRNNLQ4OGLMCvPVZmB7Q0itwguZagqfx9p8p06BP 7oTQZ6MzCfBIDRPGhFcgH7aoqCsNmL/xkeKyvGsmQtDPa31ZN5K+HbeN4TIOpSSrvtIqLDY6cWv fbnGYRpLRYWZ9nRhHIoFuzoV2MDQO+jtdTHLjfOoCWGBYUkB9V8eQgJHyB3H9+TYGikOUMHaKFv +VXiVToWUSAZFmxS/U4YQvjcgU+IfypgOd5U3x/eWQapsDwtqiRYtA9KX2RgiCPGhF2WoLbzjKz JslSGgQGBYN30Bc6AmQKnox8pF6I/WDIi/t6ZNLO0aLYhXZVSSW5SGOe+SBSCOKz8+84TM50luF m/iuwTDxgNE+AIyTVcIEZUIaFoI+Z/c X-Received: by 2002:a05:600c:8283:b0:490:d38c:7836 with SMTP id 5b1f17b1804b1-492333a1683mr12829605e9.3.1781636856314; Tue, 16 Jun 2026 12:07:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 49/61] target/arm: Implement SVE bitwise unary operations (predicated, zeroing) Date: Tue, 16 Jun 2026 20:06:26 +0100 Message-ID: <20260616190639.3462006-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637021509158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This includes CLS, CLZ, CNT, CNOT, NOT, FABS, FNEG. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 8 ++++++++ target/arm/tcg/translate-sve.c | 21 ++++++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 31b65fab1b..e79b5e84c1 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -400,6 +400,14 @@ NOT_zpz_m 00000100 .. 011 110 101 ... ..... ....= . @rd_pg_rn FABS_m 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn FNEG_m 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn =20 +CLS_z 00000100 .. 001 000 101 ... ..... ..... @rd_pg_rn +CLZ_z 00000100 .. 001 001 101 ... ..... ..... @rd_pg_rn +CNT_zpz_z 00000100 .. 001 010 101 ... ..... ..... @rd_pg_rn +CNOT_z 00000100 .. 001 011 101 ... ..... ..... @rd_pg_rn +NOT_zpz_z 00000100 .. 001 110 101 ... ..... ..... @rd_pg_rn +FABS_z 00000100 .. 001 100 101 ... ..... ..... @rd_pg_rn +FNEG_z 00000100 .. 001 101 101 ... ..... ..... @rd_pg_rn + # SVE integer unary operations (predicated) # Note esz > original size for extensions. ABS_m 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index afbed77ec3..d6a1683719 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -781,30 +781,41 @@ static gen_helper_gvec_3 * const sve_cls_fns[4] =3D { gen_helper_sve_cls_s, gen_helper_sve_cls_d, }; TRANS_FEAT(CLS_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_cls_fns[a->es= z], a, 0) +TRANS_FEAT(CLS_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, sve_cls_fns= [a->esz], a, 1) =20 static gen_helper_gvec_3 * const sve_clz_fns[4] =3D { gen_helper_sve_clz_b, gen_helper_sve_clz_h, gen_helper_sve_clz_s, gen_helper_sve_clz_d, }; TRANS_FEAT(CLZ_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_clz_fns[a->es= z], a, 0) +TRANS_FEAT(CLZ_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, sve_clz_fns= [a->esz], a, 1) =20 static gen_helper_gvec_3 * const sve_cnt_zpz_fns[4] =3D { gen_helper_sve_cnt_zpz_b, gen_helper_sve_cnt_zpz_h, gen_helper_sve_cnt_zpz_s, gen_helper_sve_cnt_zpz_d, }; -TRANS_FEAT(CNT_zpz_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_cnt_zpz_f= ns[a->esz], a, 0) +TRANS_FEAT(CNT_zpz_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + sve_cnt_zpz_fns[a->esz], a, 0) +TRANS_FEAT(CNT_zpz_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + sve_cnt_zpz_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const sve_cnot_fns[4] =3D { gen_helper_sve_cnot_b, gen_helper_sve_cnot_h, gen_helper_sve_cnot_s, gen_helper_sve_cnot_d, }; -TRANS_FEAT(CNOT_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_cnot_fns[a->= esz], a, 0) +TRANS_FEAT(CNOT_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + sve_cnot_fns[a->esz], a, 0) +TRANS_FEAT(CNOT_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + sve_cnot_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const sve_not_zpz_fns[4] =3D { gen_helper_sve_not_zpz_b, gen_helper_sve_not_zpz_h, gen_helper_sve_not_zpz_s, gen_helper_sve_not_zpz_d, }; -TRANS_FEAT(NOT_zpz_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_not_zpz_f= ns[a->esz], a, 0) +TRANS_FEAT(NOT_zpz_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + sve_not_zpz_fns[a->esz], a, 0) +TRANS_FEAT(NOT_zpz_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + sve_not_zpz_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const sve_abs_fns[4] =3D { gen_helper_sve_abs_b, gen_helper_sve_abs_h, @@ -857,6 +868,8 @@ static gen_helper_gvec_3 * const fabs_ah_fns[4] =3D { }; TRANS_FEAT(FABS_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, s->fpcr_ah ? fabs_ah_fns[a->esz] : fabs_fns[a->esz], a, 0) +TRANS_FEAT(FABS_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + s->fpcr_ah ? fabs_ah_fns[a->esz] : fabs_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const fneg_fns[4] =3D { NULL, gen_helper_sve_fneg_h, @@ -868,6 +881,8 @@ static gen_helper_gvec_3 * const fneg_ah_fns[4] =3D { }; TRANS_FEAT(FNEG_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, s->fpcr_ah ? fneg_ah_fns[a->esz] : fneg_fns[a->esz], a, 0) +TRANS_FEAT(FNEG_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + s->fpcr_ah ? fneg_ah_fns[a->esz] : fneg_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const sxtb_fns[4] =3D { NULL, gen_helper_sve_sxtb_h, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637266; cv=none; d=zohomail.com; s=zohoarc; b=Ep8kCOVHRg94DL8vz2p7uwdYNyXhN3n5D3psJi8hdaCeqyGcnGmkm5ueLW4ljgvELlT4Oa41/9HQDXP2ilgVryFNg+PqogshjQEqsAv16f4mdy5oOJ2cHPEl6rA4KoLCcERy79fCpNK2PcSPzqF+hrzl1tpKCgsn866OAiojs1I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637266; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=gdadH/7yzWF4YFsnZKXvCn1rp8rkx7uY4acc5Pbtdfs=; b=KR7FmdWowoYXpAthX/iw9q7Ll+FcgoURUZrnI8jdpyrcGkwpLx8BNF+uq38oRmVlbjGYci2B1iBQ4IKx2gvw+NhUX/NVMfJgtQImuLieL0VqJ3VG0qoOY05TOgQJP9vFXpWgucUeMV2CC/eaNNcR30nAKF56hS2bBF1TW594xUo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637266189684.7016254215919; Tue, 16 Jun 2026 12:14:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZCJ-0002SU-Vf; Tue, 16 Jun 2026 15:11:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8W-0004jS-S9 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:51 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8T-0001Bm-Mg for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:48 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-490cdae130cso24688915e9.0 for ; Tue, 16 Jun 2026 12:07:38 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636857; x=1782241657; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gdadH/7yzWF4YFsnZKXvCn1rp8rkx7uY4acc5Pbtdfs=; b=JBR4ahYvi+HHQQIpwM4rt2qk+qpY5npnqUbgy03pwC2mvFUJGjDwc2AQwMzhn7gGZo D8rW4nbmpl+l+c8yQr96Ps6M9gvNY/sRSAmqYJm3YdQUeqbZWqSXhgR9PUUfx9ZqXtH3 i56ATiZ7Drf8ikKQ1r5c5V1Tauj17ljhfK2g9ArCuVB9VKMeVauxEYGiGKnfggSlumG7 7tk4bH5Q9tCFYi+zNuBNoflRmbALRkwjS5dOFUt70JGWuKunfFlyJt/wn94Nf23fuizt bc1RjcifqfJN5Rst6N6+5t/SuoM7ceu/PfJyUpvgNumrrzIU5UO5eXiHn0PMCu5GSHA1 wENg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636857; x=1782241657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=gdadH/7yzWF4YFsnZKXvCn1rp8rkx7uY4acc5Pbtdfs=; b=LYStPcYjj93HJ4aLq3aKdj/6FLZ1hVU4/Ib6XznLNzHxsZTFw0dN9jjEz0uGvT1m3q 6vz8WksJrKpYYqCPRSfVoA8Rfws4y7fnCFJcPlC4DGS6QTHLAOQGZEFG6IfBvtEABJfi 2NcCh4RB48MPxDwiMEulgSYXDpkonHB2u5TtrHSiKqO7MputdtvB1z86/JJPKqrWKDCw xyE9HrhBQ5zqA+n8mv1s+Bd8UPAHSY4lnhEpToNqLFcBVSs/4qwzKMmsEsU2VDo9d931 e2v2lWecqFzW7YeXWmOyzfFFTo4tl44XjNXg/0uacuFmvF/p26xr4T/VpG1d93UTLkkP z7IQ== X-Gm-Message-State: AOJu0YzZZRtGX1g4LN8EY9Y74u4cccukjDYE7ivzqQk8YzUtLzm98mr4 KuUYyGNm1PCoNIjRxiNVcRTO3JbwEceOpuh7LlGSX26VOru9HHeEanSc+Qo3hA4ehtSHugeiA4F tV99A X-Gm-Gg: Acq92OEdhAvbGip6JwaKIgLnVBpMvsaSN9Gt74g6bYzu3fBtPaqW+cImlj8o3KQdJxc F9F0QPjOFyrrGccQ10TKehQ720fvtOgiUTG8zym6cyT3V1EskDL3sUyQfqeBMdyG+MkGzc4YPkI HrREvhAeu80sS4/vyniiWPIqw5emixF92MfDY6kIbMfXDzsuOvtNUw24XFVpEukA8IxzMHvjsbM itzjST8IR9TdkYhMR+yz4ma7NHiQX1n1eki9PCNKpDhsg+nWPeJXEaEUwNtwLIIJVATPv02kqGb VS9LbU3Zp3/Aji5fltkb21F7BO/CrXBylXrziI8F6keFIrqB9dd9ELK6P/KkXbOJj3FXCbtAESE ONjEdn3KHv03d9bj/g1PH9/OQmW/zR6rI+BqF5KwNBPNjmDJ3NG5f0NnyMJG5Pc4symFZ53cSxt qpSZ24PdN7R3kCZkkH5zS2rCZzICOSLi06J9WjFXFJ0fy9IsURz8fq4FjW1TPaQiVBIe7ZcrQ7/ 7oWrljO27Zt27p6M8SfrCyjXx+t/EpDSe1AJsLaJ6Y= X-Received: by 2002:a05:600c:e557:20b0:490:e5c1:b8bf with SMTP id 5b1f17b1804b1-492333bfa01mr10036535e9.13.1781636857166; Tue, 16 Jun 2026 12:07:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/61] target/arm: Implement SVE reverse within elements (zeroing) Date: Tue, 16 Jun 2026 20:06:27 +0100 Message-ID: <20260616190639.3462006-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637267260158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This includes REVB, REVH, REVW, RBIT. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 5 +++++ target/arm/tcg/translate-sve.c | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index e79b5e84c1..867ae2916e 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -730,6 +730,11 @@ REVW_m 00000101 .. 1001 10 100 ... ..... ....= . @rd_pg_rn RBIT_m 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn REVD_m 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_= e0 =20 +REVB_z 00000101 .. 1001 00 101 ... ..... ..... @rd_pg_rn +REVH_z 00000101 .. 1001 01 101 ... ..... ..... @rd_pg_rn +REVW_z 00000101 .. 1001 10 101 ... ..... ..... @rd_pg_rn +RBIT_z 00000101 .. 1001 11 101 ... ..... ..... @rd_pg_rn + # SVE vector splice (predicated, destructive) SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm =20 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index d6a1683719..cd1e0e744d 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -836,6 +836,7 @@ static gen_helper_gvec_3 * const sve_rbit_fns[4] =3D { gen_helper_sve_rbit_s, gen_helper_sve_rbit_d, }; TRANS_FEAT(RBIT_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_rbit_fns[a->= esz], a, 0) +TRANS_FEAT(RBIT_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, sve_rbit_f= ns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const sve2p1_orqv_fns[4] =3D { gen_helper_sve2p1_orqv_b, gen_helper_sve2p1_orqv_h, @@ -3070,15 +3071,21 @@ static gen_helper_gvec_3 * const revb_fns[4] =3D { }; TRANS_FEAT(REVB_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], a, 0) +TRANS_FEAT(REVB_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + revb_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const revh_fns[4] =3D { NULL, NULL, gen_helper_sve_revh_s, gen_helper_sve_revh_d, }; TRANS_FEAT(REVH_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0) +TRANS_FEAT(REVH_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + revh_fns[a->esz], a, 1) =20 TRANS_FEAT(REVW_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_revw_d : NULL, a, 0) +TRANS_FEAT(REVW_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + a->esz =3D=3D 3 ? gen_helper_sve_revw_d : NULL, a, 1) =20 TRANS_FEAT(REVD_m, aa64_sme_or_sve2p1, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a, 0) --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637344; cv=none; d=zohomail.com; s=zohoarc; b=mPtijvW5JSSpZl6LfK8X/nKUZP4NCsrENUloM9ESED6bP0z/SnlceZMeCIpUIme8jOgy1SgJu2RYJ4LRAhKSBN15fr7qNi1IzIlrKcDVviM4+pO6/cDFspiypwztLDNgfEbIk1Xl8hMZoRPMbmeizTSX2a0aaGc8CmmZY6X78So= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637344; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=V6sLBGdgtQYDIl7E66w9tV0s+p4xqf8JGUH+izJ1pxI=; b=iRkNa/DBmuXgNgXMIOvUPBz7O/xkC9n3kydV++EsvqY7uDhdDA8EeTvS7UqncVhcPTb4qPGlXxrgGAoMDQHBoJHNXARZRCLVORpkNbb70egP98Ty7bM2y55rMR86PVS+LEiLXAgjIlyYK3Um2iiTrTnB7o+TDBvxMCTGOJAbU2E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637344674570.4922442922849; Tue, 16 Jun 2026 12:15:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZDz-0004OE-OM; Tue, 16 Jun 2026 15:13:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8W-0004jQ-QH for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:51 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8S-0001C0-Mt for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:48 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-45fe59255beso2781471f8f.1 for ; Tue, 16 Jun 2026 12:07:39 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636858; x=1782241658; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=V6sLBGdgtQYDIl7E66w9tV0s+p4xqf8JGUH+izJ1pxI=; b=UfcOD8vCi7A8c4/NK1MO5/sqOe73V7bRnNklypOB3CLgNWMluBXlGZky9SQi2d43Ls USl99rhy//pH1HejtQHti4HH6Jd0rCylJ9t9Qw2yflctNCCxDtcMAbEvRGB7kax8Xpx8 aeIrnW3iFvjJNJWDpCW0HkI72hEuuailswYdu9mKPp4ADXOZEytYOFauPoXAZDI29quw EbHO37v1RMq6xJLSnKHmNoEF6lpD5dEGRGX2sNbLJR13R0fJl7jMAf58wkBo1iadGWJ3 ZKAJBjGqD12mpHTohbBU/zmmAfoSlF1/UpyyKj3oqBirKGipMi6mNAodNONCK+nEgU4P liAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636858; x=1782241658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=V6sLBGdgtQYDIl7E66w9tV0s+p4xqf8JGUH+izJ1pxI=; b=kpN2eQWLyzQgpeWj3Xy/6WGszUDR/flkhYcJBsdmeLbiNC3ncTK1x8FMK6r21MUijQ rfqPD/KGlqimunkJHjoUQGmdFUoLczrPEwwNHzYu647LkmttQv3WrYCxcnYkk5EO06wd Ktqi8n7MO9qefeQ+uO5Wl/2GbPWw/GTTxl82yO1ZnxeUXJlCJ39mI5nUldlNii90kTVI 3GOeHVMyHIhd97Hio7540TVjgcBsGg9jYqExfB1mHwFJv34yM60fArp0gGM5zfR4cP9C F7Vg+Uqk7Ut8mSFEeOZZy7PIM/3NOR5VPqMylGuTSJ0jp9RdlSuBxMrRpkZFuvuR4xcS u+AA== X-Gm-Message-State: AOJu0YyVTw4AtU9LFmADtO5S5FD0XC5eMribPc9U+sslibf/1PNYB3Sc le2zBGB8ns5BWcfKEvN3tZ2bFpLjk/0KbLNxzMS3QOZeNOLlXI5y7qrpt4G+CgNJSg+pDgu7sFI Gu2Gd X-Gm-Gg: Acq92OGjHN5MbKTd4T3CZMegYOZZFs8OshheUi0OTujCcISBVtEWd7tHUPdhDt/Ypxb WKCiqjKpJHuxcxGTzIyGmgBCnAqQzPifY83kE6d80XKh4kyseYesJBHv2VEQUd5jek83ftkdwIT 63Cv1KpzRpuK7wjYRh82WY2brQyKA0GvSBanVyaEwz8tGstQXrb3D040VnXrGgDTQwy/UkE/CNp de6Y6NxDc3C5MsyUvx1GGtM1AtypSRSzlBRm0C+1G973TZSG9r3NkUHGApMYyGwB5/0qR7Iw4H6 UD/UQyIcML/5UezUchKLIzpFEFyWap4fKUQBsFYvx7cxHPlxjRlhYkV0I7ZMdF46oOt9GwCp8N3 6/zr1g7JS2GYxLRG0rnfAkU8PQjzjETr2By6xVNirkWw40eW7N6yvu7WeiISDrh7mZPSOfvwmd7 D/jyHf7tjVLeAz+pikYukD0BO43UH32ZGIiEfplgzRNDkhDmb1FxsocLIyK3VcLjS8LsHe5e5qA 56Kyv3XUIMnCTYea8iNmkwznSu1F5+D X-Received: by 2002:adf:fc09:0:b0:45f:f142:d55a with SMTP id ffacd0b85a97d-4623f8b3005mr883612f8f.14.1781636858069; Tue, 16 Jun 2026 12:07:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 51/61] target/arm: Implement SVE reverse doublewords (zeroing) Date: Tue, 16 Jun 2026 20:06:28 +0100 Message-ID: <20260616190639.3462006-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637345617158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 1 + target/arm/tcg/sve_helper.c | 4 ++++ target/arm/tcg/translate-sve.c | 2 ++ 3 files changed, 7 insertions(+) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 867ae2916e..45f8633fd3 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -734,6 +734,7 @@ REVB_z 00000101 .. 1001 00 101 ... ..... .....= @rd_pg_rn REVH_z 00000101 .. 1001 01 101 ... ..... ..... @rd_pg_rn REVW_z 00000101 .. 1001 10 101 ... ..... ..... @rd_pg_rn RBIT_z 00000101 .. 1001 11 101 ... ..... ..... @rd_pg_rn +REVD_z 00000101 00 1011 10 101 ... ..... ..... @rd_pg_rn_= e0 =20 # SVE vector splice (predicated, destructive) SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 9634517925..1711444800 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -971,6 +971,7 @@ DO_ZPZ_D(sve_revw_d, uint64_t, wswap64) void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc) { intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + bool zeroing =3D simd_data(desc) & 1; uint64_t *d =3D vd, *n =3D vn; uint8_t *pg =3D vg; =20 @@ -980,6 +981,9 @@ void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, u= int32_t desc) uint64_t n1 =3D n[i + 1]; d[i + 0] =3D n1; d[i + 1] =3D n0; + } else if (zeroing) { + d[i + 0] =3D 0; + d[i + 1] =3D 0; } } } diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index cd1e0e744d..6a29c1e43e 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3089,6 +3089,8 @@ TRANS_FEAT(REVW_z, aa64_sme2p2_or_sve2p2, gen_gvec_oo= l_arg_zpz, =20 TRANS_FEAT(REVD_m, aa64_sme_or_sve2p1, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a, 0) +TRANS_FEAT(REVD_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + gen_helper_sme_revd_q, a, 1) =20 TRANS_FEAT(SPLICE, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz, gen_helper_sve_splice, a, a->esz) --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637352; cv=none; d=zohomail.com; s=zohoarc; b=HaiV9zqcrQxLhTm7rDcEqhi2CIR/zmGfP1IDqBJNTZoBK//covejeLDySjD/swS08whe/5xjtF+cgS5+Xj30QDyvLn6J0lvob//56kDYx2ctF3uMUQ7tsHJoYF7B38dBfoqNnmuHVekvLQkQ6IXzI+I7yqYNsBG4lLhYz1ZaMsM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637352; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=5uyUfjoY4WfX9Ygr06+TwtDiXD3NaYulNpaMCXE18co=; b=lHdi2+phFJIuNOj+9sRFXUYu7J3PLmgmjxqU7Ql/wiEpM5WIuhvObw63LcNEgt16nsuz8ns+KY37vC+QSQfNLayVtwrRBYmwveDEvBrcaQwuhzmzaEOtxtwwWyt8e8GaL4BcAJJd7trhMFk7QsY2I6ul36glUP5LB+MxS8VbPTA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637352534297.8814123645699; Tue, 16 Jun 2026 12:15:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZFM-0006Gw-Q4; Tue, 16 Jun 2026 15:14:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8W-0004jC-GC for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:51 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8R-0001CE-TY for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:48 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-4619990ca5fso1663946f8f.1 for ; Tue, 16 Jun 2026 12:07:40 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636859; x=1782241659; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5uyUfjoY4WfX9Ygr06+TwtDiXD3NaYulNpaMCXE18co=; b=OnXquPiEhbbZqE1TVBXXH6k+xinvK8jtAwBkgSSj2piz0lqT1aZkeIxoR6an2JLTtD zx8VAKPjkfavzbuggBsGnWOIiPgKfBPGPeyyb9Ax1ofyCDaswHu5wI6Z/IVKaDFEGrU8 y3uknT33TPbrxb+BhU37JSjl+1RQWZb3QqqITG9ulIbNdrPreRCFMVE9tAuzO3z0AQmL YC2DmiLnwgnOnn0mMEjh6+8CZpcCeUt+9hEMVX9cJ5DvLlroixG/LVU20Yvpx8UBvh6P hJCoaF0+Pxl8zjXf1A1BslywvNB+N28X8GUIWZuFBl6QenWHLod3GRDcfw0SnXWydgAT dn1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636859; x=1782241659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=5uyUfjoY4WfX9Ygr06+TwtDiXD3NaYulNpaMCXE18co=; b=nultd3/ri3Zn3lKwH56Ps5g0vC9Lyf5Kp9z4Ir7wKQyOZJz5vfTX8b5TsoBDhPX+kD HqWx82DroGrWVQXivEd4mK1XY+MaHwNHVCgQdF/saFO9NwN3gGFqRfzf6K0Xru8Q2xi8 S4X23GRAmrG0lFaJa/Gg3xt9NCyIUIqInmOduqodl9dAc585OBt2sGHYi4gMoWOjMsRD H7Ps0p6Ml3KgcWDszcJ034DCCVEOEg1i+diVPEA3YxpUlj8g1nRHZVTuwCgaUQ2z2NQm vEWjfRhsYxmAf+J9ze7MuXwSFNSGaL+aVk9GPt/7tg0STmmC44r6ebH/cNsBjnw1yWhu b/dg== X-Gm-Message-State: AOJu0Yygnh4iyYp0Qjzsp/1P2u1gx6Evar+X7PzZrWymyQLbQm7lcq1X H/6uxRCKMNAzl5O0u3vj+ye6UJfR2lkKeti86bfKsQApygyL9Mugn5TDNj4WcSqFCmXLReaQEnl BjTm5 X-Gm-Gg: Acq92OFDztFa5hBu6vsmc0EsU7GNClLC4zlgz0ln5lfjhFfd+tUR8OfHyNPutzGnEd6 ACajm8mFdWrqS3NfLqcy1IWYmLo5Yon64IXmGIzDZyyeBoXcrTBaG+j45Qep5D0Hq8e+1OSPfBj zUO2cMZJWRrqZvpcGrGNvwJxFDnuUoA+TclhbSQhGIxt0c9NBOwbczc54qRXpxl5ozN+sg+3E98 0xq76zj+043SuceHCv5fhzlpxdwy5tcoMATCoSqkATkvYFeRiVAkBaS/Re/v6z2CfjH2mFTFkhF HXGyK1s5BZz8sFWL34EtOlOrZIPiEY+Rgqo+EG/TWYnPiOScAfq23feXA7mJlezuRxoiHCf7DJp 4iZ82Zh5Y6WtKen8VFAUuwFwSjaO1grqaSr8cfiTFN8nzYINQszUtncZkMwPfaH9hooVTP4va0e SlqvL/wLZOO0B7KTOfqao6faUvPkP/J+izZwfXUXY7+iw9d0l32qwIPGXfOpMbCBNEjGBTvR2kG +WJ2zimDr2WZie713hK9fmio/5OcaO0 X-Received: by 2002:adf:ea48:0:b0:45f:f142:d563 with SMTP id ffacd0b85a97d-4623646201dmr1105300f8f.16.1781636859080; Tue, 16 Jun 2026 12:07:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 52/61] target/arm: Implement SVE2 integer unary operations (predicated, zeroing) Date: Tue, 16 Jun 2026 20:06:29 +0100 Message-ID: <20260616190639.3462006-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637353748158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This includes URECPE, URSQRTE, SQABS, SQNEG. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 5 +++++ target/arm/tcg/translate-sve.c | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 45f8633fd3..f1cf7a628d 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1545,6 +1545,11 @@ URSQRTE_m 01000100 .. 000 001 101 ... ..... ..= ... @rd_pg_rn SQABS_m 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn SQNEG_m 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn =20 +URECPE_z 01000100 .. 000 010 101 ... ..... ..... @rd_pg_rn +URSQRTE_z 01000100 .. 000 011 101 ... ..... ..... @rd_pg_rn +SQABS_z 01000100 .. 001 010 101 ... ..... ..... @rd_pg_rn +SQNEG_z 01000100 .. 001 011 101 ... ..... ..... @rd_pg_rn + ### SVE2 saturating/rounding bitwise shift left (predicated) =20 SRSHL 01000100 .. 000 010 100 ... ..... ..... @rdn_pg_rm diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 6a29c1e43e..fe78e4dda1 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -6791,21 +6791,27 @@ TRANS_FEAT(UADALP_zpzz, aa64_sme_or_sve2, gen_gvec_= ool_arg_zpzz, =20 TRANS_FEAT(URECPE_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, a->esz =3D=3D 2 ? gen_helper_sve2_urecpe_s : NULL, a, 0) +TRANS_FEAT(URECPE_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + a->esz =3D=3D 2 ? gen_helper_sve2_urecpe_s : NULL, a, 1) =20 TRANS_FEAT(URSQRTE_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, a->esz =3D=3D 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 0) +TRANS_FEAT(URSQRTE_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + a->esz =3D=3D 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 1) =20 static gen_helper_gvec_3 * const sqabs_fns[4] =3D { gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h, gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d, }; TRANS_FEAT(SQABS_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->e= sz], a, 0) +TRANS_FEAT(SQABS_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, sqabs_fns= [a->esz], a, 1) =20 static gen_helper_gvec_3 * const sqneg_fns[4] =3D { gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h, gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d, }; TRANS_FEAT(SQNEG_m, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->e= sz], a, 0) +TRANS_FEAT(SQNEG_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, sqneg_fns= [a->esz], a, 1) =20 DO_ZPZZ(SQSHL, aa64_sme_or_sve2, sve2_sqshl) DO_ZPZZ(SQRSHL, aa64_sme_or_sve2, sve2_sqrshl) --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637333; cv=none; d=zohomail.com; s=zohoarc; b=ESKudVeAnGc1VNFUGavEZjIfp3rkaDMFuNNx5OYzntPYaD8tuG2MSfDjEQpAL0iB7+AKjDo9yEVxN74SBbzB/7w3MGjhhk5niRqXxNfffIRFT1h5DQPnwdON5YmSlZQ25E94JVuqoxJERpL+3U8ra5SNgZPJEqGHXAgFh8U/Hfg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637333; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=sdhhYYWWcr0IknSn1CgIlq95XqkUC12aNgNn4QU2pX4=; b=e4nLkkumhieLRO2mEjZ/8CqPaXHUi2VqlUn9QMwVYZHfmSp4WihGUQIi+Ubpy6OGkPPikd/s10ag/rvG0JYr/KTEQE3Wu2sx0L+0Tsl9J/HkKERShQpWDBCFf3XTyTtHQbM168na4wQLmYwoI3L8mL3UMurVyXbGRglVxPy7k1s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178163733328729.581212375526434; Tue, 16 Jun 2026 12:15:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZFJ-00067k-0P; Tue, 16 Jun 2026 15:14:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8V-0004ij-2w for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:51 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8R-0001CV-UJ for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:46 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-45ef1198766so125261f8f.0 for ; Tue, 16 Jun 2026 12:07:41 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636860; x=1782241660; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=sdhhYYWWcr0IknSn1CgIlq95XqkUC12aNgNn4QU2pX4=; b=XDHokEhPz/Q5KxTjUxIKGZoXOPUDQNeEM3vbVOjs82uUYguMgOXLqP5GUOr1qh0cF8 dvWn++hufDVH3IEiTDUh4MvSLyW0gx9MigQDFyZ5LZF1HXVUJmEOMxdFL8u3eyh2AQOi KVlCMeSrzg7jH5WCoW6Kz2PrAMCEwd5zI6UubYRIW63icm44XW4L4iefZZnmDn1aZ+0Z ymDe9SnlxIer4cvPgS8YQnw/ZufAX6SKcQuBl/qHGF6qE2nti6mSXzaCk7IzwBeRZR4h nJYCt0eqBDpADd9YojsH9QwwpoNWORsVkDRVPZAEvD2PmoCwThuX8KOh/3nnzRyEPFVh kQhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636860; x=1782241660; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=sdhhYYWWcr0IknSn1CgIlq95XqkUC12aNgNn4QU2pX4=; b=Q8/UH3CKuHhlL1Ae9DEiAQs7Ri2m45UPIwg8f/H5eUBO3QAkSlZurpuFBvWL2Z3vaG nz+awyXwuU4uxBm/+Fn/mw4cuuxXfFnLlVlycsVm2KIymAnOZiKqUWnHTnaylR1kSR/A 9N60wyIkTpLF7qVKBU0GRIc1whrlXZVXE6MCVzi1I2vNsLR7qsWFaT+k7/DQGXWfed6C xtj7MaeunEtAzE1P78ndX/4iG6GsAuIbWs06gJFZbw5iifXSEFwZuZw3VUTEq/HZ2n7f 8kl9bi/d0gg8IWawcc56qsXUI6AMf4JXC+rg+HbMMmO2tkrSu6yEN4pLcGSwqZyTKuW4 2cBw== X-Gm-Message-State: AOJu0Yw0NGYRXt6Mb7MGJDqGMB1aBbt5w+hLZC2URbRp60dyLW+TPNDk Nk69LBP/A2eFAU1vdO43Y+ObI5YM2vD7FsicZKweuEyjC8Dfour1R4rI7LuvFDBXAWPcplR+b72 1Cq6M X-Gm-Gg: Acq92OGAJQ5SC5gjMoDXZ3VmvzQIIDrHp30uWDJvfA8l/Ri8ivwp7JEcN+qUOV0R2vV f6oNqgRFbl/QkoH20m5mWURGEmNyImSPprujnsW2I7F7VdKi/Q3KHv5Pmva0OHhBFMPzSyRc7YI 8fL/qTEBQJq4ny5Ub/TRiNwvh40Hu2LSliC2hWbSawb+h+iwnndol3KBsIuXaocqkeemsGwJlTy M2nLhNGIZkgxKiesRy8H8lR+mOSLtvihDlEsRwKMYrriDYjnEYizFOZCofHGwQn8SYqhI0WQDb7 T3hWGpwLOFJr7ECndMNkzhj/8ARgrfYgpBJdOr/rY1bxSJVox7u82SlP6OZfagni5szZ6orYlEf Wlo7tKWxudVCyzFmGnsPXOYDG2V/zI21xFXsStEvtPnLm0HXNen+VnpDUu6ZmZMzUf1UQkp/df+ l+5VlIflpGBRCB48ym6usaFOjEK7TsEwG22tlt/GIPrP3tKltFtfJ9HGfyAlzDQPl+G4KWa9scE q3L97AUVT6QSnpTAeLZIphD2ZoK0hKx X-Received: by 2002:a5d:59ad:0:b0:45e:9304:a4c3 with SMTP id ffacd0b85a97d-4622d70775amr1651375f8f.19.1781636860154; Tue, 16 Jun 2026 12:07:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 53/61] target/arm: Add data argument to do_frint_mode Date: Tue, 16 Jun 2026 20:06:30 +0100 Message-ID: <20260616190639.3462006-54-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637333577158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Prepare for needing a non-zero value. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-sve.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index fe78e4dda1..ea936669ef 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4656,7 +4656,8 @@ TRANS_FEAT(FRINTX_m, aa64_sme_or_sve, gen_gvec_fpst_a= rg_zpz, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); =20 static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, - ARMFPRounding mode, gen_helper_gvec_3_ptr *fn) + ARMFPRounding mode, int data, + gen_helper_gvec_3_ptr *fn) { unsigned vsz; TCGv_i32 tmode; @@ -4676,22 +4677,22 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_= esz *a, tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), pred_full_reg_offset(s, a->pg), - status, vsz, vsz, 0, fn); + status, vsz, vsz, data, fn); =20 gen_restore_rmode(tmode, status); return true; } =20 TRANS_FEAT(FRINTN_m, aa64_sme_or_sve, do_frint_mode, a, - FPROUNDING_TIEEVEN, frint_fns[a->esz]) + FPROUNDING_TIEEVEN, 0, frint_fns[a->esz]) TRANS_FEAT(FRINTP_m, aa64_sme_or_sve, do_frint_mode, a, - FPROUNDING_POSINF, frint_fns[a->esz]) + FPROUNDING_POSINF, 0, frint_fns[a->esz]) TRANS_FEAT(FRINTM_m, aa64_sme_or_sve, do_frint_mode, a, - FPROUNDING_NEGINF, frint_fns[a->esz]) + FPROUNDING_NEGINF, 0, frint_fns[a->esz]) TRANS_FEAT(FRINTZ_m, aa64_sme_or_sve, do_frint_mode, a, - FPROUNDING_ZERO, frint_fns[a->esz]) + FPROUNDING_ZERO, 0, frint_fns[a->esz]) TRANS_FEAT(FRINTA_m, aa64_sme_or_sve, do_frint_mode, a, - FPROUNDING_TIEAWAY, frint_fns[a->esz]) + FPROUNDING_TIEAWAY, 0, frint_fns[a->esz]) =20 static gen_helper_gvec_3_ptr * const frecpx_fns[] =3D { NULL, gen_helper_sve_frecpx_h, @@ -7998,9 +7999,9 @@ TRANS_FEAT(FCVTLT_sd_m, aa64_sme_or_sve2, gen_gvec_fp= st_arg_zpz, gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64) =20 TRANS_FEAT(FCVTX_ds_m, aa64_sme_or_sve2, do_frint_mode, a, - FPROUNDING_ODD, gen_helper_sve_fcvt_ds) + FPROUNDING_ODD, 0, gen_helper_sve_fcvt_ds) TRANS_FEAT(FCVTXNT_ds_m, aa64_sme_or_sve2, do_frint_mode, a, - FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds) + FPROUNDING_ODD, 0, gen_helper_sve2_fcvtnt_ds) =20 static gen_helper_gvec_3_ptr * const flogb_fns[] =3D { NULL, gen_helper_flogb_h, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637323; cv=none; d=zohomail.com; s=zohoarc; b=THMcRFtCcNDdovDTTD8L44H63j1kDkhiy8RYzFIV2CJRmMi3MzRTNuVUg9S8rpZy/wMvqRgxwZ9U15dN7idapYGs72sJ0WooeR0vZ4XGPN/Q1K1Dii4PVnuy8YcFlVzr+QS6639Ae+YSymv6mA2Jru5VjefPGnT81NSdAhqlsfE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637323; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=MwaapcHas6wJYffFDMxOfKBoZytTIETCsbZAfwXMMp0=; b=T1b71mCs7IDH9Y4nj3LvmAj8EKVV+KWvvhe4Cxd3rNwnxVHPdPX2Hi1dU7LkMpVTEOxYerfL2OzvUVMOEgrWNbkXECqWeO03YEVZpKkeFchWOO0ODs4U0UCyJnWNiVHwTe2L0csF04J3+L5qakDpjYTL1Q7g9vDRE1brwyem2As= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637323385718.0675641363478; Tue, 16 Jun 2026 12:15:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZEl-0005NU-Q6; Tue, 16 Jun 2026 15:14:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8V-0004ik-Em for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:51 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8R-0001Cy-TS for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:47 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-4600cbb06deso106920f8f.1 for ; Tue, 16 Jun 2026 12:07:42 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636861; x=1782241661; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MwaapcHas6wJYffFDMxOfKBoZytTIETCsbZAfwXMMp0=; b=fCqm7HAP9NB8qrRp0QhRQNWqQGPP+qsehi45XJf5Kazcqu7jAEGYPO5oFBm6z19W1W mtswxTcJC55mANESCQP8vD4ftd2h9RPOGDYFQftFmS58EKi7Tpb5BPu2BsCLhC8WpG16 c27VB16yMJvGIhpe/uytAzxAI4CT7JrFgWNd6pvpTItRHP+yXAOjgFCz/wq9ITnDK7PL le6Z3+uJrFV+6dqrRBN/QLCQSox0gjpsbDo3hpLPdaFJ83aQnOZFA+/yP5YxjlPv+nRg b65SPAezJTfpWHhTXWO7M3oytCg1KclFMBaXBmNb5k1GJbz/NL2yHHWYV9crs82N69HK 697Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636861; x=1782241661; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=MwaapcHas6wJYffFDMxOfKBoZytTIETCsbZAfwXMMp0=; b=pgjRKXsf1ups3tL8cyH3lhN9Apd92M3k+BjFYl2M3MDe7yCzl5F5+XuXyP/MFDdV6G 2ulG6zYtHQr29PCVGtlkMYtmtmcHB6Ss+zUtYyMMw5fOnoyQl2umoHRZtLAkYsOc8wkt It4YbcgHDNKpYMtOwn7jVYTL/xqYGvkldmDLbduywXlb5jT0wYf/pveuhxH668/SfJgm hkLUGT4LNKekl8edIhBlBMKE1jCPymzaZ51cP7Yz0R7Z2Mg7Z1/ix6Y7p9Xtrx41aFYx xHWaRBbp+NiM88+0EuWVgoPR4T0V1NuYomEdY9vORuTFbQ/Sc4YAQ5iL6b0uZDUC0WNQ aGtA== X-Gm-Message-State: AOJu0Yz7P5rGmLZAQ2V2jfKloUO0qwf15LWHKJJdIVhXtP6lfgxoeO81 FjnZnFAAgRQv2d4eU+ahUCk1MygxJvr3mT0uEl1I8k0aUszFhKKlubLpslTXonyYq9DLpMVXIti UNmuf X-Gm-Gg: AfdE7ckeF7mx9eGpgM+mdKK/fFgCVXEW62rDO+S2JlZ8b66ykoN5kFlFXDP6Q9dE0GX W/xSOPfcVsqKiQODsX0qLUjhz3mmL+cVugT+TWI/F0Pc9yM7JJQs2uXDTwmUsDJA18zX3GOS+m7 9T6JI96ySPVkiW7f0ak6p1ZY5+VVEyDBe2VxNDoAwz4CErgN3T+231kx6afNVCMTT3lWpW0nZEg YUME0LMY1wXfRYZdqraawxK2B+uBrxkWjaVnr1dsg9VTAWt5/pnUWRSgRkN5Mlwm+5KzQMzls40 PmGgsQjsxBzyiajRs01/gMZCFDwmcsOWj8RP/eOYX+qK3ZepiptxhbCcvIAbgnffjpsPoZh3BY3 7nfh2XjCUeiRmiF3I0Lv+bddkzEgJANXQfXic98Q4AshR+A5/jPz1dz15Yq6Z61m25Efk6OX4WW /sVIbaM4VlfTwL+eHNsnTsNNJY6o8updiWUSMTdv76tLDT5KI4O62SbHYFVuqTGklob10ssQV8z qRYI0+bMLhhDyTbSIUKhaNOSxUciIeg X-Received: by 2002:a05:6000:25c8:b0:457:ff13:b2a4 with SMTP id ffacd0b85a97d-46268e20762mr46784f8f.3.1781636861008; Tue, 16 Jun 2026 12:07:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 54/61] target/arm: Implement Floating-point round to integral value (predicated, zeroing) Date: Tue, 16 Jun 2026 20:06:31 +0100 Message-ID: <20260616190639.3462006-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637325550158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is the various FRINT rounding modes. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 8 ++++++++ target/arm/tcg/translate-sve.c | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index f1cf7a628d..099cd4e93d 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1240,6 +1240,14 @@ FRINTA_m 01100101 .. 000 100 101 ... ..... ..= ... @rd_pg_rn FRINTX_m 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn FRINTI_m 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn =20 +FRINTN_z 01100100 .. 011 000 100 ... ..... ..... @rd_pg_rn +FRINTP_z 01100100 .. 011 000 101 ... ..... ..... @rd_pg_rn +FRINTM_z 01100100 .. 011 000 110 ... ..... ..... @rd_pg_rn +FRINTZ_z 01100100 .. 011 000 111 ... ..... ..... @rd_pg_rn +FRINTA_z 01100100 .. 011 001 100 ... ..... ..... @rd_pg_rn +FRINTX_z 01100100 .. 011 001 110 ... ..... ..... @rd_pg_rn +FRINTI_z 01100100 .. 011 001 111 ... ..... ..... @rd_pg_rn + # SVE floating-point unary operations FRECPX_m 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn FSQRT_m 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index ea936669ef..64ee1f7752 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4644,6 +4644,9 @@ static gen_helper_gvec_3_ptr * const frint_fns[] =3D { TRANS_FEAT(FRINTI_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) +TRANS_FEAT(FRINTI_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + frint_fns[a->esz], a, 1, + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static gen_helper_gvec_3_ptr * const frintx_fns[] =3D { NULL, @@ -4654,6 +4657,9 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] =3D= { TRANS_FEAT(FRINTX_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); +TRANS_FEAT(FRINTX_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + frintx_fns[a->esz], a, 1, + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); =20 static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, ARMFPRounding mode, int data, @@ -4694,6 +4700,17 @@ TRANS_FEAT(FRINTZ_m, aa64_sme_or_sve, do_frint_mode,= a, TRANS_FEAT(FRINTA_m, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_TIEAWAY, 0, frint_fns[a->esz]) =20 +TRANS_FEAT(FRINTN_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a, + FPROUNDING_TIEEVEN, 1, frint_fns[a->esz]) +TRANS_FEAT(FRINTP_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a, + FPROUNDING_POSINF, 1, frint_fns[a->esz]) +TRANS_FEAT(FRINTM_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a, + FPROUNDING_NEGINF, 1, frint_fns[a->esz]) +TRANS_FEAT(FRINTZ_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a, + FPROUNDING_ZERO, 1, frint_fns[a->esz]) +TRANS_FEAT(FRINTA_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a, + FPROUNDING_TIEAWAY, 1, frint_fns[a->esz]) + static gen_helper_gvec_3_ptr * const frecpx_fns[] =3D { NULL, gen_helper_sve_frecpx_h, gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637390; cv=none; d=zohomail.com; s=zohoarc; b=ZyH7raqXNbvgY077lh7NonhDYYg0fyoK2dEVN4Jaz0TNe5ny+b91H7AcWGkn/dnayZmsL0EM5zdMrD7qiW+Pwlo5Ux/BctjWqo5jGXONqWa6AWhAuA9/DVX7hreMN91huXloLPPVrDZNRbU7kPro+Z7yMg6XoFn9BfW+7Y6ITJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637390; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=jQlAupbk8yS2XMtWWkeHglESBt2Myt7OXOOVYx/Sdaw=; b=CZDK62vRFvTUgAXV3SXgedAt+tKqmBnjk30CgcXMfU2OW07WQy/dmrN5Dlz0pEbABa7YxhxFU63iODtU1myXIa4CFpPIhX3t2kjnpTQEW5GBmgXEE3+94Wttcf5JXCe9m2FfyqjX8eMjwABp63YUCifglWOdVevrR7AqjGU3ZMY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637390235925.322594567966; Tue, 16 Jun 2026 12:16:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAs-0000Yk-Vq; Tue, 16 Jun 2026 15:10:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8V-0004ii-2Z for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:51 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8R-0001Db-U2 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:46 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-461edb387ddso546094f8f.3 for ; Tue, 16 Jun 2026 12:07:43 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636862; x=1782241662; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jQlAupbk8yS2XMtWWkeHglESBt2Myt7OXOOVYx/Sdaw=; b=t/nJN2Ik5N6J5C3FXKGHQNzfNEcWCZNG/nUQT9msXliKylBTSV5WKeF5Mzqwbhwopa 6uNM5NA8Lvl8wutNK6EvmT8ARAj5iWzhm/DxDG9/N/Tk1n7B9rLS4HVHrXjm/uO9TLKZ 17NDdCgiyg6qccVMok0/Q0ZkeUHQwMhjN29t5EPIxkAhPU++faZRUjUPNeMjTE/7D1Ho IE2jUX1IMn+KTBg/E9SR5dOCQwid/muRiZ+RDb/Z/xjP1NWM51yRMp4aSC6Nuy+DuCkp MJYEJp9GHUVHsU6EkL4nNLSg9i91VseWay1Kh6OkB8RFQoujS+FcVMAk/Ypj13axD/po DaFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636862; x=1782241662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=jQlAupbk8yS2XMtWWkeHglESBt2Myt7OXOOVYx/Sdaw=; b=hFtgsNzIXE6JmjA/lqHjZcv/DWlRFvCLDK7X+RVAaAtaJnn78fDu/7MX8pLcy/UEZK rY0KFnuAUVnI7xovD42G+96aqd6NijKG1KjiHkkzjtZ1lMco1qpVNeyZJMiJ1OqxaPcv kaT43MG3ZaN41g8V6MGAVyjt0gQu+aF30Ohc+NWLGsp4VxZVdEDFkbyzBAM0FfLr0PSS mw1s9mC3+wxBU6ekU/Ix9V94/4luQ2klXmGQK/9BcEk/K9YcBRoZ/SaBWf6m1Wi+uWwm KmufUAcvd6eZNovWI+3qW9y1grDa1E/UDFD/vWmCTqQbPGT3YVGZnQndt9/iRm5zubdy n3ZQ== X-Gm-Message-State: AOJu0YxbmiiwABGpGvExhjSzWIONJN9BjRA8SZhmd2ew5nGXOUGoAofL 1YbKZ6CO7gb+D4cgNYx1VT399O3rz/CXXX0Ip7Ck9X7TIjzY2CYfWglzEu0NUmq61N4iosWjNTo prhb1 X-Gm-Gg: Acq92OFQ+RYKK6Y3tIwVePDtPov/S5WvuE63D88NVfywt0bjjMNfLFuQeIfXbM4nv0a n/wUOZdyx6RqF6dyr+wfvJjDtSA98tTT79Ihzl5SXN1uU827OZ5ytyQ501M36SWdGfjoLCc7oNB Pf7nhCeEXVU3bnzTdmc4IcDsh16O5U4hnt+PwcS2FVV22fG8ZxqfO+RqivNb2qHTh9C+gGv9YoM HaemcQFsVyp1BYcsd9qQvc9U3EzRX2CtAeIoa2i8JNwHpieR5jTCQKNfiAhrCQsUpbtH3PXLfws +CWp/G1fv2IoFGwlVJkSGrxSOPEKFNlXCUD2WVm91mX6dxXcTjvkx2IU9GuGuqP1C8IJzV6Q0jx dHMVyg8HFKSIK7y/wo2o6acpeMQeACN11w3TEczZybXSDGLEF0vGphJjHzs3r61uTmqdA5gU9ha /YLHgpjpfN3vQRCzzQMVqmLlXEwihY05+dT9xiTk1O7wIGG7Og2ic6TFughrKJmxmsaKmd1cZKz GmCH0IgxjFb5cpUD9YYGJBHErqiY+jj X-Received: by 2002:adf:fcca:0:b0:45e:f302:95b with SMTP id ffacd0b85a97d-46238f972damr797946f8f.37.1781636862258; Tue, 16 Jun 2026 12:07:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 55/61] target/arm: Implement Floating-point convert (predicated, zeroing) Date: Tue, 16 Jun 2026 20:06:32 +0100 Message-ID: <20260616190639.3462006-56-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637391901158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is FCVTX, FCVT and BFCVT. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 11 +++++++++++ target/arm/tcg/translate-sve.c | 22 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 099cd4e93d..889ff85f72 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1215,6 +1215,17 @@ FCVT_hd_m 01100101 11 0010 01 101 ... ..... ..= ... @rd_pg_rn_e0 FCVT_ds_m 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_= e0 FCVT_sd_m 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_= e0 =20 +FCVTX_ds_z 01100100 00 0110 101 10 ... ..... ..... @rd_pg_rn_= e0 + +FCVT_sh_z 01100100 10 0110 101 00 ... ..... ..... @rd_pg_rn_= e0 +FCVT_hs_z 01100100 10 0110 101 01 ... ..... ..... @rd_pg_rn_= e0 +BFCVT_z 01100100 10 0110 101 10 ... ..... ..... @rd_pg_rn_= e0 + +FCVT_dh_z 01100100 11 0110 101 00 ... ..... ..... @rd_pg_rn_= e0 +FCVT_hd_z 01100100 11 0110 101 01 ... ..... ..... @rd_pg_rn_= e0 +FCVT_ds_z 01100100 11 0110 101 10 ... ..... ..... @rd_pg_rn_= e0 +FCVT_sd_z 01100100 11 0110 101 11 ... ..... ..... @rd_pg_rn_= e0 + # SVE floating-point convert to integer FCVTZS_hh_m 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_= e0 FCVTZU_hh_m 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_= e0 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 64ee1f7752..d610ea561d 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4588,21 +4588,40 @@ TRANS_FEAT(FCMLA_zzxz, aa64_sme_or_sve, gen_gvec_fp= st_zzzz, fcmla_idx_fns[a->esz =20 TRANS_FEAT(FCVT_sh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sh, a, 0, FPST_A64) +TRANS_FEAT(FCVT_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvt_sh, a, 1, FPST_A64) + TRANS_FEAT(FCVT_hs_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16) +TRANS_FEAT(FCVT_hs_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvt_hs, a, 1, FPST_A64_F16) =20 TRANS_FEAT(BFCVT_m, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) +TRANS_FEAT(BFCVT_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_bfcvt, a, 1, + s->fpcr_ah ? FPST_AH : FPST_A64) =20 TRANS_FEAT(FCVT_dh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_dh, a, 0, FPST_A64) +TRANS_FEAT(FCVT_dh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvt_dh, a, 1, FPST_A64) + TRANS_FEAT(FCVT_hd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hd, a, 0, FPST_A64_F16) +TRANS_FEAT(FCVT_hd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvt_hd, a, 1, FPST_A64_F16) + TRANS_FEAT(FCVT_ds_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_ds, a, 0, FPST_A64) +TRANS_FEAT(FCVT_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvt_ds, a, 1, FPST_A64) + TRANS_FEAT(FCVT_sd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sd, a, 0, FPST_A64) +TRANS_FEAT(FCVT_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvt_sd, a, 1, FPST_A64) =20 TRANS_FEAT(FCVTZS_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hh, a, 0, FPST_A64_F16) @@ -8017,6 +8036,9 @@ TRANS_FEAT(FCVTLT_sd_m, aa64_sme_or_sve2, gen_gvec_fp= st_arg_zpz, =20 TRANS_FEAT(FCVTX_ds_m, aa64_sme_or_sve2, do_frint_mode, a, FPROUNDING_ODD, 0, gen_helper_sve_fcvt_ds) +TRANS_FEAT(FCVTX_ds_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a, + FPROUNDING_ODD, 1, gen_helper_sve_fcvt_ds) + TRANS_FEAT(FCVTXNT_ds_m, aa64_sme_or_sve2, do_frint_mode, a, FPROUNDING_ODD, 0, gen_helper_sve2_fcvtnt_ds) =20 --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637346; cv=none; d=zohomail.com; s=zohoarc; b=H1qwKJYr6u5ncN6Oujw9uanYbLTDIN9OrcSV9l7sqvF4apIAzQwxgZHmlkcasC1bOXSnWKsLzmtk5lPtkVZ8l2K24Aqhlynyx1GL2ez+1iHlCgMh2x6kzs+PUpsU4OulworPA2LIYY68rf1lmnSW1GZOr7rALWgr8UUxVpb9jf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637346; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=q0v3JcOtGra5T2P8x7jT2gjDT/0evPGezEh4zg5AF2E=; b=UBNNbI+HKJziEsR0mlp6InDK5/ra2AF4uSUanIX50mVrDYz7s4xl26RkgKGRzz3sAoo+HOgCmRZ6gLE1ski6f6YQnMksGV1j4AcGdQ53sFk3Vojk1pMbcBmUAtS4fiFaBrqKIj6JG4rDlm+NzV2cbjihk9a7du0DoNBP93Be5SA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637346163382.54327522701897; Tue, 16 Jun 2026 12:15:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZCD-0002GR-RP; Tue, 16 Jun 2026 15:11:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8W-0004jT-Sp for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:51 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8T-0001E0-Mb for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:48 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-490b1bbcf3aso37694145e9.1 for ; Tue, 16 Jun 2026 12:07:44 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636863; x=1782241663; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=q0v3JcOtGra5T2P8x7jT2gjDT/0evPGezEh4zg5AF2E=; b=Gmy/a9B9YqHWn34HlPGJgge5ZwEnfnvY03SmwKs7PGCzshmDa0Oa5jUZ0UcrqG/jl2 rKdkcHuFFoirGpSDrAOY69kZ9BZ/3agSQdsU/NvUmNg+HZ2XtCt8gZ5t9Y2eXLeI2BFO GNheiWMN364pQtOt08rQO4lpLBqUuGJ3M+OPsJJW0GqoCl9YpT4GdI9EWD0sGoTLaDK6 /aue+FnOPAxDHOIFowVUsCXS0+3ndU4vwclbjsJSOjuNHAusPK5wCv1JiblSUvc+g3WI L3dG9HM8lb0QJbSnQLT1qX0d1gh4vXlHW+7vkANHC4Oppy4LMKW9m7pnwwwX9bylARbm 2NAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636863; x=1782241663; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=q0v3JcOtGra5T2P8x7jT2gjDT/0evPGezEh4zg5AF2E=; b=cQUhsdxjzGcQfFioOLJmP2vodkGWumH3CjNc4mxLFmUMjpwFsjfU3G+Nt/HyOZTqxp esq36SWFJEpzEc3hyfpKG5CTnhlDW2JoIVJdBi4LtRjQNzfOl63PEM8NRU0SruQ+kYb+ 4sRsxYIijvBxM6VbfCVUW9yesuztZtMC2oipn+wt0jyxgSxnouxluZBLVksxaPWWBdRY QHQPce+G97HoZkkSJYgo6Rko0avHC5exULtSpkN6wWKAoyaY7O0WGM0uaIZTenZgclnh /wYoJGaKp8DNQKm8Vo1hdmtc4ZPj79DQ6dB75qVfZqUB1U9NWRUEjI4eO5L1AWIQ/BUm 6l7A== X-Gm-Message-State: AOJu0YwUz36mR//B36zxY/18wrQxyaP7SyqvDWw+gicPVV7AjlOiYdyF I5ILlZn/GUWhMx5IC6jBORoycETLs/TPRGQlohSEqb9sq9x2chdM10K9VMWPjwNgivelISB03f5 en2QT X-Gm-Gg: Acq92OFirnH3b88Exuje0WKgAItqF7x0Mozv32oSGz7Mn08NliBC4AW3X+NlH0mxxPD sYZQvxQcyvhfNOnPqDqccIavarbkVayLm5gabzzVXSdbHhRZRsPEQgFmk139pJxN/To0VPeYIYM /TvpqEOWfFTSNZk6Tsje478Znyadj6gWWwTWkBB8GnDJVL/8s5vHFvaEAhe039DRd5DwxNa19oI IksWjA9K2nevye66S858JwiUf8RhzBLTauYERCnAgu/8oakbtwoR91KH7RAl+w7+ahGGgAf5IY9 T/TlU14/VSx3blIisNzy4WB/s4boeAFNM94B7UOMBvsS7rSABZ0wUpLc6wfUqTUVVXwzZ3Z/hs9 zESHWr8pzW3TBadt4UKxSmM/2W0dLGOHnBuO1OZQZ5YdqIG06vS4ZpklI6NwGWZocEfqEntkAlQ yOj5wuLj9JOqUuV29nuQFJ8wgjQukQckL9PUkjRXka3toqYflNZ86zY25G5e74y5ZQOpuYm0v/D 4cvy6IhLaqiQmfXORKq67bt4UM2lhd7 X-Received: by 2002:a05:600c:8189:b0:490:688b:f9f8 with SMTP id 5b1f17b1804b1-492333dd136mr14472375e9.27.1781636863228; Tue, 16 Jun 2026 12:07:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 56/61] target/arm: Implement Floating-point square root (predicated, zeroing) Date: Tue, 16 Jun 2026 20:06:33 +0100 Message-ID: <20260616190639.3462006-57-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637347624158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is FRECPX and FSQRT. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 3 +++ target/arm/tcg/translate-sve.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 889ff85f72..c39d80360f 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1263,6 +1263,9 @@ FRINTI_z 01100100 .. 011 001 111 ... ..... ...= .. @rd_pg_rn FRECPX_m 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn FSQRT_m 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn =20 +FRECPX_z 01100100 .. 011 011 100 ... ..... ..... @rd_pg_rn +FSQRT_z 01100100 .. 011 011 101 ... ..... ..... @rd_pg_rn + # SVE integer convert to floating-point SCVTF_hh_m 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_= e0 SCVTF_sh_m 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_= e0 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index d610ea561d..1ea9454267 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4736,6 +4736,8 @@ static gen_helper_gvec_3_ptr * const frecpx_fns[] =3D= { }; TRANS_FEAT(FRECPX_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->esz], a, 0, select_ah_fpst(s, a->esz)) +TRANS_FEAT(FRECPX_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + frecpx_fns[a->esz], a, 1, select_ah_fpst(s, a->esz)) =20 static gen_helper_gvec_3_ptr * const fsqrt_fns[] =3D { NULL, gen_helper_sve_fsqrt_h, @@ -4744,6 +4746,9 @@ static gen_helper_gvec_3_ptr * const fsqrt_fns[] =3D { TRANS_FEAT(FSQRT_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) +TRANS_FEAT(FSQRT_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + fsqrt_fns[a->esz], a, 1, + a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 TRANS_FEAT(SCVTF_hh_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_hh, a, 0, FPST_A64_F16) --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637336; cv=none; d=zohomail.com; s=zohoarc; b=Zb8cDC8DDZdeBYAW2ZXfbTi1UV/A6zS5I3A4BlEYOq1SIrPpXllocuf+owDGbBk5CtGZ6r9pQUOH4z1xjGyU1GS5+hThZxnKaUtCvfhwUbO0EKdwrI03v4JmjO4UBZ2OwUHsPrm39IqePylMq3Sbv/xqlh36cB24WHpGEhTKCqI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637336; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=i/smW6GL8OKBS/PXid8fym6NYK4D3UNHQvOfP4IehXY=; b=fXrFLp6t9rAb9XMYzmRjN41nBDLgP4QYg+NcpZThx/zA7sNF2Xj0SnfPir/QbQzrmBR4FG8UfRhaQIDU1LSVJuBEfRlG1B7LEG4U+akE/x7LbwlR6+g9uurWxVjCeRqgK+FzkH54D21iFJ2BlbKwFnfSn/vtLEoEcedTJ5JztJs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637336820226.74862903661574; Tue, 16 Jun 2026 12:15:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZDM-00033k-EG; Tue, 16 Jun 2026 15:12:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8Z-0004mn-Ip for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:53 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8V-0001Fk-5B for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:51 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-46019edc13dso2389778f8f.1 for ; Tue, 16 Jun 2026 12:07:46 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636865; x=1782241665; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=i/smW6GL8OKBS/PXid8fym6NYK4D3UNHQvOfP4IehXY=; b=OwF6TPWG/uiYSg4XoxZJ0DzoUT9j31LYROi21M0pXIAOFOxVe/GUOv+Ba6/jzRTyRI IncQrc4rljYnMuC5xLwmZUh7mkfwX8p8m++yQJ7J1P5MQm0QJdOQJ8SzQ5O6Ts0FxYa2 QECGNChSIS3+lqmzxxmJMksLNA/EU5g3USG3l3Jd6z6jQCwZp6jAW6d9e8OQ8xsmpaei hgwkrbx/6kke6zZ3g36Hi8pWYR5aHq4kBAHjGB0PROaKy5LVo+ke2whd+2SZ2H4aveLh DjHIeS3KUAz/jHGxRB/uOaHexkzFB4cFK/9zhOz+JMMMaNgzUwse8GYgo7qnDtSlQau3 8pfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636865; x=1782241665; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=i/smW6GL8OKBS/PXid8fym6NYK4D3UNHQvOfP4IehXY=; b=O3IxMfEP8hamBzwi2hIXSVS74FTcJDmy0xT2p4NT5vBKCtn6WNbtDP+i8J+gWZFCPs yVxIcYyUgG1mi7Le3lNZa9BfykTf1y//4+4680JL2RJU8MN9JWBoJVWzMpZO/TTv45+x doh7v0LaG7xwREK2Kjr1tF+fQfmuuY/ngFIAXt59/0Ihp+UOUmLDPalefYecbjh4GlTZ yXuqSZ2DCWyYLNCcUJ7kWwaX0b39ZRu+xXW4Tgd2KcWGDHfESZuYMMB0N5Wz6KL9iPu0 LcCwCYy4r36pj3Fp3XHExPgfbWl+ZL1LXrNtYE+qDtFooaiLNgu5cEmEDcoxpuAyGJQJ 2Lwg== X-Gm-Message-State: AOJu0YzyJp831lEXwA15KxDGgP2AULiUS3UXPBY6bAAhdpeVH54qUbZZ ComD2bNEVxEG5CWz0MAYwmPDEE+JpxK5lO/UskKUFVqOUUSCdVtbvP8tE6yh4pgKp6lTFsb9XAZ 9pw1r X-Gm-Gg: Acq92OHm1rPwSsN393aLS+JaDWsalRcGpCtUzOqwfyx631tbYFSzMkI7V4Ot5bmSCSg n8t+1rZVBijHTp9/38hX/zSGeMxcdvKsEVzpucljLkBb3sN+sBejqYOShSIujMUXrOCkLkScK8A DZTl7Evd9U1X+KqWJ7YqtDc1Pi0YkbhbB6WyNhvOnYvZJbVNhhBsm+yxuhuD1rgWTriDlO/P6i4 gFiypRUkcrUwhHGLU0rpJxNLJPRJQRSmCJYaebgxlyHM7iD9dz5o9mk8WqmbB+x6h75J7EeMP0r h1ijZqsw5wOWzZXXbQKcSksWU529Tu7Ve1tY8vLS6WqxTNzWLeiq6JkKH5hYPQP3Sisx+89zT/x hI94JVFZkeaFICIDtJD6WDKtJsSmh01bLNV7zzwz5vte0X+2z0LjOpwgGs5l/rLygqh+KoH4VAU pr5Ph24AAy46poxSKkwMpkQ2954aW2z8qDLg2iSTaxyLBj1p1qXrkf0OtS/VB6bddrFeWW8FVc6 K7bpqNrh6Vr3ECUnn76w/jnshovGPil X-Received: by 2002:a5d:4ec4:0:b0:461:a15f:66c2 with SMTP id ffacd0b85a97d-46240cf967emr686568f8f.22.1781636864961; Tue, 16 Jun 2026 12:07:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 57/61] target/arm: Implement SCVTF, UCVTF (predicated, zeroing) Date: Tue, 16 Jun 2026 20:06:34 +0100 Message-ID: <20260616190639.3462006-58-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637337709158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 16 ++++++++++++++++ target/arm/tcg/translate-sve.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index c39d80360f..7460eee4a9 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1283,6 +1283,22 @@ UCVTF_sd_m 01100101 11 010 00 1 101 ... ..... .= .... @rd_pg_rn_e0 UCVTF_ds_m 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_= e0 UCVTF_dd_m 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_= e0 =20 +SCVTF_hh_z 01100100 01 011 10 0 110 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_sh_z 01100100 01 011 10 1 100 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_ss_z 01100100 10 011 10 1 100 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_sd_z 01100100 11 011 10 0 100 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_dh_z 01100100 01 011 10 1 110 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_ds_z 01100100 11 011 10 1 100 ... ..... ..... @rd_pg_rn_= e0 +SCVTF_dd_z 01100100 11 011 10 1 110 ... ..... ..... @rd_pg_rn_= e0 + +UCVTF_hh_z 01100100 01 011 10 0 111 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_sh_z 01100100 01 011 10 1 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_ss_z 01100100 10 011 10 1 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_sd_z 01100100 11 011 10 0 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_dh_z 01100100 01 011 10 1 111 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_ds_z 01100100 11 011 10 1 101 ... ..... ..... @rd_pg_rn_= e0 +UCVTF_dd_z 01100100 11 011 10 1 111 ... ..... ..... @rd_pg_rn_= e0 + ### SVE Memory - 32-bit Gather and Unsized Contiguous Group =20 # SVE load predicate register diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 1ea9454267..4ac59664ae 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4784,6 +4784,40 @@ TRANS_FEAT(UCVTF_sd_m, aa64_sme_or_sve, gen_gvec_fps= t_arg_zpz, TRANS_FEAT(UCVTF_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_dd, a, 0, FPST_A64) =20 +TRANS_FEAT(SCVTF_hh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_scvt_hh, a, 1, FPST_A64_F16) +TRANS_FEAT(SCVTF_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_scvt_sh, a, 1, FPST_A64_F16) +TRANS_FEAT(SCVTF_dh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_scvt_dh, a, 1, FPST_A64_F16) + +TRANS_FEAT(SCVTF_ss_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_scvt_ss, a, 1, FPST_A64) +TRANS_FEAT(SCVTF_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_scvt_ds, a, 1, FPST_A64) + +TRANS_FEAT(SCVTF_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_scvt_sd, a, 1, FPST_A64) +TRANS_FEAT(SCVTF_dd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_scvt_dd, a, 1, FPST_A64) + +TRANS_FEAT(UCVTF_hh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_ucvt_hh, a, 1, FPST_A64_F16) +TRANS_FEAT(UCVTF_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_ucvt_sh, a, 1, FPST_A64_F16) +TRANS_FEAT(UCVTF_dh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_ucvt_dh, a, 1, FPST_A64_F16) + +TRANS_FEAT(UCVTF_ss_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_ucvt_ss, a, 1, FPST_A64) +TRANS_FEAT(UCVTF_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_ucvt_ds, a, 1, FPST_A64) +TRANS_FEAT(UCVTF_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_ucvt_sd, a, 1, FPST_A64) + +TRANS_FEAT(UCVTF_dd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_ucvt_dd, a, 1, FPST_A64) + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637078; cv=none; d=zohomail.com; s=zohoarc; b=J3rpPzODpYPtFegriE22zOwv3TNLBbcJJWErF45B9fWbRFAhFpeS/0HE8uyeUIGZI7DEDJ4du20D0d+yTshqVuYwLAWQHLc8amr5xoA60ZkXiEu4YFm9NDx8XqTaQvep50v28diVVWBtZQPN6fdR5KBy6jGsl0LT2BAm24xtrvQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637078; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=It2pF6sViWJlDXaYTTIEvh4jj09OMY/MajD0dUSjtmM=; b=j8v0PHolBORk+QKfGBG5ZO9qMAG9/IW3v9/Gu5UI/8rxEA2LosnBW6lrdJXHfZcUy6YSStkSNyXO2fMyG4r2IxbUdt8KgquMMmNf7dFZWAPbutma4rYORe7+B8d/qtfe3gVlLTyGJjTQZZ+p/HV5kcJQDGlC9BYTLr3xeN2CjOs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637078537708.3021140308491; Tue, 16 Jun 2026 12:11:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZBZ-00014U-44; Tue, 16 Jun 2026 15:10:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8Z-0004my-Vh for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:54 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8V-0001GM-RZ for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:51 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-490be29c1c5so53333385e9.2 for ; Tue, 16 Jun 2026 12:07:47 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636866; x=1782241666; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=It2pF6sViWJlDXaYTTIEvh4jj09OMY/MajD0dUSjtmM=; b=LBy0+z3goQMSg1ba0lzzCO9As4cBvNnXNuaBBS0kMCTLeRATpvvdXHh/YWHKGgSChX PtDLTNvT0+Jo50xmc6r2RcF46PAJ6x/brmVX9LPIzXrrciar86258Wx/XPwaP+1VlS4C IZlHN3kimDfIHcU2gq+hKhwdNkw2kJFyuovsE+McJSyo9UmmF6Fx9Qp+H9flJnUPvrmk N2//Cpxk4rsSxaMxDxfJ8DL3OlqxQcCl8laY5K0/KC/CfIbm+9koDAu4UgX2ARzOZmRE MFKfwtETW81OlTfZAjhCAkUKjsOEVkU8PdJ9x+ss0FbTgWLtNr27kluw+ut0JLGiMN5e 2CUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636866; x=1782241666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=It2pF6sViWJlDXaYTTIEvh4jj09OMY/MajD0dUSjtmM=; b=Tn8NiZd2pONEMVwuWsT/9MPoDjJMSTkSie88FWLrh2mHjDFEsXRX3oyBotpG3OdOt3 3KnhYojER5IeUmTHYW5qjS0odJE+jooqZqgTIQ43DBiSTYH0m6ZelFqg4Gr/f7wWFjhS PrcoPZUPaWJFdURSyt7GScvs/55B4ci/CuDbw0CYkSQBTQat+ESVeduMGmHfy1HMRndX 8TnfA+qbJSOZuqNZ4W92De195Oj2iLpXc4PGz2Vov2VEZhB7KBX+TcFWcMLVK10q+x9D eCX2ebezQ8dj1PJlb79Oa0XWKFmbRx7iJVUz82XPTFKT/atM7AA9StIXHl0NH9+3IFtB SOtA== X-Gm-Message-State: AOJu0YyKqnH4fJqu6gb8Ltrt+RFfvR2/8LsuC9j8lQS9+aOjq+EBdYMF UcLzZbBokFlnu525vSnDs/etRPpK3Z/DHO1v4iBuEL5/9tRQn1VAnZvqXCnxCw5v4SGS6XtsUy7 OAuPY X-Gm-Gg: Acq92OFixGRln6MCQxhiIMaYRNGNkQ0OUsF/oINu9l5FU4qQXWOgz9hJrFQdXII6NYF KLg38SNHOw3WpuJIdwKlmgvZ5yiADwUL2Xlue8HP3kheZXfbUZuJ2fcolAYdKPJCpsYPXP6soql /+Ir+XJmFYIWAaoRva+cQzAtsteF+L8S+OmraWB3OzEa3rhDgzrx3RLlVcfrPonadvgWUJ0/AIP ZY/8yQNANZQ5PGy1rDosbA/bVPh1goxmwcLS+lB0wnapywACJ0//6WMSWj2mVjkP7avyWytINHt 9IDOaNAY8Luu9IcVCVUMyUuVUdl5/QfvodnGjkT5CF9J7AyIhiCFcA/JzeuIIbD9Npsjmk9kQDQ 7yWikNrFKrOl1U2hFdNkPim+FhJmKTwdidKcuSiPcDM/1GSSCHdIBYD33iai5VNC8LKejfhFD85 a/+ixTai323Jmw1cen0N6oXbVv+GQ02nTbRC8g0k7+m0cXQMq0aD5qGOhgEHCidbTVbjfDZ87+q 1Z0zpspzI2+KJtXnx6wRbJV/LQD1im8YnHFdlXIQ3c= X-Received: by 2002:a05:600c:1e0f:b0:490:e5c1:b88d with SMTP id 5b1f17b1804b1-492333babfbmr14323085e9.1.1781636866092; Tue, 16 Jun 2026 12:07:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 58/61] target/arm: Implement FRINT{32,64}{X,Z} Date: Tue, 16 Jun 2026 20:06:35 +0100 Message-ID: <20260616190639.3462006-59-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637079897158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve-defs.h | 9 ++++++++ target/arm/tcg/sve.decode | 20 ++++++++++++++++++ target/arm/tcg/sve_helper.c | 5 +++++ target/arm/tcg/translate-sve.c | 36 ++++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) diff --git a/target/arm/tcg/helper-sve-defs.h b/target/arm/tcg/helper-sve-d= efs.h index f97c31763f..de2254bb19 100644 --- a/target/arm/tcg/helper-sve-defs.h +++ b/target/arm/tcg/helper-sve-defs.h @@ -1441,6 +1441,15 @@ DEF_HELPER_FLAGS_5(sve_frintx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_frintx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) =20 +DEF_HELPER_FLAGS_5(sve2p2_frint32_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(sve2p2_frint64_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(sve2p2_frint32_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(sve2p2_frint64_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + DEF_HELPER_FLAGS_5(sve_frecpx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_5(sve_frecpx_s, TCG_CALL_NO_RWG, diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 7460eee4a9..5c814c7769 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1259,6 +1259,26 @@ FRINTA_z 01100100 .. 011 001 100 ... ..... ..= ... @rd_pg_rn FRINTX_z 01100100 .. 011 001 110 ... ..... ..... @rd_pg_rn FRINTI_z 01100100 .. 011 001 111 ... ..... ..... @rd_pg_rn =20 +FRINT32X_s_m 01100101 00 010 001 101 ... ..... ..... @rd_pg_rn_= e0 +FRINT32X_d_m 01100101 00 010 011 101 ... ..... ..... @rd_pg_rn_= e0 +FRINT64X_s_m 01100101 00 010 101 101 ... ..... ..... @rd_pg_rn_= e0 +FRINT64X_d_m 01100101 00 010 111 101 ... ..... ..... @rd_pg_rn_= e0 + +FRINT32X_s_z 01100100 00 011 100 101 ... ..... ..... @rd_pg_rn_= e0 +FRINT32X_d_z 01100100 00 011 100 111 ... ..... ..... @rd_pg_rn_= e0 +FRINT64X_s_z 01100100 00 011 101 101 ... ..... ..... @rd_pg_rn_= e0 +FRINT64X_d_z 01100100 00 011 101 111 ... ..... ..... @rd_pg_rn_= e0 + +FRINT32Z_s_m 01100101 00 010 000 101 ... ..... ..... @rd_pg_rn_= e0 +FRINT32Z_d_m 01100101 00 010 010 101 ... ..... ..... @rd_pg_rn_= e0 +FRINT64Z_s_m 01100101 00 010 100 101 ... ..... ..... @rd_pg_rn_= e0 +FRINT64Z_d_m 01100101 00 010 110 101 ... ..... ..... @rd_pg_rn_= e0 + +FRINT32Z_s_z 01100100 00 011 100 100 ... ..... ..... @rd_pg_rn_= e0 +FRINT32Z_d_z 01100100 00 011 100 110 ... ..... ..... @rd_pg_rn_= e0 +FRINT64Z_s_z 01100100 00 011 101 100 ... ..... ..... @rd_pg_rn_= e0 +FRINT64Z_d_z 01100100 00 011 101 110 ... ..... ..... @rd_pg_rn_= e0 + # SVE floating-point unary operations FRECPX_m 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn FSQRT_m 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 1711444800..f8e62cb11b 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -5017,6 +5017,11 @@ DO_ZPZ_FP(sve_frintx_h, uint16_t, H1_2, float16_roun= d_to_int) DO_ZPZ_FP(sve_frintx_s, uint32_t, H1_4, float32_round_to_int) DO_ZPZ_FP(sve_frintx_d, uint64_t, H1_8, float64_round_to_int) =20 +DO_ZPZ_FP(sve2p2_frint32_s, uint32_t, H1_4, helper_frint32_s) +DO_ZPZ_FP(sve2p2_frint64_s, uint32_t, H1_4, helper_frint64_s) +DO_ZPZ_FP(sve2p2_frint32_d, uint64_t, H1_8, helper_frint32_d) +DO_ZPZ_FP(sve2p2_frint64_d, uint64_t, H1_8, helper_frint64_d) + DO_ZPZ_FP(sve_frecpx_h, uint16_t, H1_2, helper_frecpx_f16) DO_ZPZ_FP(sve_frecpx_s, uint32_t, H1_4, helper_frecpx_f32) DO_ZPZ_FP(sve_frecpx_d, uint64_t, H1_8, helper_frecpx_f64) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 4ac59664ae..a8d21dedca 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4730,6 +4730,42 @@ TRANS_FEAT(FRINTZ_z, aa64_sme2p2_or_sve2p2, do_frint= _mode, a, TRANS_FEAT(FRINTA_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a, FPROUNDING_TIEAWAY, 1, frint_fns[a->esz]) =20 +TRANS_FEAT(FRINT32X_s_m, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2p2_frint32_s, a, 0, FPST_A64) +TRANS_FEAT(FRINT32X_d_m, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2p2_frint32_d, a, 0, FPST_A64) +TRANS_FEAT(FRINT64X_s_m, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2p2_frint64_s, a, 0, FPST_A64) +TRANS_FEAT(FRINT64X_d_m, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2p2_frint64_d, a, 0, FPST_A64) + +TRANS_FEAT(FRINT32X_s_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2p2_frint32_s, a, 1, FPST_A64) +TRANS_FEAT(FRINT32X_d_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2p2_frint32_d, a, 1, FPST_A64) +TRANS_FEAT(FRINT64X_s_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2p2_frint64_s, a, 1, FPST_A64) +TRANS_FEAT(FRINT64X_d_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2p2_frint64_d, a, 1, FPST_A64) + +TRANS_FEAT(FRINT32Z_s_m, aa64_sme2p2_or_sve2p2, do_frint_mode, + a, FPROUNDING_ZERO, 0, gen_helper_sve2p2_frint32_s) +TRANS_FEAT(FRINT32Z_d_m, aa64_sme2p2_or_sve2p2, do_frint_mode, + a, FPROUNDING_ZERO, 0, gen_helper_sve2p2_frint32_d) +TRANS_FEAT(FRINT64Z_s_m, aa64_sme2p2_or_sve2p2, do_frint_mode, + a, FPROUNDING_ZERO, 0, gen_helper_sve2p2_frint64_s) +TRANS_FEAT(FRINT64Z_d_m, aa64_sme2p2_or_sve2p2, do_frint_mode, + a, FPROUNDING_ZERO, 0, gen_helper_sve2p2_frint64_d) + +TRANS_FEAT(FRINT32Z_s_z, aa64_sme2p2_or_sve2p2, do_frint_mode, + a, FPROUNDING_ZERO, 1, gen_helper_sve2p2_frint32_s) +TRANS_FEAT(FRINT32Z_d_z, aa64_sme2p2_or_sve2p2, do_frint_mode, + a, FPROUNDING_ZERO, 1, gen_helper_sve2p2_frint32_d) +TRANS_FEAT(FRINT64Z_s_z, aa64_sme2p2_or_sve2p2, do_frint_mode, + a, FPROUNDING_ZERO, 1, gen_helper_sve2p2_frint64_s) +TRANS_FEAT(FRINT64Z_d_z, aa64_sme2p2_or_sve2p2, do_frint_mode, + a, FPROUNDING_ZERO, 1, gen_helper_sve2p2_frint64_d) + static gen_helper_gvec_3_ptr * const frecpx_fns[] =3D { NULL, gen_helper_sve_frecpx_h, gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637265; cv=none; d=zohomail.com; s=zohoarc; b=k/7VswCrJmCXxy4mmaXnbWhYI3yBoBAL0Wucit0KaPz0PpWacS3fcnsSgblyq/sgY0zESOXHzvi6YgdisfacZBu3wg9xdnrbaPGtrAAAuEJkrE/U/PxV1rfaJvz4by8NyBlxz2+ehavm/IQTzY6Lw9cd77QJUkwf0v6NcrA+/3o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637265; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=YZz7HH0GB8/vK9KUD+19bLJ7tmE5IW5AABeSFZsxDV0=; b=ISmdqVjbTZlyWAyXs9xodDdQhg1Bs0ACZsgGC/ilo2uWcDYwkvsu5z8sosinUTeLxsvabNFNMGHf7MBEvO1V7hbzgHfv4gOyokJcvi9uh712gUaMtv3xB0Wz21ZYaXjMnqb50s6PUHlaHrd6OE4RmVcO0OzUjc9/yBuyueL40xU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637265671333.7385384967167; Tue, 16 Jun 2026 12:14:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZAf-0008BT-9U; Tue, 16 Jun 2026 15:10:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8a-0004n1-VQ for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:55 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8W-0001Gk-N8 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:52 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-4624c1409c9so80360f8f.3 for ; Tue, 16 Jun 2026 12:07:48 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636867; x=1782241667; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=YZz7HH0GB8/vK9KUD+19bLJ7tmE5IW5AABeSFZsxDV0=; b=Wxtk3m4+yxXaRujtwhwFrHofVAysUz45FRTQShrbxPmI8vDk3/3ohrWZpKmwutQVgd 2ChOYhCm4Jwab/P/SZYsobPRxk73a6Wup5ZK70jQ/aIxGiEPkQQeTssz+CUZ1vPpAmgw XIG8Jz7BoXoSQHsPMeTgxs8YFm9XfpYKjGYTFXyAk9aOKLr4YRY3fRZo5QbQVbBeggB5 bpTEN9O+AhhwUD3s5aF6YBmtY4j34dx2vINXsOmWm/Jpp5IwMRN7d3RC3yww2QJiPRIS CAimoAQ+sy30Mxw0pdUR2PhRhprGxB3T/lz92HXL7j9JlOgIJWGjVMfd3mNgdYnF0H5O hEjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636867; x=1782241667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=YZz7HH0GB8/vK9KUD+19bLJ7tmE5IW5AABeSFZsxDV0=; b=hMnIbVE+Otcpx2xPX8w8Mss0DO8EZwTFkR5OSKuty8xu9DebmEEzYzYeq2P7tCm833 8YNCrxFo/sFtcMtQNtiw0rng6tnYAUefG7kHdwObPLSecg7RBvUHeaq9/7kkBA3mQMJW g+DEBNBbqARd/pQbDV9XV9YrQAiXyyDN0YHjijhcZiPfDeROeLGw466AsO4tAuu9NP7B +9O/D5YnrUZz64DYTZnNVEE+ZF3NSUyLRabBUzbdqkHx5WUGn1WASE/6SBFZwLi3z/ev t6teUFu88uLPb2nxrS7zr+bOZ5Soyko1w6zadCRyzzVUm8lJYw8s4JJW44lh5y4k8You 07TA== X-Gm-Message-State: AOJu0Yzred7Jrl3nT4w0KvOKOjGUaksxmJQlklPgI6yYbk4v5pWHOTmZ I8xcHBbQveh1DNIrF/IaICA6TV1VRKrZuYSTU0/VrdR3F4oFxjQyNlvYZxvcXWS3sM/rAhSAPvc 7bBYy X-Gm-Gg: Acq92OHEEMOTdrrWRiZ2GtRMDems6Ct2TntdWgmSlyt6jRk3Sxss8R7UJd/gQb0trv6 rWDCo4kAsvj/sklESCZkUN2nm7PwcfvM85v+ck8wQTs/yoNs8PHNdB8QcnjMTz5SpLx+mMcFDvV 2Ijhh4XtqYl5m+ybWgJb8vpxMDCnM/7tdmbj6Ff7GFZkvkHAj7iNq2W1T3mNdWfJ9A7FvUdyG8M YCsmZ9gAObKDEP7Kiaq6R4QQdrjzh3M5DlSrnvKbf85uuVxxeOkMHSX8jQNZDuhN0pjhwFUiA5l G6Rc/ATbVqGyIpd7wnrdA+TJuEXQb6TRYpW7V5AXybQEA6zKW6GsFBjEtpED3MCgvjlcPFV6TUW JP42Z6kGVsseQLyOdQqCyI7kUkqZmiTulqMffT1cQuKtJ+n+8JW/1dhNMHH48Uz5Pwwi8tKCHGo QACNhYOomTnBvP1OBChLLwmf3JOSbtG2frSHupV5klWtE2kLvXCkA7TZEG74d8AIgNBICvLxyI/ a5OoaC0FgNcPr5aOWwaKtPTBJcmUulrUfECMSESD2o= X-Received: by 2002:adf:f883:0:b0:45e:ea9b:edf6 with SMTP id ffacd0b85a97d-46238acb28bmr1183462f8f.36.1781636866932; Tue, 16 Jun 2026 12:07:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 59/61] target/arm: Enable zeroing in DO_FCVT{N, L}T macros in sve_helper.c Date: Tue, 16 Jun 2026 20:06:36 +0100 Message-ID: <20260616190639.3462006-60-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637267287158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use the low bit of simd_data to hold a 'zeroing' bit. The simd_data field is currently unused and always 0. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index f8e62cb11b..a0a189eb1e 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -8595,6 +8595,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, = \ float_status *status, uint32_t desc) = \ { = \ intptr_t i =3D simd_oprsz(desc); = \ + bool zeroing =3D simd_data(desc) & 1; = \ uint64_t *g =3D vg; = \ do { = \ uint64_t pg =3D g[(i - 1) >> 6]; = \ @@ -8603,6 +8604,8 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, = \ if (likely((pg >> (i & 63)) & 1)) { = \ TYPEW nn =3D *(TYPEW *)(vn + HW(i)); = \ *(TYPEN *)(vd + HN(i + sizeof(TYPEN))) =3D OP(nn, status);= \ + } else if (zeroing) { = \ + *(TYPEN *)(vd + HN(i + sizeof(TYPEN))) =3D 0; = \ } = \ } while (i & 63); = \ } while (i !=3D 0); = \ @@ -8617,6 +8620,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, = \ float_status *status, uint32_t desc) = \ { = \ intptr_t i =3D simd_oprsz(desc); = \ + bool zeroing =3D simd_data(desc) & 1; = \ uint64_t *g =3D vg; = \ do { = \ uint64_t pg =3D g[(i - 1) >> 6]; = \ @@ -8625,6 +8629,8 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, = \ if (likely((pg >> (i & 63)) & 1)) { = \ TYPEN nn =3D *(TYPEN *)(vn + HN(i + sizeof(TYPEN))); = \ *(TYPEW *)(vd + HW(i)) =3D OP(nn, status); = \ + } else if (zeroing) { = \ + *(TYPEW *)(vd + HW(i)) =3D 0; = \ } = \ } while (i & 63); = \ } while (i !=3D 0); = \ --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637327; cv=none; d=zohomail.com; s=zohoarc; b=G/s7jvFKm2l148J2wecnnnmMvWDw/8jX5+wqW/G1kxFX7nU/26bdoaQkcfpv0qFl4qncV9gcnmoNH0xn8fJWvZdory1Lrz6A2UVtAhY2DBqeBrOFzvXszB9MBf3+zvPGmbe0VNFwq4b5mXaXY48IYivPtzEx4K8ogNueKpSicVM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637327; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=pydwboiAW0ie4TrQJ57zGqQSKcjPD0l8ffuTD4pEfpg=; b=WbjBH5xq8olrBGfSObd9ml5I8r3YJvKsI3FaqdiSB+LUtwTJGQdfkBuzm1ACorksHbnolVp8RSTny8bGAcB8PJoi7WoKyCGzGvaZtyxlTkMXW+f3ax4RHPbfqxTqmDyQMp31DAlvDMB4V+qfjsAasDa4DyzGJH9YZ1OAVbiJv0E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637327051291.0094898529384; Tue, 16 Jun 2026 12:15:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZEa-00057a-MG; Tue, 16 Jun 2026 15:14:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8b-0004n6-0m for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:55 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8X-0001H6-IA for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:52 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-46066e640easo3025347f8f.1 for ; Tue, 16 Jun 2026 12:07:48 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636868; x=1782241668; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=pydwboiAW0ie4TrQJ57zGqQSKcjPD0l8ffuTD4pEfpg=; b=Gf7We0RpWi0nTEyU4yg8w7za9rWa6WDBN8q3nykvEK0lRx4Eiwnzukxn/XEwzXXvSF KNBOv6E2P+/J9UcHOnr+s06J+WxYh8IOVS3KaA/svd/tbzSeicQRpA2N5uF0RWeiOIay G1BBcAEVRarKx3iupl7meCM8BTd4X8mjgsyfkpVjgUNds1ekqXMCME7L6RgX/ThJCMWZ j6WaQnNKNFu/kFw4Pf/WNKDytPXWXljCwTQ65CTEzMtm5V6+gippdW/qggf4yAj58+aq veGA/+NN58e1XJRPbjsbPsARpOTkrYh+m3E1vgzm0B3W9tM96zRwM4PR/uB+1hSIE7wI Qnsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636868; x=1782241668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=pydwboiAW0ie4TrQJ57zGqQSKcjPD0l8ffuTD4pEfpg=; b=U+MRnA+M+pVLO0hbftpV4hqRYAYCDtb5fBftDwIdkg+Ssma9lZDMxPi6O3K6nDeFgH +O0nH767EmjihblGGJ8hZAy4DPhoxHMnxUmTnIRum78vEaX/IY7yuCZOtDCCHGCgRJ0n ZjCP5eaQ9D0P1h8L90QdVQj99DlESvGa22FncKzwNOeX9Vmu3shn2ulIxZYspYB29OTI 17vG+QA+D8H8U19hpN3lNkXIqncGeGvImoG+Qks+AWLpu47be8tNMKTB0NnMF8tf5A36 MAX6c6rTGbTuNcU2/LsJtvB9KvZP+1wGc1bXwcIJEtr1jx1SRGxuFPc9gjG51F+vARFP bflA== X-Gm-Message-State: AOJu0YwpnKjAXzvS7VHSdlODhDCummB9O9fzKz0YonuMeOC/MBxxl1X7 JXh+3wMrF/5CRP4TkBHpfDHcFiaLcqIj8IPM2sxmSp8rvE/RQN3nTN3ByX/Nh6D5S2UrIdToE0+ EhWAW X-Gm-Gg: Acq92OHn95qACoKjpsbE9YQE4qgUka2aE3fhwwTZW8wYOAamZDR5rQ00b0KP8+8PxCe uBVO0OU0U4bJX9SQTl//IuYNI2UkPo++U7F1dvIE3APhwI+FECGWUN3uIv0IuDqGFTrMcZxWFNA u0qqoGKpLhZsVDk53h33kg6FkdKqIifN7hHnFgNusx/2ofAUnE4/5fMW3KWkp3RXupnV0u7D2a/ s87yXm4e9buZldM0Lw+aVwEKwd6304W9hSwy1n306tYpBs4GxSDyDSHd2Z1dI9XS26gJiKpvHRn PXGgki68oeLJUsR/7xs45mKDcSVHg8ThFPCfrwRXYBJRg0XOUj1ySHiT7uvsZ9EP4q4/QeuxI75 FCYux/UJjs2lAEc1nHbB2KTfJtpX7fdR9Xq9Aia4S0aLpRK7c91lhuOxooTlrlNRfhTIDJbNaMx KmpB66BaIDXfccKRdF2DA2lMWtfS8iWyqAoZI3Qm4+tDcJx3YIxyXgTMzIZThExD8T84uNkL2f8 FwP1IYpyv2v6Spk4h+kfvXGLS1HWcpu X-Received: by 2002:a05:6000:2204:b0:45e:f381:cd7f with SMTP id ffacd0b85a97d-46235e98d57mr1305097f8f.5.1781636867788; Tue, 16 Jun 2026 12:07:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 60/61] target/arm: Implement SVE floating-point convert (top, predicated, zeroing) Date: Tue, 16 Jun 2026 20:06:37 +0100 Message-ID: <20260616190639.3462006-61-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637327543158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This includes FCVTXNT, BFCVTNT, FCVTNT, FCVTLT. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 7 +++++++ target/arm/tcg/translate-sve.c | 13 +++++++++++++ 2 files changed, 20 insertions(+) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 5c814c7769..673cbaae57 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1941,6 +1941,13 @@ FCVTLT_hs_m 01100100 10 0010 01 101 ... ..... ..= ... @rd_pg_rn_e0 FCVTNT_ds_m 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 FCVTLT_sd_m 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 =20 +FCVTXNT_ds_z 01100100 00 0000 10 101 ... ..... ..... @rd_pg_rn_e0 +FCVTNT_sh_z 01100100 10 0000 00 101 ... ..... ..... @rd_pg_rn_e0 +FCVTNT_ds_z 01100100 11 0000 10 101 ... ..... ..... @rd_pg_rn_e0 +BFCVTNT_z 01100100 10 0000 10 101 ... ..... ..... @rd_pg_rn_e0 +FCVTLT_hs_z 01100100 10 0000 01 101 ... ..... ..... @rd_pg_rn_e0 +FCVTLT_sd_z 01100100 11 0000 11 101 ... ..... ..... @rd_pg_rn_e0 + ### SVE2 floating-point convert to integer FLOGB_m 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz =20 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index a8d21dedca..21ee10ee5c 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -8097,17 +8097,28 @@ static bool trans_RAX1(DisasContext *s, arg_RAX1 *a) =20 TRANS_FEAT(FCVTNT_sh_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) +TRANS_FEAT(FCVTNT_sh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2_fcvtnt_sh, a, 1, FPST_A64) TRANS_FEAT(FCVTNT_ds_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64) +TRANS_FEAT(FCVTNT_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2_fcvtnt_ds, a, 1, FPST_A64) =20 TRANS_FEAT(BFCVTNT_m, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvtnt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) +TRANS_FEAT(BFCVTNT_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_bfcvtnt, a, 1, + s->fpcr_ah ? FPST_AH : FPST_A64) =20 TRANS_FEAT(FCVTLT_hs_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64_F16) +TRANS_FEAT(FCVTLT_hs_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2_fcvtlt_hs, a, 1, FPST_A64_F16) TRANS_FEAT(FCVTLT_sd_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64) +TRANS_FEAT(FCVTLT_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve2_fcvtlt_sd, a, 1, FPST_A64) =20 TRANS_FEAT(FCVTX_ds_m, aa64_sme_or_sve2, do_frint_mode, a, FPROUNDING_ODD, 0, gen_helper_sve_fcvt_ds) @@ -8116,6 +8127,8 @@ TRANS_FEAT(FCVTX_ds_z, aa64_sme2p2_or_sve2p2, do_frin= t_mode, a, =20 TRANS_FEAT(FCVTXNT_ds_m, aa64_sme_or_sve2, do_frint_mode, a, FPROUNDING_ODD, 0, gen_helper_sve2_fcvtnt_ds) +TRANS_FEAT(FCVTXNT_ds_z, aa64_sme2p2_or_sve2p2, do_frint_mode, a, + FPROUNDING_ODD, 1, gen_helper_sve2_fcvtnt_ds) =20 static gen_helper_gvec_3_ptr * const flogb_fns[] =3D { NULL, gen_helper_flogb_h, --=20 2.43.0 From nobody Sun Jul 26 13:29:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1781637468; cv=none; d=zohomail.com; s=zohoarc; b=O0mpj4JYpzkVzRBHZ7LdwO5K6d1G/8A7WPMKgGIJdimOK74NtkARFZ7T8nDzO+buwuuR0LhpMLr6P8zZQFIR2k7GmYcxvne+DK7Pg/lU+2+r782NvsbXzs8A8vpv8JdHDu3fFaHBu8gvuktLO9V+vJx5Zsg2WMORJQFlCgw5IjI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781637468; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=dheMmu+0unel+GTEMjXNAMvglHoJHnIs68/xfZg7lu0=; b=MgaHxM3eNTnCo37TICJ8d5WA+ypWPaC+/JqJ3pNDUY/tIyGb/fv9FIjCyjmb5ltSt6W7byPDWSr5+qzbq44cy5XXkeA/ykCRli8alWxymrgDz2z59/nLNJbrVn4W5A1CnvLsdhvdZibEDc8OYsW7l8BexolsAI+ihATbq59b9rU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781637468338991.8306523887211; Tue, 16 Jun 2026 12:17:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZZDg-0003Zk-Ub; Tue, 16 Jun 2026 15:13:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZZ8b-0004nD-3J for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:55 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wZZ8Y-0001Hn-4G for qemu-devel@nongnu.org; Tue, 16 Jun 2026 15:07:52 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-460662fcb4eso3413300f8f.0 for ; Tue, 16 Jun 2026 12:07:49 -0700 (PDT) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f2d9becsm45078765f8f.34.2026.06.16.12.07.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 12:07:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1781636868; x=1782241668; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dheMmu+0unel+GTEMjXNAMvglHoJHnIs68/xfZg7lu0=; b=DuNtag9Lvff4PIWu4C7Ys0c7cDZDBIwJAkSI3sHIAZtGOEh1ZIvFgmAjXfy1WQuPNq 3pvHlihcACgGbZddTwWvn+vvZnrTlRvUm4GlcWw0DiAY+NKcfsswoKF7dvDZNS+gogjO Pt+Ku8fjhiG05sITuPe2bqGKb/sJFuqEpqx265YpGZImKLh35Ay+ZQPdQGSqIxzMW+87 WI/e+Cc+pQLfPDbGkUpT8fjxEPLHaz2UD9RTZX0NPfx+cWIahsiRc3ceWRtqI4dMbxxr WbhyJPI3Sg0e+3p5whYD/4yPJj8frNJ5HN9TOWm4UE4SLff3cHWEkXDDQZANXbzNXu1O UjjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781636868; x=1782241668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dheMmu+0unel+GTEMjXNAMvglHoJHnIs68/xfZg7lu0=; b=cduzhwjNwKlfoJwxSHh71j6xk+93cNuaK4BITGQ64I+kPHrmnnAk4hRUquNvGvOoec BnA+VQklx8/3xmdIphWismQpF4ujuKSMpsAIVtdfk9rNhwyHm+wMmskbCZjVwDMRxKsO kjHcgE8pNRsRxvRedn8S4z7V1c7gUmq67e+ERpdI2xueaMGkDPpfJvQ9WIr0wNCrTqH0 N1n4bwyo5QioUyE97jvGiX3wHEXrlO3SJHoEREopu0Iay95jcNzJKby5gBBNK0XbBgYj peW110GJ6q6QDGWiPro+DAiHIBiJapR/ILw2SMRHm4ewOMK6O/T6xQA5unHMfJt3f0/8 ULKQ== X-Gm-Message-State: AOJu0YzST7dfTMgfxamD+UTcTIf/N/FfPVoEnClKSEG9/qJVJhjqGZ+8 JMic/9aRJNj9pPysBoU5xWSCIW2TLEVJMyC3wLKnQgMEKltVnrODDb+zjJvTYsEX/hnvEZZm6p8 F08iT X-Gm-Gg: Acq92OFYuynhU/rRiP2CkB7TfeUxknr8GpLZkKrdg3ZgwfqPqhZetKsupXiS4zIe6iA fZ8qc43ZNCf1ga+tlPR3d7NSwe7XWDVTr9MZxe4eEcCdYkG1wk5N2P5f8I1Z4LgjAovhzwEfoMz RGe8ICzvedj1Lq0Lm8VWjTWPoeJHXJ21MEvGvMM2yGJIzCXHD0AlZN/AYOFSxr9XZ+4AOeOFMhC wOIwF8KaR7/yQ1HnHm10lVtpu/XXAqAkv8cDmcqFsYCzezy8i/OfIF0pnQ+qOFNHX7SOJnziKzE ISozCLg2wk6L663Z5s81FTXX1mpFaPxJb1hKF2NYSEulCTzSm/XqQLCljzjszZVGc35zHW+wwEr ggcvJJaAZRSW5PLhj6DUMpprDSv1HocvhUlVhuiFssjGvuoFLafh/MExvM0BoYU6ZuBocYMp6sr Cvk7kcsCZrSbMc3BnbdKMSjdKb9emel6lQngLrAvgOQfWaw5WYFOLNm+w8JGsJZOdZnMGwt++46 kqL10+Ek8lTbmLxuEZ6RIh20EdUtSPW X-Received: by 2002:a05:6000:2913:b0:460:1987:7bb9 with SMTP id ffacd0b85a97d-46238132d53mr1329851f8f.29.1781636868563; Tue, 16 Jun 2026 12:07:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 61/61] target/arm: Implement floating-point log and convert to integer (zeroing) Date: Tue, 16 Jun 2026 20:06:38 +0100 Message-ID: <20260616190639.3462006-62-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616190639.3462006-1-peter.maydell@linaro.org> References: <20260616190639.3462006-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1781637470486158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is FLOGB, FCVTZS, FCVTZU. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 16 +++++++++++++++ target/arm/tcg/translate-sve.c | 37 ++++++++++++++++++++++++++++++++-- 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 673cbaae57..2795c2ec7f 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -1242,6 +1242,21 @@ FCVTZU_sd_m 01100101 11 011 10 1 101 ... ..... .= .... @rd_pg_rn_e0 FCVTZS_dd_m 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_= e0 FCVTZU_dd_m 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_= e0 =20 +FCVTZS_hh_z 01100100 01 011 11 0 110 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_hh_z 01100100 01 011 11 0 111 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_hs_z 01100100 01 011 11 1 100 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_hs_z 01100100 01 011 11 1 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_hd_z 01100100 01 011 11 1 110 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_hd_z 01100100 01 011 11 1 111 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_ss_z 01100100 10 011 11 1 100 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_ss_z 01100100 10 011 11 1 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_sd_z 01100100 11 011 11 1 100 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_sd_z 01100100 11 011 11 1 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_ds_z 01100100 11 011 11 0 100 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_ds_z 01100100 11 011 11 0 101 ... ..... ..... @rd_pg_rn_= e0 +FCVTZS_dd_z 01100100 11 011 11 1 110 ... ..... ..... @rd_pg_rn_= e0 +FCVTZU_dd_z 01100100 11 011 11 1 111 ... ..... ..... @rd_pg_rn_= e0 + # SVE floating-point round to integral value FRINTN_m 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn FRINTP_m 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn @@ -1950,6 +1965,7 @@ FCVTLT_sd_z 01100100 11 0000 11 101 ... ..... ...= .. @rd_pg_rn_e0 =20 ### SVE2 floating-point convert to integer FLOGB_m 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz +FLOGB_z 01100100 00 011 1101 esz:2 pg:3 rn:5 rd:5 &rpr_esz =20 ### SVE2 floating-point multiply-add long (vectors) FMLALB_zzzw 01100100 10 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex e= sz=3D2 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 21ee10ee5c..9a72e03513 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4654,6 +4654,37 @@ TRANS_FEAT(FCVTZS_dd_m, aa64_sme_or_sve, gen_gvec_fp= st_arg_zpz, TRANS_FEAT(FCVTZU_dd_m, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_dd, a, 0, FPST_A64) =20 +TRANS_FEAT(FCVTZS_hh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzs_hh, a, 1, FPST_A64_F16) +TRANS_FEAT(FCVTZU_hh_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzu_hh, a, 1, FPST_A64_F16) +TRANS_FEAT(FCVTZS_hs_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzs_hs, a, 1, FPST_A64_F16) +TRANS_FEAT(FCVTZU_hs_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzu_hs, a, 1, FPST_A64_F16) +TRANS_FEAT(FCVTZS_hd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzs_hd, a, 1, FPST_A64_F16) +TRANS_FEAT(FCVTZU_hd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzu_hd, a, 1, FPST_A64_F16) + +TRANS_FEAT(FCVTZS_ss_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzs_ss, a, 1, FPST_A64) +TRANS_FEAT(FCVTZU_ss_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzu_ss, a, 1, FPST_A64) +TRANS_FEAT(FCVTZS_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzs_sd, a, 1, FPST_A64) +TRANS_FEAT(FCVTZU_sd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzu_sd, a, 1, FPST_A64) +TRANS_FEAT(FCVTZS_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzs_ds, a, 1, FPST_A64) +TRANS_FEAT(FCVTZU_ds_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzu_ds, a, 1, FPST_A64) + +TRANS_FEAT(FCVTZS_dd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzs_dd, a, 1, FPST_A64) +TRANS_FEAT(FCVTZU_dd_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + gen_helper_sve_fcvtzu_dd, a, 1, FPST_A64) + static gen_helper_gvec_3_ptr * const frint_fns[] =3D { NULL, gen_helper_sve_frint_h, @@ -8134,8 +8165,10 @@ static gen_helper_gvec_3_ptr * const flogb_fns[] =3D= { NULL, gen_helper_flogb_h, gen_helper_flogb_s, gen_helper_flogb_d }; -TRANS_FEAT(FLOGB_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->= esz], - a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) +TRANS_FEAT(FLOGB_m, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, + flogb_fns[a->esz], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : F= PST_A64) +TRANS_FEAT(FLOGB_z, aa64_sme2p2_or_sve2p2, gen_gvec_fpst_arg_zpz, + flogb_fns[a->esz], a, 1, a->esz =3D=3D MO_16 ? FPST_A64_F16 : F= PST_A64) =20 static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool= sel) { --=20 2.43.0