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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616409; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=F71HBHl1W+M/uo5lCzlKVd+GPVdXLXIc1bRDPajNYkk=; b=Ram9aaAzXrcOpcYHsuxcD1E0uHWelHxXAnQArkifzD/4AVODd2MYQYkpHQDHu0gyZD7DZF xcUk3N9G9ZSVxlXsNsomnahPs5TvZbHiic+AgDjm86GcLcppgrGiGO3Wu1ALly1q0o5jci xZq0nIb9rQAapveW+wL6cMmjc3d/xXQ= X-MC-Unique: URZxmMdFN6yUu-9_z5Ru1g-1 X-Mimecast-MFC-AGG-ID: URZxmMdFN6yUu-9_z5Ru1g_1781616404 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 01/17] scripts: introduce scripts/update-aarch64-cpu-sysregs-header.py Date: Tue, 16 Jun 2026 15:16:48 +0200 Message-ID: <20260616132625.1732031-2-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1781616441422158500 Content-Type: text/plain; charset="utf-8" Introduce a script that takes as input the Registers.json file delivered in the AARCHMRS Features Model downloadable from the Arm Developer A-Profile Architecture Exploration Tools page: https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc under the form of DEF(, , , , , ). We only care about IDregs with opcodes satisfying: op0 =3D 3, op1 =3D {0,1,3}, crn =3D 0, crm within [0, 7], op2 within [0, 7] Signed-off-by: Eric Auger [CH: note correct op1 range, don't skip CCSIDR] Signed-off-by: Cornelia Huck Message-ID: <20251208163751.611186-2-eric.auger@redhat.com> --- scripts/update-aarch64-cpu-sysregs-header.py | 134 +++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100755 scripts/update-aarch64-cpu-sysregs-header.py diff --git a/scripts/update-aarch64-cpu-sysregs-header.py b/scripts/update-= aarch64-cpu-sysregs-header.py new file mode 100755 index 0000000000..8c337147dd --- /dev/null +++ b/scripts/update-aarch64-cpu-sysregs-header.py @@ -0,0 +1,134 @@ +#!/usr/bin/env python3 + +# This script takes as input the Registers.json file delivered in +# the AARCHMRS Features Model downloadable from the Arm Developer +# A-Profile Architecture Exploration Tools page: +# https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloa= ds +# and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc +# under the form of DEF(, , , , , ) +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os +import sys + +# Some regs have op code values like 000x, 001x. Anyway we don't need +# them. Besides some regs are undesired in the generated file such as +# VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we +# are interested in and are tricky to decode as their system accessor +# refer to MPIDR_EL1/MIDR_EL1 respectively + +skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ + 'VMPIDR_EL2', 'VPIDR_EL2'] + +# returns the int value of a given @opcode for a reg @encoding +def get_opcode(encoding, opcode): + fvalue =3D encoding.get(opcode) + if fvalue: + value =3D fvalue.get('value') + if isinstance(value, str): + value =3D value.strip("'") + value =3D int(value, 2) + return value + return -1 + +def extract_idregs_from_registers_json(filename): + """ + Load a Registers.json file and extract all ID registers, decode their + opcode and dump the information in target/arm/cpu-sysregs.h.inc + + Args: + filename (str): The path to the Registers.json + returns: + idregs: list of ID regs and their encoding + """ + if not os.path.exists(filename): + print(f"Error: {filename} could not be found!") + return {} + + try: + with open(filename, 'r') as f: + register_data =3D json.load(f) + + except json.JSONDecodeError: + print(f"Could not decode json from '{filename}'!") + return {} + except Exception as e: + print(f"Unexpected error while reading {filename}: {e}") + return {} + + registers =3D [r for r in register_data if isinstance(r, dict) and \ + r.get('_type') =3D=3D 'Register'] + + idregs =3D {} + + for register in registers: + reg_name =3D register.get('name') + + is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) + + if reg_name and not is_skipped: + accessors =3D register.get('accessors', []) + + for accessor in accessors: + type =3D accessor.get('_type') + if type in ['Accessors.SystemAccessor']: + encoding_list =3D accessor.get('encoding') + + if isinstance(encoding_list, list) and encoding_list a= nd \ + isinstance(encoding_list[0], dict): + encoding_wrapper =3D encoding_list[0] + encoding_source =3D encoding_wrapper.get('encoding= s', \ + encoding_wr= apper) + + if isinstance(encoding_source, dict): + op0 =3D get_opcode(encoding_source, 'op0') + op1 =3D get_opcode(encoding_source, 'op1') + op2 =3D get_opcode(encoding_source, 'op2') + crn =3D get_opcode(encoding_source, 'CRn') + crm =3D get_opcode(encoding_source, 'CRm') + encoding_str=3Df"{op0} {op1} {crn} {crm} {= op2}" + + # ID regs are assumed within this scope + if op0 =3D=3D 3 and (op1 =3D=3D 0 or op1 =3D=3D 1 or op1 = =3D=3D 3) and \ + crn =3D=3D 0 and (crm >=3D 0 and crm <=3D 7) and (op2 >= =3D 0 and op2 <=3D 7): + idregs[reg_name] =3D encoding_str + + return idregs + +if __name__ =3D=3D "__main__": + # Single arg expected: the path to the Registers.json file + if len(sys.argv) < 2: + print("Usage: python scripts/update-aarch64-cpu-sysregs-header.py " + "") + sys.exit(1) + else: + json_file_path =3D sys.argv[1] + + extracted_registers =3D extract_idregs_from_registers_json(json_file_p= ath) + + if extracted_registers: + output_list =3D extracted_registers.items() + + # Sort by register name + sorted_output =3D sorted(output_list, key=3Dlambda item: item[0]) + + # format lines as DEF(, , , , , ) + final_output =3D "" + for reg_name, encoding in sorted_output: + reformatted_encoding =3D encoding.replace(" ", ", ") + final_output +=3D f"DEF({reg_name}, {reformatted_encoding})\n" + + with open("target/arm/cpu-sysregs.h.inc", 'w') as f: + f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") + f.write("/* This file is autogenerated by ") + f.write("scripts/update-aarch64-cpu-sysregs-header.py */\n") + f.write("/* DEF(, , , , , ) */\= n\n") + f.write(final_output) + print("updated target/arm/cpu-sysregs.h.inc") --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616418; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bTs/ktWx3rW7HFZBOxDG+4OtZn4ymwK9rqHIbClYMpM=; b=FIvBg5dqIyWuQN6asXoOCqMzgBmjBdZe0d4oJO8tPAderCxlZ3yqeYu5Lq8QYE5FomcxOG FkfQo7ebKMmSxY4fb/XKxWceW1HmszosBMEBrmcd89EhUrjAkeDAPi21aWC60g1i109fC0 DgRAuQLuCuIN3v4hIx6W3w4p03m2bMc= X-MC-Unique: z8FaUCv8NJK8EZaBdXYE4w-1 X-Mimecast-MFC-AGG-ID: z8FaUCv8NJK8EZaBdXYE4w_1781616410 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 02/17] target/arm/cpu-sysregs.h.inc: Sort by name alphabetical order Date: Tue, 16 Jun 2026 15:16:49 +0200 Message-ID: <20260616132625.1732031-3-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Sort by register name alphabetical order. This will allow to easily diff with the future content, automatically generated. No functional change intended. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Shameer Kolothum --- v5 -> v6: - v5 version conflicted because ID_AA64FPFR0_EL1 has been added v4 -> v5: - remove spurious CCSIDR definition --- target/arm/cpu-sysregs.h.inc | 44 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 6e8b335b8f..ec5a12b0f4 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) -DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) -DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) -DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) -DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) -DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) -DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(CLIDR_EL1, 3, 1, 0, 0, 1) +DEF(CTR_EL0, 3, 3, 0, 0, 1) +DEF(DCZID_EL0, 3, 3, 0, 0, 7) DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) +DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) +DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) @@ -17,29 +16,30 @@ DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) -DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) -DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) -DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) +DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) +DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) +DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3) -DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) -DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) -DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) -DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7) +DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) DEF(ID_ISAR0_EL1, 3, 0, 0, 2, 0) DEF(ID_ISAR1_EL1, 3, 0, 0, 2, 1) DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2) DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3) DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4) DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5) -DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7) +DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) +DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) +DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) +DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7) +DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) +DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) +DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) +DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) +DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) -DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) -DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) -DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) -DEF(CLIDR_EL1, 3, 1, 0, 0, 1) -DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) -DEF(CTR_EL0, 3, 3, 0, 0, 1) -DEF(DCZID_EL0, 3, 3, 0, 0, 7) --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616426; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9Q1MRRO+oFa8DFbRumsxnZz4i4gGeVWxNqhJGe6XFoQ=; b=AQUHg25CaeJASjYPWufnum2dFC9n3WAObOsOaZemUbZFIU2nq/jmg1Iu3PVye/LFl9zHvL JN9SBd0prCOFqEj90sIMbX5LH7RLib12QeNxI5PmQJ5G026O1MzAkROkocnRuwe0SlVC/j JzY2Z0P7p+VRk84hh6W9ABN+rLAl3j4= X-MC-Unique: qba89ywpOZ6xb42AmoUREg-1 X-Mimecast-MFC-AGG-ID: qba89ywpOZ6xb42AmoUREg_1781616417 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 03/17] target/arm/cpu-sysregs.h.inc: Update with automatic generation Date: Tue, 16 Jun 2026 15:16:50 +0200 Message-ID: <20260616132625.1732031-4-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1781616443576158500 Content-Type: text/plain; charset="utf-8" Generated definitions with scripts/update-aarch64-cpu-sysregs-header.py based on "AARCHMRS containing the JSON files for Arm A-profile architecture (2026-03)" Registers.json file. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Shameer Kolothum --- target/arm/cpu-sysregs.h.inc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index ec5a12b0f4..2188cd7be0 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -1,11 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This file is autogenerated by scripts/update-aarch64-cpu-sysregs-header= .py */ +/* DEF(, , , , , ) */ + +DEF(AIDR_EL1, 3, 1, 0, 0, 7) +DEF(CCSIDR2_EL1, 3, 1, 0, 0, 2) +DEF(CCSIDR_EL1, 3, 1, 0, 0, 0) DEF(CLIDR_EL1, 3, 1, 0, 0, 1) DEF(CTR_EL0, 3, 3, 0, 0, 1) DEF(DCZID_EL0, 3, 3, 0, 0, 7) +DEF(GMID_EL1, 3, 1, 0, 0, 4) DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2) DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) @@ -40,6 +49,10 @@ DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) +DEF(MIDR_EL1, 3, 0, 0, 0, 0) +DEF(MPIDR_EL1, 3, 0, 0, 0, 5) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) +DEF(REVIDR_EL1, 3, 0, 0, 0, 6) +DEF(SMIDR_EL1, 3, 1, 0, 0, 6) --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616428; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DhixsKWT24zFPVpdhrpfzjTHfnfa7NPGnY2SIEHR/6Y=; b=UE7EjAw9uTA5CBU3SOnDt7sJXo11nm74iFVNQy4nk0lQxiiabwibMMwVGI8bREiXpG8H6A Ej91D2AEAz99JFsziha3g/bfYcDxeS1Puqmtk+ODjcnp3+Zl+/jhLbJ9Z50z1MB86adSvq aGwcEPIFbp2ShNs2P8nFzYYLQ8rrhM8= X-MC-Unique: XlnVw-NVPoaBs9B9tpwVRA-1 X-Mimecast-MFC-AGG-ID: XlnVw-NVPoaBs9B9tpwVRA_1781616424 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 04/17] arm/cpu: Add infra to handle generated ID register definitions Date: Tue, 16 Jun 2026 15:16:51 +0200 Message-ID: <20260616132625.1732031-5-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Introduce an infrastructure to store the definition of all ID regs: This include their name, index and array of named fields. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Co-authored-by: Khushit Shah --- v5 -> v6: - add ArmIdRegArchVal --- target/arm/cpu-idregs.h | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 target/arm/cpu-idregs.h diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h new file mode 100644 index 0000000000..245f1c8103 --- /dev/null +++ b/target/arm/cpu-idregs.h @@ -0,0 +1,41 @@ +/* + * handle ID registers and their fields + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef TARGET_ARM_CPU_IDREGS_H +#define TARGET_ARM_CPU_IDREGS_H + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "cpu-sysregs.h" + +typedef struct ArmIdRegArchVal { + uint64_t value; + const char *name; +} ArmIdRegArchVal; + +typedef struct ARM64SysRegField { + const char *name; /* name of the field, for instance CTR_EL0_IDC */ + ARMIDRegisterIdx index; /* parent register, e.g. CTR_EL0_IDX */ + int shift; /* lsb of the field in the register */ + int length; /* highest bit number */ + ArmIdRegArchVal *arch_vals; + uint32_t arch_vals_count; +} ARM64SysRegField; + +typedef struct ARM64SysReg { + const char *name; /* name of the sysreg, for instance CTR_EL0 */ + ARMIDRegisterIdx index; /* register index, e.g. CTR_EL0_IDX */ + struct ARM64SysRegField *fields; + uint32_t fields_count; + uint64_t writable_mask; +} ARM64SysReg; + +/* + * List of exposed ID regs (automatically populated from AARCHMRS Register= s.json) + */ +extern ARM64SysReg arm64_id_regs[NUM_ID_IDX]; + +#endif --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1781616489; cv=none; d=zohomail.com; s=zohoarc; b=SaIMYUDMmEMkwoAZVxa9GNbKWWV6O+0gKhfRayMgC8fR1qln871Hy3weYl2GZOv8BtXYB3S1gboih0VxYjpZtFNIijlGYiGDLqMTgnIJSQSjdojdLCSlE5sPNgkkGxvnUgJEO5RJNN4AgnYRuvY/t4uPwKGGPsODpcSc7XhBfa4= ARC-Message-Signature: i=1; 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charset="utf-8" We plan to reuse get_opcode() and extract_idregs_from_registers_json() functions in another script. So let's move them into a module No functional change intended. Signed-off-by: Eric Auger --- scripts/aarch64_sysreg_helpers.py | 109 +++++++++++++++++++ scripts/update-aarch64-cpu-sysregs-header.py | 85 +-------------- 2 files changed, 110 insertions(+), 84 deletions(-) create mode 100644 scripts/aarch64_sysreg_helpers.py diff --git a/scripts/aarch64_sysreg_helpers.py b/scripts/aarch64_sysreg_hel= pers.py new file mode 100644 index 0000000000..dd5ec4bafa --- /dev/null +++ b/scripts/aarch64_sysreg_helpers.py @@ -0,0 +1,109 @@ +#!/usr/bin/env python3 + +# Helpers used in aarch64 sysreg definition generation +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os + +# Some regs have op code values like 000x, 001x. Anyway we don't need +# them. Besides some regs are undesired in the generated file such as +# VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we +# are interested in and are tricky to decode as their system accessor +# refer to MPIDR_EL1/MIDR_EL1 respectively + +skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ + 'VMPIDR_EL2', 'VPIDR_EL2'] + +# returns the int value of a given @opcode for a reg @encoding +def get_opcode(encoding, opcode): + fvalue =3D encoding.get(opcode) + if fvalue: + value =3D fvalue.get('value') + if isinstance(value, str): + value =3D value.strip("'") + value =3D int(value, 2) + return value + return -1 + +def extract_idregs_from_registers_json(filename): + """ + Load a Registers.json file and extract all ID registers, decode their + opcode and dump the information in target/arm/cpu-sysregs.h.inc + + Args: + filename (str): The path to the Registers.json + returns: + idregs: list of ID regs and their encoding + """ + if not os.path.exists(filename): + print(f"Error: {filename} could not be found!") + return {} + + try: + with open(filename, 'r') as f: + register_data =3D json.load(f) + + except json.JSONDecodeError: + print(f"Could not decode json from '{filename}'!") + return {} + except Exception as e: + print(f"Unexpected error while reading {filename}: {e}") + return {} + + registers =3D [r for r in register_data if isinstance(r, dict) and \ + r.get('_type') =3D=3D 'Register'] + + idregs =3D {} + + # Some regs have op code values like 000x, 001x. Anyway we don't need + # them. Besides some regs are undesired in the generated file such as + # VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we + # are interested in and are tricky to decode as their system accessor + # refer to MPIDR_EL1/MIDR_EL1 respectively + + skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ + 'VMPIDR_EL2', 'VPIDR_EL2'] + + for register in registers: + reg_name =3D register.get('name') + + is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) + + if reg_name and not is_skipped: + accessors =3D register.get('accessors', []) + + for accessor in accessors: + type =3D accessor.get('_type') + if type in ['Accessors.SystemAccessor']: + encoding_list =3D accessor.get('encoding') + + if isinstance(encoding_list, list) and encoding_list a= nd \ + isinstance(encoding_list[0], dict): + encoding_wrapper =3D encoding_list[0] + encoding_source =3D encoding_wrapper.get('encoding= s', \ + encoding_wr= apper) + + if isinstance(encoding_source, dict): + op0 =3D get_opcode(encoding_source, 'op0') + op1 =3D get_opcode(encoding_source, 'op1') + op2 =3D get_opcode(encoding_source, 'op2') + crn =3D get_opcode(encoding_source, 'CRn') + crm =3D get_opcode(encoding_source, 'CRm') + encoding_str=3Df"{op0} {op1} {crn} {crm} {= op2}" + + # ID regs are assumed within this scope + if op0 =3D=3D 3 and (op1 =3D=3D 0 or op1 =3D=3D 1 or op1 = =3D=3D 3) and \ + crn =3D=3D 0 and (crm >=3D 0 and crm <=3D 7) and (op2 >= =3D 0 and op2 <=3D 7): + idregs[reg_name] =3D encoding_str + + return idregs + + + diff --git a/scripts/update-aarch64-cpu-sysregs-header.py b/scripts/update-= aarch64-cpu-sysregs-header.py index 8c337147dd..43107264e9 100755 --- a/scripts/update-aarch64-cpu-sysregs-header.py +++ b/scripts/update-aarch64-cpu-sysregs-header.py @@ -17,90 +17,7 @@ import json import os import sys - -# Some regs have op code values like 000x, 001x. Anyway we don't need -# them. Besides some regs are undesired in the generated file such as -# VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we -# are interested in and are tricky to decode as their system accessor -# refer to MPIDR_EL1/MIDR_EL1 respectively - -skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ - 'VMPIDR_EL2', 'VPIDR_EL2'] - -# returns the int value of a given @opcode for a reg @encoding -def get_opcode(encoding, opcode): - fvalue =3D encoding.get(opcode) - if fvalue: - value =3D fvalue.get('value') - if isinstance(value, str): - value =3D value.strip("'") - value =3D int(value, 2) - return value - return -1 - -def extract_idregs_from_registers_json(filename): - """ - Load a Registers.json file and extract all ID registers, decode their - opcode and dump the information in target/arm/cpu-sysregs.h.inc - - Args: - filename (str): The path to the Registers.json - returns: - idregs: list of ID regs and their encoding - """ - if not os.path.exists(filename): - print(f"Error: {filename} could not be found!") - return {} - - try: - with open(filename, 'r') as f: - register_data =3D json.load(f) - - except json.JSONDecodeError: - print(f"Could not decode json from '{filename}'!") - return {} - except Exception as e: - print(f"Unexpected error while reading {filename}: {e}") - return {} - - registers =3D [r for r in register_data if isinstance(r, dict) and \ - r.get('_type') =3D=3D 'Register'] - - idregs =3D {} - - for register in registers: - reg_name =3D register.get('name') - - is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) - - if reg_name and not is_skipped: - accessors =3D register.get('accessors', []) - - for accessor in accessors: - type =3D accessor.get('_type') - if type in ['Accessors.SystemAccessor']: - encoding_list =3D accessor.get('encoding') - - if isinstance(encoding_list, list) and encoding_list a= nd \ - isinstance(encoding_list[0], dict): - encoding_wrapper =3D encoding_list[0] - encoding_source =3D encoding_wrapper.get('encoding= s', \ - encoding_wr= apper) - - if isinstance(encoding_source, dict): - op0 =3D get_opcode(encoding_source, 'op0') - op1 =3D get_opcode(encoding_source, 'op1') - op2 =3D get_opcode(encoding_source, 'op2') - crn =3D get_opcode(encoding_source, 'CRn') - crm =3D get_opcode(encoding_source, 'CRm') - encoding_str=3Df"{op0} {op1} {crn} {crm} {= op2}" - - # ID regs are assumed within this scope - if op0 =3D=3D 3 and (op1 =3D=3D 0 or op1 =3D=3D 1 or op1 = =3D=3D 3) and \ - crn =3D=3D 0 and (crm >=3D 0 and crm <=3D 7) and (op2 >= =3D 0 and op2 <=3D 7): - idregs[reg_name] =3D encoding_str - - return idregs +from aarch64_sysreg_helpers import extract_idregs_from_registers_json =20 if __name__ =3D=3D "__main__": # Single arg expected: the path to the Registers.json file --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616442; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0MgtnSaVh9ax7ryBzZLi/K7BKaomljz1Cy0WeKLK4ak=; b=JAj9A5keCL9l8cHRniKj9HRfb0jfPh2c9+kDi/YB2CTkf5tcOMNcShnp7Eu0Q3P7+VbkHD 58SEbM8Mhzfx0E+pssXM6DAm7E1gL8FEKOGzqsftePbZeb++9EsKTHwMIi5SyBt18tSXPP 0EOlnMsqiOEGw2Scg7E12Y7ohlvXk04= X-MC-Unique: Gp9KaIkuO3Ox10zTUViyNg-1 X-Mimecast-MFC-AGG-ID: Gp9KaIkuO3Ox10zTUViyNg_1781616437 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 06/17] scripts: Introduce scripts/update-aarch64-cpu-sysreg-properties.py Date: Tue, 16 Jun 2026 15:16:53 +0200 Message-ID: <20260616132625.1732031-7-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1781616455910158500 Content-Type: text/plain; charset="utf-8" Introduce a script that takes as input the Registers.json file delivered in the AARCHMRS Features Model downloadable from the Arm Developer A-Profile Architecture Exploration Tools page: https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads and automates the generation of system register properties definitions. generates target/arm/cpu-idregs.h.inc containing definitions for feature ID registers. We only care about IDregs with opcodes satisfying: op0 =3D 3, op1 =3D {0,1,3}, crn =3D 0, crm within [0, 7], op2 within [0, 7] Signed-off-by: Eric Auger --- v5 -> v6 - add ident --- .../update-aarch64-cpu-sysreg-properties.py | 166 ++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 scripts/update-aarch64-cpu-sysreg-properties.py diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/upda= te-aarch64-cpu-sysreg-properties.py new file mode 100644 index 0000000000..6f5edb88d2 --- /dev/null +++ b/scripts/update-aarch64-cpu-sysreg-properties.py @@ -0,0 +1,166 @@ +#!/usr/bin/env python3 + +# This script takes as input the Registers.json file delivered in +# the AARCHMRS Features Model downloadable from the Arm Developer +# A-Profile Architecture Exploration Tools page: +# https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloa= ds +# and outputs target/arm/cpu-idregs.h.inc content. +# ID regs are defined using this pattern: +# +# IDREG_START(REG) +# IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) +# ... +# IDREG_END(REG) +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os +import sys +from aarch64_sysreg_helpers import extract_idregs_from_registers_json + +def collect_fields(item, bit_offset=3D0): + """ + Recursively finds all field-like objects, handling Fields.Array, + Fields.ArrayField, and ConditionalField structures. + Applies bit_offset from containers to child fields. + """ + fields =3D [] + if not isinstance(item, dict): + return fields + + _type =3D item.get('_type', '') + + # Array types (for example CLIDR_EL1 Ctype, Ttype) + if _type =3D=3D 'Fields.Array': + name_template =3D item.get('name') or item.get('label', '') + index_info =3D item.get('indexes', [{}])[0] + start_idx =3D index_info.get('start', 0) + count =3D index_info.get('width', 0) + + full_range =3D item.get('rangeset', [{}])[0] + bit_start =3D full_range.get('start', 0) + bit_offset + elem_width =3D full_range.get('width', 0) // count if count else 0 + + for i in range(count): + idx =3D start_idx + i + # Correctly handle indexed names like Ctype1, Ctype2 + field_name =3D name_template.replace('', str(idx)) + fields.append({ + 'name': field_name, + 'rangeset': [{ + 'start': bit_start + (i * elem_width), + 'width': elem_width + }], + '_type': 'Fields.Field' + }) + return fields + + # ConditionalFields + elif _type =3D=3D 'Fields.ConditionalField': + inner_offset =3D bit_offset + if item.get('rangeset'): + # Parent container defines the absolute start bit + inner_offset =3D item['rangeset'][0].get('start', bit_offset) + + for entry in item.get('fields', []): + inner =3D entry.get('field') + if inner: + fields.extend(collect_fields(inner, inner_offset)) + return fields + + # Normal Field Types + leaf_types =3D ['Fields.Field', 'Fields.ConstantField', + 'Fields.EnumeratedField', 'Fields.Bitfield'] + if _type in leaf_types: + field_copy =3D item.copy() + if field_copy.get('rangeset'): + new_ranges =3D [] + for r in field_copy['rangeset']: + nr =3D r.copy() + # Apply the cumulative offset to the field's start bit + nr['start'] =3D r.get('start', 0) + bit_offset + new_ranges.append(nr) + field_copy['rangeset'] =3D new_ranges + fields.append(field_copy) + return fields + + # Traverse the hierarchy for other cases + for key in ['fields', 'values', 'fieldsets']: + for nested in item.get(key, []): + fields.extend(collect_fields(nested, bit_offset)) + + return fields + + +def generate_sysreg_properties_from_registers_json(id_reg_names, raw_json_= path): + with open(raw_json_path, 'r') as f: + register_data =3D json.load(f) + + regs =3D {r.get('name'): r for r in register_data if r.get('_type') = =3D=3D 'Register'} + + final_output =3D "" + + for reg_name in id_reg_names: + register =3D regs.get(reg_name) + if not register: + continue + + final_output +=3D f"IDREG_START({reg_name})\n" + + unique_fields =3D {} + for fieldset in register.get('fieldsets', []): + candidates =3D collect_fields(fieldset) + for val in candidates: + name =3D (val.get('name') or val.get('label', '')).strip() + if not name or "RESERVED" in name.upper(): + continue + for r in val.get('rangeset', []): + lsb =3D int(r.get('start')) + width =3D r.get('width') + msb =3D lsb + int(width) - 1 + + # Only keep the fields with the highest MSB + # needed fir CCSIDR_EL1 + if name not in unique_fields or msb > unique_fields[na= me]['msb']: + unique_fields[name] =3D {'lsb': lsb, 'msb': msb, '= width': width} + + # Sort decreasing lsbs + sorted_fields =3D sorted(unique_fields.items(), + key=3Dlambda x: x[1]['lsb'], reverse=3DTrue) + + for name, bits in sorted_fields: + line =3D (f" IDREG_FIELD({reg_name}, " + f"{name}, {bits['lsb']}, {bits['width']})\n") + final_output +=3D line + final_output +=3D f"IDREG_END({reg_name})\n" + final_output +=3D "\n" + + os.makedirs("target/arm", exist_ok=3DTrue) + with open("target/arm/cpu-idregs.h.inc", 'w') as f: + f.write("/* AUTOMATICALLY GENERATED, DO NOT MODIFY */\n\n") + f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") + f.write("/* IDREG_START(REG) */\n") + f.write("/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */\n") + f.write("/* ... */\n") + f.write("/* IDREG_END(REG) */\n\n") + f.write(final_output) + +if __name__ =3D=3D "__main__": + if len(sys.argv) < 2: + print("Usage: python scripts/update-aarch64-cpu-sysreg-properties.= py " + "") + else: + json_path =3D sys.argv[1] + + id_regs_dict =3D extract_idregs_from_registers_json(json_path) + sorted_names =3D sorted(id_regs_dict.keys()) + + if sorted_names: + generate_sysreg_properties_from_registers_json(sorted_names, j= son_path) + print("Generated target/arm/cpu-idregs.h.inc") --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616450; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=54KmJfhQtok5YdgNrGtGT1SUofwdFbir6IqaWbabYsc=; b=OahQaMI7jgcXzBSAhhQiAyRNHUXzi5kh6OV1ZOUcDXmneu4cjWLIPNnE7gifiRTRUjNabF Orc28ikkGoaIBT9/1RgGd6yycE1/1B/yD29wXLgIstrokiusx6APx6sOR58ON2MAVkrkWN mUk2FyRJ0PIzkLmBsz0/uN7sQ85N0vE= X-MC-Unique: HcljlZewNW-STEx59G0HHQ-1 X-Mimecast-MFC-AGG-ID: HcljlZewNW-STEx59G0HHQ_1781616444 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 07/17] target/arm/cpu-idregs.h.inc: generate with script Date: Tue, 16 Jun 2026 15:16:54 +0200 Message-ID: <20260616132625.1732031-8-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1781616461590158500 Content-Type: text/plain; charset="utf-8" Generate ID reg definitions with the scripts/update-aarch64-cpu-sysreg-prop= erties.py based on AARCHMRS_OPENSOURCE_A_profile_FAT-2026-03 Registers.json Each register and fields are described with this pattern: IDREG_START(REG) IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) ... IDREG_END(REG) Signed-off-by: Eric Auger Suggested-by: Khushit Shah Suggested-by: Shaju Abraham --- target/arm/cpu-idregs.h.inc | 617 ++++++++++++++++++++++++++++++++++++ 1 file changed, 617 insertions(+) create mode 100644 target/arm/cpu-idregs.h.inc diff --git a/target/arm/cpu-idregs.h.inc b/target/arm/cpu-idregs.h.inc new file mode 100644 index 0000000000..a10d750123 --- /dev/null +++ b/target/arm/cpu-idregs.h.inc @@ -0,0 +1,617 @@ +/* AUTOMATICALLY GENERATED, DO NOT MODIFY */ + +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* IDREG_START(REG) */ +/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */ +/* ... */ +/* IDREG_END(REG) */ + +IDREG_START(AIDR_EL1) +IDREG_END(AIDR_EL1) + +IDREG_START(CCSIDR2_EL1) + IDREG_FIELD(CCSIDR2_EL1, NumSets, 0, 24) +IDREG_END(CCSIDR2_EL1) + +IDREG_START(CCSIDR_EL1) + IDREG_FIELD(CCSIDR_EL1, NumSets, 32, 24) + IDREG_FIELD(CCSIDR_EL1, Associativity, 3, 21) + IDREG_FIELD(CCSIDR_EL1, LineSize, 0, 3) +IDREG_END(CCSIDR_EL1) + +IDREG_START(CLIDR_EL1) + IDREG_FIELD(CLIDR_EL1, Ttype7, 45, 2) + IDREG_FIELD(CLIDR_EL1, Ttype6, 43, 2) + IDREG_FIELD(CLIDR_EL1, Ttype5, 41, 2) + IDREG_FIELD(CLIDR_EL1, Ttype4, 39, 2) + IDREG_FIELD(CLIDR_EL1, Ttype3, 37, 2) + IDREG_FIELD(CLIDR_EL1, Ttype2, 35, 2) + IDREG_FIELD(CLIDR_EL1, Ttype1, 33, 2) + IDREG_FIELD(CLIDR_EL1, ICB, 30, 3) + IDREG_FIELD(CLIDR_EL1, LoUU, 27, 3) + IDREG_FIELD(CLIDR_EL1, LoC, 24, 3) + IDREG_FIELD(CLIDR_EL1, LoUIS, 21, 3) + IDREG_FIELD(CLIDR_EL1, Ctype7, 18, 3) + IDREG_FIELD(CLIDR_EL1, Ctype6, 15, 3) + IDREG_FIELD(CLIDR_EL1, Ctype5, 12, 3) + IDREG_FIELD(CLIDR_EL1, Ctype4, 9, 3) + IDREG_FIELD(CLIDR_EL1, Ctype3, 6, 3) + IDREG_FIELD(CLIDR_EL1, Ctype2, 3, 3) + IDREG_FIELD(CLIDR_EL1, Ctype1, 0, 3) +IDREG_END(CLIDR_EL1) + +IDREG_START(CTR_EL0) + IDREG_FIELD(CTR_EL0, TminLine, 32, 6) + IDREG_FIELD(CTR_EL0, DIC, 29, 1) + IDREG_FIELD(CTR_EL0, IDC, 28, 1) + IDREG_FIELD(CTR_EL0, CWG, 24, 4) + IDREG_FIELD(CTR_EL0, ERG, 20, 4) + IDREG_FIELD(CTR_EL0, DminLine, 16, 4) + IDREG_FIELD(CTR_EL0, L1Ip, 14, 2) + IDREG_FIELD(CTR_EL0, IminLine, 0, 4) +IDREG_END(CTR_EL0) + +IDREG_START(DCZID_EL0) + IDREG_FIELD(DCZID_EL0, TBS, 5, 4) + IDREG_FIELD(DCZID_EL0, DZP, 4, 1) + IDREG_FIELD(DCZID_EL0, BS, 0, 4) +IDREG_END(DCZID_EL0) + +IDREG_START(GMID_EL1) + IDREG_FIELD(GMID_EL1, BS, 0, 4) +IDREG_END(GMID_EL1) + +IDREG_START(ID_AA64AFR0_EL1) +IDREG_END(ID_AA64AFR0_EL1) + +IDREG_START(ID_AA64AFR1_EL1) +IDREG_END(ID_AA64AFR1_EL1) + +IDREG_START(ID_AA64DFR0_EL1) + IDREG_FIELD(ID_AA64DFR0_EL1, HPMN0, 60, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, ExtTrcBuff, 56, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, BRBE, 52, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, MTPMU, 48, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceBuffer, 44, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceFilt, 40, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, DoubleLock, 36, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMSVer, 32, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, WRPs, 20, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMSS, 16, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, BRPs, 12, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMUVer, 8, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceVer, 4, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, DebugVer, 0, 4) +IDREG_END(ID_AA64DFR0_EL1) + +IDREG_START(ID_AA64DFR1_EL1) + IDREG_FIELD(ID_AA64DFR1_EL1, ABL_CMPs, 56, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, DPFZS, 52, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, EBEP, 48, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, ITE, 44, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, ABLE, 40, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, PMICNTR, 36, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, SPMU, 32, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, WRPs, 16, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, BRPs, 8, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, SYSPMUID, 0, 8) +IDREG_END(ID_AA64DFR1_EL1) + +IDREG_START(ID_AA64DFR2_EL1) + IDREG_FIELD(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, SPE_nVM, 20, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, SPE_EXC, 16, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, BWE, 4, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, STEP, 0, 4) +IDREG_END(ID_AA64DFR2_EL1) + +IDREG_START(ID_AA64FPFR0_EL1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8CVT, 31, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8FMA, 30, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP4, 29, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP2, 28, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM8, 27, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM4, 26, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F16MM2, 15, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8E5M2, 0, 1) +IDREG_END(ID_AA64FPFR0_EL1) + +IDREG_START(ID_AA64ISAR0_EL1) + IDREG_FIELD(ID_AA64ISAR0_EL1, RNDR, 60, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, TLB, 56, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, TS, 52, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, FHM, 48, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, DP, 44, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SM4, 40, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SM3, 36, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA3, 32, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, RDM, 28, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, Atomic, 20, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, CRC32, 16, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA2, 12, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA1, 8, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, AES, 4, 4) +IDREG_END(ID_AA64ISAR0_EL1) + +IDREG_START(ID_AA64ISAR1_EL1) + IDREG_FIELD(ID_AA64ISAR1_EL1, LS64, 60, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, XS, 56, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, I8MM, 52, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, DGH, 48, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, BF16, 44, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, SPECRES, 40, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, SB, 36, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, FRINTTS, 32, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, GPI, 28, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, GPA, 24, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, LRCPC, 20, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, FCMA, 16, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, JSCVT, 12, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, API, 8, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, APA, 4, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, DPB, 0, 4) +IDREG_END(ID_AA64ISAR1_EL1) + +IDREG_START(ID_AA64ISAR2_EL1) + IDREG_FIELD(ID_AA64ISAR2_EL1, ATS1A, 60, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, LUT, 56, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, CSSC, 52, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, RPRFM, 48, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PCDPHINT, 44, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PRFMSLC, 40, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, SYSINSTR_128, 36, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, SYSREG_128, 32, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, CLRBHB, 28, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PAC_frac, 24, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, BC, 20, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, MOPS, 16, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, APA3, 12, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, GPA3, 8, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, RPRES, 4, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, WFxT, 0, 4) +IDREG_END(ID_AA64ISAR2_EL1) + +IDREG_START(ID_AA64ISAR3_EL1) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSCP, 44, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSCSHINT, 40, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, MTETC, 36, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, PAC_frac2, 32, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, FPRCVT, 28, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSUI, 24, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, OCCMO, 20, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSFE, 16, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, PACM, 12, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, TLBIW, 8, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, FAMINMAX, 4, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, CPA, 0, 4) +IDREG_END(ID_AA64ISAR3_EL1) + +IDREG_START(ID_AA64MMFR0_EL1) + IDREG_FIELD(ID_AA64MMFR0_EL1, ECV, 60, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, FGT, 56, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, ExS, 44, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4_2, 40, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64_2, 36, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16_2, 32, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4, 28, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64, 24, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16, 20, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, BigEndEL0, 16, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, SNSMem, 12, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, BigEnd, 8, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, ASIDBits, 4, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, PARange, 0, 4) +IDREG_END(ID_AA64MMFR0_EL1) + +IDREG_START(ID_AA64MMFR1_EL1) + IDREG_FIELD(ID_AA64MMFR1_EL1, ECBHB, 60, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, CMOW, 56, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, TIDCP1, 52, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, nTLBPA, 48, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, AFP, 44, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HCX, 40, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, ETS, 36, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, TWED, 32, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, XNX, 28, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, SpecSEI, 24, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, PAN, 20, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, LO, 16, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HPDS, 12, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, VH, 8, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, VMIDBits, 4, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HAFDBS, 0, 4) +IDREG_END(ID_AA64MMFR1_EL1) + +IDREG_START(ID_AA64MMFR2_EL1) + IDREG_FIELD(ID_AA64MMFR2_EL1, E0PD, 60, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, EVT, 56, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, BBM, 52, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, TTL, 48, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, FWB, 40, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, IDS, 36, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, AT, 32, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, ST, 28, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, NV, 24, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, CCIDX, 20, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, VARange, 16, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, IESB, 12, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, LSM, 8, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, UAO, 4, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, CnP, 0, 4) +IDREG_END(ID_AA64MMFR2_EL1) + +IDREG_START(ID_AA64MMFR3_EL1) + IDREG_FIELD(ID_AA64MMFR3_EL1, Spec_FPACC, 60, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, ADERR, 56, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SDERR, 52, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, ANERR, 44, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SNERR, 40, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, D128_2, 36, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, D128, 32, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, MEC, 28, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, AIE, 24, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S2POE, 20, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S1POE, 16, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S2PIE, 12, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S1PIE, 8, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SCTLRX, 4, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, TCRX, 0, 4) +IDREG_END(ID_AA64MMFR3_EL1) + +IDREG_START(ID_AA64MMFR4_EL1) + IDREG_FIELD(ID_AA64MMFR4_EL1, MTEFGT, 60, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, SCRX, 56, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TEV, 52, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TPS, 48, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, SRMASK, 44, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TLBID, 40, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, E3DSE, 36, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, EAESR, 32, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, RMEGDI, 28, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, E2H0, 24, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, NV_frac, 20, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, FGWTE3, 16, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, HACDBS, 12, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, ASID2, 8, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, EIESB, 4, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, PoPS, 0, 4) +IDREG_END(ID_AA64MMFR4_EL1) + +IDREG_START(ID_AA64PFR0_EL1) + IDREG_FIELD(ID_AA64PFR0_EL1, CSV3, 60, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, CSV2, 56, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, RME, 52, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, DIT, 48, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, AMU, 44, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, MPAM, 40, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, SEL2, 36, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, SVE, 32, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, RAS, 28, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, GIC, 24, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, AdvSIMD, 20, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, FP, 16, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL3, 12, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL2, 8, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL1, 4, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL0, 0, 4) +IDREG_END(ID_AA64PFR0_EL1) + +IDREG_START(ID_AA64PFR1_EL1) + IDREG_FIELD(ID_AA64PFR1_EL1, PFAR, 60, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, DF2, 56, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTEX, 52, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, THE, 48, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, GCS, 44, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTE_frac, 40, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, NMI, 36, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, CSV2_frac, 32, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, RNDR_trap, 28, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, SME, 24, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, RAS_frac, 12, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTE, 8, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, SSBS, 4, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, BT, 0, 4) +IDREG_END(ID_AA64PFR1_EL1) + +IDREG_START(ID_AA64PFR2_EL1) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTETCL, 44, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTETC, 40, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTE, 36, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, FPMR, 32, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MPAM2, 28, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, FGDT, 24, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEEIRG, 20, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, UINJ, 16, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, GCIE, 12, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEFAR, 8, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTESTOREONLY, 4, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEPERM, 0, 4) +IDREG_END(ID_AA64PFR2_EL1) + +IDREG_START(ID_AA64SMFR0_EL1) + IDREG_FIELD(ID_AA64SMFR0_EL1, FA64, 63, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, LUT6, 61, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, LUTv2, 60, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SMEver, 56, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, I16I64, 52, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, F64F64, 48, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, I16I32, 44, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, B16B16, 43, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F16F16, 42, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F8F16, 41, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F8F32, 40, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, I8I32, 36, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, F16F32, 35, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, B16F32, 34, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, BI32I32, 33, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F32F32, 32, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP4, 29, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP2, 28, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, AES, 24, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SFEXPA, 23, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, STMOP, 16, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SMOP4, 0, 1) +IDREG_END(ID_AA64SMFR0_EL1) + +IDREG_START(ID_AA64ZFR0_EL1) + IDREG_FIELD(ID_AA64ZFR0_EL1, F64MM, 56, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, F32MM, 52, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, F16MM, 48, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, I8MM, 44, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SM4, 40, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SHA3, 32, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, B16B16, 24, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, BF16, 20, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, BitPerm, 16, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, EltPerm, 12, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, AES, 4, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SVEver, 0, 4) +IDREG_END(ID_AA64ZFR0_EL1) + +IDREG_START(ID_AFR0_EL1) +IDREG_END(ID_AFR0_EL1) + +IDREG_START(ID_DFR0_EL1) + IDREG_FIELD(ID_DFR0_EL1, TraceFilt, 28, 4) + IDREG_FIELD(ID_DFR0_EL1, PerfMon, 24, 4) + IDREG_FIELD(ID_DFR0_EL1, MProfDbg, 20, 4) + IDREG_FIELD(ID_DFR0_EL1, MMapTrc, 16, 4) + IDREG_FIELD(ID_DFR0_EL1, CopTrc, 12, 4) + IDREG_FIELD(ID_DFR0_EL1, MMapDbg, 8, 4) + IDREG_FIELD(ID_DFR0_EL1, CopSDbg, 4, 4) + IDREG_FIELD(ID_DFR0_EL1, CopDbg, 0, 4) +IDREG_END(ID_DFR0_EL1) + +IDREG_START(ID_DFR1_EL1) + IDREG_FIELD(ID_DFR1_EL1, HPMN0, 4, 4) + IDREG_FIELD(ID_DFR1_EL1, MTPMU, 0, 4) +IDREG_END(ID_DFR1_EL1) + +IDREG_START(ID_ISAR0_EL1) + IDREG_FIELD(ID_ISAR0_EL1, Divide, 24, 4) + IDREG_FIELD(ID_ISAR0_EL1, Debug, 20, 4) + IDREG_FIELD(ID_ISAR0_EL1, Coproc, 16, 4) + IDREG_FIELD(ID_ISAR0_EL1, CmpBranch, 12, 4) + IDREG_FIELD(ID_ISAR0_EL1, BitField, 8, 4) + IDREG_FIELD(ID_ISAR0_EL1, BitCount, 4, 4) + IDREG_FIELD(ID_ISAR0_EL1, Swap, 0, 4) +IDREG_END(ID_ISAR0_EL1) + +IDREG_START(ID_ISAR1_EL1) + IDREG_FIELD(ID_ISAR1_EL1, Jazelle, 28, 4) + IDREG_FIELD(ID_ISAR1_EL1, Interwork, 24, 4) + IDREG_FIELD(ID_ISAR1_EL1, Immediate, 20, 4) + IDREG_FIELD(ID_ISAR1_EL1, IfThen, 16, 4) + IDREG_FIELD(ID_ISAR1_EL1, Extend, 12, 4) + IDREG_FIELD(ID_ISAR1_EL1, Except_AR, 8, 4) + IDREG_FIELD(ID_ISAR1_EL1, Except, 4, 4) + IDREG_FIELD(ID_ISAR1_EL1, Endian, 0, 4) +IDREG_END(ID_ISAR1_EL1) + +IDREG_START(ID_ISAR2_EL1) + IDREG_FIELD(ID_ISAR2_EL1, Reversal, 28, 4) + IDREG_FIELD(ID_ISAR2_EL1, PSR_AR, 24, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultU, 20, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultS, 16, 4) + IDREG_FIELD(ID_ISAR2_EL1, Mult, 12, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultiAccessInt, 8, 4) + IDREG_FIELD(ID_ISAR2_EL1, MemHint, 4, 4) + IDREG_FIELD(ID_ISAR2_EL1, LoadStore, 0, 4) +IDREG_END(ID_ISAR2_EL1) + +IDREG_START(ID_ISAR3_EL1) + IDREG_FIELD(ID_ISAR3_EL1, T32EE, 28, 4) + IDREG_FIELD(ID_ISAR3_EL1, TrueNOP, 24, 4) + IDREG_FIELD(ID_ISAR3_EL1, T32Copy, 20, 4) + IDREG_FIELD(ID_ISAR3_EL1, TabBranch, 16, 4) + IDREG_FIELD(ID_ISAR3_EL1, SynchPrim, 12, 4) + IDREG_FIELD(ID_ISAR3_EL1, SVC, 8, 4) + IDREG_FIELD(ID_ISAR3_EL1, SIMD, 4, 4) + IDREG_FIELD(ID_ISAR3_EL1, Saturate, 0, 4) +IDREG_END(ID_ISAR3_EL1) + +IDREG_START(ID_ISAR4_EL1) + IDREG_FIELD(ID_ISAR4_EL1, SWP_frac, 28, 4) + IDREG_FIELD(ID_ISAR4_EL1, PSR_M, 24, 4) + IDREG_FIELD(ID_ISAR4_EL1, SynchPrim_frac, 20, 4) + IDREG_FIELD(ID_ISAR4_EL1, Barrier, 16, 4) + IDREG_FIELD(ID_ISAR4_EL1, SMC, 12, 4) + IDREG_FIELD(ID_ISAR4_EL1, Writeback, 8, 4) + IDREG_FIELD(ID_ISAR4_EL1, WithShifts, 4, 4) + IDREG_FIELD(ID_ISAR4_EL1, Unpriv, 0, 4) +IDREG_END(ID_ISAR4_EL1) + +IDREG_START(ID_ISAR5_EL1) + IDREG_FIELD(ID_ISAR5_EL1, VCMA, 28, 4) + IDREG_FIELD(ID_ISAR5_EL1, RDM, 24, 4) + IDREG_FIELD(ID_ISAR5_EL1, CRC32, 16, 4) + IDREG_FIELD(ID_ISAR5_EL1, SHA2, 12, 4) + IDREG_FIELD(ID_ISAR5_EL1, SHA1, 8, 4) + IDREG_FIELD(ID_ISAR5_EL1, AES, 4, 4) + IDREG_FIELD(ID_ISAR5_EL1, SEVL, 0, 4) +IDREG_END(ID_ISAR5_EL1) + +IDREG_START(ID_ISAR6_EL1) + IDREG_FIELD(ID_ISAR6_EL1, CLRBHB, 28, 4) + IDREG_FIELD(ID_ISAR6_EL1, I8MM, 24, 4) + IDREG_FIELD(ID_ISAR6_EL1, BF16, 20, 4) + IDREG_FIELD(ID_ISAR6_EL1, SPECRES, 16, 4) + IDREG_FIELD(ID_ISAR6_EL1, SB, 12, 4) + IDREG_FIELD(ID_ISAR6_EL1, FHM, 8, 4) + IDREG_FIELD(ID_ISAR6_EL1, DP, 4, 4) + IDREG_FIELD(ID_ISAR6_EL1, JSCVT, 0, 4) +IDREG_END(ID_ISAR6_EL1) + +IDREG_START(ID_MMFR0_EL1) + IDREG_FIELD(ID_MMFR0_EL1, InnerShr, 28, 4) + IDREG_FIELD(ID_MMFR0_EL1, FCSE, 24, 4) + IDREG_FIELD(ID_MMFR0_EL1, AuxReg, 20, 4) + IDREG_FIELD(ID_MMFR0_EL1, TCM, 16, 4) + IDREG_FIELD(ID_MMFR0_EL1, ShareLvl, 12, 4) + IDREG_FIELD(ID_MMFR0_EL1, OuterShr, 8, 4) + IDREG_FIELD(ID_MMFR0_EL1, PMSA, 4, 4) + IDREG_FIELD(ID_MMFR0_EL1, VMSA, 0, 4) +IDREG_END(ID_MMFR0_EL1) + +IDREG_START(ID_MMFR1_EL1) + IDREG_FIELD(ID_MMFR1_EL1, BPred, 28, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1TstCln, 24, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1Uni, 20, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1Hvd, 16, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1UniSW, 12, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1HvdSW, 8, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1UniVA, 4, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1HvdVA, 0, 4) +IDREG_END(ID_MMFR1_EL1) + +IDREG_START(ID_MMFR2_EL1) + IDREG_FIELD(ID_MMFR2_EL1, HWAccFlg, 28, 4) + IDREG_FIELD(ID_MMFR2_EL1, WFIStall, 24, 4) + IDREG_FIELD(ID_MMFR2_EL1, MemBarr, 20, 4) + IDREG_FIELD(ID_MMFR2_EL1, UniTLB, 16, 4) + IDREG_FIELD(ID_MMFR2_EL1, HvdTLB, 12, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdRng, 8, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdBG, 4, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdFG, 0, 4) +IDREG_END(ID_MMFR2_EL1) + +IDREG_START(ID_MMFR3_EL1) + IDREG_FIELD(ID_MMFR3_EL1, Supersec, 28, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMemSz, 24, 4) + IDREG_FIELD(ID_MMFR3_EL1, CohWalk, 20, 4) + IDREG_FIELD(ID_MMFR3_EL1, PAN, 16, 4) + IDREG_FIELD(ID_MMFR3_EL1, MaintBcst, 12, 4) + IDREG_FIELD(ID_MMFR3_EL1, BPMaint, 8, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMaintSW, 4, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMaintVA, 0, 4) +IDREG_END(ID_MMFR3_EL1) + +IDREG_START(ID_MMFR4_EL1) + IDREG_FIELD(ID_MMFR4_EL1, EVT, 28, 4) + IDREG_FIELD(ID_MMFR4_EL1, CCIDX, 24, 4) + IDREG_FIELD(ID_MMFR4_EL1, LSM, 20, 4) + IDREG_FIELD(ID_MMFR4_EL1, HPDS, 16, 4) + IDREG_FIELD(ID_MMFR4_EL1, CnP, 12, 4) + IDREG_FIELD(ID_MMFR4_EL1, XNX, 8, 4) + IDREG_FIELD(ID_MMFR4_EL1, AC2, 4, 4) + IDREG_FIELD(ID_MMFR4_EL1, SpecSEI, 0, 4) +IDREG_END(ID_MMFR4_EL1) + +IDREG_START(ID_MMFR5_EL1) + IDREG_FIELD(ID_MMFR5_EL1, nTLBPA, 4, 4) + IDREG_FIELD(ID_MMFR5_EL1, ETS, 0, 4) +IDREG_END(ID_MMFR5_EL1) + +IDREG_START(ID_PFR0_EL1) + IDREG_FIELD(ID_PFR0_EL1, RAS, 28, 4) + IDREG_FIELD(ID_PFR0_EL1, DIT, 24, 4) + IDREG_FIELD(ID_PFR0_EL1, AMU, 20, 4) + IDREG_FIELD(ID_PFR0_EL1, CSV2, 16, 4) + IDREG_FIELD(ID_PFR0_EL1, State3, 12, 4) + IDREG_FIELD(ID_PFR0_EL1, State2, 8, 4) + IDREG_FIELD(ID_PFR0_EL1, State1, 4, 4) + IDREG_FIELD(ID_PFR0_EL1, State0, 0, 4) +IDREG_END(ID_PFR0_EL1) + +IDREG_START(ID_PFR1_EL1) + IDREG_FIELD(ID_PFR1_EL1, GIC, 28, 4) + IDREG_FIELD(ID_PFR1_EL1, Virt_frac, 24, 4) + IDREG_FIELD(ID_PFR1_EL1, Sec_frac, 20, 4) + IDREG_FIELD(ID_PFR1_EL1, GenTimer, 16, 4) + IDREG_FIELD(ID_PFR1_EL1, Virtualization, 12, 4) + IDREG_FIELD(ID_PFR1_EL1, MProgMod, 8, 4) + IDREG_FIELD(ID_PFR1_EL1, Security, 4, 4) + IDREG_FIELD(ID_PFR1_EL1, ProgMod, 0, 4) +IDREG_END(ID_PFR1_EL1) + +IDREG_START(ID_PFR2_EL1) + IDREG_FIELD(ID_PFR2_EL1, RAS_frac, 8, 4) + IDREG_FIELD(ID_PFR2_EL1, SSBS, 4, 4) + IDREG_FIELD(ID_PFR2_EL1, CSV3, 0, 4) +IDREG_END(ID_PFR2_EL1) + +IDREG_START(MIDR_EL1) + IDREG_FIELD(MIDR_EL1, Implementer, 24, 8) + IDREG_FIELD(MIDR_EL1, Variant, 20, 4) + IDREG_FIELD(MIDR_EL1, Architecture, 16, 4) + IDREG_FIELD(MIDR_EL1, PartNum, 4, 12) + IDREG_FIELD(MIDR_EL1, Revision, 0, 4) +IDREG_END(MIDR_EL1) + +IDREG_START(MPIDR_EL1) + IDREG_FIELD(MPIDR_EL1, Aff3, 32, 8) + IDREG_FIELD(MPIDR_EL1, U, 30, 1) + IDREG_FIELD(MPIDR_EL1, MT, 24, 1) + IDREG_FIELD(MPIDR_EL1, Aff2, 16, 8) + IDREG_FIELD(MPIDR_EL1, Aff1, 8, 8) + IDREG_FIELD(MPIDR_EL1, Aff0, 0, 8) +IDREG_END(MPIDR_EL1) + +IDREG_START(MVFR0_EL1) + IDREG_FIELD(MVFR0_EL1, FPRound, 28, 4) + IDREG_FIELD(MVFR0_EL1, FPShVec, 24, 4) + IDREG_FIELD(MVFR0_EL1, FPSqrt, 20, 4) + IDREG_FIELD(MVFR0_EL1, FPDivide, 16, 4) + IDREG_FIELD(MVFR0_EL1, FPTrap, 12, 4) + IDREG_FIELD(MVFR0_EL1, FPDP, 8, 4) + IDREG_FIELD(MVFR0_EL1, FPSP, 4, 4) + IDREG_FIELD(MVFR0_EL1, SIMDReg, 0, 4) +IDREG_END(MVFR0_EL1) + +IDREG_START(MVFR1_EL1) + IDREG_FIELD(MVFR1_EL1, SIMDFMAC, 28, 4) + IDREG_FIELD(MVFR1_EL1, FPHP, 24, 4) + IDREG_FIELD(MVFR1_EL1, SIMDHP, 20, 4) + IDREG_FIELD(MVFR1_EL1, SIMDSP, 16, 4) + IDREG_FIELD(MVFR1_EL1, SIMDInt, 12, 4) + IDREG_FIELD(MVFR1_EL1, SIMDLS, 8, 4) + IDREG_FIELD(MVFR1_EL1, FPDNaN, 4, 4) + IDREG_FIELD(MVFR1_EL1, FPFtZ, 0, 4) +IDREG_END(MVFR1_EL1) + +IDREG_START(MVFR2_EL1) + IDREG_FIELD(MVFR2_EL1, FPMisc, 4, 4) + IDREG_FIELD(MVFR2_EL1, SIMDMisc, 0, 4) +IDREG_END(MVFR2_EL1) + +IDREG_START(REVIDR_EL1) +IDREG_END(REVIDR_EL1) + +IDREG_START(SMIDR_EL1) + IDREG_FIELD(SMIDR_EL1, NSMC, 56, 4) + IDREG_FIELD(SMIDR_EL1, HIP, 52, 4) + IDREG_FIELD(SMIDR_EL1, Affinity2, 32, 20) + IDREG_FIELD(SMIDR_EL1, Implementer, 24, 8) + IDREG_FIELD(SMIDR_EL1, Revision, 16, 8) + IDREG_FIELD(SMIDR_EL1, SMPS, 15, 1) + IDREG_FIELD(SMIDR_EL1, SH, 13, 2) + IDREG_FIELD(SMIDR_EL1, Affinity, 0, 12) +IDREG_END(SMIDR_EL1) + --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1781616516; cv=none; d=zohomail.com; s=zohoarc; b=oDod81goLzaKBe97mATCoKFSx8E/11rCAQnmEHjiwLdgdXUMuiulx4tTmfIx2GV/mZXHrSJPg50EjPplDGow9dHSDl/XmmbO+luJAyzF4dcwSkjdTpiyPJcqnzwe14kPM9Ax1o1fpfWDnrGmjkzD6f1svdISivM4S7XnmyPaiPo= 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mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 17CC519540F1; Tue, 16 Jun 2026 13:27:31 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.48.30]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 8A0DC3000203; Tue, 16 Jun 2026 13:27:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616456; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=46WM/OIHlsoh+e2G7KideMp1fLqP+4oDrB6UIdo7IoU=; b=SBdgzWu52BgwzUKSZ8jkt3vw5m9dAvWNMoDczcLjyeHeVow8dxQcZ2xvEom+c1B00wgUXW YJhKscDicq54D2+312IHYfEc/RWn9WRWDPUUKIyxd+orBhAhiVN3AMjBS9w0BlUuNUnp7i OwonKqKak8urQ8l7S9rwGEfFND7JdmE= X-MC-Unique: UBk8NBhJOsCHkBGPd82wDQ-1 X-Mimecast-MFC-AGG-ID: UBk8NBhJOsCHkBGPd82wDQ_1781616451 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 08/17] target/arm/cpu-idregs.h.inc: Generate enum values Date: Tue, 16 Jun 2026 15:16:55 +0200 Message-ID: <20260616132625.1732031-9-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_75_100=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1781616518072158500 Content-Type: text/plain; charset="utf-8" Modify the python script so that enum values are also extracted from Registers.json. If enum values are found, the field and its enum values are defined within IDREG_FIELD_START/END. Each enum value is defined with IDREG_FIELD_ARCH_VAL() macro. Signed-off-by: Eric Auger --- target/arm/cpu-idregs.h.inc | 2290 ++++++++++++++--- .../update-aarch64-cpu-sysreg-properties.py | 77 +- 2 files changed, 1959 insertions(+), 408 deletions(-) diff --git a/target/arm/cpu-idregs.h.inc b/target/arm/cpu-idregs.h.inc index a10d750123..1c8b26133b 100644 --- a/target/arm/cpu-idregs.h.inc +++ b/target/arm/cpu-idregs.h.inc @@ -4,7 +4,11 @@ =20 /* IDREG_START(REG) */ /* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */ +/* or for fields with enum values */ +/* IDREG_FIELD_START(REG, FIELD, SHIFT, LENGTH) */ +/* IDREG_FIELD_ARCH_VAL(VALUE) */ /* ... */ +/* IDREG_FIELD_END(REG, FIELD) */ /* IDREG_END(REG) */ =20 IDREG_START(AIDR_EL1) @@ -28,7 +32,16 @@ IDREG_START(CLIDR_EL1) IDREG_FIELD(CLIDR_EL1, Ttype3, 37, 2) IDREG_FIELD(CLIDR_EL1, Ttype2, 35, 2) IDREG_FIELD(CLIDR_EL1, Ttype1, 33, 2) - IDREG_FIELD(CLIDR_EL1, ICB, 30, 3) + IDREG_FIELD_START(CLIDR_EL1, ICB, 30, 3) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_END(CLIDR_EL1, ICB) IDREG_FIELD(CLIDR_EL1, LoUU, 27, 3) IDREG_FIELD(CLIDR_EL1, LoC, 24, 3) IDREG_FIELD(CLIDR_EL1, LoUIS, 21, 3) @@ -43,12 +56,23 @@ IDREG_END(CLIDR_EL1) =20 IDREG_START(CTR_EL0) IDREG_FIELD(CTR_EL0, TminLine, 32, 6) - IDREG_FIELD(CTR_EL0, DIC, 29, 1) - IDREG_FIELD(CTR_EL0, IDC, 28, 1) + IDREG_FIELD_START(CTR_EL0, DIC, 29, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(CTR_EL0, DIC) + IDREG_FIELD_START(CTR_EL0, IDC, 28, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(CTR_EL0, IDC) IDREG_FIELD(CTR_EL0, CWG, 24, 4) IDREG_FIELD(CTR_EL0, ERG, 20, 4) IDREG_FIELD(CTR_EL0, DminLine, 16, 4) - IDREG_FIELD(CTR_EL0, L1Ip, 14, 2) + IDREG_FIELD_START(CTR_EL0, L1Ip, 14, 2) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(CTR_EL0, L1Ip) IDREG_FIELD(CTR_EL0, IminLine, 0, 4) IDREG_END(CTR_EL0) =20 @@ -69,549 +93,2007 @@ IDREG_START(ID_AA64AFR1_EL1) IDREG_END(ID_AA64AFR1_EL1) =20 IDREG_START(ID_AA64DFR0_EL1) - IDREG_FIELD(ID_AA64DFR0_EL1, HPMN0, 60, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, ExtTrcBuff, 56, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, BRBE, 52, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, MTPMU, 48, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, TraceBuffer, 44, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, TraceFilt, 40, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, DoubleLock, 36, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, PMSVer, 32, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4) + IDREG_FIELD_START(ID_AA64DFR0_EL1, HPMN0, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR0_EL1, HPMN0) + IDREG_FIELD_START(ID_AA64DFR0_EL1, ExtTrcBuff, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR0_EL1, ExtTrcBuff) + IDREG_FIELD_START(ID_AA64DFR0_EL1, BRBE, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64DFR0_EL1, BRBE) + IDREG_FIELD_START(ID_AA64DFR0_EL1, MTPMU, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, MTPMU) + IDREG_FIELD_START(ID_AA64DFR0_EL1, TraceBuffer, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64DFR0_EL1, TraceBuffer) + IDREG_FIELD_START(ID_AA64DFR0_EL1, TraceFilt, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR0_EL1, TraceFilt) + IDREG_FIELD_START(ID_AA64DFR0_EL1, DoubleLock, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, DoubleLock) + IDREG_FIELD_START(ID_AA64DFR0_EL1, PMSVer, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_END(ID_AA64DFR0_EL1, PMSVer) + IDREG_FIELD_START(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, CTX_CMPs) IDREG_FIELD(ID_AA64DFR0_EL1, WRPs, 20, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, PMSS, 16, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, BRPs, 12, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, PMUVer, 8, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, TraceVer, 4, 4) - IDREG_FIELD(ID_AA64DFR0_EL1, DebugVer, 0, 4) + IDREG_FIELD_START(ID_AA64DFR0_EL1, PMSS, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR0_EL1, PMSS) + IDREG_FIELD_START(ID_AA64DFR0_EL1, BRPs, 12, 4) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, BRPs) + IDREG_FIELD_START(ID_AA64DFR0_EL1, PMUVer, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64DFR0_EL1, PMUVer) + IDREG_FIELD_START(ID_AA64DFR0_EL1, TraceVer, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR0_EL1, TraceVer) + IDREG_FIELD_START(ID_AA64DFR0_EL1, DebugVer, 0, 4) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_END(ID_AA64DFR0_EL1, DebugVer) IDREG_END(ID_AA64DFR0_EL1) =20 IDREG_START(ID_AA64DFR1_EL1) IDREG_FIELD(ID_AA64DFR1_EL1, ABL_CMPs, 56, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, DPFZS, 52, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, EBEP, 48, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, ITE, 44, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, ABLE, 40, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, PMICNTR, 36, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, SPMU, 32, 4) - IDREG_FIELD(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, WRPs, 16, 8) - IDREG_FIELD(ID_AA64DFR1_EL1, BRPs, 8, 8) + IDREG_FIELD_START(ID_AA64DFR1_EL1, DPFZS, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR1_EL1, DPFZS) + IDREG_FIELD_START(ID_AA64DFR1_EL1, EBEP, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR1_EL1, EBEP) + IDREG_FIELD_START(ID_AA64DFR1_EL1, ITE, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR1_EL1, ITE) + IDREG_FIELD_START(ID_AA64DFR1_EL1, ABLE, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR1_EL1, ABLE) + IDREG_FIELD_START(ID_AA64DFR1_EL1, PMICNTR, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR1_EL1, PMICNTR) + IDREG_FIELD_START(ID_AA64DFR1_EL1, SPMU, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64DFR1_EL1, SPMU) + IDREG_FIELD_START(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_END(ID_AA64DFR1_EL1, CTX_CMPs) + IDREG_FIELD_START(ID_AA64DFR1_EL1, WRPs, 16, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_END(ID_AA64DFR1_EL1, WRPs) + IDREG_FIELD_START(ID_AA64DFR1_EL1, BRPs, 8, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_END(ID_AA64DFR1_EL1, BRPs) IDREG_FIELD(ID_AA64DFR1_EL1, SYSPMUID, 0, 8) IDREG_END(ID_AA64DFR1_EL1) =20 IDREG_START(ID_AA64DFR2_EL1) - IDREG_FIELD(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, SPE_nVM, 20, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, SPE_EXC, 16, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, BWE, 4, 4) - IDREG_FIELD(ID_AA64DFR2_EL1, STEP, 0, 4) + IDREG_FIELD_START(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR2_EL1, TRBE_EXC) + IDREG_FIELD_START(ID_AA64DFR2_EL1, SPE_nVM, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR2_EL1, SPE_nVM) + IDREG_FIELD_START(ID_AA64DFR2_EL1, SPE_EXC, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR2_EL1, SPE_EXC) + IDREG_FIELD_START(ID_AA64DFR2_EL1, BWE, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64DFR2_EL1, BWE) + IDREG_FIELD_START(ID_AA64DFR2_EL1, STEP, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64DFR2_EL1, STEP) IDREG_END(ID_AA64DFR2_EL1) =20 IDREG_START(ID_AA64FPFR0_EL1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8CVT, 31, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8FMA, 30, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP4, 29, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP2, 28, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM8, 27, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM4, 26, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F16MM2, 15, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) - IDREG_FIELD(ID_AA64FPFR0_EL1, F8E5M2, 0, 1) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8CVT, 31, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8CVT) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8FMA, 30, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8FMA) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8DP4, 29, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8DP4) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8DP2, 28, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8DP2) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8MM8, 27, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8MM8) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8MM4, 26, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8MM4) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F16MM2, 15, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F16MM2) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8E4M3) + IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8E5M2, 0, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8E5M2) IDREG_END(ID_AA64FPFR0_EL1) =20 IDREG_START(ID_AA64ISAR0_EL1) - IDREG_FIELD(ID_AA64ISAR0_EL1, RNDR, 60, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, TLB, 56, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, TS, 52, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, FHM, 48, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, DP, 44, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SM4, 40, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SM3, 36, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SHA3, 32, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, RDM, 28, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, Atomic, 20, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, CRC32, 16, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SHA2, 12, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, SHA1, 8, 4) - IDREG_FIELD(ID_AA64ISAR0_EL1, AES, 4, 4) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, RNDR, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, RNDR) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, TLB, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, TLB) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, TS, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, TS) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, FHM, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, FHM) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, DP, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, DP) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, SM4, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, SM4) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, SM3, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, SM3) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, SHA3, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, SHA3) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, RDM, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, RDM) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, Atomic, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, Atomic) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, CRC32, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, CRC32) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, SHA2, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, SHA2) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, SHA1, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, SHA1) + IDREG_FIELD_START(ID_AA64ISAR0_EL1, AES, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR0_EL1, AES) IDREG_END(ID_AA64ISAR0_EL1) =20 IDREG_START(ID_AA64ISAR1_EL1) - IDREG_FIELD(ID_AA64ISAR1_EL1, LS64, 60, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, XS, 56, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, I8MM, 52, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, DGH, 48, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, BF16, 44, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, SPECRES, 40, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, SB, 36, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, FRINTTS, 32, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, GPI, 28, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, GPA, 24, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, LRCPC, 20, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, FCMA, 16, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, JSCVT, 12, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, API, 8, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, APA, 4, 4) - IDREG_FIELD(ID_AA64ISAR1_EL1, DPB, 0, 4) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, LS64, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, LS64) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, XS, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, XS) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, I8MM, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, I8MM) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, DGH, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, DGH) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, BF16, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, BF16) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, SPECRES, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, SPECRES) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, SB, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, SB) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, FRINTTS, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, FRINTTS) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, GPI, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, GPI) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, GPA, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, GPA) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, LRCPC, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, LRCPC) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, FCMA, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, FCMA) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, JSCVT, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, JSCVT) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, API, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, API) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, APA, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, APA) + IDREG_FIELD_START(ID_AA64ISAR1_EL1, DPB, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR1_EL1, DPB) IDREG_END(ID_AA64ISAR1_EL1) =20 IDREG_START(ID_AA64ISAR2_EL1) - IDREG_FIELD(ID_AA64ISAR2_EL1, ATS1A, 60, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, LUT, 56, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, CSSC, 52, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, RPRFM, 48, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, PCDPHINT, 44, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, PRFMSLC, 40, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, SYSINSTR_128, 36, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, SYSREG_128, 32, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, CLRBHB, 28, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, PAC_frac, 24, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, BC, 20, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, MOPS, 16, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, APA3, 12, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, GPA3, 8, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, RPRES, 4, 4) - IDREG_FIELD(ID_AA64ISAR2_EL1, WFxT, 0, 4) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, ATS1A, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, ATS1A) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, LUT, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, LUT) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, CSSC, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, CSSC) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, RPRFM, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, RPRFM) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, PCDPHINT, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, PCDPHINT) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, PRFMSLC, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, PRFMSLC) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, SYSINSTR_128, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, SYSINSTR_128) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, SYSREG_128, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, SYSREG_128) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, CLRBHB, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, CLRBHB) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, PAC_frac, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, PAC_frac) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, BC, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, BC) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, MOPS, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, MOPS) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, APA3, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, APA3) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, GPA3, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, GPA3) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, RPRES, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, RPRES) + IDREG_FIELD_START(ID_AA64ISAR2_EL1, WFxT, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR2_EL1, WFxT) IDREG_END(ID_AA64ISAR2_EL1) =20 IDREG_START(ID_AA64ISAR3_EL1) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSCP, 44, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSCSHINT, 40, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, MTETC, 36, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, PAC_frac2, 32, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, FPRCVT, 28, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSUI, 24, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, OCCMO, 20, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, LSFE, 16, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, PACM, 12, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, TLBIW, 8, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, FAMINMAX, 4, 4) - IDREG_FIELD(ID_AA64ISAR3_EL1, CPA, 0, 4) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, LSCP, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, LSCP) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, LSCSHINT, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, LSCSHINT) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, MTETC, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, MTETC) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, PAC_frac2, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, PAC_frac2) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, FPRCVT, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, FPRCVT) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, LSUI, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, LSUI) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, OCCMO, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, OCCMO) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, LSFE, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, LSFE) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, PACM, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, PACM) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, TLBIW, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, TLBIW) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, FAMINMAX, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, FAMINMAX) + IDREG_FIELD_START(ID_AA64ISAR3_EL1, CPA, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ISAR3_EL1, CPA) IDREG_END(ID_AA64ISAR3_EL1) =20 IDREG_START(ID_AA64MMFR0_EL1) - IDREG_FIELD(ID_AA64MMFR0_EL1, ECV, 60, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, FGT, 56, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, ExS, 44, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4_2, 40, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64_2, 36, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16_2, 32, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4, 28, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64, 24, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16, 20, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, BigEndEL0, 16, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, SNSMem, 12, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, BigEnd, 8, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, ASIDBits, 4, 4) - IDREG_FIELD(ID_AA64MMFR0_EL1, PARange, 0, 4) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, ECV, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, ECV) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, FGT, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, FGT) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, ExS, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, ExS) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran4_2, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran4_2) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran64_2, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran64_2) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran16_2, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran16_2) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran4, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran4) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran64, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran64) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, TGran16, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, TGran16) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, BigEndEL0, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, BigEndEL0) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, SNSMem, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, SNSMem) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, BigEnd, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, BigEnd) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, ASIDBits, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, ASIDBits) + IDREG_FIELD_START(ID_AA64MMFR0_EL1, PARange, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_END(ID_AA64MMFR0_EL1, PARange) IDREG_END(ID_AA64MMFR0_EL1) =20 IDREG_START(ID_AA64MMFR1_EL1) - IDREG_FIELD(ID_AA64MMFR1_EL1, ECBHB, 60, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, CMOW, 56, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, TIDCP1, 52, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, nTLBPA, 48, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, AFP, 44, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, HCX, 40, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, ETS, 36, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, TWED, 32, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, XNX, 28, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, SpecSEI, 24, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, PAN, 20, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, LO, 16, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, HPDS, 12, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, VH, 8, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, VMIDBits, 4, 4) - IDREG_FIELD(ID_AA64MMFR1_EL1, HAFDBS, 0, 4) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, ECBHB, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, ECBHB) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, CMOW, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, CMOW) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, TIDCP1, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, TIDCP1) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, nTLBPA, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, nTLBPA) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, AFP, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, AFP) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, HCX, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, HCX) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, ETS, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, ETS) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, TWED, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, TWED) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, XNX, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, XNX) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, SpecSEI, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, SpecSEI) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, PAN, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, PAN) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, LO, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, LO) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, HPDS, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, HPDS) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, VH, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, VH) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, VMIDBits, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, VMIDBits) + IDREG_FIELD_START(ID_AA64MMFR1_EL1, HAFDBS, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_AA64MMFR1_EL1, HAFDBS) IDREG_END(ID_AA64MMFR1_EL1) =20 IDREG_START(ID_AA64MMFR2_EL1) - IDREG_FIELD(ID_AA64MMFR2_EL1, E0PD, 60, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, EVT, 56, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, BBM, 52, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, TTL, 48, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, FWB, 40, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, IDS, 36, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, AT, 32, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, ST, 28, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, NV, 24, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, CCIDX, 20, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, VARange, 16, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, IESB, 12, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, LSM, 8, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, UAO, 4, 4) - IDREG_FIELD(ID_AA64MMFR2_EL1, CnP, 0, 4) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, E0PD, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, E0PD) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, EVT, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, EVT) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, BBM, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, BBM) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, TTL, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, TTL) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, FWB, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, FWB) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, IDS, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, IDS) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, AT, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, AT) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, ST, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, ST) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, NV, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, NV) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, CCIDX, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, CCIDX) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, VARange, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, VARange) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, IESB, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, IESB) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, LSM, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, LSM) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, UAO, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, UAO) + IDREG_FIELD_START(ID_AA64MMFR2_EL1, CnP, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR2_EL1, CnP) IDREG_END(ID_AA64MMFR2_EL1) =20 IDREG_START(ID_AA64MMFR3_EL1) - IDREG_FIELD(ID_AA64MMFR3_EL1, Spec_FPACC, 60, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, ADERR, 56, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, SDERR, 52, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, ANERR, 44, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, SNERR, 40, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, D128_2, 36, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, D128, 32, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, MEC, 28, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, AIE, 24, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S2POE, 20, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S1POE, 16, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S2PIE, 12, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, S1PIE, 8, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, SCTLRX, 4, 4) - IDREG_FIELD(ID_AA64MMFR3_EL1, TCRX, 0, 4) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, Spec_FPACC, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, Spec_FPACC) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, ADERR, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, ADERR) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, SDERR, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, SDERR) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, ANERR, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, ANERR) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, SNERR, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, SNERR) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, D128_2, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, D128_2) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, D128, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, D128) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, MEC, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, MEC) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, AIE, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, AIE) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, S2POE, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, S2POE) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, S1POE, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, S1POE) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, S2PIE, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, S2PIE) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, S1PIE, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, S1PIE) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, SCTLRX, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, SCTLRX) + IDREG_FIELD_START(ID_AA64MMFR3_EL1, TCRX, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR3_EL1, TCRX) IDREG_END(ID_AA64MMFR3_EL1) =20 IDREG_START(ID_AA64MMFR4_EL1) - IDREG_FIELD(ID_AA64MMFR4_EL1, MTEFGT, 60, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, SCRX, 56, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, TEV, 52, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, TPS, 48, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, SRMASK, 44, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, TLBID, 40, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, E3DSE, 36, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, EAESR, 32, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, RMEGDI, 28, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, E2H0, 24, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, NV_frac, 20, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, FGWTE3, 16, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, HACDBS, 12, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, ASID2, 8, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, EIESB, 4, 4) - IDREG_FIELD(ID_AA64MMFR4_EL1, PoPS, 0, 4) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, MTEFGT, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, MTEFGT) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, SCRX, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, SCRX) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, TEV, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, TEV) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, TPS, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, TPS) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, SRMASK, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, SRMASK) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, TLBID, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, TLBID) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, E3DSE, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, E3DSE) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, EAESR, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, EAESR) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, RMEGDI, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, RMEGDI) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, E2H0, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(14) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, E2H0) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, NV_frac, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, NV_frac) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, FGWTE3, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, FGWTE3) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, HACDBS, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, HACDBS) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, ASID2, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, ASID2) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, EIESB, 4, 4) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, EIESB) + IDREG_FIELD_START(ID_AA64MMFR4_EL1, PoPS, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64MMFR4_EL1, PoPS) IDREG_END(ID_AA64MMFR4_EL1) =20 IDREG_START(ID_AA64PFR0_EL1) - IDREG_FIELD(ID_AA64PFR0_EL1, CSV3, 60, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, CSV2, 56, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, RME, 52, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, DIT, 48, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, AMU, 44, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, MPAM, 40, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, SEL2, 36, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, SVE, 32, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, RAS, 28, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, GIC, 24, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, AdvSIMD, 20, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, FP, 16, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL3, 12, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL2, 8, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL1, 4, 4) - IDREG_FIELD(ID_AA64PFR0_EL1, EL0, 0, 4) + IDREG_FIELD_START(ID_AA64PFR0_EL1, CSV3, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR0_EL1, CSV3) + IDREG_FIELD_START(ID_AA64PFR0_EL1, CSV2, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR0_EL1, CSV2) + IDREG_FIELD_START(ID_AA64PFR0_EL1, RME, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR0_EL1, RME) + IDREG_FIELD_START(ID_AA64PFR0_EL1, DIT, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, DIT) + IDREG_FIELD_START(ID_AA64PFR0_EL1, AMU, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, AMU) + IDREG_FIELD_START(ID_AA64PFR0_EL1, MPAM, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR0_EL1, MPAM) + IDREG_FIELD_START(ID_AA64PFR0_EL1, SEL2, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR0_EL1, SEL2) + IDREG_FIELD_START(ID_AA64PFR0_EL1, SVE, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR0_EL1, SVE) + IDREG_FIELD_START(ID_AA64PFR0_EL1, RAS, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR0_EL1, RAS) + IDREG_FIELD_START(ID_AA64PFR0_EL1, GIC, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR0_EL1, GIC) + IDREG_FIELD_START(ID_AA64PFR0_EL1, AdvSIMD, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64PFR0_EL1, AdvSIMD) + IDREG_FIELD_START(ID_AA64PFR0_EL1, FP, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64PFR0_EL1, FP) + IDREG_FIELD_START(ID_AA64PFR0_EL1, EL3, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, EL3) + IDREG_FIELD_START(ID_AA64PFR0_EL1, EL2, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, EL2) + IDREG_FIELD_START(ID_AA64PFR0_EL1, EL1, 4, 4) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, EL1) + IDREG_FIELD_START(ID_AA64PFR0_EL1, EL0, 0, 4) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR0_EL1, EL0) IDREG_END(ID_AA64PFR0_EL1) =20 IDREG_START(ID_AA64PFR1_EL1) - IDREG_FIELD(ID_AA64PFR1_EL1, PFAR, 60, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, DF2, 56, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MTEX, 52, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, THE, 48, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, GCS, 44, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MTE_frac, 40, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, NMI, 36, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, CSV2_frac, 32, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, RNDR_trap, 28, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, SME, 24, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, RAS_frac, 12, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, MTE, 8, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, SSBS, 4, 4) - IDREG_FIELD(ID_AA64PFR1_EL1, BT, 0, 4) + IDREG_FIELD_START(ID_AA64PFR1_EL1, PFAR, 60, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, PFAR) + IDREG_FIELD_START(ID_AA64PFR1_EL1, DF2, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, DF2) + IDREG_FIELD_START(ID_AA64PFR1_EL1, MTEX, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, MTEX) + IDREG_FIELD_START(ID_AA64PFR1_EL1, THE, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, THE) + IDREG_FIELD_START(ID_AA64PFR1_EL1, GCS, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, GCS) + IDREG_FIELD_START(ID_AA64PFR1_EL1, MTE_frac, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64PFR1_EL1, MTE_frac) + IDREG_FIELD_START(ID_AA64PFR1_EL1, NMI, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, NMI) + IDREG_FIELD_START(ID_AA64PFR1_EL1, CSV2_frac, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR1_EL1, CSV2_frac) + IDREG_FIELD_START(ID_AA64PFR1_EL1, RNDR_trap, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, RNDR_trap) + IDREG_FIELD_START(ID_AA64PFR1_EL1, SME, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR1_EL1, SME) + IDREG_FIELD_START(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, MPAM_frac) + IDREG_FIELD_START(ID_AA64PFR1_EL1, RAS_frac, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR1_EL1, RAS_frac) + IDREG_FIELD_START(ID_AA64PFR1_EL1, MTE, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR1_EL1, MTE) + IDREG_FIELD_START(ID_AA64PFR1_EL1, SSBS, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR1_EL1, SSBS) + IDREG_FIELD_START(ID_AA64PFR1_EL1, BT, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR1_EL1, BT) IDREG_END(ID_AA64PFR1_EL1) =20 IDREG_START(ID_AA64PFR2_EL1) - IDREG_FIELD(ID_AA64PFR2_EL1, VMTETCL, 44, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, VMTETC, 40, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, VMTE, 36, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, FPMR, 32, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MPAM2, 28, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, FGDT, 24, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTEEIRG, 20, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, UINJ, 16, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, GCIE, 12, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTEFAR, 8, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTESTOREONLY, 4, 4) - IDREG_FIELD(ID_AA64PFR2_EL1, MTEPERM, 0, 4) + IDREG_FIELD_START(ID_AA64PFR2_EL1, VMTETCL, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, VMTETCL) + IDREG_FIELD_START(ID_AA64PFR2_EL1, VMTETC, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64PFR2_EL1, VMTETC) + IDREG_FIELD_START(ID_AA64PFR2_EL1, VMTE, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR2_EL1, VMTE) + IDREG_FIELD_START(ID_AA64PFR2_EL1, FPMR, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, FPMR) + IDREG_FIELD_START(ID_AA64PFR2_EL1, MPAM2, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, MPAM2) + IDREG_FIELD_START(ID_AA64PFR2_EL1, FGDT, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64PFR2_EL1, FGDT) + IDREG_FIELD_START(ID_AA64PFR2_EL1, MTEEIRG, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, MTEEIRG) + IDREG_FIELD_START(ID_AA64PFR2_EL1, UINJ, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, UINJ) + IDREG_FIELD_START(ID_AA64PFR2_EL1, GCIE, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, GCIE) + IDREG_FIELD_START(ID_AA64PFR2_EL1, MTEFAR, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, MTEFAR) + IDREG_FIELD_START(ID_AA64PFR2_EL1, MTESTOREONLY, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, MTESTOREONLY) + IDREG_FIELD_START(ID_AA64PFR2_EL1, MTEPERM, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64PFR2_EL1, MTEPERM) IDREG_END(ID_AA64PFR2_EL1) =20 IDREG_START(ID_AA64SMFR0_EL1) - IDREG_FIELD(ID_AA64SMFR0_EL1, FA64, 63, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, LUT6, 61, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, LUTv2, 60, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SMEver, 56, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, I16I64, 52, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, F64F64, 48, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, I16I32, 44, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, B16B16, 43, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F16F16, 42, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F8F16, 41, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F8F32, 40, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, I8I32, 36, 4) - IDREG_FIELD(ID_AA64SMFR0_EL1, F16F32, 35, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, B16F32, 34, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, BI32I32, 33, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, F32F32, 32, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP4, 29, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP2, 28, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, AES, 24, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SFEXPA, 23, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, STMOP, 16, 1) - IDREG_FIELD(ID_AA64SMFR0_EL1, SMOP4, 0, 1) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, FA64, 63, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, FA64) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, LUT6, 61, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, LUT6) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, LUTv2, 60, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, LUTv2) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SMEver, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SMEver) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, I16I64, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, I16I64) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F64F64, 48, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F64F64) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, I16I32, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, I16I32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, B16B16, 43, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, B16B16) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F16F16, 42, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F16F16) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F8F16, 41, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F8F16) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F8F32, 40, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F8F32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, I8I32, 36, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, I8I32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F16F32, 35, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F16F32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, B16F32, 34, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, B16F32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, BI32I32, 33, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, BI32I32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, F32F32, 32, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, F32F32) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SF8FMA) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SF8DP4, 29, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SF8DP4) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SF8DP2, 28, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SF8DP2) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SBitPerm) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, AES, 24, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, AES) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SFEXPA, 23, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SFEXPA) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, STMOP, 16, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, STMOP) + IDREG_FIELD_START(ID_AA64SMFR0_EL1, SMOP4, 0, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64SMFR0_EL1, SMOP4) IDREG_END(ID_AA64SMFR0_EL1) =20 IDREG_START(ID_AA64ZFR0_EL1) - IDREG_FIELD(ID_AA64ZFR0_EL1, F64MM, 56, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, F32MM, 52, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, F16MM, 48, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, I8MM, 44, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, SM4, 40, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, SHA3, 32, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, B16B16, 24, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, BF16, 20, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, BitPerm, 16, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, EltPerm, 12, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, AES, 4, 4) - IDREG_FIELD(ID_AA64ZFR0_EL1, SVEver, 0, 4) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, F64MM, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, F64MM) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, F32MM, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, F32MM) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, F16MM, 48, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, F16MM) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, I8MM, 44, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, I8MM) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, SM4, 40, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, SM4) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, SHA3, 32, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, SHA3) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, B16B16, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, B16B16) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, BF16, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, BF16) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, BitPerm, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, BitPerm) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, EltPerm, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, EltPerm) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, AES, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, AES) + IDREG_FIELD_START(ID_AA64ZFR0_EL1, SVEver, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_AA64ZFR0_EL1, SVEver) IDREG_END(ID_AA64ZFR0_EL1) =20 IDREG_START(ID_AFR0_EL1) IDREG_END(ID_AFR0_EL1) =20 IDREG_START(ID_DFR0_EL1) - IDREG_FIELD(ID_DFR0_EL1, TraceFilt, 28, 4) - IDREG_FIELD(ID_DFR0_EL1, PerfMon, 24, 4) - IDREG_FIELD(ID_DFR0_EL1, MProfDbg, 20, 4) - IDREG_FIELD(ID_DFR0_EL1, MMapTrc, 16, 4) - IDREG_FIELD(ID_DFR0_EL1, CopTrc, 12, 4) - IDREG_FIELD(ID_DFR0_EL1, MMapDbg, 8, 4) + IDREG_FIELD_START(ID_DFR0_EL1, TraceFilt, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_DFR0_EL1, TraceFilt) + IDREG_FIELD_START(ID_DFR0_EL1, PerfMon, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_DFR0_EL1, PerfMon) + IDREG_FIELD_START(ID_DFR0_EL1, MProfDbg, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_DFR0_EL1, MProfDbg) + IDREG_FIELD_START(ID_DFR0_EL1, MMapTrc, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_DFR0_EL1, MMapTrc) + IDREG_FIELD_START(ID_DFR0_EL1, CopTrc, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_DFR0_EL1, CopTrc) + IDREG_FIELD_START(ID_DFR0_EL1, MMapDbg, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_END(ID_DFR0_EL1, MMapDbg) IDREG_FIELD(ID_DFR0_EL1, CopSDbg, 4, 4) - IDREG_FIELD(ID_DFR0_EL1, CopDbg, 0, 4) + IDREG_FIELD_START(ID_DFR0_EL1, CopDbg, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(8) + IDREG_FIELD_ARCH_VAL(9) + IDREG_FIELD_ARCH_VAL(10) + IDREG_FIELD_ARCH_VAL(11) + IDREG_FIELD_END(ID_DFR0_EL1, CopDbg) IDREG_END(ID_DFR0_EL1) =20 IDREG_START(ID_DFR1_EL1) - IDREG_FIELD(ID_DFR1_EL1, HPMN0, 4, 4) - IDREG_FIELD(ID_DFR1_EL1, MTPMU, 0, 4) + IDREG_FIELD_START(ID_DFR1_EL1, HPMN0, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_DFR1_EL1, HPMN0) + IDREG_FIELD_START(ID_DFR1_EL1, MTPMU, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_DFR1_EL1, MTPMU) IDREG_END(ID_DFR1_EL1) =20 IDREG_START(ID_ISAR0_EL1) - IDREG_FIELD(ID_ISAR0_EL1, Divide, 24, 4) - IDREG_FIELD(ID_ISAR0_EL1, Debug, 20, 4) - IDREG_FIELD(ID_ISAR0_EL1, Coproc, 16, 4) - IDREG_FIELD(ID_ISAR0_EL1, CmpBranch, 12, 4) - IDREG_FIELD(ID_ISAR0_EL1, BitField, 8, 4) - IDREG_FIELD(ID_ISAR0_EL1, BitCount, 4, 4) - IDREG_FIELD(ID_ISAR0_EL1, Swap, 0, 4) + IDREG_FIELD_START(ID_ISAR0_EL1, Divide, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR0_EL1, Divide) + IDREG_FIELD_START(ID_ISAR0_EL1, Debug, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR0_EL1, Debug) + IDREG_FIELD_START(ID_ISAR0_EL1, Coproc, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_ISAR0_EL1, Coproc) + IDREG_FIELD_START(ID_ISAR0_EL1, CmpBranch, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR0_EL1, CmpBranch) + IDREG_FIELD_START(ID_ISAR0_EL1, BitField, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR0_EL1, BitField) + IDREG_FIELD_START(ID_ISAR0_EL1, BitCount, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR0_EL1, BitCount) + IDREG_FIELD_START(ID_ISAR0_EL1, Swap, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR0_EL1, Swap) IDREG_END(ID_ISAR0_EL1) =20 IDREG_START(ID_ISAR1_EL1) - IDREG_FIELD(ID_ISAR1_EL1, Jazelle, 28, 4) - IDREG_FIELD(ID_ISAR1_EL1, Interwork, 24, 4) - IDREG_FIELD(ID_ISAR1_EL1, Immediate, 20, 4) - IDREG_FIELD(ID_ISAR1_EL1, IfThen, 16, 4) - IDREG_FIELD(ID_ISAR1_EL1, Extend, 12, 4) - IDREG_FIELD(ID_ISAR1_EL1, Except_AR, 8, 4) - IDREG_FIELD(ID_ISAR1_EL1, Except, 4, 4) - IDREG_FIELD(ID_ISAR1_EL1, Endian, 0, 4) + IDREG_FIELD_START(ID_ISAR1_EL1, Jazelle, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, Jazelle) + IDREG_FIELD_START(ID_ISAR1_EL1, Interwork, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_ISAR1_EL1, Interwork) + IDREG_FIELD_START(ID_ISAR1_EL1, Immediate, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, Immediate) + IDREG_FIELD_START(ID_ISAR1_EL1, IfThen, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, IfThen) + IDREG_FIELD_START(ID_ISAR1_EL1, Extend, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR1_EL1, Extend) + IDREG_FIELD_START(ID_ISAR1_EL1, Except_AR, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, Except_AR) + IDREG_FIELD_START(ID_ISAR1_EL1, Except, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, Except) + IDREG_FIELD_START(ID_ISAR1_EL1, Endian, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR1_EL1, Endian) IDREG_END(ID_ISAR1_EL1) =20 IDREG_START(ID_ISAR2_EL1) - IDREG_FIELD(ID_ISAR2_EL1, Reversal, 28, 4) - IDREG_FIELD(ID_ISAR2_EL1, PSR_AR, 24, 4) - IDREG_FIELD(ID_ISAR2_EL1, MultU, 20, 4) - IDREG_FIELD(ID_ISAR2_EL1, MultS, 16, 4) - IDREG_FIELD(ID_ISAR2_EL1, Mult, 12, 4) - IDREG_FIELD(ID_ISAR2_EL1, MultiAccessInt, 8, 4) - IDREG_FIELD(ID_ISAR2_EL1, MemHint, 4, 4) - IDREG_FIELD(ID_ISAR2_EL1, LoadStore, 0, 4) + IDREG_FIELD_START(ID_ISAR2_EL1, Reversal, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR2_EL1, Reversal) + IDREG_FIELD_START(ID_ISAR2_EL1, PSR_AR, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR2_EL1, PSR_AR) + IDREG_FIELD_START(ID_ISAR2_EL1, MultU, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR2_EL1, MultU) + IDREG_FIELD_START(ID_ISAR2_EL1, MultS, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_ISAR2_EL1, MultS) + IDREG_FIELD_START(ID_ISAR2_EL1, Mult, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR2_EL1, Mult) + IDREG_FIELD_START(ID_ISAR2_EL1, MultiAccessInt, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR2_EL1, MultiAccessInt) + IDREG_FIELD_START(ID_ISAR2_EL1, MemHint, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_ISAR2_EL1, MemHint) + IDREG_FIELD_START(ID_ISAR2_EL1, LoadStore, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR2_EL1, LoadStore) IDREG_END(ID_ISAR2_EL1) =20 IDREG_START(ID_ISAR3_EL1) - IDREG_FIELD(ID_ISAR3_EL1, T32EE, 28, 4) - IDREG_FIELD(ID_ISAR3_EL1, TrueNOP, 24, 4) - IDREG_FIELD(ID_ISAR3_EL1, T32Copy, 20, 4) - IDREG_FIELD(ID_ISAR3_EL1, TabBranch, 16, 4) - IDREG_FIELD(ID_ISAR3_EL1, SynchPrim, 12, 4) - IDREG_FIELD(ID_ISAR3_EL1, SVC, 8, 4) - IDREG_FIELD(ID_ISAR3_EL1, SIMD, 4, 4) - IDREG_FIELD(ID_ISAR3_EL1, Saturate, 0, 4) + IDREG_FIELD_START(ID_ISAR3_EL1, T32EE, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, T32EE) + IDREG_FIELD_START(ID_ISAR3_EL1, TrueNOP, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, TrueNOP) + IDREG_FIELD_START(ID_ISAR3_EL1, T32Copy, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, T32Copy) + IDREG_FIELD_START(ID_ISAR3_EL1, TabBranch, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, TabBranch) + IDREG_FIELD_START(ID_ISAR3_EL1, SynchPrim, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR3_EL1, SynchPrim) + IDREG_FIELD_START(ID_ISAR3_EL1, SVC, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, SVC) + IDREG_FIELD_START(ID_ISAR3_EL1, SIMD, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_ISAR3_EL1, SIMD) + IDREG_FIELD_START(ID_ISAR3_EL1, Saturate, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR3_EL1, Saturate) IDREG_END(ID_ISAR3_EL1) =20 IDREG_START(ID_ISAR4_EL1) - IDREG_FIELD(ID_ISAR4_EL1, SWP_frac, 28, 4) - IDREG_FIELD(ID_ISAR4_EL1, PSR_M, 24, 4) - IDREG_FIELD(ID_ISAR4_EL1, SynchPrim_frac, 20, 4) - IDREG_FIELD(ID_ISAR4_EL1, Barrier, 16, 4) - IDREG_FIELD(ID_ISAR4_EL1, SMC, 12, 4) - IDREG_FIELD(ID_ISAR4_EL1, Writeback, 8, 4) - IDREG_FIELD(ID_ISAR4_EL1, WithShifts, 4, 4) - IDREG_FIELD(ID_ISAR4_EL1, Unpriv, 0, 4) + IDREG_FIELD_START(ID_ISAR4_EL1, SWP_frac, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR4_EL1, SWP_frac) + IDREG_FIELD_START(ID_ISAR4_EL1, PSR_M, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR4_EL1, PSR_M) + IDREG_FIELD_START(ID_ISAR4_EL1, SynchPrim_frac, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_ISAR4_EL1, SynchPrim_frac) + IDREG_FIELD_START(ID_ISAR4_EL1, Barrier, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR4_EL1, Barrier) + IDREG_FIELD_START(ID_ISAR4_EL1, SMC, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR4_EL1, SMC) + IDREG_FIELD_START(ID_ISAR4_EL1, Writeback, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR4_EL1, Writeback) + IDREG_FIELD_START(ID_ISAR4_EL1, WithShifts, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_ISAR4_EL1, WithShifts) + IDREG_FIELD_START(ID_ISAR4_EL1, Unpriv, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR4_EL1, Unpriv) IDREG_END(ID_ISAR4_EL1) =20 IDREG_START(ID_ISAR5_EL1) - IDREG_FIELD(ID_ISAR5_EL1, VCMA, 28, 4) - IDREG_FIELD(ID_ISAR5_EL1, RDM, 24, 4) - IDREG_FIELD(ID_ISAR5_EL1, CRC32, 16, 4) - IDREG_FIELD(ID_ISAR5_EL1, SHA2, 12, 4) - IDREG_FIELD(ID_ISAR5_EL1, SHA1, 8, 4) - IDREG_FIELD(ID_ISAR5_EL1, AES, 4, 4) - IDREG_FIELD(ID_ISAR5_EL1, SEVL, 0, 4) + IDREG_FIELD_START(ID_ISAR5_EL1, VCMA, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, VCMA) + IDREG_FIELD_START(ID_ISAR5_EL1, RDM, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, RDM) + IDREG_FIELD_START(ID_ISAR5_EL1, CRC32, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, CRC32) + IDREG_FIELD_START(ID_ISAR5_EL1, SHA2, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, SHA2) + IDREG_FIELD_START(ID_ISAR5_EL1, SHA1, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, SHA1) + IDREG_FIELD_START(ID_ISAR5_EL1, AES, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR5_EL1, AES) + IDREG_FIELD_START(ID_ISAR5_EL1, SEVL, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR5_EL1, SEVL) IDREG_END(ID_ISAR5_EL1) =20 IDREG_START(ID_ISAR6_EL1) - IDREG_FIELD(ID_ISAR6_EL1, CLRBHB, 28, 4) - IDREG_FIELD(ID_ISAR6_EL1, I8MM, 24, 4) - IDREG_FIELD(ID_ISAR6_EL1, BF16, 20, 4) - IDREG_FIELD(ID_ISAR6_EL1, SPECRES, 16, 4) - IDREG_FIELD(ID_ISAR6_EL1, SB, 12, 4) - IDREG_FIELD(ID_ISAR6_EL1, FHM, 8, 4) - IDREG_FIELD(ID_ISAR6_EL1, DP, 4, 4) - IDREG_FIELD(ID_ISAR6_EL1, JSCVT, 0, 4) + IDREG_FIELD_START(ID_ISAR6_EL1, CLRBHB, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, CLRBHB) + IDREG_FIELD_START(ID_ISAR6_EL1, I8MM, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, I8MM) + IDREG_FIELD_START(ID_ISAR6_EL1, BF16, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, BF16) + IDREG_FIELD_START(ID_ISAR6_EL1, SPECRES, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_ISAR6_EL1, SPECRES) + IDREG_FIELD_START(ID_ISAR6_EL1, SB, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, SB) + IDREG_FIELD_START(ID_ISAR6_EL1, FHM, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, FHM) + IDREG_FIELD_START(ID_ISAR6_EL1, DP, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, DP) + IDREG_FIELD_START(ID_ISAR6_EL1, JSCVT, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_ISAR6_EL1, JSCVT) IDREG_END(ID_ISAR6_EL1) =20 IDREG_START(ID_MMFR0_EL1) - IDREG_FIELD(ID_MMFR0_EL1, InnerShr, 28, 4) - IDREG_FIELD(ID_MMFR0_EL1, FCSE, 24, 4) - IDREG_FIELD(ID_MMFR0_EL1, AuxReg, 20, 4) - IDREG_FIELD(ID_MMFR0_EL1, TCM, 16, 4) - IDREG_FIELD(ID_MMFR0_EL1, ShareLvl, 12, 4) - IDREG_FIELD(ID_MMFR0_EL1, OuterShr, 8, 4) - IDREG_FIELD(ID_MMFR0_EL1, PMSA, 4, 4) - IDREG_FIELD(ID_MMFR0_EL1, VMSA, 0, 4) + IDREG_FIELD_START(ID_MMFR0_EL1, InnerShr, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_MMFR0_EL1, InnerShr) + IDREG_FIELD_START(ID_MMFR0_EL1, FCSE, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR0_EL1, FCSE) + IDREG_FIELD_START(ID_MMFR0_EL1, AuxReg, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR0_EL1, AuxReg) + IDREG_FIELD_START(ID_MMFR0_EL1, TCM, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR0_EL1, TCM) + IDREG_FIELD_START(ID_MMFR0_EL1, ShareLvl, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR0_EL1, ShareLvl) + IDREG_FIELD_START(ID_MMFR0_EL1, OuterShr, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_MMFR0_EL1, OuterShr) + IDREG_FIELD_START(ID_MMFR0_EL1, PMSA, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR0_EL1, PMSA) + IDREG_FIELD_START(ID_MMFR0_EL1, VMSA, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_END(ID_MMFR0_EL1, VMSA) IDREG_END(ID_MMFR0_EL1) =20 IDREG_START(ID_MMFR1_EL1) - IDREG_FIELD(ID_MMFR1_EL1, BPred, 28, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1TstCln, 24, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1Uni, 20, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1Hvd, 16, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1UniSW, 12, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1HvdSW, 8, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1UniVA, 4, 4) - IDREG_FIELD(ID_MMFR1_EL1, L1HvdVA, 0, 4) + IDREG_FIELD_START(ID_MMFR1_EL1, BPred, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(ID_MMFR1_EL1, BPred) + IDREG_FIELD_START(ID_MMFR1_EL1, L1TstCln, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR1_EL1, L1TstCln) + IDREG_FIELD_START(ID_MMFR1_EL1, L1Uni, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR1_EL1, L1Uni) + IDREG_FIELD_START(ID_MMFR1_EL1, L1Hvd, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR1_EL1, L1Hvd) + IDREG_FIELD_START(ID_MMFR1_EL1, L1UniSW, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR1_EL1, L1UniSW) + IDREG_FIELD_START(ID_MMFR1_EL1, L1HvdSW, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR1_EL1, L1HvdSW) + IDREG_FIELD_START(ID_MMFR1_EL1, L1UniVA, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR1_EL1, L1UniVA) + IDREG_FIELD_START(ID_MMFR1_EL1, L1HvdVA, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR1_EL1, L1HvdVA) IDREG_END(ID_MMFR1_EL1) =20 IDREG_START(ID_MMFR2_EL1) - IDREG_FIELD(ID_MMFR2_EL1, HWAccFlg, 28, 4) - IDREG_FIELD(ID_MMFR2_EL1, WFIStall, 24, 4) - IDREG_FIELD(ID_MMFR2_EL1, MemBarr, 20, 4) - IDREG_FIELD(ID_MMFR2_EL1, UniTLB, 16, 4) + IDREG_FIELD_START(ID_MMFR2_EL1, HWAccFlg, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR2_EL1, HWAccFlg) + IDREG_FIELD_START(ID_MMFR2_EL1, WFIStall, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR2_EL1, WFIStall) + IDREG_FIELD_START(ID_MMFR2_EL1, MemBarr, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR2_EL1, MemBarr) + IDREG_FIELD_START(ID_MMFR2_EL1, UniTLB, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_END(ID_MMFR2_EL1, UniTLB) IDREG_FIELD(ID_MMFR2_EL1, HvdTLB, 12, 4) - IDREG_FIELD(ID_MMFR2_EL1, L1HvdRng, 8, 4) - IDREG_FIELD(ID_MMFR2_EL1, L1HvdBG, 4, 4) - IDREG_FIELD(ID_MMFR2_EL1, L1HvdFG, 0, 4) + IDREG_FIELD_START(ID_MMFR2_EL1, L1HvdRng, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR2_EL1, L1HvdRng) + IDREG_FIELD_START(ID_MMFR2_EL1, L1HvdBG, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR2_EL1, L1HvdBG) + IDREG_FIELD_START(ID_MMFR2_EL1, L1HvdFG, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR2_EL1, L1HvdFG) IDREG_END(ID_MMFR2_EL1) =20 IDREG_START(ID_MMFR3_EL1) - IDREG_FIELD(ID_MMFR3_EL1, Supersec, 28, 4) - IDREG_FIELD(ID_MMFR3_EL1, CMemSz, 24, 4) - IDREG_FIELD(ID_MMFR3_EL1, CohWalk, 20, 4) - IDREG_FIELD(ID_MMFR3_EL1, PAN, 16, 4) - IDREG_FIELD(ID_MMFR3_EL1, MaintBcst, 12, 4) - IDREG_FIELD(ID_MMFR3_EL1, BPMaint, 8, 4) - IDREG_FIELD(ID_MMFR3_EL1, CMaintSW, 4, 4) - IDREG_FIELD(ID_MMFR3_EL1, CMaintVA, 0, 4) + IDREG_FIELD_START(ID_MMFR3_EL1, Supersec, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(ID_MMFR3_EL1, Supersec) + IDREG_FIELD_START(ID_MMFR3_EL1, CMemSz, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR3_EL1, CMemSz) + IDREG_FIELD_START(ID_MMFR3_EL1, CohWalk, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR3_EL1, CohWalk) + IDREG_FIELD_START(ID_MMFR3_EL1, PAN, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR3_EL1, PAN) + IDREG_FIELD_START(ID_MMFR3_EL1, MaintBcst, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR3_EL1, MaintBcst) + IDREG_FIELD_START(ID_MMFR3_EL1, BPMaint, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR3_EL1, BPMaint) + IDREG_FIELD_START(ID_MMFR3_EL1, CMaintSW, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR3_EL1, CMaintSW) + IDREG_FIELD_START(ID_MMFR3_EL1, CMaintVA, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR3_EL1, CMaintVA) IDREG_END(ID_MMFR3_EL1) =20 IDREG_START(ID_MMFR4_EL1) - IDREG_FIELD(ID_MMFR4_EL1, EVT, 28, 4) - IDREG_FIELD(ID_MMFR4_EL1, CCIDX, 24, 4) - IDREG_FIELD(ID_MMFR4_EL1, LSM, 20, 4) - IDREG_FIELD(ID_MMFR4_EL1, HPDS, 16, 4) - IDREG_FIELD(ID_MMFR4_EL1, CnP, 12, 4) - IDREG_FIELD(ID_MMFR4_EL1, XNX, 8, 4) - IDREG_FIELD(ID_MMFR4_EL1, AC2, 4, 4) - IDREG_FIELD(ID_MMFR4_EL1, SpecSEI, 0, 4) + IDREG_FIELD_START(ID_MMFR4_EL1, EVT, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR4_EL1, EVT) + IDREG_FIELD_START(ID_MMFR4_EL1, CCIDX, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, CCIDX) + IDREG_FIELD_START(ID_MMFR4_EL1, LSM, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, LSM) + IDREG_FIELD_START(ID_MMFR4_EL1, HPDS, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_MMFR4_EL1, HPDS) + IDREG_FIELD_START(ID_MMFR4_EL1, CnP, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, CnP) + IDREG_FIELD_START(ID_MMFR4_EL1, XNX, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, XNX) + IDREG_FIELD_START(ID_MMFR4_EL1, AC2, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, AC2) + IDREG_FIELD_START(ID_MMFR4_EL1, SpecSEI, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR4_EL1, SpecSEI) IDREG_END(ID_MMFR4_EL1) =20 IDREG_START(ID_MMFR5_EL1) - IDREG_FIELD(ID_MMFR5_EL1, nTLBPA, 4, 4) - IDREG_FIELD(ID_MMFR5_EL1, ETS, 0, 4) + IDREG_FIELD_START(ID_MMFR5_EL1, nTLBPA, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_MMFR5_EL1, nTLBPA) + IDREG_FIELD_START(ID_MMFR5_EL1, ETS, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_MMFR5_EL1, ETS) IDREG_END(ID_MMFR5_EL1) =20 IDREG_START(ID_PFR0_EL1) - IDREG_FIELD(ID_PFR0_EL1, RAS, 28, 4) - IDREG_FIELD(ID_PFR0_EL1, DIT, 24, 4) - IDREG_FIELD(ID_PFR0_EL1, AMU, 20, 4) - IDREG_FIELD(ID_PFR0_EL1, CSV2, 16, 4) - IDREG_FIELD(ID_PFR0_EL1, State3, 12, 4) - IDREG_FIELD(ID_PFR0_EL1, State2, 8, 4) - IDREG_FIELD(ID_PFR0_EL1, State1, 4, 4) - IDREG_FIELD(ID_PFR0_EL1, State0, 0, 4) + IDREG_FIELD_START(ID_PFR0_EL1, RAS, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_PFR0_EL1, RAS) + IDREG_FIELD_START(ID_PFR0_EL1, DIT, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR0_EL1, DIT) + IDREG_FIELD_START(ID_PFR0_EL1, AMU, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR0_EL1, AMU) + IDREG_FIELD_START(ID_PFR0_EL1, CSV2, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR0_EL1, CSV2) + IDREG_FIELD_START(ID_PFR0_EL1, State3, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR0_EL1, State3) + IDREG_FIELD_START(ID_PFR0_EL1, State2, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR0_EL1, State2) + IDREG_FIELD_START(ID_PFR0_EL1, State1, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_PFR0_EL1, State1) + IDREG_FIELD_START(ID_PFR0_EL1, State0, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR0_EL1, State0) IDREG_END(ID_PFR0_EL1) =20 IDREG_START(ID_PFR1_EL1) - IDREG_FIELD(ID_PFR1_EL1, GIC, 28, 4) - IDREG_FIELD(ID_PFR1_EL1, Virt_frac, 24, 4) - IDREG_FIELD(ID_PFR1_EL1, Sec_frac, 20, 4) - IDREG_FIELD(ID_PFR1_EL1, GenTimer, 16, 4) - IDREG_FIELD(ID_PFR1_EL1, Virtualization, 12, 4) - IDREG_FIELD(ID_PFR1_EL1, MProgMod, 8, 4) - IDREG_FIELD(ID_PFR1_EL1, Security, 4, 4) - IDREG_FIELD(ID_PFR1_EL1, ProgMod, 0, 4) + IDREG_FIELD_START(ID_PFR1_EL1, GIC, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(ID_PFR1_EL1, GIC) + IDREG_FIELD_START(ID_PFR1_EL1, Virt_frac, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR1_EL1, Virt_frac) + IDREG_FIELD_START(ID_PFR1_EL1, Sec_frac, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR1_EL1, Sec_frac) + IDREG_FIELD_START(ID_PFR1_EL1, GenTimer, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR1_EL1, GenTimer) + IDREG_FIELD_START(ID_PFR1_EL1, Virtualization, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR1_EL1, Virtualization) + IDREG_FIELD_START(ID_PFR1_EL1, MProgMod, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR1_EL1, MProgMod) + IDREG_FIELD_START(ID_PFR1_EL1, Security, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(ID_PFR1_EL1, Security) + IDREG_FIELD_START(ID_PFR1_EL1, ProgMod, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR1_EL1, ProgMod) IDREG_END(ID_PFR1_EL1) =20 IDREG_START(ID_PFR2_EL1) - IDREG_FIELD(ID_PFR2_EL1, RAS_frac, 8, 4) - IDREG_FIELD(ID_PFR2_EL1, SSBS, 4, 4) - IDREG_FIELD(ID_PFR2_EL1, CSV3, 0, 4) + IDREG_FIELD_START(ID_PFR2_EL1, RAS_frac, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR2_EL1, RAS_frac) + IDREG_FIELD_START(ID_PFR2_EL1, SSBS, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR2_EL1, SSBS) + IDREG_FIELD_START(ID_PFR2_EL1, CSV3, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(ID_PFR2_EL1, CSV3) IDREG_END(ID_PFR2_EL1) =20 IDREG_START(MIDR_EL1) - IDREG_FIELD(MIDR_EL1, Implementer, 24, 8) + IDREG_FIELD_START(MIDR_EL1, Implementer, 24, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(65) + IDREG_FIELD_ARCH_VAL(66) + IDREG_FIELD_ARCH_VAL(67) + IDREG_FIELD_ARCH_VAL(68) + IDREG_FIELD_ARCH_VAL(70) + IDREG_FIELD_ARCH_VAL(73) + IDREG_FIELD_ARCH_VAL(77) + IDREG_FIELD_ARCH_VAL(78) + IDREG_FIELD_ARCH_VAL(80) + IDREG_FIELD_ARCH_VAL(81) + IDREG_FIELD_ARCH_VAL(86) + IDREG_FIELD_ARCH_VAL(105) + IDREG_FIELD_ARCH_VAL(192) + IDREG_FIELD_END(MIDR_EL1, Implementer) IDREG_FIELD(MIDR_EL1, Variant, 20, 4) - IDREG_FIELD(MIDR_EL1, Architecture, 16, 4) + IDREG_FIELD_START(MIDR_EL1, Architecture, 16, 4) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_ARCH_VAL(5) + IDREG_FIELD_ARCH_VAL(6) + IDREG_FIELD_ARCH_VAL(7) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(MIDR_EL1, Architecture) IDREG_FIELD(MIDR_EL1, PartNum, 4, 12) IDREG_FIELD(MIDR_EL1, Revision, 0, 4) IDREG_END(MIDR_EL1) =20 IDREG_START(MPIDR_EL1) IDREG_FIELD(MPIDR_EL1, Aff3, 32, 8) - IDREG_FIELD(MPIDR_EL1, U, 30, 1) - IDREG_FIELD(MPIDR_EL1, MT, 24, 1) + IDREG_FIELD_START(MPIDR_EL1, U, 30, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MPIDR_EL1, U) + IDREG_FIELD_START(MPIDR_EL1, MT, 24, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MPIDR_EL1, MT) IDREG_FIELD(MPIDR_EL1, Aff2, 16, 8) IDREG_FIELD(MPIDR_EL1, Aff1, 8, 8) IDREG_FIELD(MPIDR_EL1, Aff0, 0, 8) IDREG_END(MPIDR_EL1) =20 IDREG_START(MVFR0_EL1) - IDREG_FIELD(MVFR0_EL1, FPRound, 28, 4) - IDREG_FIELD(MVFR0_EL1, FPShVec, 24, 4) - IDREG_FIELD(MVFR0_EL1, FPSqrt, 20, 4) - IDREG_FIELD(MVFR0_EL1, FPDivide, 16, 4) - IDREG_FIELD(MVFR0_EL1, FPTrap, 12, 4) - IDREG_FIELD(MVFR0_EL1, FPDP, 8, 4) - IDREG_FIELD(MVFR0_EL1, FPSP, 4, 4) - IDREG_FIELD(MVFR0_EL1, SIMDReg, 0, 4) + IDREG_FIELD_START(MVFR0_EL1, FPRound, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR0_EL1, FPRound) + IDREG_FIELD_START(MVFR0_EL1, FPShVec, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR0_EL1, FPShVec) + IDREG_FIELD_START(MVFR0_EL1, FPSqrt, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR0_EL1, FPSqrt) + IDREG_FIELD_START(MVFR0_EL1, FPDivide, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR0_EL1, FPDivide) + IDREG_FIELD_START(MVFR0_EL1, FPTrap, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR0_EL1, FPTrap) + IDREG_FIELD_START(MVFR0_EL1, FPDP, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(MVFR0_EL1, FPDP) + IDREG_FIELD_START(MVFR0_EL1, FPSP, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(MVFR0_EL1, FPSP) + IDREG_FIELD_START(MVFR0_EL1, SIMDReg, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(MVFR0_EL1, SIMDReg) IDREG_END(MVFR0_EL1) =20 IDREG_START(MVFR1_EL1) - IDREG_FIELD(MVFR1_EL1, SIMDFMAC, 28, 4) - IDREG_FIELD(MVFR1_EL1, FPHP, 24, 4) - IDREG_FIELD(MVFR1_EL1, SIMDHP, 20, 4) - IDREG_FIELD(MVFR1_EL1, SIMDSP, 16, 4) - IDREG_FIELD(MVFR1_EL1, SIMDInt, 12, 4) - IDREG_FIELD(MVFR1_EL1, SIMDLS, 8, 4) - IDREG_FIELD(MVFR1_EL1, FPDNaN, 4, 4) - IDREG_FIELD(MVFR1_EL1, FPFtZ, 0, 4) + IDREG_FIELD_START(MVFR1_EL1, SIMDFMAC, 28, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, SIMDFMAC) + IDREG_FIELD_START(MVFR1_EL1, FPHP, 24, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(MVFR1_EL1, FPHP) + IDREG_FIELD_START(MVFR1_EL1, SIMDHP, 20, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_END(MVFR1_EL1, SIMDHP) + IDREG_FIELD_START(MVFR1_EL1, SIMDSP, 16, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, SIMDSP) + IDREG_FIELD_START(MVFR1_EL1, SIMDInt, 12, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, SIMDInt) + IDREG_FIELD_START(MVFR1_EL1, SIMDLS, 8, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, SIMDLS) + IDREG_FIELD_START(MVFR1_EL1, FPDNaN, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, FPDNaN) + IDREG_FIELD_START(MVFR1_EL1, FPFtZ, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(MVFR1_EL1, FPFtZ) IDREG_END(MVFR1_EL1) =20 IDREG_START(MVFR2_EL1) - IDREG_FIELD(MVFR2_EL1, FPMisc, 4, 4) - IDREG_FIELD(MVFR2_EL1, SIMDMisc, 0, 4) + IDREG_FIELD_START(MVFR2_EL1, FPMisc, 4, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_ARCH_VAL(4) + IDREG_FIELD_END(MVFR2_EL1, FPMisc) + IDREG_FIELD_START(MVFR2_EL1, SIMDMisc, 0, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(MVFR2_EL1, SIMDMisc) IDREG_END(MVFR2_EL1) =20 IDREG_START(REVIDR_EL1) IDREG_END(REVIDR_EL1) =20 IDREG_START(SMIDR_EL1) - IDREG_FIELD(SMIDR_EL1, NSMC, 56, 4) - IDREG_FIELD(SMIDR_EL1, HIP, 52, 4) + IDREG_FIELD_START(SMIDR_EL1, NSMC, 56, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(15) + IDREG_FIELD_END(SMIDR_EL1, NSMC) + IDREG_FIELD_START(SMIDR_EL1, HIP, 52, 4) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_END(SMIDR_EL1, HIP) IDREG_FIELD(SMIDR_EL1, Affinity2, 32, 20) - IDREG_FIELD(SMIDR_EL1, Implementer, 24, 8) + IDREG_FIELD_START(SMIDR_EL1, Implementer, 24, 8) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(65) + IDREG_FIELD_ARCH_VAL(66) + IDREG_FIELD_ARCH_VAL(67) + IDREG_FIELD_ARCH_VAL(68) + IDREG_FIELD_ARCH_VAL(70) + IDREG_FIELD_ARCH_VAL(73) + IDREG_FIELD_ARCH_VAL(77) + IDREG_FIELD_ARCH_VAL(78) + IDREG_FIELD_ARCH_VAL(80) + IDREG_FIELD_ARCH_VAL(81) + IDREG_FIELD_ARCH_VAL(86) + IDREG_FIELD_ARCH_VAL(105) + IDREG_FIELD_ARCH_VAL(192) + IDREG_FIELD_END(SMIDR_EL1, Implementer) IDREG_FIELD(SMIDR_EL1, Revision, 16, 8) - IDREG_FIELD(SMIDR_EL1, SMPS, 15, 1) - IDREG_FIELD(SMIDR_EL1, SH, 13, 2) + IDREG_FIELD_START(SMIDR_EL1, SMPS, 15, 1) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_END(SMIDR_EL1, SMPS) + IDREG_FIELD_START(SMIDR_EL1, SH, 13, 2) + IDREG_FIELD_ARCH_VAL(0) + IDREG_FIELD_ARCH_VAL(1) + IDREG_FIELD_ARCH_VAL(2) + IDREG_FIELD_ARCH_VAL(3) + IDREG_FIELD_END(SMIDR_EL1, SH) IDREG_FIELD(SMIDR_EL1, Affinity, 0, 12) IDREG_END(SMIDR_EL1) =20 diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/upda= te-aarch64-cpu-sysreg-properties.py index 6f5edb88d2..e1d6c4afef 100644 --- a/scripts/update-aarch64-cpu-sysreg-properties.py +++ b/scripts/update-aarch64-cpu-sysreg-properties.py @@ -9,7 +9,12 @@ # # IDREG_START(REG) # IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) -# ... +# or for fields with enum values +# IDREG_FIELD_START(REG, FIELD, SHIFT, LENGTH) +# IDREG_FIELD_ARCH_VAL(VALUE) +# ../.. +# IDREG_FIELD_END(REG, FIELD) +# ../..=20 # IDREG_END(REG) # # Copyright (C) 2026 Red Hat, Inc. @@ -98,6 +103,51 @@ def collect_fields(item, bit_offset=3D0): return fields =20 =20 +def extract_field_enums(field): + enums =3D [] + if not isinstance(field, dict): + return enums + + value_obj =3D field.get("value") + if not isinstance(value_obj, dict): + return enums + + constraints =3D value_obj.get("constraints") + if not isinstance(constraints, dict): + return enums + + val_entries =3D constraints.get("values", []) + if not isinstance(val_entries, list): + return enums + + for val_entry in val_entries: + if not isinstance(val_entry, dict): + continue + =20 + if val_entry.get("_type") =3D=3D "Values.Value": + raw_val =3D val_entry.get("value") + if raw_val is None: + continue + =20 + # some of the values have ' like "'0100'" + raw_val_str =3D str(raw_val).strip().replace("'", "") + =20 + try: + # convert into bin=20 + int_val =3D int(raw_val_str, 2) + except ValueError: + try: + # Fallback to dec if not bin + int_val =3D int(raw_val_str, 0) + except ValueError: + continue + =20 + enums.append({ + 'value': int_val + }) + =20 + return enums + def generate_sysreg_properties_from_registers_json(id_reg_names, raw_json_= path): with open(raw_json_path, 'r') as f: register_data =3D json.load(f) @@ -128,16 +178,31 @@ def generate_sysreg_properties_from_registers_json(id= _reg_names, raw_json_path): # Only keep the fields with the highest MSB # needed fir CCSIDR_EL1 if name not in unique_fields or msb > unique_fields[na= me]['msb']: - unique_fields[name] =3D {'lsb': lsb, 'msb': msb, '= width': width} + # extract enum values if any + enums =3D extract_field_enums(val) + unique_fields[name] =3D {'lsb': lsb, 'msb': msb, '= width': width, 'enums': enums} =20 # Sort decreasing lsbs sorted_fields =3D sorted(unique_fields.items(), key=3Dlambda x: x[1]['lsb'], reverse=3DTrue) =20 for name, bits in sorted_fields: - line =3D (f" IDREG_FIELD({reg_name}, " - f"{name}, {bits['lsb']}, {bits['width']})\n") + enums_list =3D bits.get('enums', []) + + if enums_list: + line =3D (f" IDREG_FIELD_START({reg_name}, " + f"{name}, {bits['lsb']}, {bits['width']})\n") + else: + line =3D (f" IDREG_FIELD({reg_name}, " + f"{name}, {bits['lsb']}, {bits['width']})\n") final_output +=3D line + # add the enum value definition if any + for enum_item in enums_list: + final_output +=3D (f" IDREG_FIELD_ARCH_VAL({enum_it= em['value']})\n") + if enums_list: + line =3D (f" IDREG_FIELD_END({reg_name}, {name})\n") + final_output +=3D line + =20 final_output +=3D f"IDREG_END({reg_name})\n" final_output +=3D "\n" =20 @@ -147,7 +212,11 @@ def generate_sysreg_properties_from_registers_json(id_= reg_names, raw_json_path): f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") f.write("/* IDREG_START(REG) */\n") f.write("/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */\n") + f.write("/* or for fields with enum values */\n") + f.write("/* IDREG_FIELD_START(REG, FIELD, SHIFT, LENGTH) */\n") + f.write("/* IDREG_FIELD_ARCH_VAL(VALUE) */\n") f.write("/* ... */\n") + f.write("/* IDREG_FIELD_END(REG, FIELD) */\n") f.write("/* IDREG_END(REG) */\n\n") f.write(final_output) =20 --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) 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s=mimecast20190719; t=1781616463; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DWqDgY6YptJE+OeZiINF/nTpYHVswL+HXXlWl6zC+ZM=; b=duEaGQ7skqySfE8TK8WbSgWscxsX9AGqNWhObaH3wDmDv1z+KtwZZmK2o6WfUDKTt/q20B gn8305i6WMoolA4ZkXpJtSf9rhEP1yKqWkmY70Mn5EoCBRdPw0OGrb8l4z8DJE4TIMILEt aGiGrKGjL8oK+G/Z3XP7npNbSl88l3E= X-MC-Unique: D9dqYA-wNueUcUxByP4iTQ-1 X-Mimecast-MFC-AGG-ID: D9dqYA-wNueUcUxByP4iTQ_1781616458 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 09/17] target/arm/cpu_idregs: generate tables for Arm64 ID registers and fields Date: Tue, 16 Jun 2026 15:16:56 +0200 Message-ID: <20260616132625.1732031-10-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1781616584569158500 Content-Type: text/plain; charset="utf-8" From: Shaju Abraham Include cpu-idregs.h.inc multiple times with different definitions for the X-macros. This will generate tables for all Arm64 ID registers and their fields. Additionally, initialize the tables with all architecturally defined values. These tables will be consumed by the property layer in future patches. Co-authored-by: Khushit Shah Signed-off-by: Shaju Abraham Signed-off-by: Eric Auger --- v5 -> v6 - restored support of enum values --- target/arm/cpu-idregs.c | 96 +++++++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 1 + 2 files changed, 97 insertions(+) create mode 100644 target/arm/cpu-idregs.c diff --git a/target/arm/cpu-idregs.c b/target/arm/cpu-idregs.c new file mode 100644 index 0000000000..c41d0ab0c4 --- /dev/null +++ b/target/arm/cpu-idregs.c @@ -0,0 +1,96 @@ +/* + * ARM ID register field table. + * + * Builds the per-id-register field descriptor arrays and the global + * arm_idregs[] table. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "cpu.h" +#include "cpu-idregs.h" + +/* + * Generate an array of architecturely defined values for each field + * associated with enum values + */ + +#define IDREG_START(reg) +#define IDREG_END(reg) +#define IDREG_FIELD(reg, field, shift, length) +#define IDREG_FIELD_START(reg, field, shift, length) \ + static const ArmIdRegArchVal reg##_##field##_arch_vals[] =3D { +#define IDREG_FIELD_ARCH_VAL(v) { (v), "" }, +#define IDREG_FIELD_END(reg, field) \ + }; + +#include "cpu-idregs.h.inc" + +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD +#undef IDREG_FIELD_START +#undef IDREG_FIELD_END +#undef IDREG_FIELD_ARCH_VAL + +/* generate an array of per-register ArmIdRegField[] descriptors */ + +#define IDREG_START(reg) \ + static ARM64SysRegField reg##_fields[] =3D { + +#define IDREG_END(reg) \ + }; + +#define IDREG_FIELD_START(reg, field, _shift, _length) \ + { \ + .name =3D #field, \ + .index =3D reg##_IDX, \ + .shift =3D (_shift), \ + .length =3D (_length), \ + .arch_vals =3D (ArmIdRegArchVal *)reg##_##field##_arch_vals, \ + .arch_vals_count =3D ARRAY_SIZE(reg##_##field##_arch_vals), \ + }, + +#define IDREG_FIELD(reg, field, _shift, _length) \ + { \ + .name =3D #field, \ + .index =3D reg##_IDX, \ + .shift =3D (_shift), \ + .length =3D (_length), \ + }, + +#define IDREG_FIELD_ARCH_VAL(v) + +#define IDREG_FIELD_END(reg, field) + +#include "cpu-idregs.h.inc" + +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD +#undef IDREG_FIELD_START +#undef IDREG_FIELD_END +#undef IDREG_FIELD_ARCH_VAL + +/* generate an array of top level ID registers */ + +#define IDREG_END(reg) +#define IDREG_FIELD(reg, field, shift, length) +#define IDREG_FIELD_START(reg, field, shift, length) +#define IDREG_FIELD_ARCH_VAL(v) +#define IDREG_FIELD_END(reg, field) + +#define IDREG_START(reg) \ + [reg##_IDX] =3D { \ + .name =3D #reg, \ + .index =3D reg##_IDX, \ + .fields =3D reg##_fields, \ + .fields_count =3D ARRAY_SIZE(reg##_fields), \ + }, + +ARM64SysReg arm64_id_regs[NUM_ID_IDX] =3D { +#include "cpu-idregs.h.inc" +}; + diff --git a/target/arm/meson.build b/target/arm/meson.build index 4412fde065..ed8535192c 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -30,6 +30,7 @@ arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_= true: files( =20 arm_common_system_ss.add(files( 'arm-qmp-cmds.c', + 'cpu-idregs.c', )) arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm= .c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1781616501; cv=none; d=zohomail.com; s=zohoarc; b=XQgvGfe6TXrXM7e7QE7VYnxv/SN+4duiHrM1F7G0mTgvfuhQoTwTX6/R0tjFaEWicVELvANFb2Vx2gK8xjpdTDEGsysRZ7G0fL0M4M4idR7Glt2/suw1kzUBOUZpc4JeScihByPc1xH/gbq8YWW4VfRRKZxV2Rz5BwbeRe64b7A= ARC-Message-Signature: i=1; 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Tue, 16 Jun 2026 13:27:44 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.48.30]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id BC2353008B3B; Tue, 16 Jun 2026 13:27:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616471; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qySDmpGubd1jDBl8VeG5Y8I9gHIq9QwIiLHxNZ7iLZI=; b=jDIv023kWjHT6kPFDGxL2tBiQNH0UPm0jrN8LBFKtgLxZhgPUOZRYOFmJqkdToNFBcWmjj CraXypg91PNMP+NIFYCOiSC0ZZFdVZvBJvW2rD6PfMaIF4YyiCnakMetTJyIRBI3tEg8w5 wSf54+x8G5z5/KjtVWzuXXY0nDfKkxo= X-MC-Unique: C5W2-Wa8NoS7vpCoZazcbQ-1 X-Mimecast-MFC-AGG-ID: C5W2-Wa8NoS7vpCoZazcbQ_1781616464 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 10/17] target/arm/kvm: Retrieve writable ID reg map Date: Tue, 16 Jun 2026 15:16:57 +0200 Message-ID: <20260616132625.1732031-11-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Cornelia Huck Add an helper to retrieve the writable id reg bitmask. then retrieve the writable_map array and dispatch it in the writable_map fields of arm64_id_regs[] elements. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v5 -> v6 - use arm64_id_regs[].writable_map - squashed 2 commits (helper + user) - removed stub --- target/arm/kvm.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index a54ef51ec2..6f91407d41 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -28,6 +28,7 @@ #include "kvm_arm.h" #include "cpu.h" #include "cpu-sysregs.h" +#include "cpu-idregs.h" #include "trace.h" #include "internals.h" #include "hw/pci/pci.h" @@ -51,6 +52,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = =3D { static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; static bool cap_has_inject_ext_dabt; +static bool writable_map_dispatched; =20 /** * ARMHostCPUFeatures: information about the host CPU (identified @@ -273,6 +275,21 @@ static uint32_t kvm_arm_sve_get_vls(int fd) return vls[0] & MAKE_64BIT_MASK(0, ARM_MAX_VQ); } =20 +static int kvm_feature_idx_to_idregs_idx(int kidx) +{ + int op1, crm, op2; + ARMSysRegs sysreg; + + op1 =3D kidx / 64; + if (op1 =3D=3D 2) { + op1 =3D 3; + } + crm =3D (kidx % 64) / 8; + op2 =3D kidx % 8; + sysreg =3D ENCODE_ID_REG(3, op1, 0, crm, op2); + return get_sysreg_idx(sysreg); +} + static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -480,9 +497,53 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) ahcf->features =3D features; } =20 +static int kvm_arm_get_writable_id_regs(uint64_t *idregmap) +{ + int cap_writable_id_regs; + struct reg_mask_range range =3D { + .range =3D KVM_ARM_FEATURE_ID_RANGE, + .reserved =3D {0}, + .addr =3D (uint64_t)idregmap, + }; + + cap_writable_id_regs =3D + kvm_check_extension(kvm_state, KVM_CAP_ARM_SUPPORTED_REG_MASK_RANG= ES); + + if (!cap_writable_id_regs || + !(cap_writable_id_regs & (1 << KVM_ARM_FEATURE_ID_RANGE))) { + return -ENOSYS; + } + + if (kvm_vm_ioctl(kvm_state, KVM_ARM_GET_REG_WRITABLE_MASKS, &range)) { + return -errno; + } + return 0; +} + void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; + uint64_t *writable_map; + + writable_map =3D g_new(uint64_t, KVM_ARM_FEATURE_ID_RANGE_SIZE); + + if (!writable_map_dispatched && + !kvm_arm_get_writable_id_regs(writable_map)) { + for (int i =3D 0; i < KVM_ARM_FEATURE_ID_RANGE_SIZE; i++) { + uint64_t mask =3D writable_map[i]; + + if (mask) { + int idx =3D kvm_feature_idx_to_idregs_idx(i); + + if (idx < 0 || idx > ARRAY_SIZE(arm64_id_regs)) { + continue; + } + arm64_id_regs[idx].writable_mask =3D mask; + } + } + writable_map_dispatched =3D true; + } + g_free(writable_map); =20 if (!arm_host_cpu_features.dtb_compatible) { kvm_arm_get_host_cpu_features(&arm_host_cpu_features); --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=V3k13HWLBzqhn8oKd5ium3yTmyAAkAbwd6yjy5cp3nU+vKQ0l6wCVoZStVsAuFfM8bZWM3 jGaEKGkSlKCXXpZt/GE8CDJ5MTzcuH5QdU7XnVbdSHvDNN11YNHQnlrm4HQMwBc1gouPr9 1seFzUL8f4Nzkd7gx5EgQNuTdxAo8ng= X-MC-Unique: VTTFumi0NguQ0GwZwXKeXw-1 X-Mimecast-MFC-AGG-ID: VTTFumi0NguQ0GwZwXKeXw_1781616471 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 11/17] arm/kvm: Initialize all writable ID registers from host Date: Tue, 16 Jun 2026 15:16:58 +0200 Message-ID: <20260616132625.1732031-12-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1781616514041158500 Content-Type: text/plain; charset="utf-8" We want to allow overwriting writable fields of some ID registers. However currently some of them are never touched, neither read nor w. Examples are CLIDR_EL1, CTR_EL0, REVIDR_EL1, MIDR_EL1. We want to initialize them from the host value, allow overwrite and write back for kvm afterwards. This patch implements the initialization. Introduce a new get_host_cpu_idregs() helper that gets the host values for all writable ID regs and store them in isar.idregs[]. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v5 -> v6 - do not check writable_map anymore --- target/arm/kvm.c | 98 +++++++++++++++++++++++++++++++++++++++-- target/arm/trace-events | 2 + 2 files changed, 97 insertions(+), 3 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 6f91407d41..71a214f228 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -43,6 +43,7 @@ #include "hw/acpi/ghes.h" #include "target/arm/gtimer.h" #include "migration/blocker.h" +#include "cpu-idregs.h" =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_INFO(DEVICE_CTRL), @@ -290,7 +291,44 @@ static int kvm_feature_idx_to_idregs_idx(int kidx) return get_sysreg_idx(sysreg); } =20 -static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +/* + * get_host_cpu_idregs: Read all the writable ID reg host values + * + * Need to be called once the writable mask has been populated + * Note we may want to read all the known id regs but some of them are not + * writable and return an error, hence the choice of reading only those wh= ich + * are writable. Those are also readable! + */ +static int get_host_cpu_idregs(ARMCPU *cpu, int fd, ARMHostCPUFeatures *ah= cf) +{ + int err =3D 0; + int i; + + for (i =3D 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc =3D &arm64_id_regs[i]; + ARMSysRegs sysreg =3D id_register_sysreg[i]; + uint64_t *reg; + int ret; + + if (!sysregdesc->writable_mask) { + continue; + } + + reg =3D &ahcf->isar.idregs[i]; + ret =3D read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg)); + trace_get_host_cpu_idregs(sysregdesc->name, *reg); + if (ret) { + error_report("%s error reading value of host %s register (%m)", + __func__, sysregdesc->name); + + err =3D ret; + } + } + return err; +} + +static void +kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -376,6 +414,16 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64= only */ err =3D 0; } else { + /* Make sure all writable ID reg values are initialized */ + err |=3D get_host_cpu_idregs(cpu, fd, ahcf); + + /* + * temporarily override the CLIDR_EL1 value since some host values + * trigger "Unified type is not implemented at level n" error in + * fdt_add_cpu_nodes() + */ + SET_IDREG(&ahcf->isar, CLIDR, 0x0); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR2_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); @@ -546,7 +594,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) g_free(writable_map); =20 if (!arm_host_cpu_features.dtb_compatible) { - kvm_arm_get_host_cpu_features(&arm_host_cpu_features); + kvm_arm_get_host_cpu_features(cpu, &arm_host_cpu_features); } =20 cpu->kvm_target =3D arm_host_cpu_features.target; @@ -1161,6 +1209,34 @@ bool kvm_arm_cpu_post_load(ARMCPU *cpu) return true; } =20 +/* + * Copy writable ID regs from isar.idregs[] to cpreg_list + * in case their value differs from the original init cpreg value + */ +static void kvm_arm_writable_idregs_to_cpreg_list(ARMCPU *cpu) +{ + for (int i =3D 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc =3D &arm64_id_regs[i]; + ARMSysRegs sysreg =3D id_register_sysreg[i]; + uint64_t previous, new; + uint64_t *cpreg; + + if (!sysregdesc->writable_mask) { + continue; + } + + cpreg =3D kvm_arm_get_cpreg_ptr(cpu, idregs_sysreg_to_kvm_reg(sysr= eg)); + previous =3D *cpreg; + new =3D cpu->isar.idregs[i]; + + if (previous !=3D new) { + *cpreg =3D new; + trace_kvm_arm_writable_idregs_to_cpreg_list(sysregdesc->name, + previous, new); + } + } +} + void kvm_arm_reset_vcpu(ARMCPU *cpu) { int ret; @@ -2113,7 +2189,23 @@ int kvm_arch_init_vcpu(CPUState *cs) } cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 - return kvm_arm_init_cpreg_list(cpu); + ret =3D kvm_arm_init_cpreg_list(cpu); + if (ret) { + return ret; + } + /* overwrite writable ID regs with their updated property values */ + kvm_arm_writable_idregs_to_cpreg_list(cpu); + ret =3D write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE); + if (!ret) { + return -1; + } + /* + * modified values may have changed the visibility of some regs, + * reinitialize the cpreg_list accordingly + */ + ret =3D kvm_arm_init_cpreg_list(cpu); + + return ret; } =20 int kvm_arch_destroy_vcpu(CPUState *cs) diff --git a/target/arm/trace-events b/target/arm/trace-events index 8502fb3265..c25d2a1191 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -13,6 +13,8 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" =20 # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 +get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 +kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous,= uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616484; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Gh68cijheTqVFJPOiChbFylAMbtUDn2JoOSaWYjZSOQ=; b=b0viYKtbls/1i4JIkUFm+IuxAIjikWIKKdX1QRq6tQMNaKpmjP8/2MOguUbBOf/SsYLNjf 7J3xaS7e6+LmQiHH5ablTUOjRAK+3guldfsAHBHUpWVdX4iSHeq+Pg0//f3128PpfIX6/e d1spR2+2e5ew4khXtVx1ZUvHVbbwFQ0= X-MC-Unique: abO3NdMiMoKhYV8Ao9a1PA-1 X-Mimecast-MFC-AGG-ID: abO3NdMiMoKhYV8Ao9a1PA_1781616478 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 12/17] target/arm/kvm: Introduce kvm_arm_expose_idreg_properties Date: Tue, 16 Jun 2026 15:16:59 +0200 Message-ID: <20260616132625.1732031-13-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1781616512056158500 Content-Type: text/plain; charset="utf-8" This helper decode the ID reg writable mask, matches it against ID reg fields defined in target/arm/cpu-idregs.h.inc and for each writable named field, generates a uint64 property. REVIDR_EL1 and AIDR_EL1 are writable but they do not expose any field. They will be handled separately. Signed-off-by: Eric Auger --- v5 -> v6 - for enum values, check against value value when setting the prop - do not check writable_map flag anymore v4 -> v5: - free prop_name - check cpu->writable_map as a preamble in kvm_arm_expose_idreg_properties --- target/arm/kvm_arm.h | 10 +++ target/arm/kvm.c | 144 ++++++++++++++++++++++++++++++++++++++++ target/arm/trace-events | 4 ++ 3 files changed, 158 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e7c40fb003..2b3474cc36 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -142,6 +142,16 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); */ void kvm_arm_add_vcpu_properties(ARMCPU *cpu); =20 +typedef struct ARM64SysReg ARM64SysReg; +/** + * kvm_arm_expose_idreg_properties: + * @cpu: The CPU object to generate the properties for + * @reg: registers from the host + * + * analyze the writable mask and generate properties for writable fields + */ +void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM64SysReg *regs); + /** * kvm_arm_steal_time_finalize: * @cpu: ARMCPU for which to finalize kvm-steal-time diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 71a214f228..54392f3077 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -327,6 +327,150 @@ static int get_host_cpu_idregs(ARMCPU *cpu, int fd, A= RMHostCPUFeatures *ahcf) return err; } =20 +static ARM64SysRegField *get_field(int i, ARM64SysReg *reg) +{ + for (int f =3D 0; f < reg->fields_count; f++) { + struct ARM64SysRegField *field =3D ®->fields[f]; + int upper =3D field->shift + field->length - 1; + + if (i >=3D field->shift && i <=3D upper) { + return field; + } + } + return NULL; +} + +static void set_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t *idregs =3D cpu->isar.idregs; + uint64_t old, value, mask; + int lower =3D field->shift; + int length =3D field->length; + int index =3D field->index; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (length < 64 && value > ((1 << length) - 1)) { + error_setg(errp, + "idreg %s set value (0x%lx) exceeds length of field (%d= )!", + name, value, length); + return; + } + + if (field->arch_vals) { + /* this field has some enum values */ + for (int i =3D 0; i < field->arch_vals_count; i++) { + if (value =3D=3D field->arch_vals[i].value) { + goto valid; + } + } + error_setg(errp, + "idreg %s set value (0x%lx) does not match any " + "arch valid enum value!", name, value); + return; + } + +valid: + + mask =3D MAKE_64BIT_MASK(lower, length); + value =3D value << lower; + old =3D idregs[index]; + idregs[index] =3D old & ~mask; + idregs[index] |=3D value; + trace_set_sysreg_prop(name, old, mask, value, idregs[index]); +} + +static void get_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t *idregs =3D cpu->isar.idregs; + uint64_t value, mask; + int lower =3D field->shift; + int length =3D field->length; + int index =3D field->index; + + mask =3D MAKE_64BIT_MASK(lower, length); + value =3D (idregs[index] & mask) >> lower; + visit_type_uint64(v, name, &value, errp); + trace_get_sysreg_prop(name, value); +} + +/* + * decode_idreg_writemap: Generate props for writable fields + * + * @obj: CPU object + * @reg: description of the sysreg + */ +static int +decode_idreg_writemap(Object *obj, ARM64SysReg *reg) +{ + uint64_t map =3D reg->writable_mask; + int i =3D ctz64(map); + int nb_sysreg_props =3D 0; + + while (map) { + ARM64SysRegField *field =3D get_field(i, reg); + int lower, upper; + char *prop_name; + uint64_t field_mask; + + if (!field) { + warn_report("%s bit %d of %s is writable but no named field " + "in target/arm/cpu-idregs.h.inc", + __func__, i, reg->name); + warn_report("%s is target/arm/cpu-idregs.h.inc up-to-date?", _= _func__); + map =3D map & ~BIT_ULL(i); + i =3D ctz64(map); + continue; + } + lower =3D field->shift; + upper =3D field->shift + field->length - 1; + prop_name =3D g_strdup_printf("SYSREG_%s_%s", reg->name, field->na= me); + trace_decode_idreg_writemap(field->name, lower, upper, prop_name); + object_property_add(obj, prop_name, "uint64", + get_sysreg_prop, set_sysreg_prop, NULL, field); + g_free(prop_name); + nb_sysreg_props++; + + field_mask =3D MAKE_64BIT_MASK(lower, field->length); + map =3D map & ~field_mask; + i =3D ctz64(map); + } + trace_nb_sysreg_props(reg->name, nb_sysreg_props); + return 0; +} + +/* analyze the writable mask and generate properties for writable fields */ +void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM64SysReg *regs) +{ + Object *obj =3D OBJECT(cpu); + + for (int i =3D 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc =3D ®s[i]; + + if (sysregdesc->writable_mask) { + /* + * special case REVIDR_EL1 and AIDR_EL1 which are writable but + * do not expose named fields. They will need to be handled + * separately + */ + if (strcmp(sysregdesc->name, "REVIDR_EL1") && + strcmp(sysregdesc->name, "AIDR_EL1")) { + decode_idreg_writemap(obj, sysregdesc); + } + } + } +} + static void kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf) { diff --git a/target/arm/trace-events b/target/arm/trace-events index c25d2a1191..d72ad6b671 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -15,6 +15,10 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_ir= q: timer %d irqstate %d" kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous,= uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 +decode_idreg_writemap(const char* name, int lower, int upper, char *prop_n= ame) "%s [%d:%d] is writable (prop %s)" +get_sysreg_prop(const char *name, uint64_t value) "%s 0x%"PRIx64 +set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t fi= eld_value, uint64_t new) "%s old reg value=3D0x%"PRIx64" mask=3D0x%"PRIx64"= new field value=3D0x%"PRIx64" new reg value=3D0x%"PRIx64 +nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616490; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aAUvyW8XM/MoP2Fagjs5c0VuePcOU0ts+uJ4JlRpEoU=; b=cQmZXEpz57khhu74KRs1zldEKmlZoxBwRYAApJHe/oq/5SqgYrnRu6MVfymjJjroQC03zY 7YM9+ybArCoWx4oXwD2yCvrj+jVwwtdet/SphOd+Dz5pgngNQhV+xE5nXJ01JzdrngsKU3 mlQhBaYltGKl0jzeND2GHXxg/8oIIsQ= X-MC-Unique: sBaWpOSdOHGsoELbp3UDpw-1 X-Mimecast-MFC-AGG-ID: sBaWpOSdOHGsoELbp3UDpw_1781616485 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 13/17] target/arm/cpu: Expose writable ID reg field properties on the kvm host vcpu model Date: Tue, 16 Jun 2026 15:17:00 +0200 Message-ID: <20260616132625.1732031-14-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" If the host supports KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES and KVM_ARM_GET_REG_WRITABLE_MASKS ioctl successfully retrieved the mask of writable fields for all ID regs, expose uint64 SYSREG properties for all the writable ID reg fields exposed by the host kernel which can be matched in target/arm/cpu-idregs.h.inc. Properties are named SYSREG__ with REG and FIELD being those used ARCHMRS Registers.json. When such properties are set, they override the default field value retrieved from the host and reinjected into KVM. Then the actual value being applied at KVM depends on the register, ie. it can be sanitized. In case the field value is rejected by KVM, the vpcu init fails. Anyway there is a first attempt to write back this value into KVM. Then legacy CPU options (virtualization, secure, ...) can still override the previous value. So low level IDREG field properties apply before the legacy ones. An example of invocation is: -cpu host,SYSREG_ID_AA64MMFR0_EL1_ECV=3D0x0 which sets ECV field of ID_AA64MMFR0_EL1 to 0 (enhanced counter virtualization). Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott --- v5 -> v6: - do not check writable_map anymore v4 -> v5: - get rid of ret local variable, dynamically allocate and free writable_map here --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2816735577..d5d02515df 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -37,6 +37,7 @@ #include "hw/core/qdev-properties.h" #include "internals.h" #include "cpu-features.h" +#include "cpu-idregs.h" =20 /* convert between _IDX and SYS_ */ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ @@ -806,6 +807,10 @@ void aarch64_host_initfn(Object *obj) kvm_arm_set_cpreg_mig_tolerances(cpu); kvm_arm_set_cpu_features_from_host(cpu); aarch64_add_sve_properties(obj); + + /* generate SYSREG properties according to writable masks */ + kvm_arm_expose_idreg_properties(cpu, arm64_id_regs); + #elif defined(CONFIG_HVF) hvf_arm_set_cpu_features_from_host(cpu); #elif defined(CONFIG_WHPX) --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1781616525; cv=none; d=zohomail.com; s=zohoarc; b=PKaXIbWv/mfliEHChb0C/OFCZRKW8U4T+1/ImQ6Yj028vafKiBbDY5lHt2bRwJSTlphaYoVz3O7Mz+GZm6KocLlpIVgqOLhIY8nlYGfFNi6OWuRnu6v6Cz9TwaajqRaC69W/gLm3/ZiSChOFa4EqJ5zPF1VOSvc/XHWPdj3bIjg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781616525; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=m+A/vxmsYMKabhk+ehh5QLIxfuqjhwoqhOGg2BRC+lg=; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616497; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m+A/vxmsYMKabhk+ehh5QLIxfuqjhwoqhOGg2BRC+lg=; b=itOUUuJgtc923kU4bKDs+pPJEjc6fslt7oVIMefHOM0/XnAHahPCZ8cf2bMufia3qaGjwo 7rStOwYaht/5/5IVTZhCvBIzvklmwi5QR592gCDy57to7keApYKGdFNJsMDcN+pvQZTOcY Ls25XroU02O9PiPXnJ1X69xd/xQ+F7U= X-MC-Unique: E4Wf4MNxOuiusikl6tK3Kg-1 X-Mimecast-MFC-AGG-ID: E4Wf4MNxOuiusikl6tK3Kg_1781616491 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 14/17] arm-qmp-cmds: introspection for ID register props Date: Tue, 16 Jun 2026 15:17:01 +0200 Message-ID: <20260616132625.1732031-15-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1781616528053158500 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Implement the capability to query available ID register values by adding SYSREG_* options and values to the cpu model expansion for the host model, if available. Excerpt: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} {"return": {"model": {"name": "host", "props": {"SYSREG_ID_AA64PFR0_EL1_EL3= ": 1, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, "SYSREG_CTR_EL0_L1Ip": 3, "SYSREG_MIDR_EL1_PartNum": 3407, "SYSREG_CTR_EL0_DminLine": 4, "SYSREG_ID_AA64MMFR0_EL1_PARange": 5, "SYSREG_ID_AA64MMFR1_EL1_ECBHB": 0 ../.. So this allows the upper stack to detect available writable ID regs and the "host passthrough model" values. It also allows to test some ID reg field values: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host","props"= :{"SYSREG_ID_AA64ISAR0_EL1_DP":0x13}} {"error": {"class": "GenericError", "desc": "idreg SYSREG_ID_AA64ISAR0_EL1_= DP set value (0x13) exceeds length of field (4)!"}} (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host","props"= :{"SYSREG_ID_AA64ISAR0_EL1_DP":0x2}} {"error": {"class": "GenericError", "desc": "idreg SYSREG_ID_AA64ISAR0_EL1_= DP set value (0x2) does not match any arch valid enum value!"}} Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v5 -> v6: - add the write capability --- target/arm/arm-qmp-cmds.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 83ec95c290..edcfc82a25 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -21,6 +21,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/target-info.h" #include "hw/core/boards.h" #include "kvm_arm.h" @@ -84,6 +85,8 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuM= odelExpansionType type, Error **errp) { CpuModelExpansionInfo *expansion_info; + ObjectPropertyIterator iter; + ObjectProperty *idregprop; const QDict *qdict_in; QDict *qdict_out; ObjectClass *oc; @@ -145,6 +148,20 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, } =20 qdict_in =3D qobject_to(QDict, model->props); + + object_property_iter_init(&iter, obj); + + while ((idregprop =3D object_property_iter_next(&iter))) { + if (!g_str_has_prefix(idregprop->name, "SYSREG_")) { + continue; + } + if (qdict_get(qdict_in, idregprop->name)) { + if (!object_property_set(obj, idregprop->name, visitor, &e= rr)) { + break; + } + } + } + i =3D 0; while ((name =3D cpu_model_advertised_features[i++]) !=3D NULL) { if (qdict_get(qdict_in, name)) { @@ -190,6 +207,18 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, } } =20 + object_property_iter_init(&iter, obj); + + while ((idregprop =3D object_property_iter_next(&iter))) { + QObject *value; + + if (!g_str_has_prefix(idregprop->name, "SYSREG_")) { + continue; + } + value =3D object_property_get_qobject(obj, idregprop->name, &error= _abort); + qdict_put_obj(qdict_out, idregprop->name, value); + } + if (!qdict_size(qdict_out)) { qobject_unref(qdict_out); } else { --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1781616548; cv=none; d=zohomail.com; s=zohoarc; b=VZG2pbwTOYRASo1lNi/dFOhhsrKtVqddDjTAuqb8AgYXcAOVY5ntdYh+UkILl3wURXRwUQzU4b1bI/8dIUWCf6hb775odYjXJcj8z2K2Vnntt3hGjAOK10NYFt6HKjbTaIyA949JBXlzPCorQ54xYIxJATf48nacu1AEyMzH6QE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781616548; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 16 Jun 2026 13:28:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616504; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0kG+75f11rlVDCq0jFrsgDaYRGqvIM4/OjycDQgMeu4=; b=g3dZpJ1u7c1vA8481B1B7DMFHNFCjsgTIsODZnnkh51GKRUrUrYFWBVaII98G5rcTjYFX+ haqjKYYVdvwEB0E76gGLyGjzVco2wSsz07iR1iyi9j9QUUMCletuyYur1IUgTgTEmPtzNo lzywIxQHDG9U2dC0aKsnj6mv1pScQvQ= X-MC-Unique: 8_vXgqm2OUmnUOa8koyb2Q-1 X-Mimecast-MFC-AGG-ID: 8_vXgqm2OUmnUOa8koyb2Q_1781616498 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 15/17] target/arm/cpu-idregs.h.inc: Generate reserved fields Date: Tue, 16 Jun 2026 15:17:02 +0200 Message-ID: <20260616132625.1732031-16-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Extract reserved fields: RES0, RES1, RAZ, ... Signed-off-by: Eric Auger --- target/arm/cpu-idregs.h.inc | 69 ++++++++++++++- .../update-aarch64-cpu-sysreg-properties.py | 83 +++++++++++++++---- 2 files changed, 136 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu-idregs.h.inc b/target/arm/cpu-idregs.h.inc index 1c8b26133b..5fdc84237c 100644 --- a/target/arm/cpu-idregs.h.inc +++ b/target/arm/cpu-idregs.h.inc @@ -15,16 +15,20 @@ IDREG_START(AIDR_EL1) IDREG_END(AIDR_EL1) =20 IDREG_START(CCSIDR2_EL1) + IDREG_FIELD(CCSIDR2_EL1, RES0, 24, 40) IDREG_FIELD(CCSIDR2_EL1, NumSets, 0, 24) IDREG_END(CCSIDR2_EL1) =20 IDREG_START(CCSIDR_EL1) + IDREG_FIELD(CCSIDR_EL1, RES0, 56, 8) IDREG_FIELD(CCSIDR_EL1, NumSets, 32, 24) + IDREG_FIELD(CCSIDR_EL1, RES0, 24, 8) IDREG_FIELD(CCSIDR_EL1, Associativity, 3, 21) IDREG_FIELD(CCSIDR_EL1, LineSize, 0, 3) IDREG_END(CCSIDR_EL1) =20 IDREG_START(CLIDR_EL1) + IDREG_FIELD(CLIDR_EL1, RES0, 47, 17) IDREG_FIELD(CLIDR_EL1, Ttype7, 45, 2) IDREG_FIELD(CLIDR_EL1, Ttype6, 43, 2) IDREG_FIELD(CLIDR_EL1, Ttype5, 41, 2) @@ -55,7 +59,10 @@ IDREG_START(CLIDR_EL1) IDREG_END(CLIDR_EL1) =20 IDREG_START(CTR_EL0) + IDREG_FIELD(CTR_EL0, RES0, 38, 26) IDREG_FIELD(CTR_EL0, TminLine, 32, 6) + IDREG_FIELD(CTR_EL0, RES1, 31, 1) + IDREG_FIELD(CTR_EL0, RES0, 30, 1) IDREG_FIELD_START(CTR_EL0, DIC, 29, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -73,23 +80,28 @@ IDREG_START(CTR_EL0) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_ARCH_VAL(3) IDREG_FIELD_END(CTR_EL0, L1Ip) + IDREG_FIELD(CTR_EL0, RES0, 4, 10) IDREG_FIELD(CTR_EL0, IminLine, 0, 4) IDREG_END(CTR_EL0) =20 IDREG_START(DCZID_EL0) + IDREG_FIELD(DCZID_EL0, RES0, 9, 55) IDREG_FIELD(DCZID_EL0, TBS, 5, 4) IDREG_FIELD(DCZID_EL0, DZP, 4, 1) IDREG_FIELD(DCZID_EL0, BS, 0, 4) IDREG_END(DCZID_EL0) =20 IDREG_START(GMID_EL1) + IDREG_FIELD(GMID_EL1, RES0, 4, 60) IDREG_FIELD(GMID_EL1, BS, 0, 4) IDREG_END(GMID_EL1) =20 IDREG_START(ID_AA64AFR0_EL1) + IDREG_FIELD(ID_AA64AFR0_EL1, RES0, 32, 32) IDREG_END(ID_AA64AFR0_EL1) =20 IDREG_START(ID_AA64AFR1_EL1) + IDREG_FIELD(ID_AA64AFR1_EL1, RES0, 0, 64) IDREG_END(ID_AA64AFR1_EL1) =20 IDREG_START(ID_AA64DFR0_EL1) @@ -136,6 +148,7 @@ IDREG_START(ID_AA64DFR0_EL1) IDREG_FIELD_START(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4) IDREG_FIELD_ARCH_VAL(15) IDREG_FIELD_END(ID_AA64DFR0_EL1, CTX_CMPs) + IDREG_FIELD(ID_AA64DFR0_EL1, RES0, 24, 4) IDREG_FIELD(ID_AA64DFR0_EL1, WRPs, 20, 4) IDREG_FIELD_START(ID_AA64DFR0_EL1, PMSS, 16, 4) IDREG_FIELD_ARCH_VAL(0) @@ -209,6 +222,7 @@ IDREG_START(ID_AA64DFR1_EL1) IDREG_END(ID_AA64DFR1_EL1) =20 IDREG_START(ID_AA64DFR2_EL1) + IDREG_FIELD(ID_AA64DFR2_EL1, RES0, 28, 36) IDREG_FIELD_START(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -221,6 +235,7 @@ IDREG_START(ID_AA64DFR2_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64DFR2_EL1, SPE_EXC) + IDREG_FIELD(ID_AA64DFR2_EL1, RES0, 8, 8) IDREG_FIELD_START(ID_AA64DFR2_EL1, BWE, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -233,6 +248,7 @@ IDREG_START(ID_AA64DFR2_EL1) IDREG_END(ID_AA64DFR2_EL1) =20 IDREG_START(ID_AA64FPFR0_EL1) + IDREG_FIELD(ID_AA64FPFR0_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8CVT, 31, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -257,10 +273,13 @@ IDREG_START(ID_AA64FPFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64FPFR0_EL1, F8MM4) + IDREG_FIELD(ID_AA64FPFR0_EL1, RES0, 16, 10) IDREG_FIELD_START(ID_AA64FPFR0_EL1, F16MM2, 15, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64FPFR0_EL1, F16MM2) + IDREG_FIELD(ID_AA64FPFR0_EL1, RES0, 8, 7) + IDREG_FIELD(ID_AA64FPFR0_EL1, RAZ, 2, 6) IDREG_FIELD_START(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -312,6 +331,7 @@ IDREG_START(ID_AA64ISAR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64ISAR0_EL1, RDM) + IDREG_FIELD(ID_AA64ISAR0_EL1, RES0, 24, 4) IDREG_FIELD_START(ID_AA64ISAR0_EL1, Atomic, 20, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(2) @@ -335,6 +355,7 @@ IDREG_START(ID_AA64ISAR0_EL1) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_END(ID_AA64ISAR0_EL1, AES) + IDREG_FIELD(ID_AA64ISAR0_EL1, RES0, 0, 4) IDREG_END(ID_AA64ISAR0_EL1) =20 IDREG_START(ID_AA64ISAR1_EL1) @@ -498,6 +519,7 @@ IDREG_START(ID_AA64ISAR2_EL1) IDREG_END(ID_AA64ISAR2_EL1) =20 IDREG_START(ID_AA64ISAR3_EL1) + IDREG_FIELD(ID_AA64ISAR3_EL1, RES0, 48, 16) IDREG_FIELD_START(ID_AA64ISAR3_EL1, LSCP, 44, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -561,6 +583,7 @@ IDREG_START(ID_AA64MMFR0_EL1) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_END(ID_AA64MMFR0_EL1, FGT) + IDREG_FIELD(ID_AA64MMFR0_EL1, RES0, 48, 8) IDREG_FIELD_START(ID_AA64MMFR0_EL1, ExS, 44, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -713,6 +736,7 @@ IDREG_START(ID_AA64MMFR2_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64MMFR2_EL1, TTL) + IDREG_FIELD(ID_AA64MMFR2_EL1, RES0, 44, 4) IDREG_FIELD_START(ID_AA64MMFR2_EL1, FWB, 40, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -778,6 +802,7 @@ IDREG_START(ID_AA64MMFR3_EL1) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_ARCH_VAL(3) IDREG_FIELD_END(ID_AA64MMFR3_EL1, SDERR) + IDREG_FIELD(ID_AA64MMFR3_EL1, RES0, 48, 4) IDREG_FIELD_START(ID_AA64MMFR3_EL1, ANERR, 44, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1031,6 +1056,7 @@ IDREG_START(ID_AA64PFR1_EL1) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_END(ID_AA64PFR1_EL1, SME) + IDREG_FIELD(ID_AA64PFR1_EL1, RES0, 20, 4) IDREG_FIELD_START(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1058,6 +1084,7 @@ IDREG_START(ID_AA64PFR1_EL1) IDREG_END(ID_AA64PFR1_EL1) =20 IDREG_START(ID_AA64PFR2_EL1) + IDREG_FIELD(ID_AA64PFR2_EL1, RES0, 48, 16) IDREG_FIELD_START(ID_AA64PFR2_EL1, VMTETCL, 44, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1117,6 +1144,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64SMFR0_EL1, FA64) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 62, 1) IDREG_FIELD_START(ID_AA64SMFR0_EL1, LUT6, 61, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1136,6 +1164,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(15) IDREG_FIELD_END(ID_AA64SMFR0_EL1, I16I64) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 49, 3) IDREG_FIELD_START(ID_AA64SMFR0_EL1, F64F64, 48, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1180,6 +1209,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64SMFR0_EL1, F32F32) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 31, 1) IDREG_FIELD_START(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1192,6 +1222,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64SMFR0_EL1, SF8DP2) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 26, 2) IDREG_FIELD_START(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1204,10 +1235,12 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64SMFR0_EL1, SFEXPA) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 17, 6) IDREG_FIELD_START(ID_AA64SMFR0_EL1, STMOP, 16, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64SMFR0_EL1, STMOP) + IDREG_FIELD(ID_AA64SMFR0_EL1, RES0, 1, 15) IDREG_FIELD_START(ID_AA64SMFR0_EL1, SMOP4, 0, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1215,6 +1248,7 @@ IDREG_START(ID_AA64SMFR0_EL1) IDREG_END(ID_AA64SMFR0_EL1) =20 IDREG_START(ID_AA64ZFR0_EL1) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 60, 4) IDREG_FIELD_START(ID_AA64ZFR0_EL1, F64MM, 56, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1235,10 +1269,12 @@ IDREG_START(ID_AA64ZFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64ZFR0_EL1, SM4) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 36, 4) IDREG_FIELD_START(ID_AA64ZFR0_EL1, SHA3, 32, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64ZFR0_EL1, SHA3) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 28, 4) IDREG_FIELD_START(ID_AA64ZFR0_EL1, B16B16, 24, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1258,6 +1294,7 @@ IDREG_START(ID_AA64ZFR0_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_AA64ZFR0_EL1, EltPerm) + IDREG_FIELD(ID_AA64ZFR0_EL1, RES0, 8, 4) IDREG_FIELD_START(ID_AA64ZFR0_EL1, AES, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1274,9 +1311,11 @@ IDREG_START(ID_AA64ZFR0_EL1) IDREG_END(ID_AA64ZFR0_EL1) =20 IDREG_START(ID_AFR0_EL1) + IDREG_FIELD(ID_AFR0_EL1, RES0, 0, 64) IDREG_END(ID_AFR0_EL1) =20 IDREG_START(ID_DFR0_EL1) + IDREG_FIELD(ID_DFR0_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_DFR0_EL1, TraceFilt, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1328,6 +1367,7 @@ IDREG_START(ID_DFR0_EL1) IDREG_END(ID_DFR0_EL1) =20 IDREG_START(ID_DFR1_EL1) + IDREG_FIELD(ID_DFR1_EL1, RES0, 8, 56) IDREG_FIELD_START(ID_DFR1_EL1, HPMN0, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1340,6 +1380,7 @@ IDREG_START(ID_DFR1_EL1) IDREG_END(ID_DFR1_EL1) =20 IDREG_START(ID_ISAR0_EL1) + IDREG_FIELD(ID_ISAR0_EL1, RES0, 28, 36) IDREG_FIELD_START(ID_ISAR0_EL1, Divide, 24, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1375,6 +1416,7 @@ IDREG_START(ID_ISAR0_EL1) IDREG_END(ID_ISAR0_EL1) =20 IDREG_START(ID_ISAR1_EL1) + IDREG_FIELD(ID_ISAR1_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR1_EL1, Jazelle, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1413,6 +1455,7 @@ IDREG_START(ID_ISAR1_EL1) IDREG_END(ID_ISAR1_EL1) =20 IDREG_START(ID_ISAR2_EL1) + IDREG_FIELD(ID_ISAR2_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR2_EL1, Reversal, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1458,6 +1501,7 @@ IDREG_START(ID_ISAR2_EL1) IDREG_END(ID_ISAR2_EL1) =20 IDREG_START(ID_ISAR3_EL1) + IDREG_FIELD(ID_ISAR3_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR3_EL1, T32EE, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1495,6 +1539,7 @@ IDREG_START(ID_ISAR3_EL1) IDREG_END(ID_ISAR3_EL1) =20 IDREG_START(ID_ISAR4_EL1) + IDREG_FIELD(ID_ISAR4_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR4_EL1, SWP_frac, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1519,12 +1564,12 @@ IDREG_START(ID_ISAR4_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_ISAR4_EL1, Writeback) - IDREG_FIELD_START(ID_ISAR4_EL1, WithShifts, 4, 4) + IDREG_FIELD_START(ID_ISAR4_EL1, WI, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_ARCH_VAL(3) IDREG_FIELD_ARCH_VAL(4) - IDREG_FIELD_END(ID_ISAR4_EL1, WithShifts) + IDREG_FIELD_END(ID_ISAR4_EL1, WI) IDREG_FIELD_START(ID_ISAR4_EL1, Unpriv, 0, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1533,6 +1578,7 @@ IDREG_START(ID_ISAR4_EL1) IDREG_END(ID_ISAR4_EL1) =20 IDREG_START(ID_ISAR5_EL1) + IDREG_FIELD(ID_ISAR5_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR5_EL1, VCMA, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1541,6 +1587,7 @@ IDREG_START(ID_ISAR5_EL1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(ID_ISAR5_EL1, RDM) + IDREG_FIELD(ID_ISAR5_EL1, RES0, 20, 4) IDREG_FIELD_START(ID_ISAR5_EL1, CRC32, 16, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1565,6 +1612,7 @@ IDREG_START(ID_ISAR5_EL1) IDREG_END(ID_ISAR5_EL1) =20 IDREG_START(ID_ISAR6_EL1) + IDREG_FIELD(ID_ISAR6_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_ISAR6_EL1, CLRBHB, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1601,6 +1649,7 @@ IDREG_START(ID_ISAR6_EL1) IDREG_END(ID_ISAR6_EL1) =20 IDREG_START(ID_MMFR0_EL1) + IDREG_FIELD(ID_MMFR0_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_MMFR0_EL1, InnerShr, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1647,6 +1696,7 @@ IDREG_START(ID_MMFR0_EL1) IDREG_END(ID_MMFR0_EL1) =20 IDREG_START(ID_MMFR1_EL1) + IDREG_FIELD(ID_MMFR1_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_MMFR1_EL1, BPred, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1695,6 +1745,7 @@ IDREG_START(ID_MMFR1_EL1) IDREG_END(ID_MMFR1_EL1) =20 IDREG_START(ID_MMFR2_EL1) + IDREG_FIELD(ID_MMFR2_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_MMFR2_EL1, HWAccFlg, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1733,6 +1784,7 @@ IDREG_START(ID_MMFR2_EL1) IDREG_END(ID_MMFR2_EL1) =20 IDREG_START(ID_MMFR3_EL1) + IDREG_FIELD(ID_MMFR3_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_MMFR3_EL1, Supersec, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(15) @@ -1772,6 +1824,7 @@ IDREG_START(ID_MMFR3_EL1) IDREG_END(ID_MMFR3_EL1) =20 IDREG_START(ID_MMFR4_EL1) + IDREG_FIELD(ID_MMFR4_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_MMFR4_EL1, EVT, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1809,6 +1862,7 @@ IDREG_START(ID_MMFR4_EL1) IDREG_END(ID_MMFR4_EL1) =20 IDREG_START(ID_MMFR5_EL1) + IDREG_FIELD(ID_MMFR5_EL1, RES0, 8, 56) IDREG_FIELD_START(ID_MMFR5_EL1, nTLBPA, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1822,6 +1876,7 @@ IDREG_START(ID_MMFR5_EL1) IDREG_END(ID_MMFR5_EL1) =20 IDREG_START(ID_PFR0_EL1) + IDREG_FIELD(ID_PFR0_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_PFR0_EL1, RAS, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1863,6 +1918,7 @@ IDREG_START(ID_PFR0_EL1) IDREG_END(ID_PFR0_EL1) =20 IDREG_START(ID_PFR1_EL1) + IDREG_FIELD(ID_PFR1_EL1, RES0, 32, 32) IDREG_FIELD_START(ID_PFR1_EL1, GIC, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1902,6 +1958,7 @@ IDREG_START(ID_PFR1_EL1) IDREG_END(ID_PFR1_EL1) =20 IDREG_START(ID_PFR2_EL1) + IDREG_FIELD(ID_PFR2_EL1, RES0, 12, 52) IDREG_FIELD_START(ID_PFR2_EL1, RAS_frac, 8, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1949,11 +2006,14 @@ IDREG_START(MIDR_EL1) IDREG_END(MIDR_EL1) =20 IDREG_START(MPIDR_EL1) + IDREG_FIELD(MPIDR_EL1, RES0, 40, 24) IDREG_FIELD(MPIDR_EL1, Aff3, 32, 8) + IDREG_FIELD(MPIDR_EL1, RES1, 31, 1) IDREG_FIELD_START(MPIDR_EL1, U, 30, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) IDREG_FIELD_END(MPIDR_EL1, U) + IDREG_FIELD(MPIDR_EL1, RES0, 25, 5) IDREG_FIELD_START(MPIDR_EL1, MT, 24, 1) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -1964,6 +2024,7 @@ IDREG_START(MPIDR_EL1) IDREG_END(MPIDR_EL1) =20 IDREG_START(MVFR0_EL1) + IDREG_FIELD(MVFR0_EL1, RES0, 32, 32) IDREG_FIELD_START(MVFR0_EL1, FPRound, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2002,6 +2063,7 @@ IDREG_START(MVFR0_EL1) IDREG_END(MVFR0_EL1) =20 IDREG_START(MVFR1_EL1) + IDREG_FIELD(MVFR1_EL1, RES0, 32, 32) IDREG_FIELD_START(MVFR1_EL1, SIMDFMAC, 28, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2040,6 +2102,7 @@ IDREG_START(MVFR1_EL1) IDREG_END(MVFR1_EL1) =20 IDREG_START(MVFR2_EL1) + IDREG_FIELD(MVFR2_EL1, RES0, 8, 56) IDREG_FIELD_START(MVFR2_EL1, FPMisc, 4, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(1) @@ -2059,6 +2122,7 @@ IDREG_START(REVIDR_EL1) IDREG_END(REVIDR_EL1) =20 IDREG_START(SMIDR_EL1) + IDREG_FIELD(SMIDR_EL1, RES0, 60, 4) IDREG_FIELD_START(SMIDR_EL1, NSMC, 56, 4) IDREG_FIELD_ARCH_VAL(0) IDREG_FIELD_ARCH_VAL(15) @@ -2094,6 +2158,7 @@ IDREG_START(SMIDR_EL1) IDREG_FIELD_ARCH_VAL(2) IDREG_FIELD_ARCH_VAL(3) IDREG_FIELD_END(SMIDR_EL1, SH) + IDREG_FIELD(SMIDR_EL1, RES0, 12, 1) IDREG_FIELD(SMIDR_EL1, Affinity, 0, 12) IDREG_END(SMIDR_EL1) =20 diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/upda= te-aarch64-cpu-sysreg-properties.py index e1d6c4afef..9e829fda2e 100644 --- a/scripts/update-aarch64-cpu-sysreg-properties.py +++ b/scripts/update-aarch64-cpu-sysreg-properties.py @@ -81,9 +81,13 @@ def collect_fields(item, bit_offset=3D0): =20 # Normal Field Types leaf_types =3D ['Fields.Field', 'Fields.ConstantField', - 'Fields.EnumeratedField', 'Fields.Bitfield'] + 'Fields.EnumeratedField', 'Fields.Bitfield', 'Fields.Res= erved'] if _type in leaf_types: field_copy =3D item.copy() + + if _type =3D=3D 'Fields.Reserved' and not field_copy.get('name'): + field_copy['name'] =3D item.get('value', 'RES0') + if field_copy.get('rangeset'): new_ranges =3D [] for r in field_copy['rangeset']: @@ -96,7 +100,7 @@ def collect_fields(item, bit_offset=3D0): return fields =20 # Traverse the hierarchy for other cases - for key in ['fields', 'values', 'fieldsets']: + for key in ['fields', 'values', 'fieldsets', 'constants']: for nested in item.get(key, []): fields.extend(collect_fields(nested, bit_offset)) =20 @@ -163,44 +167,95 @@ def generate_sysreg_properties_from_registers_json(id= _reg_names, raw_json_path): =20 final_output +=3D f"IDREG_START({reg_name})\n" =20 - unique_fields =3D {} + fieldset_variants =3D [] + for fieldset in register.get('fieldsets', []): + current_fieldset_fields =3D {} candidates =3D collect_fields(fieldset) + for val in candidates: - name =3D (val.get('name') or val.get('label', '')).strip() - if not name or "RESERVED" in name.upper(): + raw_name =3D val.get('name') or val.get('label') or val.ge= t('value') or '' + name =3D raw_name.strip() + if not name: continue + + name_upper =3D name.upper() + + # Check for architectural target states, including UNKNOWN= remapping + base_reserved =3D None + for r_type in ["RES0", "RES1", "RAZ", "RAO", "WI", "UNKNOW= N"]: + if r_type in name_upper: + base_reserved =3D "RES0" if r_type =3D=3D "UNKNOWN= " else r_type + break + + is_valid_reserved =3D base_reserved is not None + if "RESERVED" in name_upper and not is_valid_reserved: + continue + + # Force naming uniformity across padding blocks + if is_valid_reserved: + name =3D base_reserved + for r in val.get('rangeset', []): lsb =3D int(r.get('start')) width =3D r.get('width') msb =3D lsb + int(width) - 1 =20 - # Only keep the fields with the highest MSB - # needed fir CCSIDR_EL1 - if name not in unique_fields or msb > unique_fields[na= me]['msb']: - # extract enum values if any + if is_valid_reserved: + unique_key =3D f"{name}_{lsb}" + else: + unique_key =3D name + + if unique_key not in current_fieldset_fields or \ + msb > current_fieldset_fields[unique_key]['msb']: enums =3D extract_field_enums(val) - unique_fields[name] =3D {'lsb': lsb, 'msb': msb, '= width': width, 'enums': enums} + current_fieldset_fields[unique_key] =3D { + 'raw_name': name, + 'lsb': lsb, + 'msb': msb, + 'width': width, + 'enums': enums + } + + if current_fieldset_fields: + fieldset_variants.append(current_fieldset_fields) + + best_fieldset =3D {} + max_total_width =3D -1 + + for variant in fieldset_variants: + total_width =3D sum(f['width'] for f in variant.values()) + # prioritize layout variants with the highest MSB coverage + max_msb =3D max(f['msb'] for f in variant.values()) if variant= else 0 + + # Combine width and max_msb into a fitness score tuple + if (total_width, max_msb) > (max_total_width, max_total_width): + max_total_width =3D total_width + best_fieldset =3D variant + + unique_fields =3D best_fieldset =20 # Sort decreasing lsbs sorted_fields =3D sorted(unique_fields.items(), key=3Dlambda x: x[1]['lsb'], reverse=3DTrue) =20 - for name, bits in sorted_fields: + for unique_key, bits in sorted_fields: enums_list =3D bits.get('enums', []) =20 + clean_name =3D bits.get('raw_name', unique_key) + if enums_list: line =3D (f" IDREG_FIELD_START({reg_name}, " - f"{name}, {bits['lsb']}, {bits['width']})\n") + f"{clean_name}, {bits['lsb']}, {bits['width']})\n") else: line =3D (f" IDREG_FIELD({reg_name}, " - f"{name}, {bits['lsb']}, {bits['width']})\n") + f"{clean_name}, {bits['lsb']}, {bits['width']})\n") final_output +=3D line # add the enum value definition if any for enum_item in enums_list: final_output +=3D (f" IDREG_FIELD_ARCH_VAL({enum_it= em['value']})\n") if enums_list: - line =3D (f" IDREG_FIELD_END({reg_name}, {name})\n") + line =3D (f" IDREG_FIELD_END({reg_name}, {clean_name})\n= ") final_output +=3D line =20 final_output +=3D f"IDREG_END({reg_name})\n" --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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2026 13:28:25 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.48.30]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 0762D3000203; Tue, 16 Jun 2026 13:28:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616510; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iiWgOdy0RqtOoE1IxywPHeIoO2TxlI32Vfz46laKIp8=; b=fA9XNpwo3x/1Irn/7ksIBMsVva6vNQzPg4IWdPEaz49qagTTotWIW8gTY+FZSUe6qQs0zq Vlf0gkZU92fBCB6gyG8vTYyo/l5S7iDv11kdoQSo/g88da/sGlCm57Kd0t66u58AbrlpYK u3w6ykqo3DIjd8s5W9/gOngLL/OUBEU= X-MC-Unique: YeTqhneFPiKxH7fZYx_9jQ-1 X-Mimecast-MFC-AGG-ID: YeTqhneFPiKxH7fZYx_9jQ_1781616505 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 16/17] target/arm/kvm: Ignore and trace unexpected writable reserved fields Date: Tue, 16 Jun 2026 15:17:03 +0200 Message-ID: <20260616132625.1732031-17-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1781616542184158502 Content-Type: text/plain; charset="utf-8" KVM currently reports some bits as writable whereas they are RES0 or RAZ. The code easily allows to do some sanity checking for such inconsistencies. Let's add a trace event when this is encountered and skip the field Signed-off-by: Eric Auger --- target/arm/kvm.c | 8 ++++++++ target/arm/trace-events | 1 + 2 files changed, 9 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 54392f3077..90e069f582 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -434,6 +434,14 @@ decode_idreg_writemap(Object *obj, ARM64SysReg *reg) } lower =3D field->shift; upper =3D field->shift + field->length - 1; + + /* Sanity check the field is not a reserved field */ + if (strstr(field->name, "RES0") || strstr(field->name, "RES1") || + strstr(field->name, "RAZ")) { + trace_unexpected_writable_reserved_field(reg->name, field->nam= e, + lower, upper); + continue; + } prop_name =3D g_strdup_printf("SYSREG_%s_%s", reg->name, field->na= me); trace_decode_idreg_writemap(field->name, lower, upper, prop_name); object_property_add(obj, prop_name, "uint64", diff --git a/target/arm/trace-events b/target/arm/trace-events index d72ad6b671..e67730de6b 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -19,6 +19,7 @@ decode_idreg_writemap(const char* name, int lower, int up= per, char *prop_name) " get_sysreg_prop(const char *name, uint64_t value) "%s 0x%"PRIx64 set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t fi= eld_value, uint64_t new) "%s old reg value=3D0x%"PRIx64" mask=3D0x%"PRIx64"= new field value=3D0x%"PRIx64" new reg value=3D0x%"PRIx64 nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" +unexpected_writable_reserved_field(const char *reg_name, const char *field= _name, int lower, int upper) "Unexpected writable reserved field: %s.%s [%d= ,%d], skip it ..." =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Thu Jun 18 15:07:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781616516; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7t3/6OthMgSGaRs8vrnLHPfTMlQhBxcgyyk0T/BvuEc=; b=UA89TTMJ1t/C92847jlW63/d2oGcn+uRC0yZhLPCeHoBnfc5vNf332GFHIVTCMaATqmAdd SJKXrgofYg+teH7cx9GF1AxGhQ+MTeYu1pbm9XgiG00DmtspSKFKPv5skq3hDPlNLPfirz IyiuWqBWqBADpmfbhBJp3VbSYrzi2fw= X-MC-Unique: B7DwBgrKNb2c7z60jzOqxg-1 X-Mimecast-MFC-AGG-ID: B7DwBgrKNb2c7z60jzOqxg_1781616511 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [RFC PATCH v6 17/17] arm/cpu-features: document ID reg properties Date: Tue, 16 Jun 2026 15:17:04 +0200 Message-ID: <20260616132625.1732031-18-eric.auger@redhat.com> In-Reply-To: <20260616132625.1732031-1-eric.auger@redhat.com> References: <20260616132625.1732031-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Cornelia Huck Add some documentation for how individual ID registers can be configured with the host cpu model. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott --- docs/system/arm/cpu-features.rst | 106 ++++++++++++++++++++++++++++--- 1 file changed, 98 insertions(+), 8 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 10b0eff27e..3a07a87bc3 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -2,7 +2,10 @@ Arm CPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 CPU features are optional features that a CPU of supporting type may -choose to implement or not. In QEMU, optional CPU features have +choose to implement or not. QEMU provides two different mechanisms +to configure those features: + +1. For most CPU models, optional CPU features may have corresponding boolean CPU proprieties that, when enabled, indicate that the feature is implemented, and, conversely, when disabled, indicate that it is not implemented. An example of an Arm CPU feature @@ -31,6 +34,18 @@ running guests in AArch32. CPU features that are inherently specific to KVM are prefixed with "kvm-" and are described in "KVM VCPU Features". =20 +2. Additionally, the ``host`` CPU model on KVM allows to configure optional +CPU features via the corresponding ID registers. The host kernel allows +to write a subset of ID register fields. The host model exposes +properties for each writable ID register field. Those options are named +SYSREG__. IDREG and FIELD names are those used in the +ARM Architecture Reference Manual. Their availability depend on the host +capability to let the userspace write those fields. Values set with those +properties override the initial values retrieved from the host. They are +written back to KVM and the eventual value applied by KVM depends on wheth= er +the value is sanitized or not by the host kernel. Then those field values +are likely to be overriden again by legacy CPU options which apply at the = end. + CPU Feature Probing =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -126,13 +141,20 @@ A note about CPU models and KVM =20 Named CPU models generally do not work with KVM. There are a few cases that do work, e.g. using the named CPU model ``cortex-a57`` with KVM on a -seattle host, but mostly if KVM is enabled the ``host`` CPU type must be -used. This means the guest is provided all the same CPU features as the -host CPU type has. And, for this reason, the ``host`` CPU type should -enable all CPU features that the host has by default. Indeed it's even -a bit strange to allow disabling CPU features that the host has when using -the ``host`` CPU type, but in the absence of CPU models it's the best we c= an -do if we want to launch guests without all the host's CPU features enabled. +seattle host, but mostly if KVM is enabled, the ``host`` CPU model must be +used. + +Using the ``host`` type means the guest is provided all the same CPU +features as the host CPU type has. And, for this reason, the ``host`` +CPU type should enable all CPU features that the host has by default. + +In case some features need to be hidden from the guest, and the host kernel +supports it, the ``host`` model can be instructed to disable individual +ID register values. This is especially useful for migration purposes. +However, this interface will not allow configuring an arbitrary set of +features; the ID registers must describe a subset of the host's features, +and all differences to the host's configuration must actually be supported +by the kernel to be deconfigured. =20 Enabling KVM also affects the ``query-cpu-model-expansion`` QMP command. = The affect is not only limited to specific features, as pointed out in example @@ -169,6 +191,13 @@ disabling many SVE vector lengths would be quite verbo= se, the ``sve`` CPU properties have special semantics (see "SVE CPU Property Parsing Semantics"). =20 +Additionally, if supported by KVM on the host kernel, the ``host`` CPU mod= el +may be configured via individual ID register field properties, for example= :: + + $ qemu-system-aarch64 -M virt -cpu host,SYSREG_ID_AA64ISAR0_EL1_DP=3D0x0 + +This forces ID_AA64ISAR0_EL1 DP field to 0. + KVM VCPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -495,3 +524,64 @@ Legal values for ``S`` are 30, 34, 36, and 39; the def= ault is 30. =20 As with ``x-rme``, the ``x-l0gptsz`` property may be renamed or removed in some future QEMU release. + +Configuring CPU features via ID register fields +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Note that this is currently only supported under KVM, and with the +``host`` CPU model. + +Querying available ID register fields +------------------------------------- + +QEMU will create properties for all ID register fields that are +reported as being writable by the kernel, and that are known to the +QEMU instance. Therefore, the same QEMU binary may expose different +properties when run under a different kernel. + +To find out all available writable ID register fields, use the +``query-cpu-model-expansion`` QMP command:: + + (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} + {"return": { + "model": {"name": "host", "props": { + "SYSREG_ID_AA64PFR0_EL1_EL3": 1, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, + "SYSREG_CTR_EL0_L1Ip": 3, "SYSREG_CTR_EL0_DminLine": 4, + "SYSREG_ID_AA64MMFR0_EL1_BIGEND": 1, "SYSREG_ID_AA64MMFR1_EL1_ECBHB": 0, + "SYSREG_ID_AA64MMFR2_EL1_CnP": 1, "SYSREG_ID_DFR0_EL1_PerfMon": 4, + "SYSREG_ID_AA64PFR0_EL1_DIT": 0, "SYSREG_ID_AA64MMFR1_EL1_HAFDBS": 2, + "SYSREG_ID_AA64ISAR0_EL1_FHM": 0, "SYSREG_ID_AA64ISAR2_EL1_CSSC": 0, + "SYSREG_ID_AA64ISAR0_EL1_DP": 1, (...) + }}}} + +If a certain field in an ID register does not show up in this list, it +is not writable with the specific host kernel. + +A note on compatibility +----------------------- + +A common use case for providing a defined set of ID register values is +to be able to present a fixed set of features to a guest, often referred +to as "stable guest ABI". This may take the form of ironing out differences +between two similar CPUs with the intention of being able to migrate +between machines with those CPUs, or providing the same CPU across Linux +kernel updates on the host. + +Over the course of time, the Linux kernel is changing the set of ID regist= er +fields that are writable by userspace. Newly introduced writable ID +registers should be initialized to 0 to ensure compatibility. However, ID +registers that have already been introduced that undergo a change as to +which fields are writable may introduce incompatibilities that need to be +addressed on a case-by-case basis for the systems that you wish to migrate +inbetween. + +A note on Arm CPU features (FEAT_xxx) +------------------------------------- + +Configuring CPUs is done on a feature level on other architectures, and th= is +would imply configuring FEAT_xxx values on Arm. However, differences betwe= en +CPUs may not map to FEAT_xxx, but to differences in other registers in the +ID register range; for example, differences in the cache architecture expo= sed +via ``CTR_EL0``. We therefore cannot rely on configuration via FEAT_xxx. A +feature-based interface more similar to other architectures may be impleme= nted +on top of the ID register interface in the future. --=20 2.53.0