From nobody Thu Jun 25 05:54:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781603568332891.5544801184312; Tue, 16 Jun 2026 02:52:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZQTG-0001dI-Ng; Tue, 16 Jun 2026 05:52:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wZQTD-0001cw-56 for qemu-devel@nongnu.org; Tue, 16 Jun 2026 05:52:35 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wZQT9-0007US-4a for qemu-devel@nongnu.org; Tue, 16 Jun 2026 05:52:34 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Bxt3jRHDFqLbQUAA--.29489S3; Tue, 16 Jun 2026 17:52:17 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJCxGODQHDFqkBOoAA--.56955S2; Tue, 16 Jun 2026 17:52:16 +0800 (CST) From: Xianglai Li To: qemu-devel@nongnu.org, lixianglai@loongson.cn Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bibo Mao , Song Gao Subject: [PATCH V2] target/loongarch: clear the registers when cpu is reset Date: Tue, 16 Jun 2026 17:25:54 +0800 Message-Id: <20260616092554.1704380-1-lixianglai@loongson.cn> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxGODQHDFqkBOoAA--.56955S2 X-CM-SenderInfo: 5ol0xt5qjotxo6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=lixianglai@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1781603573822158500 Use virt-manager to start a virtual machine, and then use the following command to manually trigger the crash of the virtual machine: echo c > /proc/sysrq-trigger After the VM is abnormal, the ESTAT register has a certain probability of remaining interrupted. Then the VM is forced to restart and the VM is suspended in the interrupt handling function during startup. In order to clear the remaining interrupt information in the ESTAT register, we carried out the operation and checked the status of other registers during the reset process: Set the CSR_CRMD, CSR_ESTAT, CSR_MSGIS and CSR_PERFCTRL registers to the reset state when the CPU is reset. Signed-off-by: Xianglai Li Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Alex Benn=C3=A9e Cc: Bibo Mao Cc: Song Gao changelog: V1->V2: 1.Add a description of the issues related to this patch 2.Replace the macro definition MAX_PERF_EVENTS with the variable perf_event_num as the condition for the for loop. 3.Rebase against the latest codebase. 4.Refer to the usage of end_reset_fields on ARM and other architectures, and modify the current implementation accordingly. Signed-off-by: Xianglai Li --- target/loongarch/cpu-csr.h | 7 +++++++ target/loongarch/cpu.c | 41 +++++++++++++++++--------------------- target/loongarch/cpu.h | 22 +++++++++++--------- 3 files changed, 38 insertions(+), 32 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index d860417af2..d936af8e57 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -211,6 +211,13 @@ FIELD(CSR_DMW_64, VSEG, 60, 4) #define LOONGARCH_CSR_PERFCTRL(N) (0x200 + 2 * N) #define LOONGARCH_CSR_PERFCNTR(N) (0x201 + 2 * N) =20 +FIELD(CSR_PERFCTRL, EV, 0, 10) +FIELD(CSR_PERFCTRL, PLV0, 16, 1) +FIELD(CSR_PERFCTRL, PLV1, 17, 1) +FIELD(CSR_PERFCTRL, PLV2, 18, 1) +FIELD(CSR_PERFCTRL, PLV3, 19, 1) +FIELD(CSR_PERFCTRL, PMIE, 20, 1) + /* Debug CSRs */ #define LOONGARCH_CSR_DBG 0x500 /* debug config */ FIELD(CSR_DBG, DST, 0, 1) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index fb03424ffa..aa6ecd9da2 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -623,44 +623,39 @@ static void loongarch_cpu_reset_hold(Object *obj, Res= etType type) env->fcsr0 =3D 0x0; =20 int n; - /* Set csr registers value after reset, see the manual 6.4. */ - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PLV, 0); - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, IE, 0); - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DA, 1); - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PG, 0); - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DATF, 0); - sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DATM, 0); =20 - sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, FPE, 0); - sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, SXE, 0); - sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, ASXE, 0); - sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, BTE, 0); + memset(sys, 0, offsetof(CPUSysState, end_reset_fields)); =20 - sys->CSR_MISC =3D 0; - - sys->CSR_ECFG =3D FIELD_DP64(sys->CSR_ECFG, CSR_ECFG, VS, 0); - sys->CSR_ECFG =3D FIELD_DP64(sys->CSR_ECFG, CSR_ECFG, LIE, 0); + /* Set csr registers value after reset, see the manual 6.4. */ + sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DA, 1); =20 - sys->CSR_ESTAT =3D sys->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); - sys->CSR_RVACFG =3D FIELD_DP64(sys->CSR_RVACFG, CSR_RVACFG, RBITS, 0); sys->CSR_CPUID =3D cs->cpu_index; sys->CSR_TCFG =3D FIELD_DP64(sys->CSR_TCFG, CSR_TCFG, EN, 0); sys->CSR_LLBCTL =3D FIELD_DP64(sys->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); sys->CSR_TLBRERA =3D FIELD_DP64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR,= 0); sys->CSR_MERRCTL =3D FIELD_DP64(sys->CSR_MERRCTL, CSR_MERRCTL, ISMERR,= 0); sys->CSR_TID =3D cs->cpu_index; + + sys->CSR_DBG =3D FIELD_DP64(sys->CSR_DBG, CSR_DBG, DST, 0); + for (n =3D 0; n < env->perf_event_num; n++) { + sys->CSR_PERFCTRL[n] =3D FIELD_DP64(sys->CSR_PERFCTRL[n], CSR_PERF= CTRL, + PLV0, 0); + sys->CSR_PERFCTRL[n] =3D FIELD_DP64(sys->CSR_PERFCTRL[n], CSR_PERF= CTRL, + PLV1, 0); + sys->CSR_PERFCTRL[n] =3D FIELD_DP64(sys->CSR_PERFCTRL[n], CSR_PERF= CTRL, + PLV2, 0); + sys->CSR_PERFCTRL[n] =3D FIELD_DP64(sys->CSR_PERFCTRL[n], CSR_PERF= CTRL, + PLV3, 0); + sys->CSR_PERFCTRL[n] =3D FIELD_DP64(sys->CSR_PERFCTRL[n], CSR_PERF= CTRL, + PMIE, 0); + } + /* * Workaround for edk2-stable202408, CSR PGD register is set only if * its value is equal to zero for boot cpu, it causes reboot issue. * * Here clear CSR registers relative with TLB. */ - sys->CSR_PGDH =3D 0; - sys->CSR_PGDL =3D 0; - sys->CSR_PWCH =3D 0; - sys->CSR_EENTRY =3D 0; - sys->CSR_TLBRENTRY =3D 0; - sys->CSR_MERRENTRY =3D 0; /* set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits from CSR_PRCFG2 */ if (sys->CSR_PRCFG2 =3D=3D 0) { sys->CSR_PRCFG2 =3D 0x3fffff000; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index ad30c73167..2576239b31 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -325,22 +325,30 @@ typedef struct CPUSysState { uint64_t CSR_MISC; uint64_t CSR_ECFG; uint64_t CSR_ESTAT; + uint64_t CSR_PGDL; + uint64_t CSR_PGDH; + uint64_t CSR_EENTRY; + uint64_t CSR_PWCH; + uint64_t CSR_RVACFG; + uint64_t CSR_TLBRENTRY; + uint64_t CSR_MERRENTRY; + /* Msg interrupt registers */ + uint64_t CSR_MSGIS[N_MSGIS]; + + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; + uint64_t CSR_ERA; uint64_t CSR_BADV; uint64_t CSR_BADI; - uint64_t CSR_EENTRY; uint64_t CSR_TLBIDX; uint64_t CSR_TLBEHI; uint64_t CSR_TLBELO0; uint64_t CSR_TLBELO1; uint64_t CSR_ASID; - uint64_t CSR_PGDL; - uint64_t CSR_PGDH; uint64_t CSR_PGD; uint64_t CSR_PWCL; - uint64_t CSR_PWCH; uint64_t CSR_STLBPS; - uint64_t CSR_RVACFG; uint64_t CSR_CPUID; uint64_t CSR_PRCFG1; uint64_t CSR_PRCFG2; @@ -354,7 +362,6 @@ typedef struct CPUSysState { uint64_t CSR_LLBCTL; uint64_t CSR_IMPCTL1; uint64_t CSR_IMPCTL2; - uint64_t CSR_TLBRENTRY; uint64_t CSR_TLBRBADV; uint64_t CSR_TLBRERA; uint64_t CSR_TLBRSAVE; @@ -365,7 +372,6 @@ typedef struct CPUSysState { uint64_t CSR_MERRCTL; uint64_t CSR_MERRINFO1; uint64_t CSR_MERRINFO2; - uint64_t CSR_MERRENTRY; uint64_t CSR_MERRERA; uint64_t CSR_MERRSAVE; uint64_t CSR_CTAG; @@ -375,8 +381,6 @@ typedef struct CPUSysState { uint64_t CSR_DBG; uint64_t CSR_DERA; uint64_t CSR_DSAVE; - /* Msg interrupt registers */ - uint64_t CSR_MSGIS[N_MSGIS]; uint64_t CSR_MSGIR; uint64_t CSR_MSGIE; } CPUSysState; --=20 2.39.1