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Mon, 15 Jun 2026 13:37:42 -0700 (PDT) X-Received: by 2002:a05:620a:27d2:b0:915:d443:e6db with SMTP id af79cd13be357-9161bc2337fmr2313818585a.20.1781555861564; Mon, 15 Jun 2026 13:37:41 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, Daniel Henrique Barboza , Alistair Francis , Palmer Dabbelt Subject: [PATCH 01/13] hw/riscv/sifive_u.c: add a FDT phandle to cpu-intc Date: Mon, 15 Jun 2026 17:37:21 -0300 Message-ID: <20260615203734.954428-2-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260615203734.954428-1-daniel.barboza@oss.qualcomm.com> References: <20260615203734.954428-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDIxOCBTYWx0ZWRfX8a/wLl9Owknb 7GnnYBfL/zG06/57o4/xusr0yZszaCDKz/Nc3Ks9LcNWR7sxus+L27gfGrIWPPSx2rfInHpn0H3 sdyz721ghzKyv1QF/dPUTwRYjSgYAh4= X-Authority-Analysis: v=2.4 cv=QLlYgALL c=1 sm=1 tr=0 ts=6a306297 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=gdiugJE53z4H+vvYeRBHqw==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=G410GlaaS0drJ4fCzjAA:9 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDIxOCBTYWx0ZWRfX4DGimnS8mmqM Fl9pXMrJm3xse2GbQvnqDRJNRRwYpX65tdwffRIZdC2cVSx+jVIGHlGVX8OGlzkjSMPwJA9XgdY hJysIalPrP7SbFweaUIxMsa/e96ejoa9xsaUgh8rJjB73NZ4bcX5AjV04N/JcHWfJhn+BeFJiLl mRE1qIpfCzw5VXkmtHj4P9bElA4bGzkNVBNimMPJfuCKCUXrMPx3QbIbFklknTf/tXC+OB9swSp ekxnZ97DxD09HPteFTOU2/vZv6R7twmnLkwabY1Uq/MT9E5Fbc9Rna7BHBg5XQ5/ayIy2m9t8Hu CSGI3j4UUpmzc1NGXEmC6QdKBEHhDn1tPsinSLXp/PSI2eb527kYQ+wMtMy7oJn9HxGa5A7UMBB w6NLtItCHTN+SoXNdmyuAtssNtE+5krPUjS2yRY8iySWXnPdkB7ZzgHg9CkXYo5TmXvF9Cpxdt/ cMxBjZQM8Nk85fRpPGQ== X-Proofpoint-GUID: UU-KHSa_oT84V2Pl9ld3nPxC6IDQO6Sy X-Proofpoint-ORIG-GUID: UU-KHSa_oT84V2Pl9ld3nPxC6IDQO6Sy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_05,2026-06-15_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 adultscore=0 spamscore=0 bulkscore=0 suspectscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150218 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781556160653158500 Content-Type: text/plain; charset="utf-8" We're assigning a 'cpu_phandle' phandle to the cpu-intc phandle field. Make it more in line with the other boards by assigning both a cpu_phandle and a intc phandle. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6a637e3b86..3abbd6c823 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -187,8 +187,10 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); + qemu_fdt_add_subnode(fdt, intc); - qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); + qemu_fdt_setprop_cell(fdt, intc, "phandle", phandle++); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); --=20 2.43.0 From nobody Sun Jul 26 13:29:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 15 Jun 2026 13:37:44 -0700 (PDT) X-Received: by 2002:a05:6214:f0a:b0:8a5:104b:e37b with SMTP id 6a1803df08f44-8d4502aed80mr212503056d6.42.1781555863870; Mon, 15 Jun 2026 13:37:43 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH 02/13] hw/riscv: add fdt-common helper Date: Mon, 15 Jun 2026 17:37:22 -0300 Message-ID: <20260615203734.954428-3-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260615203734.954428-1-daniel.barboza@oss.qualcomm.com> References: <20260615203734.954428-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: t6bhbCQsbf6KeuJvnzaMn7M8HAnqL0z4 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDIxOCBTYWx0ZWRfX3CIF2Vl9tpoL rLSNGBT8wbjhZYR67qMs0zHfY66chJakxsyrRwbRJUXDEHeqzmKHNNhTwlnYBUL+esjlDwyVSta M/N9HL/FW0+PxKMnK9kHGU/8DLywzBs= X-Authority-Analysis: v=2.4 cv=QrJuG1yd c=1 sm=1 tr=0 ts=6a306299 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=gdiugJE53z4H+vvYeRBHqw==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=u1ybqLB28KXXVxpIts0A:9 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-ORIG-GUID: t6bhbCQsbf6KeuJvnzaMn7M8HAnqL0z4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDIxOCBTYWx0ZWRfX4UBVIu7bBdVj PUf/xe6JoRqoKa38zxjXit+bxCpmjAh/e5avd1L3hhHEbu9d6QnpCJv1BltwP8ljVHzu/xTU2Vg LoHyOGQecjDnZBmvh8lmU8Njo2GXaU0KRTHrGYo+gA9iwURs/gXmKQNQUas+dawt4mWsPG4CWCD 9HRVmBJhgaBX3r/RmwF4Khgn26uvqL3uj26opa+3CyOpLdWc5aWeWDGJtBD7gY/ODMYMqqiqsim kVW+d/BgTrx02VavwazkhHh/8vpCWp6mxtcsAOVeCC5fXxkFvnwafd1JrMhNhZPmSbXyZ2DBH67 v/SeKbQMtAsuKL9pycNEkAB5bCUp45+tNF0RSzATW0uYFyq+U1zICrKb0ZgrhIJIIftJr70EOnm X4KbXyMZ3O/HrXIZyTXUzJSogQkXtYAObxKfut7o3hMP3eDXIIGAZ96s9IyIrNOGwlBfAU5JfFh yLjn7GkLm4xCmZDX/2g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_05,2026-06-15_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150218 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781556144695158500 Content-Type: text/plain; charset="utf-8" There's too much duplication between RISC-V boards and one of the most common culprits is the FDT functions. Add a new file for board FDT helpers. Start by creating a helper that initializes the FDT and init it with the common board boilerplate. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/fdt-common.c | 37 +++++++++++++++++++++++++++++++++++ hw/riscv/meson.build | 1 + hw/riscv/sifive_u.c | 20 +++---------------- hw/riscv/spike.c | 19 +++--------------- hw/riscv/virt.c | 19 +++--------------- include/hw/riscv/fdt-common.h | 14 +++++++++++++ 6 files changed, 61 insertions(+), 49 deletions(-) create mode 100644 hw/riscv/fdt-common.c create mode 100644 include/hw/riscv/fdt-common.h diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c new file mode 100644 index 0000000000..b155246998 --- /dev/null +++ b/hw/riscv/fdt-common.c @@ -0,0 +1,37 @@ +/* + * RISC-V board helpers for FDT generation. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "qemu/error-report.h" +#include "system/device_tree.h" +#include "hw/riscv/fdt-common.h" + +void *create_board_device_tree(const char *model, const char *compatible, + int *fdt_size) +{ + void *fdt =3D create_device_tree(fdt_size); + + if (!fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + qemu_fdt_setprop_string(fdt, "/", "model", model); + qemu_fdt_setprop_string(fdt, "/", "compatible", compatible); + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); + + qemu_fdt_add_subnode(fdt, "/soc"); + qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); + qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + + return fdt; +} diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 533472e22a..f19db0dd7f 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -1,5 +1,6 @@ riscv_ss =3D ss.source_set() riscv_ss.add(files('boot.c')) +riscv_ss.add(files('fdt-common.c')) riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) riscv_ss.add(files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 3abbd6c823..5d3b2751ad 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -52,6 +52,7 @@ #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" #include "hw/riscv/machines-qom.h" +#include "hw/riscv/fdt-common.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -112,23 +113,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, "sifive,plic-1.0.0", "riscv,plic0" }; =20 - fdt =3D ms->fdt =3D create_device_tree(&s->fdt_size); - if (!fdt) { - error_report("create_device_tree() failed"); - exit(1); - } - - qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A0= 0"); - qemu_fdt_setprop_string(fdt, "/", "compatible", - "sifive,hifive-unleashed-a00"); - qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); - - qemu_fdt_add_subnode(fdt, "/soc"); - qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + fdt =3D ms->fdt =3D create_board_device_tree("SiFive HiFive Unleashed = A00", + "sifive,hifive-unleashed-a00", &s->fdt_size); =20 hfclk_phandle =3D phandle++; nodename =3D g_strdup_printf("/hfclk"); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index f9d00e0d5c..79c9bb041f 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -32,6 +32,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/spike.h" #include "hw/riscv/boot.h" +#include "hw/riscv/fdt-common.h" #include "hw/riscv/numa.h" #include "hw/riscv/machines-qom.h" #include "hw/char/riscv_htif.h" @@ -66,16 +67,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry = *memmap, "sifive,clint0", "riscv,clint0" }; =20 - fdt =3D ms->fdt =3D create_device_tree(&fdt_size); - if (!fdt) { - error_report("create_device_tree() failed"); - exit(1); - } - - qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); - qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev= "); - qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); + fdt =3D ms->fdt =3D create_board_device_tree("ucbbar,spike-bare,qemu", + "ucbbar,spike-bare-dev", &fdt_size); =20 qemu_fdt_add_subnode(fdt, "/htif"); qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); @@ -84,12 +77,6 @@ static void create_fdt(SpikeState *s, const MemMapEntry = *memmap, 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); } =20 - qemu_fdt_add_subnode(fdt, "/soc"); - qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); - qemu_fdt_add_subnode(fdt, "/cpus"); qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0c489bb412..cb1d83fd48 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -36,6 +36,7 @@ #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" +#include "hw/riscv/fdt-common.h" #include "hw/riscv/machines-qom.h" #include "hw/riscv/numa.h" #include "kvm/kvm_riscv.h" @@ -1150,22 +1151,8 @@ static void create_fdt(RISCVVirtState *s) uint8_t rng_seed[32]; g_autofree char *name =3D NULL; =20 - ms->fdt =3D create_device_tree(&s->fdt_size); - if (!ms->fdt) { - error_report("create_device_tree() failed"); - exit(1); - } - - qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); - qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); - qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); - - qemu_fdt_add_subnode(ms->fdt, "/soc"); - qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); + ms->fdt =3D create_board_device_tree("riscv-virtio,qemu", "riscv-virti= o", + &s->fdt_size); =20 /* * The "/soc/pci@..." node is needed for PCIE hotplugs diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h new file mode 100644 index 0000000000..adf9b33dfd --- /dev/null +++ b/include/hw/riscv/fdt-common.h @@ -0,0 +1,14 @@ +/* + * RISC-V board helpers for FDT generation. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef RISCV_VIRT_FDT_H +#define RISCV_VIRT_FDT_H + +void *create_board_device_tree(const char *model, const char *compatible, + int *fdt_size); +#endif --=20 2.43.0 From nobody Sun Jul 26 13:29:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 15 Jun 2026 13:37:47 -0700 (PDT) X-Received: by 2002:a05:6214:2469:b0:8d1:d1e1:8360 with SMTP id 6a1803df08f44-8da20d0b968mr11509306d6.39.1781555866435; Mon, 15 Jun 2026 13:37:46 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH 03/13] hw/riscv/numa: make numa_enabled() public Date: Mon, 15 Jun 2026 17:37:23 -0300 Message-ID: <20260615203734.954428-4-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260615203734.954428-1-daniel.barboza@oss.qualcomm.com> References: <20260615203734.954428-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: ROb426S_m_MUSNh4JOb8tmqCWKJaE7si X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDIxOCBTYWx0ZWRfX6XFSAMBisJ1O sfVVLyAgHA9Wrg4CPGTMTbMPouPOIMYRXlzCvLzcNRrxrY+3RU+JYjsZRpVsZ5MYLNOpWLx6KQp BVj9bqZTjuQkiMtzMAx8UfjcigKIY2I= X-Authority-Analysis: v=2.4 cv=QrJuG1yd c=1 sm=1 tr=0 ts=6a30629c cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=gdiugJE53z4H+vvYeRBHqw==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=LPFoBd4iDjH1i6fID-MA:9 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-ORIG-GUID: ROb426S_m_MUSNh4JOb8tmqCWKJaE7si X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDIxOCBTYWx0ZWRfXy+rlk9n02e2j nuNyjTJX8ArgYD+gBkHSkxi7U3JsSTUN6tG8g2uD4GCK5sw7Nqd5JDuAkLksf/tkXTfGYDXszdJ Re2yda829VsqBxZDilnvdDJxSqSe4Ne3OnUORCLKGJrBiffNJUuDfhYBOWf5W8z4134nNJatIiB rSBB0wuqTJvPfporeyHn5B+Tj3gwt6T11iBzg8hj4IvkN9bCcmxla3Xp4xUO3qhau7eZoJUQ8OT jLP6XS9oHEh2QUpRhKPobvD/VE4gzfhrYI92we2oIRb4YaqFXtoLIAvr/9KkeQNk0y4Oa2oSzXB fb0POFufjjSyRV8x6GxLYsPwTZZxCsbdWuPZbIGVWGJVkJidBOscMWhsBZY682wASgP5RvynmtZ s9XYC0LTq3Qxb/cDxSb2sZesirGKwdMQh+GVGV6I92JNawJAD/cMBm3D8d0xExFcVck/iWrIkAC ieCu+IXi9gHoNRNcTvg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_05,2026-06-15_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150218 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781555921684158500 Content-Type: text/plain; charset="utf-8" There's FDT logic gated around 'numa_enabled()' in virt.c and spike.c. We want to move the FDT code to a common helper without having to call hw/riscv/numa.c functions from it, but at the same time being aware of the FDT changes if numa is enabled. To do that the boards will inform the FDT helpers if we have numa_enabled in the env or not. And for the boards to be able to do that we need the static 'numa_enabled' function to be public. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/numa.c | 20 ++++++++++---------- include/hw/riscv/numa.h | 8 ++++++++ 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index 8a144925c1..8933d9d81f 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -25,21 +25,21 @@ #include "hw/riscv/numa.h" #include "system/device_tree.h" =20 -static bool numa_enabled(const MachineState *ms) +bool riscv_numa_enabled(const MachineState *ms) { return (ms->numa_state && ms->numa_state->num_nodes) ? true : false; } =20 int riscv_socket_count(const MachineState *ms) { - return (numa_enabled(ms)) ? ms->numa_state->num_nodes : 1; + return (riscv_numa_enabled(ms)) ? ms->numa_state->num_nodes : 1; } =20 int riscv_socket_first_hartid(const MachineState *ms, int socket_id) { int i, first_hartid =3D ms->smp.cpus; =20 - if (!numa_enabled(ms)) { + if (!riscv_numa_enabled(ms)) { return (!socket_id) ? 0 : -1; } =20 @@ -59,7 +59,7 @@ int riscv_socket_last_hartid(const MachineState *ms, int = socket_id) { int i, last_hartid =3D -1; =20 - if (!numa_enabled(ms)) { + if (!riscv_numa_enabled(ms)) { return (!socket_id) ? ms->smp.cpus - 1 : -1; } =20 @@ -79,7 +79,7 @@ int riscv_socket_hart_count(const MachineState *ms, int s= ocket_id) { int first_hartid, last_hartid; =20 - if (!numa_enabled(ms)) { + if (!riscv_numa_enabled(ms)) { return (!socket_id) ? ms->smp.cpus : -1; } =20 @@ -104,7 +104,7 @@ bool riscv_socket_check_hartids(const MachineState *ms,= int socket_id) { int i, first_hartid, last_hartid; =20 - if (!numa_enabled(ms)) { + if (!riscv_numa_enabled(ms)) { return (!socket_id) ? true : false; } =20 @@ -132,7 +132,7 @@ uint64_t riscv_socket_mem_offset(const MachineState *ms= , int socket_id) int i; uint64_t mem_offset =3D 0; =20 - if (!numa_enabled(ms)) { + if (!riscv_numa_enabled(ms)) { return 0; } =20 @@ -148,7 +148,7 @@ uint64_t riscv_socket_mem_offset(const MachineState *ms= , int socket_id) =20 uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id) { - if (!numa_enabled(ms)) { + if (!riscv_numa_enabled(ms)) { return (!socket_id) ? ms->ram_size : 0; } =20 @@ -159,7 +159,7 @@ uint64_t riscv_socket_mem_size(const MachineState *ms, = int socket_id) void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_na= me, int socket_id) { - if (numa_enabled(ms)) { + if (riscv_numa_enabled(ms)) { qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_i= d); } } @@ -170,7 +170,7 @@ void riscv_socket_fdt_write_distance_matrix(const Machi= neState *ms) g_autofree uint32_t *dist_matrix =3D NULL; uint32_t dist_matrix_size; =20 - if (numa_enabled(ms) && ms->numa_state->have_numa_distance) { + if (riscv_numa_enabled(ms) && ms->numa_state->have_numa_distance) { dist_matrix_size =3D riscv_socket_count(ms) * riscv_socket_count(m= s); dist_matrix_size *=3D (3 * sizeof(uint32_t)); dist_matrix =3D g_malloc0(dist_matrix_size); diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index e68ce8e8af..ac07786555 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -23,6 +23,14 @@ #include "hw/core/sysbus.h" #include "system/numa.h" =20 +/** + * riscv_numa_enabled: + * @ms: pointer to machine state + * + * Returns: true if NUMA is enabled in the machine state. + */ +bool riscv_numa_enabled(const MachineState *ms); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781555923598158500 Content-Type: text/plain; charset="utf-8" This helper encapsulates the creation of /memory@addr FDT subnodes. Boards are responsible for calculating the adequate addr, size and inform if we have numa enabled. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/fdt-common.c | 15 +++++++++++++++ hw/riscv/sifive_u.c | 11 ++--------- hw/riscv/spike.c | 18 +++++++----------- hw/riscv/virt.c | 23 ++++++----------------- include/hw/riscv/fdt-common.h | 2 ++ 5 files changed, 32 insertions(+), 37 deletions(-) diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index b155246998..719c36e001 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -10,6 +10,7 @@ =20 #include "qemu/error-report.h" #include "system/device_tree.h" +#include "hw/core/boards.h" #include "hw/riscv/fdt-common.h" =20 void *create_board_device_tree(const char *model, const char *compatible, @@ -35,3 +36,17 @@ void *create_board_device_tree(const char *model, const = char *compatible, =20 return fdt; } + +void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, + int socket_id, bool numa_enabled) +{ + g_autofree char *mem_name =3D g_strdup_printf("/memory@%"HWADDR_PRIx, = addr); + + qemu_fdt_add_subnode(fdt, mem_name); + qemu_fdt_setprop_sized_cells(fdt, mem_name, "reg", 2, addr, 2, size); + qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); + + if (numa_enabled) { + qemu_fdt_setprop_cell(fdt, mem_name, "numa-node-id", socket_id); + } +} diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 5d3b2751ad..a00cfd08a7 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -98,7 +98,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry= *memmap, bool is_32_bit) { MachineState *ms =3D MACHINE(s); - uint64_t mem_size =3D ms->ram_size; void *fdt; int cpu; uint32_t *cells; @@ -138,14 +137,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); g_free(nodename); =20 - nodename =3D g_strdup_printf("/memory@%lx", - (long)memmap[SIFIVE_U_DEV_DRAM].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].ba= se, - mem_size >> 32, mem_size); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); - g_free(nodename); + create_fdt_socket_memory(fdt, memmap[SIFIVE_U_DEV_DRAM].base, + ms->ram_size, 0, false); =20 qemu_fdt_add_subnode(fdt, "/cpus"); qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 79c9bb041f..92facba29d 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -55,13 +55,12 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, { void *fdt; int fdt_size; - uint64_t addr, size; unsigned long clint_addr; int cpu, socket; MachineState *ms =3D MACHINE(s); uint32_t *clint_cells; uint32_t cpu_phandle, intc_phandle, phandle =3D 1; - char *mem_name, *clint_name, *clust_name; + char *clint_name, *clust_name; char *core_name, *cpu_name, *intc_name; static const char * const clint_compat[2] =3D { "sifive,clint0", "riscv,clint0" @@ -85,6 +84,10 @@ static void create_fdt(SpikeState *s, const MemMapEntry = *memmap, qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); =20 for (socket =3D (riscv_socket_count(ms) - 1); socket >=3D 0; socket--)= { + hwaddr memaddr =3D memmap[SPIKE_DRAM].base + + riscv_socket_mem_offset(ms, socket); + uint64_t memsize =3D riscv_socket_mem_size(ms, socket); + clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); qemu_fdt_add_subnode(fdt, clust_name); =20 @@ -133,15 +136,8 @@ static void create_fdt(SpikeState *s, const MemMapEntr= y *memmap, g_free(cpu_name); } =20 - addr =3D memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, soc= ket); - size =3D riscv_socket_mem_size(ms, socket); - mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); - qemu_fdt_add_subnode(fdt, mem_name); - qemu_fdt_setprop_cells(fdt, mem_name, "reg", - addr >> 32, addr, size >> 32, size); - qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(ms, mem_name, socket); - g_free(mem_name); + create_fdt_socket_memory(fdt, memaddr, memsize, socket, + riscv_numa_enabled(ms)); =20 clint_addr =3D memmap[SPIKE_CLINT].base + (memmap[SPIKE_CLINT].size * socket); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cb1d83fd48..df3eadef78 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -302,22 +302,6 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, } } =20 -static void create_fdt_socket_memory(RISCVVirtState *s, int socket) -{ - g_autofree char *mem_name =3D NULL; - hwaddr addr; - uint64_t size; - MachineState *ms =3D MACHINE(s); - - addr =3D s->memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socke= t); - size =3D riscv_socket_mem_size(ms, socket); - mem_name =3D g_strdup_printf("/memory@%"HWADDR_PRIx, addr); - qemu_fdt_add_subnode(ms->fdt, mem_name); - qemu_fdt_setprop_sized_cells(ms->fdt, mem_name, "reg", 2, addr, 2, siz= e); - qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(ms, mem_name, socket); -} - static void create_fdt_socket_clint(RISCVVirtState *s, int socket, uint32_t *intc_phandles) @@ -759,6 +743,10 @@ static void create_fdt_sockets(RISCVVirtState *s, phandle_pos =3D ms->smp.cpus; for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { g_autofree char *clust_name =3D NULL; + hwaddr memaddr =3D s->memmap[VIRT_DRAM].base + + riscv_socket_mem_offset(ms, socket); + uint64_t memsize =3D riscv_socket_mem_size(ms, socket); + phandle_pos -=3D s->soc[socket].num_harts; =20 clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); @@ -767,7 +755,8 @@ static void create_fdt_sockets(RISCVVirtState *s, create_fdt_socket_cpus(s, socket, clust_name, phandle, &intc_phandles[phandle_pos]); =20 - create_fdt_socket_memory(s, socket); + create_fdt_socket_memory(ms->fdt, memaddr, memsize, + socket, riscv_numa_enabled(ms)); =20 if (virt_aclint_allowed() && s->have_aclint) { create_fdt_socket_aclint(s, socket, diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index adf9b33dfd..81689f418b 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -11,4 +11,6 @@ =20 void *create_board_device_tree(const char *model, const char *compatible, int *fdt_size); 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Mon, 15 Jun 2026 13:37:51 -0700 (PDT) X-Received: by 2002:a05:620a:1a18:b0:8cf:f1d9:ba20 with SMTP id af79cd13be357-91c23c7c7e6mr194563585a.8.1781555871038; Mon, 15 Jun 2026 13:37:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, Daniel Henrique Barboza , Alistair Francis , Palmer Dabbelt Subject: [PATCH 05/13] hw/riscv/sifive_u.c: add intc_phandles array Date: Mon, 15 Jun 2026 17:37:25 -0300 Message-ID: <20260615203734.954428-6-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260615203734.954428-1-daniel.barboza@oss.qualcomm.com> References: <20260615203734.954428-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDIxOCBTYWx0ZWRfX7rh6x+8hE8dF iEZ31NHZKDjfZd38TLXui5t36P3bm6KMIGn5rdrY9Ot/tZYIcuoyq610991MXiHgZAlEVsLf1Z/ jYeOi/w/lbBT7siYgWxR6pLXOSxOBBZ41wUAy3ajqBy1yZl96BMYcK9oLzCt7yfm1zO5h2B/rX7 8KwFXl4k43EOdeyICv/+505I0UZj35EMAGmjBTmmY9fBUzh2EJIDsF3n7gzg0o8wJ3iazkhprVi vv3AKQOLOtjl+4Z96poZo1X3OaeinaZ3RK5RDcMOmwifdITfIrIY2TN58WLC/HVUOeJX8457u/M Tj/IvZA/RcgqtvqXuSRIJ26Q3vFEikHkNG9KY6OAENS7CZ5G7hJTvtLLMVamnttHaJ9qVQfBFye d5twNZ19e/iUuxTiWnSgLuVZzbHuipYz/uzThHMqsAdGHlPEcdTVtTwkinisQAdjNLnxwD7KLv0 q9SKkftLCwKAJVzaeMQ== X-Proofpoint-ORIG-GUID: YomEtPOb7BmRQ1T_2DxQArMkG_US8V4F X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDIxOCBTYWx0ZWRfX+wbgQTKLkJCA 6m53F/L1Bw4ihqVTWS7a1wEkwf2LoNxQM374zwsLXVfqGfNm+Pgc9Xj+MSVOot3MR31qpGoZk1L jHDD2Bd9HcSPgz3NtICZ1I4azKDALKE= X-Authority-Analysis: v=2.4 cv=HttG3UTS c=1 sm=1 tr=0 ts=6a3062a0 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=gdiugJE53z4H+vvYeRBHqw==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=KCrPqT59WbVjnSvmJHsA:9 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: YomEtPOb7BmRQ1T_2DxQArMkG_US8V4F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_05,2026-06-15_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 suspectscore=0 clxscore=1015 impostorscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150218 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781555909860158500 Content-Type: text/plain; charset="utf-8" Store the intc phandles in an 'intc_phandles' array, like the 'virt' board does, instead of re-creating the interrupt-controller FDT string and using qemu_fdt_get_phandle() to fetch it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a00cfd08a7..ce86989bc8 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -111,6 +111,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEnt= ry *memmap, static const char * const plic_compat[2] =3D { "sifive,plic-1.0.0", "riscv,plic0" }; + g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); =20 fdt =3D ms->fdt =3D create_board_device_tree("SiFive HiFive Unleashed = A00", "sifive,hifive-unleashed-a00", &s->fdt_size); @@ -168,8 +169,10 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); =20 + intc_phandles[cpu] =3D phandle++; + qemu_fdt_add_subnode(fdt, intc); - qemu_fdt_setprop_cell(fdt, intc, "phandle", phandle++); + qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandles[cpu]); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); @@ -179,14 +182,10 @@ static void create_fdt(SiFiveUState *s, const MemMapE= ntry *memmap, =20 cells =3D g_new0(uint32_t, ms->smp.cpus * 4); for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { - nodename =3D - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); - uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); + cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandles[cpu]); cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); - cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); + cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandles[cpu]); cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); - g_free(nodename); } nodename =3D g_strdup_printf("/soc/clint@%lx", (long)memmap[SIFIVE_U_DEV_CLINT].base); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781555909881158500 Content-Type: text/plain; charset="utf-8" The clint FDT generation uses a cells array (clint_cells) that are populated in the middle of the loop that creates the CPU socket FDT. This is completely fine but it differs from the other boards that creates the clint cells array right before creating the clint FDT. 'virt' and 'sifive_u' store the intc phandles in a intc_phandles array during FDT CPU socket creation, and this array is used to create the clint FDT cells. Standardize the clint FDT creation for spike doing the same here, allowing us to move everything to a common helper later. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/spike.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 92facba29d..82005ec163 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -59,7 +59,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, int cpu, socket; MachineState *ms =3D MACHINE(s); uint32_t *clint_cells; - uint32_t cpu_phandle, intc_phandle, phandle =3D 1; + uint32_t cpu_phandle, phandle =3D 1; char *clint_name, *clust_name; char *core_name, *cpu_name, *intc_name; static const char * const clint_compat[2] =3D { @@ -84,6 +84,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); =20 for (socket =3D (riscv_socket_count(ms) - 1); socket >=3D 0; socket--)= { + g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, + s->soc[socket].num_har= ts); hwaddr memaddr =3D memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket); uint64_t memsize =3D riscv_socket_mem_size(ms, socket); @@ -91,8 +93,6 @@ static void create_fdt(SpikeState *s, const MemMapEntry *= memmap, clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); qemu_fdt_add_subnode(fdt, clust_name); =20 - clint_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); - for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { cpu_phandle =3D phandle++; =20 @@ -113,20 +113,17 @@ static void create_fdt(SpikeState *s, const MemMapEnt= ry *memmap, riscv_socket_fdt_write_id(ms, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); =20 + intc_phandles[cpu] =3D phandle++; + intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_n= ame); qemu_fdt_add_subnode(fdt, intc_name); - intc_phandle =3D phandle++; - qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", + intc_phandles[cpu]); qemu_fdt_setprop_string(fdt, intc_name, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL,= 0); qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); =20 - clint_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); - clint_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); - clint_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); - clint_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); - core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); qemu_fdt_add_subnode(fdt, core_name); qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); @@ -139,6 +136,15 @@ static void create_fdt(SpikeState *s, const MemMapEntr= y *memmap, create_fdt_socket_memory(fdt, memaddr, memsize, socket, riscv_numa_enabled(ms)); =20 + clint_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); + + for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { + clint_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + clint_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); + clint_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandles[cpu]); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781556132674158501 Content-Type: text/plain; charset="utf-8" Move all clint FDT generation to fdt-common.c reducing code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/fdt-common.c | 33 +++++++++++++++++++++++++ hw/riscv/sifive_u.c | 25 +++---------------- hw/riscv/spike.c | 31 ++++------------------- hw/riscv/virt.c | 46 ++++++----------------------------- include/hw/riscv/fdt-common.h | 5 ++++ 5 files changed, 54 insertions(+), 86 deletions(-) diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index 719c36e001..d2661ec389 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -12,6 +12,7 @@ #include "system/device_tree.h" #include "hw/core/boards.h" #include "hw/riscv/fdt-common.h" +#include "target/riscv/cpu_bits.h" =20 void *create_board_device_tree(const char *model, const char *compatible, int *fdt_size) @@ -50,3 +51,35 @@ void create_fdt_socket_memory(void *fdt, hwaddr addr, ui= nt64_t size, qemu_fdt_setprop_cell(fdt, mem_name, "numa-node-id", socket_id); } } + +void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, + int socket_id, uint32_t *intc_phandles, + int num_harts, bool numa_enabled) +{ + g_autofree uint32_t *clint_cells =3D g_new0(uint32_t, num_harts * 4); + g_autofree char *clint_name =3D NULL; + static const char * const clint_compat[2] =3D { + "sifive,clint0", "riscv,clint0" + }; + + for (int cpu =3D 0; cpu < num_harts; cpu++) { + clint_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + clint_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); + clint_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandles[cpu]); + clint_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); + } + + clint_name =3D g_strdup_printf("/soc/clint@%"HWADDR_PRIx, addr); + qemu_fdt_add_subnode(fdt, clint_name); + qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", + (char **)&clint_compat, + ARRAY_SIZE(clint_compat)); + qemu_fdt_setprop_sized_cells(fdt, clint_name, "reg", + 2, addr, 2, size); + qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", + clint_cells, num_harts * sizeof(uint32_t) * 4); + + if (numa_enabled) { + qemu_fdt_setprop_cell(fdt, clint_name, "numa-node-id", socket_id); + } +} diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ce86989bc8..9a791b36d6 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -105,9 +105,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEnt= ry *memmap, uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle =3D 1; uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; static const char * const ethclk_names[2] =3D { "pclk", "hclk" }; - static const char * const clint_compat[2] =3D { - "sifive,clint0", "riscv,clint0" - }; static const char * const plic_compat[2] =3D { "sifive,plic-1.0.0", "riscv,plic0" }; @@ -180,25 +177,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, g_free(nodename); } =20 - cells =3D g_new0(uint32_t, ms->smp.cpus * 4); - for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { - cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); - cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandles[cpu]); - cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); - } - nodename =3D g_strdup_printf("/soc/clint@%lx", - (long)memmap[SIFIVE_U_DEV_CLINT].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string_array(fdt, nodename, "compatible", - (char **)&clint_compat, ARRAY_SIZE(clint_compat)); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_CLINT].base, - 0x0, memmap[SIFIVE_U_DEV_CLINT].size); - qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, ms->smp.cpus * sizeof(uint32_t) * 4); - g_free(cells); - g_free(nodename); + create_fdt_socket_clint(fdt, memmap[SIFIVE_U_DEV_CLINT].base, + memmap[SIFIVE_U_DEV_CLINT].size, 0, + intc_phandles, ms->smp.cpus, false); =20 nodename =3D g_strdup_printf("/soc/otp@%lx", (long)memmap[SIFIVE_U_DEV_OTP].base); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 82005ec163..b15188fb07 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -58,13 +58,10 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, unsigned long clint_addr; int cpu, socket; MachineState *ms =3D MACHINE(s); - uint32_t *clint_cells; uint32_t cpu_phandle, phandle =3D 1; - char *clint_name, *clust_name; + char *clust_name; char *core_name, *cpu_name, *intc_name; - static const char * const clint_compat[2] =3D { - "sifive,clint0", "riscv,clint0" - }; + bool numa_enabled =3D riscv_numa_enabled(ms); =20 fdt =3D ms->fdt =3D create_board_device_tree("ucbbar,spike-bare,qemu", "ucbbar,spike-bare-dev", &fdt_size); @@ -136,29 +133,11 @@ static void create_fdt(SpikeState *s, const MemMapEnt= ry *memmap, create_fdt_socket_memory(fdt, memaddr, memsize, socket, riscv_numa_enabled(ms)); =20 - clint_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); - - for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { - clint_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - clint_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); - clint_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandles[cpu]); - clint_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); - } - clint_addr =3D memmap[SPIKE_CLINT].base + (memmap[SPIKE_CLINT].size * socket); - clint_name =3D g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(fdt, clint_name); - qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", - (char **)&clint_compat, ARRAY_SIZE(clint_compat)); - qemu_fdt_setprop_cells(fdt, clint_name, "reg", - 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); - qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", - clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(ms, clint_name, socket); - - g_free(clint_name); - g_free(clint_cells); + create_fdt_socket_clint(fdt, clint_addr, memmap[SPIKE_CLINT].size, + socket, intc_phandles, + s->soc[socket].num_harts, numa_enabled); g_free(clust_name); } =20 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index df3eadef78..b134f11266 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -302,42 +302,6 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, } } =20 -static void create_fdt_socket_clint(RISCVVirtState *s, - int socket, - uint32_t *intc_phandles) -{ - int cpu; - g_autofree char *clint_name =3D NULL; - g_autofree uint32_t *clint_cells =3D NULL; - hwaddr clint_addr; - MachineState *ms =3D MACHINE(s); - static const char * const clint_compat[2] =3D { - "sifive,clint0", "riscv,clint0" - }; - - clint_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); - - for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { - clint_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - clint_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); - clint_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandles[cpu]); - clint_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); - } - - clint_addr =3D s->memmap[VIRT_CLINT].base + - s->memmap[VIRT_CLINT].size * socket; - clint_name =3D g_strdup_printf("/soc/clint@%"HWADDR_PRIx, clint_addr); - qemu_fdt_add_subnode(ms->fdt, clint_name); - qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", - (char **)&clint_compat, - ARRAY_SIZE(clint_compat)); - qemu_fdt_setprop_sized_cells(ms->fdt, clint_name, "reg", - 2, clint_addr, 2, s->memmap[VIRT_CLINT].size); - qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", - clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(ms, clint_name, socket); -} - static void create_fdt_socket_aclint(RISCVVirtState *s, int socket, uint32_t *intc_phandles) @@ -728,6 +692,7 @@ static void create_fdt_sockets(RISCVVirtState *s, uint32_t xplic_phandles[MAX_NODES]; g_autofree uint32_t *intc_phandles =3D NULL; int socket_count =3D riscv_socket_count(ms); + bool numa_enabled =3D riscv_numa_enabled(ms); =20 qemu_fdt_add_subnode(ms->fdt, "/cpus"); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", @@ -762,8 +727,13 @@ static void create_fdt_sockets(RISCVVirtState *s, create_fdt_socket_aclint(s, socket, &intc_phandles[phandle_pos]); } else if (tcg_enabled()) { - create_fdt_socket_clint(s, socket, - &intc_phandles[phandle_pos]); + hwaddr clintaddr =3D s->memmap[VIRT_CLINT].base + + s->memmap[VIRT_CLINT].size * socket; + + create_fdt_socket_clint(ms->fdt, clintaddr, + s->memmap[VIRT_CLINT].size, + socket, &intc_phandles[phandle_pos], + s->soc[socket].num_harts, numa_enabled= ); } } =20 diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 81689f418b..6e81d6cd6c 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -13,4 +13,9 @@ void *create_board_device_tree(const char *model, const c= har *compatible, int *fdt_size); void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, int socket_id, bool numa_enabled); +void create_fdt_clint(void *fdt, hwaddr addr, uint64_t size, + uint32_t *intc_phandles, int num_harts); +void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, + int socket_id, uint32_t *intc_phandles, + int num_harts, bool numa_enabled); #endif --=20 2.43.0 From nobody Sun Jul 26 13:29:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781556174; cv=none; d=zohomail.com; s=zohoarc; b=eDzf2CgtqcTH+qlv7kV0rzoZvdsojf+vJkHL0u0WIz9yQQ3VLvX5CIRBdnfSrNxyKcvYmFnvZHdRjaAEtWVM1DI52NebwSfmvkkltzp+cTmFd0859AyRT567nv7bBO2/a3GWz8u5fbWQXxJOiPBSTqaggbgDUCBPeg6DaSUpcPU= ARC-Message-Signature: i=1; a=rsa-sha256; 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Mon, 15 Jun 2026 13:37:58 -0700 (PDT) X-Received: by 2002:a05:6214:1c05:b0:8ca:10aa:e1f9 with SMTP id 6a1803df08f44-8da1eb4096amr11164926d6.42.1781555878267; Mon, 15 Jun 2026 13:37:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, Daniel Henrique Barboza , Alistair Francis , Palmer Dabbelt Subject: [PATCH 08/13] hw/riscv/sifive_u.c: add cpu-map, cluster and core DTs Date: Mon, 15 Jun 2026 17:37:28 -0300 Message-ID: <20260615203734.954428-9-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260615203734.954428-1-daniel.barboza@oss.qualcomm.com> References: <20260615203734.954428-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDIxOCBTYWx0ZWRfX9NMlsjiYlQ72 09gaVMvghg7YMr2YwpIloCV52T7pj9NmsJYopBy3LWd5iT+1jLIR94o5ANTfYAsNEtMt60cbq8n 8mtSDh3ap9Mso7XdEJ2EVRwxCs3reqezbFbPyE3mB5lBA6aRE8kVhA4KuR9ND6ZrrdsScbGylGN BR+eQzFudd6d2NtznfQN01VFBJI3hd5/bLjwTc8Y97bSPRGxDdq0NUWK8qrDBHPUI/bGY1Df4V3 hqiaAClFi+OH9BkL0OZfqxYdvlFa459377dPm3Mv6PqeebpGFtRF6zABmqxXMm2TemBr6oJOzS0 OhMtxCis9vtJo8oLUr9l3kfj3V3mRzCmrUK1ENgbRbkJXZS/XFauVSJCFuBG6S9ya8+rq30Cgk7 6JPHx/ulu0rEq3f4Z0ybbiyj0v/Hy3tN4qfEX4oLygopg4akcy5aA3AnbpgzhrjHkfhbHEljw4d luFNhLuPktmHu5iSdmA== X-Proofpoint-ORIG-GUID: UcLNNlpySnww6-s7rLnmD9xlRwmrqHTj X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDIxOCBTYWx0ZWRfX6ooQ9DWyjKaQ A1gTaSXpxQJvRocY4kbORFThCmdvwerFahWlAirh8aCAUG4WWZBnc1bRWe2/uhFFoyN85wOagow MeIgMYBXBR27k6RNf6tDELoNePxqJZU= X-Authority-Analysis: v=2.4 cv=HttG3UTS c=1 sm=1 tr=0 ts=6a3062a7 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=gdiugJE53z4H+vvYeRBHqw==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=De3kZSdNAtJ2C2JbOQQA:9 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-GUID: UcLNNlpySnww6-s7rLnmD9xlRwmrqHTj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_05,2026-06-15_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 suspectscore=0 clxscore=1015 impostorscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150218 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781556176772158500 Content-Type: text/plain; charset="utf-8" We want to consolidate the CPU socket FDT creation into a single helper. 'virt' and spike has the same code but sifive_u does not have cpu-map, cluster and core subnodes. These subnodes are present in other boards even in single socket configs without NUMA. This is a strong indicator that their presence doesn't hurt a NUMA-less board like sifive_u. Add these DTs to make the FDT standardization straightforward. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9a791b36d6..a4265fed0f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -109,6 +109,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEnt= ry *memmap, "sifive,plic-1.0.0", "riscv,plic0" }; g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); + g_autofree char *clust_name =3D NULL; =20 fdt =3D ms->fdt =3D create_board_device_tree("SiFive HiFive Unleashed = A00", "sifive,hifive-unleashed-a00", &s->fdt_size); @@ -143,11 +144,17 @@ static void create_fdt(SiFiveUState *s, const MemMapE= ntry *memmap, CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); + + clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", 0); + qemu_fdt_add_subnode(fdt, clust_name); =20 for (cpu =3D ms->smp.cpus - 1; cpu >=3D 0; cpu--) { int cpu_phandle =3D phandle++; nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); + g_autofree char *core_name =3D NULL; + qemu_fdt_add_subnode(fdt, nodename); /* cpu 0 is the management hart that does not have mmu */ if (cpu !=3D 0) { @@ -173,6 +180,11 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); + + core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); + qemu_fdt_add_subnode(fdt, core_name); + qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); + g_free(intc); g_free(nodename); } --=20 2.43.0 From nobody Sun Jul 26 13:29:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781556154699158500 Content-Type: text/plain; charset="utf-8" Consolidate the '/cpus' FDT root node creation into a single place. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/fdt-common.c | 10 ++++++++++ hw/riscv/sifive_u.c | 7 +------ hw/riscv/spike.c | 7 +------ hw/riscv/virt.c | 11 +++-------- include/hw/riscv/fdt-common.h | 1 + 5 files changed, 16 insertions(+), 20 deletions(-) diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index d2661ec389..02ac9ddcd8 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -83,3 +83,13 @@ void create_fdt_socket_clint(void *fdt, hwaddr addr, uin= t64_t size, qemu_fdt_setprop_cell(fdt, clint_name, "numa-node-id", socket_id); } } + +void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency) +{ + qemu_fdt_add_subnode(fdt, "/cpus"); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + timebase_frequency); + qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); +} diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a4265fed0f..27c1a74d99 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -139,12 +139,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, create_fdt_socket_memory(fdt, memmap[SIFIVE_U_DEV_DRAM].base, ms->ram_size, 0, false); =20 - qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", - CLINT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); + fdt_create_cpu_socket_subnode(fdt, CLINT_TIMEBASE_FREQ); =20 clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", 0); qemu_fdt_add_subnode(fdt, clust_name); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index b15188fb07..ee8232f734 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -73,12 +73,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry = *memmap, 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); } =20 - qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", - RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); + fdt_create_cpu_socket_subnode(fdt, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); =20 for (socket =3D (riscv_socket_count(ms) - 1); socket >=3D 0; socket--)= { g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index b134f11266..6641b60131 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -694,14 +694,9 @@ static void create_fdt_sockets(RISCVVirtState *s, int socket_count =3D riscv_socket_count(ms); bool numa_enabled =3D riscv_numa_enabled(ms); =20 - qemu_fdt_add_subnode(ms->fdt, "/cpus"); - qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", - kvm_enabled() ? - kvm_riscv_get_timebase_frequency(&s->soc->harts[= 0]) : - RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); + fdt_create_cpu_socket_subnode(ms->fdt, + kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]= ) : + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); =20 intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); =20 diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 6e81d6cd6c..27020e69c6 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -18,4 +18,5 @@ void create_fdt_clint(void *fdt, hwaddr addr, uint64_t si= ze, void create_fdt_socket_clint(void *fdt, hwaddr addr, uint64_t size, int socket_id, uint32_t *intc_phandles, int num_harts, bool numa_enabled); +void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency); #endif --=20 2.43.0 From nobody Sun Jul 26 13:29:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781556114; cv=none; d=zohomail.com; s=zohoarc; b=VF8L838KwCM96A0oi7hAfZAS42xodlFb+tg9l2jgv9C8D7jJEmmc4+QagIrzwoqOaovVXjBxtY1OL0bfS/CyPteFPX71b65pslV2CPZrnb5Dxp5D9Y49qHJpENdnHtOm/6nPOz0UJizZcRa/6B/p9of0QlPWHMeaRzAupngU+Ro= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781556116558158500 Content-Type: text/plain; charset="utf-8" Consolidate the creation of CPUs socket FDT in a helper that can be shared across all boards. The code was basically moved from the function with the same name from 'virt.c', with additional bits to create the cluster subnode beforehand. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/fdt-common.c | 74 +++++++++++++++++++++++++++++++ hw/riscv/virt.c | 83 +++-------------------------------- include/hw/riscv/fdt-common.h | 7 +++ 3 files changed, 87 insertions(+), 77 deletions(-) diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index 02ac9ddcd8..6c795409a4 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -93,3 +93,77 @@ void fdt_create_cpu_socket_subnode(void *fdt, uint64_t t= imebase_frequency) qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); } + +void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, + int socket_id, int num_harts_socket, + int socket_hartid_base, uint32_t *phandle, + uint32_t *intc_phandles, bool numa_enabled, + bool is_32_bit) +{ + g_autofree char *clust_name =3D NULL; + uint32_t cpu_phandle; + + clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket_id); + qemu_fdt_add_subnode(fdt, clust_name); + + for (int cpu =3D num_harts_socket - 1; cpu >=3D 0; cpu--) { + RISCVCPU *cpu_ptr =3D &socket_harts[cpu]; + int8_t satp_mode_max =3D cpu_ptr->cfg.max_satp_mode; + g_autofree char *cpu_name =3D NULL; + g_autofree char *core_name =3D NULL; + g_autofree char *intc_name =3D NULL; + + cpu_phandle =3D (*phandle)++; + + cpu_name =3D g_strdup_printf("/cpus/cpu@%d", socket_hartid_base + = cpu); + qemu_fdt_add_subnode(fdt, cpu_name); + + if (satp_mode_max !=3D -1) { + g_autofree char *sv_name =3D NULL; + sv_name =3D g_strdup_printf("riscv,%s", + satp_mode_str(satp_mode_max, is_32_b= it)); + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", sv_name); + } + riscv_isa_write_fdt(cpu_ptr, fdt, cpu_name); + + if (cpu_ptr->cfg.ext_zicbom) { + qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cbom-block-size", + cpu_ptr->cfg.cbom_blocksize); + } + + if (cpu_ptr->cfg.ext_zicboz) { + qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cboz-block-size", + cpu_ptr->cfg.cboz_blocksize); + } + + if (cpu_ptr->cfg.ext_zicbop) { + qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cbop-block-size", + cpu_ptr->cfg.cbop_blocksize); + } + + qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(fdt, cpu_name, "reg", + socket_hartid_base + cpu); + qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); + if (numa_enabled) { + qemu_fdt_setprop_cell(fdt, cpu_name, "numa-node-id", socket_id= ); + } + qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); + + intc_phandles[cpu] =3D (*phandle)++; + + intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_name); + qemu_fdt_add_subnode(fdt, intc_name); + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", + intc_phandles[cpu]); + qemu_fdt_setprop_string(fdt, intc_name, "compatible", + "riscv,cpu-intc"); + qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); + + core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); + qemu_fdt_add_subnode(fdt, core_name); + qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); + } +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6641b60131..33775a61fd 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -231,77 +231,6 @@ static void create_pcie_irq_map(RISCVVirtState *s, voi= d *fdt, char *nodename, 0x1800, 0, 0, 0x7); } =20 -static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, - char *clust_name, uint32_t *phandle, - uint32_t *intc_phandles) -{ - int cpu; - uint32_t cpu_phandle; - MachineState *ms =3D MACHINE(s); - bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); - - for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { - RISCVCPU *cpu_ptr =3D &s->soc[socket].harts[cpu]; - int8_t satp_mode_max =3D cpu_ptr->cfg.max_satp_mode; - g_autofree char *cpu_name =3D NULL; - g_autofree char *core_name =3D NULL; - g_autofree char *intc_name =3D NULL; - g_autofree char *sv_name =3D NULL; - - cpu_phandle =3D (*phandle)++; - - cpu_name =3D g_strdup_printf("/cpus/cpu@%d", - s->soc[socket].hartid_base + cpu); - qemu_fdt_add_subnode(ms->fdt, cpu_name); - - if (satp_mode_max !=3D -1) { - sv_name =3D g_strdup_printf("riscv,%s", - satp_mode_str(satp_mode_max, is_32_b= it)); - qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name= ); - } - - riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); - - if (cpu_ptr->cfg.ext_zicbom) { - qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-siz= e", - cpu_ptr->cfg.cbom_blocksize); - } - - if (cpu_ptr->cfg.ext_zicboz) { - qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-siz= e", - cpu_ptr->cfg.cboz_blocksize); - } - - if (cpu_ptr->cfg.ext_zicbop) { - qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-siz= e", - cpu_ptr->cfg.cbop_blocksize); - } - - qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", - s->soc[socket].hartid_base + cpu); - qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(ms, cpu_name, socket); - qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); - - intc_phandles[cpu] =3D (*phandle)++; - - intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_name); - qemu_fdt_add_subnode(ms->fdt, intc_name); - qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", - intc_phandles[cpu]); - qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", - "riscv,cpu-intc"); - qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL,= 0); - qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); - - core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(ms->fdt, core_name); - qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); - } -} - static void create_fdt_socket_aclint(RISCVVirtState *s, int socket, uint32_t *intc_phandles) @@ -693,6 +622,7 @@ static void create_fdt_sockets(RISCVVirtState *s, g_autofree uint32_t *intc_phandles =3D NULL; int socket_count =3D riscv_socket_count(ms); bool numa_enabled =3D riscv_numa_enabled(ms); + bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); =20 fdt_create_cpu_socket_subnode(ms->fdt, kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]= ) : @@ -702,18 +632,17 @@ static void create_fdt_sockets(RISCVVirtState *s, =20 phandle_pos =3D ms->smp.cpus; for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { - g_autofree char *clust_name =3D NULL; hwaddr memaddr =3D s->memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); uint64_t memsize =3D riscv_socket_mem_size(ms, socket); =20 phandle_pos -=3D s->soc[socket].num_harts; =20 - clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); - qemu_fdt_add_subnode(ms->fdt, clust_name); - - create_fdt_socket_cpus(s, socket, clust_name, phandle, - &intc_phandles[phandle_pos]); + create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, socket, + s->soc[socket].num_harts, + s->soc[socket].hartid_base, + phandle, &intc_phandles[phandle_pos], + numa_enabled, is_32_bit); =20 create_fdt_socket_memory(ms->fdt, memaddr, memsize, socket, riscv_numa_enabled(ms)); diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 27020e69c6..3af9d5c3fd 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -9,6 +9,8 @@ #ifndef RISCV_VIRT_FDT_H #define RISCV_VIRT_FDT_H =20 +#include "target/riscv/cpu.h" + void *create_board_device_tree(const char *model, const char *compatible, int *fdt_size); void create_fdt_socket_memory(void *fdt, hwaddr addr, uint64_t size, @@ -19,4 +21,9 @@ void create_fdt_socket_clint(void *fdt, hwaddr addr, uint= 64_t size, int socket_id, uint32_t *intc_phandles, int num_harts, bool numa_enabled); void fdt_create_cpu_socket_subnode(void *fdt, uint64_t timebase_frequency); +void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, + int socket_id, int num_harts_socket, + int socket_hartid_base, uint32_t *phandle, + uint32_t *intc_phandles, bool numa_enabled, + bool is_32_bit); #endif --=20 2.43.0 From nobody Sun Jul 26 13:29:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781556136587158500 Content-Type: text/plain; charset="utf-8" Use the new FDT helper to create FDTs for the CPU sockets. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/spike.c | 54 +++++++----------------------------------------- 1 file changed, 7 insertions(+), 47 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index ee8232f734..4e60724c14 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -56,11 +56,9 @@ static void create_fdt(SpikeState *s, const MemMapEntry = *memmap, void *fdt; int fdt_size; unsigned long clint_addr; - int cpu, socket; + int socket; MachineState *ms =3D MACHINE(s); - uint32_t cpu_phandle, phandle =3D 1; - char *clust_name; - char *core_name, *cpu_name, *intc_name; + uint32_t phandle =3D 1; bool numa_enabled =3D riscv_numa_enabled(ms); =20 fdt =3D ms->fdt =3D create_board_device_tree("ucbbar,spike-bare,qemu", @@ -82,48 +80,11 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, riscv_socket_mem_offset(ms, socket); uint64_t memsize =3D riscv_socket_mem_size(ms, socket); =20 - clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); - qemu_fdt_add_subnode(fdt, clust_name); - - for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { - cpu_phandle =3D phandle++; - - cpu_name =3D g_strdup_printf("/cpus/cpu@%d", - s->soc[socket].hartid_base + cpu); - qemu_fdt_add_subnode(fdt, cpu_name); - if (is_32_bit) { - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,= sv32"); - } else { - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,= sv48"); - } - riscv_isa_write_fdt(&s->soc[socket].harts[cpu], fdt, cpu_name); - qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(fdt, cpu_name, "reg", - s->soc[socket].hartid_base + cpu); - qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(ms, cpu_name, socket); - qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); - - intc_phandles[cpu] =3D phandle++; - - intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_n= ame); - qemu_fdt_add_subnode(fdt, intc_name); - qemu_fdt_setprop_cell(fdt, intc_name, "phandle", - intc_phandles[cpu]); - qemu_fdt_setprop_string(fdt, intc_name, "compatible", - "riscv,cpu-intc"); - qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL,= 0); - qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); - - core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(fdt, core_name); - qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); - - g_free(core_name); - g_free(intc_name); - g_free(cpu_name); - } + create_fdt_socket_cpus(fdt, (&s->soc[socket])->harts, socket, + s->soc[socket].num_harts, + s->soc[socket].hartid_base, + &phandle, intc_phandles, numa_enabled, + is_32_bit); =20 create_fdt_socket_memory(fdt, memaddr, memsize, socket, riscv_numa_enabled(ms)); @@ -133,7 +94,6 @@ static void create_fdt(SpikeState *s, const MemMapEntry = *memmap, create_fdt_socket_clint(fdt, clint_addr, memmap[SPIKE_CLINT].size, socket, intc_phandles, s->soc[socket].num_harts, numa_enabled); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781556024014158500 Content-Type: text/plain; charset="utf-8" The sifive_u board does not share the same CPU socket FDT bits from the other boards. In particular the riscv,isa creation is done using either CPU0 from soc.e_cpus.harts, and for all other CPUs soc.u_cups.harts is used. It would be too cumbersome to add all these details in the common code so we're going to add a special sifive_u only helper that shares the common bits with the common helper used by the other boards. create_fdt_socket_cpu_internal() contains the common bits shared between the sifive_u board and the rest. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/fdt-common.c | 108 +++++++++++++++++++++++++----------------- 1 file changed, 65 insertions(+), 43 deletions(-) diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index 6c795409a4..70168ad657 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -94,28 +94,29 @@ void fdt_create_cpu_socket_subnode(void *fdt, uint64_t = timebase_frequency) qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); } =20 -void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, - int socket_id, int num_harts_socket, - int socket_hartid_base, uint32_t *phandle, - uint32_t *intc_phandles, bool numa_enabled, - bool is_32_bit) +static void +create_fdt_socket_cpu_internal(void *fdt, char *clust_name, RISCVCPU *cpu_= ptr, + int cpu, int socket_id, int socket_hartid_b= ase, + uint32_t *phandle, uint32_t *intc_phandles, + bool numa_enabled, bool is_32_bit) { - g_autofree char *clust_name =3D NULL; - uint32_t cpu_phandle; - - clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket_id); - qemu_fdt_add_subnode(fdt, clust_name); - - for (int cpu =3D num_harts_socket - 1; cpu >=3D 0; cpu--) { - RISCVCPU *cpu_ptr =3D &socket_harts[cpu]; + g_autofree char *cpu_name =3D NULL; + g_autofree char *core_name =3D NULL; + g_autofree char *intc_name =3D NULL; + uint32_t cpu_phandle =3D (*phandle)++; + bool is_sifive_u =3D cpu_ptr =3D=3D NULL; + + cpu_name =3D g_strdup_printf("/cpus/cpu@%d", socket_hartid_base + cpu); + + /* + * The sifive_u board has an exclusive satp and riscv,isa + * schema that can't be shared with other boards, so part + * of the CPU FDT creation (i.e. the /cpus/cpu@N subnode) + * is still being done by the board. + */ + if (!is_sifive_u) { int8_t satp_mode_max =3D cpu_ptr->cfg.max_satp_mode; - g_autofree char *cpu_name =3D NULL; - g_autofree char *core_name =3D NULL; - g_autofree char *intc_name =3D NULL; - - cpu_phandle =3D (*phandle)++; =20 - cpu_name =3D g_strdup_printf("/cpus/cpu@%d", socket_hartid_base + = cpu); qemu_fdt_add_subnode(fdt, cpu_name); =20 if (satp_mode_max !=3D -1) { @@ -140,30 +141,51 @@ void create_fdt_socket_cpus(void *fdt, RISCVCPU *sock= et_harts, qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cbop-block-size", cpu_ptr->cfg.cbop_blocksize); } + } =20 - qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(fdt, cpu_name, "reg", - socket_hartid_base + cpu); - qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - if (numa_enabled) { - qemu_fdt_setprop_cell(fdt, cpu_name, "numa-node-id", socket_id= ); - } - qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); - - intc_phandles[cpu] =3D (*phandle)++; - - intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_name); - qemu_fdt_add_subnode(fdt, intc_name); - qemu_fdt_setprop_cell(fdt, intc_name, "phandle", - intc_phandles[cpu]); - qemu_fdt_setprop_string(fdt, intc_name, "compatible", - "riscv,cpu-intc"); - qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); - - core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(fdt, core_name); - qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); + qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(fdt, cpu_name, "reg", + socket_hartid_base + cpu); + qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); + if (numa_enabled) { + qemu_fdt_setprop_cell(fdt, cpu_name, "numa-node-id", socket_id); + } + qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); + + intc_phandles[cpu] =3D (*phandle)++; + + intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_name); + qemu_fdt_add_subnode(fdt, intc_name); + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", + intc_phandles[cpu]); + qemu_fdt_setprop_string(fdt, intc_name, "compatible", + "riscv,cpu-intc"); + qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); + + core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); + qemu_fdt_add_subnode(fdt, core_name); + qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); +} + +void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_harts, + int socket_id, int num_harts_socket, + int socket_hartid_base, uint32_t *phandle, + uint32_t *intc_phandles, bool numa_enabled, + bool is_32_bit) +{ + g_autofree char *clust_name =3D NULL; + + clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket_id); + qemu_fdt_add_subnode(fdt, clust_name); + + for (int cpu =3D num_harts_socket - 1; cpu >=3D 0; cpu--) { + RISCVCPU *cpu_ptr =3D &socket_harts[cpu]; + + create_fdt_socket_cpu_internal(fdt, clust_name, cpu_ptr, cpu, + socket_id, socket_hartid_base, + phandle, intc_phandles, numa_enable= d, + is_32_bit); } } --=20 2.43.0 From nobody Sun Jul 26 13:29:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781555965719158500 Content-Type: text/plain; charset="utf-8" This sifive_u only helper shares DT code with other boards. The idea is to reduce code repetition while keeping sifive_u characteristics in place. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/fdt-common.c | 11 +++++++++++ hw/riscv/sifive_u.c | 24 +++--------------------- include/hw/riscv/fdt-common.h | 4 ++++ 3 files changed, 18 insertions(+), 21 deletions(-) diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index 70168ad657..b27ff13bca 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -189,3 +189,14 @@ void create_fdt_socket_cpus(void *fdt, RISCVCPU *socke= t_harts, is_32_bit); } } + +void +create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, + int cpu_id, int socket_id, + int socket_hartid_base, uint32_t *phandle, + uint32_t *intc_phandles) +{ + create_fdt_socket_cpu_internal(fdt, clust_name, NULL, cpu_id, + socket_id, socket_hartid_base, + phandle, intc_phandles, false, false); +} diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 27c1a74d99..0c6e4204cb 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -145,12 +145,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, qemu_fdt_add_subnode(fdt, clust_name); =20 for (cpu =3D ms->smp.cpus - 1; cpu >=3D 0; cpu--) { - int cpu_phandle =3D phandle++; nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); - g_autofree char *core_name =3D NULL; - qemu_fdt_add_subnode(fdt, nodename); + /* cpu 0 is the management hart that does not have mmu */ if (cpu !=3D 0) { if (is_32_bit) { @@ -162,25 +159,10 @@ static void create_fdt(SiFiveUState *s, const MemMapE= ntry *memmap, } else { riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename); } - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); - qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); - qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); - - intc_phandles[cpu] =3D phandle++; - - qemu_fdt_add_subnode(fdt, intc); - qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandles[cpu]); - qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); =20 - core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(fdt, core_name); - qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); + create_fdt_socket_cpu_sifive(fdt, clust_name, cpu, 0, 0, + &phandle, intc_phandles); =20 - g_free(intc); g_free(nodename); } =20 diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index 3af9d5c3fd..2d6b9a5d03 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -26,4 +26,8 @@ void create_fdt_socket_cpus(void *fdt, RISCVCPU *socket_h= arts, int socket_hartid_base, uint32_t *phandle, uint32_t *intc_phandles, bool numa_enabled, bool is_32_bit); +void create_fdt_socket_cpu_sifive(void *fdt, char *clust_name, + int cpu_id, int socket_id, + int socket_hartid_base, uint32_t *phandl= e, + uint32_t *intc_phandles); #endif --=20 2.43.0