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Mon, 15 Jun 2026 06:19:50 -0700 (PDT) From: Qingwei Hu To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, jim.shu@sifive.com, nutty.liu@hotmail.com, Qingwei Hu Subject: [PATCH v2 1/2] hw/intc: riscv_aplic: Skip reset for KVM irqchip Date: Mon, 15 Jun 2026 21:19:24 +0800 Message-Id: <20260615131925.3019370-2-qingwei.hu@bytedance.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260615131925.3019370-1-qingwei.hu@bytedance.com> References: <20260615131925.3019370-1-qingwei.hu@bytedance.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=qingwei.hu@bytedance.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @bytedance.com) X-ZM-MESSAGEID: 1781529620897158500 Content-Type: text/plain; charset="utf-8" The emulated APLIC state arrays are only allocated when QEMU handles the interrupt controller state itself. With KVM AIA/APLIC-IMSIC, the interrupt controller state is owned by the KVM in-kernel irqchip, so these emulated state arrays are not allocated. The APLIC reset handler still clears those arrays unconditionally. This makes qemu_system_reset(), which runs during machine creation, dereference NULL pointers with -machine virt,aia=3Daplic-imsic and KVM. Skip the emulated APLIC reset path when the interrupt controller is handled by KVM. The emulated path is unchanged for TCG and for configurations that use QEMU emulation. Fixes: 99bfcd329a ("hw/intc: riscv_aplic: Add reset API to APLIC") Reviewed-by: Nutty Liu Signed-off-by: Qingwei Hu Reviewed-by: Alistair Francis --- hw/intc/riscv_aplic.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index c2c67c29e6..84606e9f3d 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -910,6 +910,10 @@ static void riscv_aplic_reset_enter(Object *obj, Reset= Type type) RISCVAPLICState *aplic =3D RISCV_APLIC(obj); int i; =20 + if (!riscv_use_emulated_aplic(aplic->msimode)) { + return; + } + aplic->domaincfg =3D 0; memset(aplic->sourcecfg, 0, sizeof(uint32_t) * aplic->num_irqs); memset(aplic->target, 0, sizeof(uint32_t) * aplic->num_irqs); --=20 2.47.3 From nobody Sun Jul 26 13:29:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 15 Jun 2026 06:19:59 -0700 (PDT) From: Qingwei Hu To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, jim.shu@sifive.com, nutty.liu@hotmail.com, Qingwei Hu Subject: [PATCH v2 2/2] hw/intc: riscv_imsic: Skip reset for KVM irqchip Date: Mon, 15 Jun 2026 21:19:25 +0800 Message-Id: <20260615131925.3019370-3-qingwei.hu@bytedance.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260615131925.3019370-1-qingwei.hu@bytedance.com> References: <20260615131925.3019370-1-qingwei.hu@bytedance.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=qingwei.hu@bytedance.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @bytedance.com) X-ZM-MESSAGEID: 1781529617034158500 Content-Type: text/plain; charset="utf-8" The emulated IMSIC state arrays are only allocated when QEMU handles the interrupt controller state itself. With KVM AIA/APLIC-IMSIC, the interrupt controller state is owned by the KVM in-kernel irqchip, so these emulated state arrays are not allocated. The IMSIC reset handler still clears those arrays unconditionally. This makes qemu_system_reset(), which runs during machine creation, dereference NULL pointers with -machine virt,aia=3Daplic-imsic and KVM. Skip the emulated IMSIC reset path when the interrupt controller is handled by KVM. The emulated path is unchanged for TCG and for configurations that use QEMU emulation. Fixes: 766391483b ("hw/intc: riscv_imsic: Add reset API to IMSIC") Reviewed-by: Nutty Liu Signed-off-by: Qingwei Hu Reviewed-by: Alistair Francis --- hw/intc/riscv_imsic.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index ac59496c22..f1f23c3a3e 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -347,6 +347,10 @@ static void riscv_imsic_reset_enter(Object *obj, Reset= Type type) RISCVIMSICState *imsic =3D RISCV_IMSIC(obj); int i; =20 + if (kvm_irqchip_in_kernel()) { + return; + } + memset(imsic->eidelivery, 0, sizeof(uint32_t) * imsic->num_pages); memset(imsic->eithreshold, 0, sizeof(uint32_t) * imsic->num_pages); =20 --=20 2.47.3